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Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

Chapter 5 Troubleshooting for Clock


5.1 Overview
5.1.1 Description and Fault Causes in BSC Clock System
Table 1.1 Description and fault causes in BSC clock system
Fault causes Reference source fault Description The alarms DDS control data abnormal and Clock crystal oscillator override are reported on BSC alarm console. GCKS MOD indicator flashes slowly and most of the BTSs clock are out of lock. The alarms Clock source changed and Clock reference source abnormal/normal (alternatively) are displayed at the BSC alarm console. The MOD indicator or the F0/REFA indicator on the GCKS is constantly ON. After pulling out the two cables that introduces the two clock sources in the clock frame, the output 2MHz clock in the clock frame turns normal and most of the BTSs become locked. Board fault in clock frame On the maintenance console, GCKS is displayed red, or GCKS indicator is displayed abnormal, but turns normal after GCKS replacement. Clock alarms are displayed at the alarm console, but are removed after GCKS replacement. After pulling out the two cables that introduce the two clock sources in the clock frame, the CKB output clocks (including 2MHz, 4MHz, 8kHz and 32MHz) are tested abnormal and cannot recover even after GCKS replacement. Connection cable fault in clock frame On the maintenance console, GCKS is displayed red, the CLK indicator on GCKS flashes slowly. The fault cannot be removed even after GCKS replacement. On the maintenance console, GCTN/GSNT clock fault is reported, but the CKB output clock (including 2MHz, 4MHz, 8kHz and 32MHz) is tested normal by the frequency meter. Clock reference source fault alarm is reported on the BSC alarm console, and the F0/REFA indicator on the GCKS is ON. Data configuration fault On the maintenance console, GCKS is displayed red, the CLK indicator on the GCKS flashes slowly. The fault cannot be removed after GCKS replacement.

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

5.1.2 Description and Fault Causes in BTS Clock System


I. Description and fault causes in BTS3X clock system Table 1.1 Description and fault causes in BTS3X clock system
Fault causes Reference source problem Description 13MHz clock out of lock alarm is reported. The BTS3X BSIC cannot be decode. The cell handover success rate is very low. The output 2MHz deviation of the MMU tested at the local end is large. Connection cable fault Clock-related alarms and test phase-lock ring alarm occur to all TRXs in the slots, accompanied with TRX repeated loading, TRX communication alarm and alarm removal report etc. But, no alarms occur to TMU, TDU indicators switches work normally and DIP switches set correct. Onsite operation error or BTS3X clock aging 13MHz clock out-of-lock alarm occurs. Call drop occurs frequently. Handover success rate drops substantially. The output 2MHz clock of the TMU tested at the local end is normal. Board fault (TMU, TDU and TRX) TMU mailbox fault alarm occurs. TMU clock fault occurs. Clock-related alarm and repeated reset occur to all TRXs. Connection cables and TMU work normally, and DIP switches are correctly set. But, clock-related alarm and repeated reset occur to all TRXs. Clock-related alarm occurs to some TRXs.

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

II. Description and fault causes in BTS3001C clock system Table 1.1 Description and fault causes in BTS3001C clock system
Fault causes Reference source fault Description 13MHz clock out-of-lock alarm occurs. BTS3001C BSIC cannot be unlocked. The cell handover success rate is very low. The output 2MHz deviation of the MMU tested at the local end is large. No other alarms occur to the BTS3001C. Board fault Frame No. alarm, TS No. alarm, Rx/Tx phase-locked loop alarm and other clockrelated alarms occur to the BTS3001C. MFU and MCI are repeatedly reset. No output 13MHz clocks can be tested or the deviation is large. Version fallback 13MHz clock out-of-lock alarm occurs. BTS3001C D/A value deviation is large, and the D/A value displayed is 0. Handover success rate drops substantially. The MMU operating version is 03.0301A, but the operating version of MFU and MCI is 05.0301A or even higher. Onsite operation error or clock aging 13MHz clock out-of-lock alarm occurs. BTS3001C cell handover success rate drops sharply. No other alarms occur to BTS3001C. When the BTS3001C clock is adjusted as under free-run mode, the output 13MHz clock offset is large.

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

5.2 Fundamental Knowledge


5.2.1 Introduction to BSC
I. Introduction to BSC clock signal flow
MSC

TCSM

E3M 8kHz 8kHz 2MHz 32MHz E3M GCTN GCKS 8kHz 32MHz

GSNT

GFBI

GMCC

GOPT

GNET

CKV

BIE

GNOD/GLAP/GMC2

Figure I.1 Multi-module BSC clock signal flow


As shown in Figure I.1, the path for multi-module BSC clock signals is as follows. The clock is abstracted from MSC and is transmitted via TCSM and E3M to GCKS as 8kHz reference source. GCKS traces the external reference signals and filters the jittering and drifting of the external reference signals to provide the high-stability clock signals (32MHz, 8kHz and 4MHz) which the BSC required. The clocks output from GCKS are first provided to the GCTN (32MHz, 4MHz and 8kHz) and the GSNT (32MHz and 8kHz) in AM. Then, they are driven by the GCTN to output the clock signals (32MHz, 8kHz and 4MHz) to GFBI. Clock signals are transmitted to BM through the optical paths, and GOPT extracts the clock signals (2MHz and 8kHz) and transmits them to the GNET in BM. The clock signals of the boards (GNOD, GLAP/LPN7 and GMC2) in the main control frame in BM are provided by GNET. The clock signals extracted by GCTN are first driven by CKV, and then transmitted to the boards in BTS interface frame through external HW clock cables.

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

II. Introduction to theinput reference source signals in BSC clock frame


There are three channels of input reference source in BSC clock frame.

1)

8kHz differential signal source from E3M (including 8kHz0 and 8kHz1)

8kHz0 and 8kHz1 are two sets of 8kHz reference source, most commonly used by BSC. They can be input to GCKS by JC1 or JC2 through differential cables (twisted pairs). The cable connection is illustrated in Figure II.1. The 8kHz differential signal sources from the trunk system are input by the 4-core sockets JC1 and JC2. Note that JC1 and JC2 are connected in parallel, i.e., if the two channels of 8kHz differential signal sources from the trunk frame are input from one 4-core connector, the differential cables can be connected either to JC1 or JC2.

JC2

JC1 8k08k0+ 8K18K1+

Figure II.1 The cable connection when the 8kHz differential reference sources come from the same trunk frame
If the two channels of 8kHz differential signal sources come from different trunk frames, the cable connection must be handled with care. Only two differential cables can be connected to either 4-core sockets, as shown in Figure II.2.

JC2

JC1 8k08k0+

8k18k1+
Figure II.2 Cable connection when the 8kHz differential reference sources come from different trunk frames 2)
The 2.048Mbit/s (E1 signals and HDB3 codes are converted on GCKS to 2.048MHz clocks) input reference source (including ER1 and ER2) from BITS equipment

3)

The 2.048MHz TTL clock signal input reference source (including 2MR1 and 2MR2) from BITS equipment

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

III. Introduction to the output signals in BSC clock frame 1) 2)


To GSNT: 8kHz, 32MHz To GCTN: 8kHz, 32MHz and 4MHz

Note: 8kHz and 32MHz clock signals are simultaneously output to the backplane of GSNT and that of GCTN, with the output matching resistance as 75 (150 for each board). The 4MHz signals only output to the GCTN, with the output matching resistance as 75. Therefore, set the frequency meter to the state of low resistance matching when testing the 8kHz, 32MHz and 4MHz clock signals with the meter. Otherwise, the test result might be inaccurate.

IV. Introduction to BSC clock hardware configuration 1)


Introduction to GCKS

GCKS is the board that generates the reference clock source in the clock system of the switch. In the board, there is a stratum-2 O ven voltage Control Oscillator (OCXO) in GCKS. GCKS traces the external reference signals and filters their jittering and drifting to ensure high frequency accuracy and stability of the timing signals output and provide the switch a high-quality clock source. The GCKS can provide both stratum-2 and stratum-3 clocks. GCKS works under four modes. When GCKS is first powered on, the OCXO in it will have been heated for 3 minutes. In the 3 minutes, its MOD indicator is OFF. Then, the board starts to work, its OCXO enters free-run state and the MOD indicator is OFF. If there is no reference source, the OCXO will continue in its free-run state. If there is reference source, GCKS will first check its frequency deviation. If the deviation is big, REFA indicator will be ON. If the deviation is normal, the OCXO will enter fast pull-in state and the MOD indicator will flash quickly. Usually fast pull-in state will last 10~15 minutes. After the 10~15 minutes, if the reference source is abnormal, the OCXO will enter free-run state. If the reference source is normal, the OCXO will enter locked state, MOD indicator will flash slowly and GCKS starts to work. If the reference source is abnormal during the locked state, the OCXO will enter holdover state and MOD indicator will be ON. But when the reference source resumes normal, the OXCO will re-enter locked state.

2)

Important DIP switches

(a) Configuration of GMPU and GCKS communication rate There are DIP switches on both GCKS and CKB for configuration of communication between GCKS and GMPU. Only when the DIP switches on both GCKS and CKB are correctly set, can the communication between GMPU and GCKS be normal. Otherwise, GCKS fault will occur.

Table 1.1 The DIP switches for configuring the communication rate between GCKS and CKB
BSC type GCKS S5.1 Multi module Single module ON OFF OFF OFF OFF OFF CKB S4.1 S4.2 S4.3 S4.4 ON ON ON ON Point to multi-point, high baud rate Point to point, low baud rate Communication mode

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

(b) Other DIP switches on GCKS There are other two DIP switches on GCKS for configuring the clock stratum and phase lock mode of GCKS. Usually they are set as follows.
DIP switch S5.2 S5.3 Common setting in BSC ON ON Description ON: PDH phase lock mode OFF: SDH phase lock mode ON: stratum-3 clock OFF: stratum-2 clock

3)

Indicator on GCKS
Color and normal state Meaning and description

Indicator

RUN

Red, flashing once communication is normal.

The RUN indicator flashes once every second when the communication is abnormal. The normal communication depends on the correct settings of the DIP switches. GCKS communicates with SLT or ALM with low baud rate when there is an SLT in the clock frame or there is a clock frame in the independent C&C08B standalone exchange. If the RUN indicator flashes quickly after GCKS is powered on, first check the DIP switches on the GCKS.

every second when the communication is normal, 4 times every second when the

ACT F0

Green Green, OFF when the reference source is normal

ON when the GCKS is active and OFF when the GCKS is standby. Indicator for the status of the external reference source selected. ON when the reference source is abnormal, On when the reference source is normal, flashing when the software is recapturing the reference source, OFF again when the reference source is locked. If F0 is ON after GCKS is powered on, check to ensure the reference source is correctly accessed to the GCKS. There can be six types of reference source to be accessed. Seen from the back of the backplane, J1 and J2 are the input terminals for 2048kbit/s reference source, J3 and J4 are the input terminals for 2048kHz reference source. Under locked state (MOD indicator flashes slowly. Refer to the description below), when F0 indicator flashes, GCKS is re-capturing the reference source and it will be OFF again after it locks the reference source. If F0 flashes frequently, check if SDH mode is required. For F0 flashing under other modes, check the quality of the reference source accessed.

F1

Green, OFF when the board works normally

OFF when the system works normally (including VCXO, DDS, 88915). If F1 on the GCKS is ON, GCKS fault occurs (including VCXO, DDS AND 88915 fault). Normally GCKS will be switched over automatically (if it is standby, no switchover will be

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

Indicator

Color and normal state

Meaning and description

performed). Maintenance personnel shall replace the faulty board timely according to the status of other indicators. LOF Green, OFF when the board works normally ON when the 88915 is out of lock. Under this case, the board will be automatically switched over (if it is standby, then no switchover will be implemented). Due to 88915 out-of-lock, the clock signals (frequency and amplitude) output from the board will be abnormal, so the maintenance personnel shall replace the board timely. DDS Green, OFF when DDS OFF when DDS output is normal, ON when the DDS components output is normal on GCKS work abnormally. When DDS is ON, automatic switchover of the GCKS shall occur (if the board is standby, no switchover will occur). The abnormal DDS components will make the clock signals output by the board abnormal (frequency and amplitude). DDS output abnormal is most probably caused by the inaccuracy of the reference source. Therefore, first check the reference source. If the reference source is normal, replace the board timely. LOCK Green, OFF when 88915 is normal CLK Green, OFF when 58274 is normal ON when 88915 is out of lock. The meaning of LOCK indicator is completely the same as that of LOF indicator. OFF when the time chip 58274 has calibrated the time and works normally. Otherwise, it flashes. The time chip 58274 in the C841CKS provides time to the switch, but the initial time shall be configured on the BAM. CLK indicator is OFF when 58274 works normally. If no initial time has been configured at the BAM, or 58274 chips work abnormally, CLK indicator will flash once every second. R8K0 Green,ON when R8K0 is selected The 8kHz reference source from the trunk. There are altogether 6 reference source indicators on C841CKS. When the external reference source is selected, its corresponding indicator will be ON. Otherwise, the corresponding indicator will be OFF. R8K0 is default reference source with highest priority (unless other reference source has been configured with higher priority than R8K0 on the BAM). As long as R8K0 is available, it will be configured as the default reference source. If it is unavailable, select R8K1 as the default reference source. By analog, the rest can be selected as the default reference source when all the reference sources before it in numbering are not available. If the active reference source is not available after GCKS is powered on, F0 indicator will be ON and the indicator for the active reference source will also be ON

Troubleshooting Manual M900/M1800 Base Station Subsystem

Chapter 5 Troubleshooting for Clock

Indicator

Color and normal state

Meaning and description

(R8K0 by default). If stratum-3 clock is configured for GCKS (by setting SW3.5 as ON or configuring it on the GMPU), GCKS can capture suitable reference source as active. Its stratum-2 clock will be configured by the GMPU. The active reference source states (normal or abnormal) are indicated by F0. REFA Green, OFF when the clock deviation is normal ON when the clock deviation is too large and OFF when the clock deviation is normal. REFA indicates the clock deviation when the clock is under holdover or free-run state, and it indicates the output of clocks under fast pull-in or locked state. REFA will be ON when the output frequency deviation is bigger than 0.4ppm or 4.6ppm respectively under the case that stratum-2 clock or stratum-3 clock is configured to GCKS. Only when the GCKS is in locked state, That frequency deviation check would be performed to the reference source. If the deviation is detected too big, GCKS will enter holdover state, and it returns into locked state when the reference source resumes normal. MOD Green OFF: free run (just powered on/the reference source is abnormal after fast pull-in) Flash quickly: fast pull-in (quickly lock the reference source) Flash slowly: locked (normal) ON: holdover (the reference source is abnormal after being locked) +12V Green, ON when the 12V power supply is normal 12V power supply indicator. OFF when it is normal. +12V is the power supplied to the OCXO on GCKS. If the 12V power supply is abnormal, there will be no output from the OCXO and the GCKS cannot work normally.

V. Introduction to BSC clock data configuration Table 1.1 Tables required to be configured for BSC clocks
Table name [Clock description table] [AM_CKS clock configuration table] Function Describes the clock source of the GNET Describes the work mode selection of the clock module

For multi-module BSC, the two tables in the above table are required for BSC clock data configuration. [Clock description table] configures the clock source of GNET. For multi-module BSC,

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Chapter 5 Troubleshooting for Clock

select hardware selection (module B/C2K network) and select clock frame clock (B independent office) for C&C08B standalone exchange BSC. [AM_CKS clock configuration table] configures the stratums and reference sources of the clock. [Select clock reference source] There are 3 categories, 6 types of clock reference sources, i.e., 8kHz differential signals 8K0 and 8K1, 2Mbit/s E1 signals 2MB0 and 2MB1, 2MHz TTL signals 2M0 and 2M1. Usually 8kHz differential signals are used. Generally all are selected. [Configure the priority of the reference source] Usually the priority level for reference source selection from higher to lower is 8K0, 8K1, 2MB0, 2MB1, 2M0 and 2M1. Generally all are selected. [Select the active clock after power on] Select the GCKS first used after the clock frame is powered on. Usually the active GCKS0 is firstly selected. [Set clock stratum] For GCKS combines the stratum-2 and stratum-3 clocks, this parameter is designed. Usually stratum-2 is selected for MSC and HLR, and stratum-3 for BSC. [Set clock phase lock mode] Select the PDH mode. [Select clock module work mode] Usually automatic adjustment mode is selected. Controlled mode is selected only for commissioning and clock network access acceptance test.

VI. Troubleshooting for BSC clocks 1)


Check indicators on GCKS Note especially the state of MOD and REFA indicators during the normal operation of GCKS. If the MOD indicator flashes slowly, it means GCKS is tracing normally the MSC clocks. If the MOD indicator is OFF, it means the GCKS is working under free-run mode (usually the free-run mode is not taken unless when the frequency deviation of the clock reference source obtained from MSC is too big). If the MOD indicator is in the states other than ON and OFF, it means the GCKS is working abnormally. In addition, if the REFA indicator is ON, it means the frequency deviation of the GCKS output clock is too big. Check the status of F0 indicators. If the F0 indicator is ON, it means the reference source is abnormal. If the F0 indicator is OFF, it means the reference source is locked. If the F0 indicator is flashing, it means the software is now tracing the reference source. When CLK indicator is ON, it means there is communication fault between GCKS and GMPU.

2)

Query on the maintenance console (a) Query whether GCKS is faulty or abnormal on the maintenance console. (b) Query the state of the clock source by selecting the menu [Control options/ /GCKS Board Control/Query Clock Source State] Select the menu above to query the state of the clock source. Note that the frequency deviation queried on the maintenance console is not accurate enough.

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Chapter 5 Troubleshooting for Clock

Therefore, usually the average value of multiple frequency deviations queried on the maintenance console is taken for reference. (c) Query the work state of GCKS by using the right-key menu on the maintenance console.

3)

Query clock-related alarms on the alarm console Query whether there are clock-related alarms on the alarm console, such as Clock reference source abnormal, Clock configuration data error, BTS 8kHz clock alarm, 13MHz clock out of lock, DDS control data abnormal, Clock reference source switchover and GCTN clock fault alarm etc.

4)

Check related components with meters The most commonly used test instrument for clocks is frequency meter. The commonly used frequency meter is HP53132A, used to measure the frequency accuracy. Oscillometer is used to check whether the waveforms of the clock signals are deformed and whether the phases are normal. Clock test can be performed at MSC side, BSC side and BTS side. Refer to the BSC clock test point below for clock test accuracy requirement. Usually the clock test follows a process below.

5) 6) 7) 8) 9)

First test whether the clocks output from the BSC clock frame are accurate. If the BSC clocks are accurate, test the clocks at BTS side. If the BSC clocks are not accurate, test the clock at MSC side. If the clock at MSC side are also inaccurate, test the clock reference source of MSC. If the MSC clocks are accurate, test whether there are faults on the clock transmission path between MSC and BSC.

VII. BSC clock test point 1)


Output 2MHz clock in GCKS Test instrument: frequency meter Test point: 2MH-OUT test point on the backplane of the clock frame, J16 in the Figure 1-4. This is the most commonly used clock test point and it exists in the clock frame of both MSC and BSC.

Grounding point: coaxial shield layer of the clock frame can be used as the grounding point. Test requirement: Stratum-2 clock is adopted at the MSC side and its clock accuracy should be f/f1E-8. Stratum-2 clock is adopted at the BSC/BTS side and its clock accuracy should be f/f5E-8. Therefore, the frequency deviation allowed at the MSC side is 2048000.000 1E 8 = 0.02Hz. And the frequency deviation allowed at the BSC/BTS side is 2048000.000 5E 8 = 0.1Hz. If there is too big frequency deviation, check whether the reference source, GCKS and CKB are normal.

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See Figure VII.1 for 2MHz test point.

JC2 JC1 8K08K0+


8K18K-IN

8K1+

2MH-OUT1

J16

Figure VII.1 2MHz clock output from the backplane of the clock frame 2)

8kHz reference source accuracy on the CKB of the clock frame Test instrument: Frequency meter Test point: It depends on the reference source selected, as shown in Figure 1-5. Grounding point: The GND point in Figure VII.2 is recommended, or the coaxial shield layer of the clock frame can also be used as the grounding point. Test requirement: The allowed frequency deviation of the 8kHz reference source at the MSC side is 8000.000 1E 8 = 8 1E 5 Hz

Take the 8kHz clock reference source as the example.

The allowed frequency deviation of the 8kHz reference source at the BSC/BTS side is 8000.000 5E 8 = 4 E 4 Hz

Figure VII.2 Test point for 8kHz clock reference source on CKB 3)

Clock test at the back of MSM Test instrument: Oscillometer Test point: As shown in Figure VII.3, connect the oscillometer on the upper part of pins at the back of MSM on TCB to test the 8kHz, 2MHz and 4MHz clocks. Grounding point: The GND points in Figure VII.3 are recommended.

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Test requirement: The waveform is normal.

In addition, to test the accuracy of the 8kHz clock reference source, lead the MSM Tx E1 cables to the test TMU to test the 2MHz clocks extracted by the TMU. The accuracy requirement is the same as that in testing the clocks at the back of CKB.
Pin in Up Socet of MSM Backplane 2M4M8KA 25 26 27 B C GND 2M+ 4M+ 8K+ GND GND

Figure VII.3 MSM clock signal test point 4)


Clock accuracy at the back of GCTN Test instrument: Oscillometer Test point: As shown in Figure VII.4, connect the oscillometer on the upper part of pins at the back of the backplane of corresponding GCTN to test the 8kHz, 32MHz and 4MHz clocks (two groups for each).

Grounding point: The grounding points in Figure VII.4 are recommended. Test requirement: The waveform is normal.
Pin in Up Socet of CTN Backplane A 45 B C GND 32M0 8k 0 4M0 GND GND

32M1 8k 1

4M1 46 47

Figure VII.4 Test points for the clock signals on the backplane of GCTN 5)

GSNT clock accuracy Test instrument: Oscillometer Test point: As shown in Figure VII.5, connect the oscillometer on the back of

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Chapter 5 Troubleshooting for Clock

backplane of corresponding GSNT to test the 8kHz and 32MHz clocks (two groups for each).

Grounding point: The GND points in Figure VII.5 are recommended. Test requirement: The waveform is normal.
SNT Backplane A 4 GND 8k 0 8k 1 34 35 32M0 32M1 B C

Figure VII.5 Test points for the clock signals on the backplane of GSNT

5.2.2 Fundamental Knowledge of BTS Clock System


BTS clock system performs radio link time division and radio frequency calibration function in GSM system. It plays an important role in the normal service implementation of GSM system.

I. BTS reference clock


When BTS clock reference source comes from BSC, the BTS is connected to the BIE of the BSC through the E1 cables of the BIU (BTS Interface Unit). BIU selects and processes one channel of clocks among the clocks extracted from E1 interface line, then takes it as the reference clock for the MCK module of the BTS high-precision clock. Under some cases, BIU can also provide the input for the external reference clocks. It selects one channel of clocks from the two channels of clocks it extracts from the E1 as the reference source clock for MCK module. The deviation of the clock is required to be no more than 0.05ppm.

II. BTS system clock


The OXCO, frequency divider, frequency verification unit, CPU and D/A in the MCK module comprises a closed-loop frequency calibration system to automatically trace the reference source input and provide the BTS high-performance 13MHz reference clock, as shown in Figure II.1.

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Reference source

Chapter 5 Troubleshooting for Clock

Phase discrimination

CPU

D/A

OCXO

System clock

System clock

Frequency division

Figure II.1 MCK module phase-locked loop


All clock signals used by the BTS are generated by the 13MHz signals. MCK module can decide the precision of the external reference signals, automatically pull in and lock the reference clock signals and filter their jittering so that the clock signals output can have high frequency precision and stability and can work under free-run or holdover state when the external reference clock source gets lost. There are two BTS clock software versions currently in service, V 0407 and V0529. Their algorithms are not the same. For V0407, when the phase discrimination deviation is less than 4Hz, the clocks will trace and lock the reference clock. Otherwise, they will not trace and lock the reference clock and they stay in free-run mode. For V0529, the clocks always trace and lock the reference source. MCK module has three phase lock states, free-run, pull-in and locked. Free-run state occurs under the following scenarios:

When the reference source jitters terribly and cannot stay stable for the clocks to pull in. When the reference source gets lost, MCK will enter free-run state immediately no matter what state it is in.

13MHz clock out-of-lock alarm will be reported under both the above scenarios.

When the reference source is set as the internal clock on the local MMI, the MCK module will be forced into free-run state.

Pull-in state occurs under the following scenarios.

When the reference source jittering is less than 4Hz (BTS3X) or 5Hz (BTS3001C) under free-run state, MCK module will enter pull-in state. When the clock deviation frequently exceeds the security range under the locked state, MCK module will enter pull-in state.

The locked state occurs under the following scenarios.


The 13MHz clock deviation has been less than 0.2Hz for long time; the MCK module will enter locked state.

III. The generation of BTS system clock signals


GSM system is a TDMA (Time Division Multiple Access) system, i.e., the multiple access function is accomplished through time division. Both the TDMA principle and GSM05.10 specification regulate that four signals are required for the timing at the radio interfaces, FCLK (Frame Clock), FN (Frame No.), TSCLK (Timeslot Clock) and OBCLK (Octet bit clock). As defined in GSM specification, system clock signals can be generated through the frequency division of the master clock of 13MHz. Among the clock signals, OBCLK is the sixth frequency division of the 13MHz, i.e., 13 6=2.16MHz. The FCLK, OBCLK

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and SREF signals are aligned with the rising edge of the 13MHz clocks (10-20 ns delay allowable). SREF: Frequency 13MHz/4=3.25 MHz, period 307.7 ns, duty ratio 50% OBCLK: Frequency 13MHz/6=2.167 MHz, period 461.5 ns, duty ratio 50% FCLK: Frequency 13MHz/6/10000=216.7Hz, period 4.615 ms, duty ratio 50% 13MHz: Frequency 13MHz, duty ratio 50% The period relationship between clocks of different systems is as the following: 1 FCLK=8TSCLK 1 TSCLK=156.25 BCLK=1250 OBCLK

IV. The calibration of 13MHz clocks


Because the frequency dispersion of the 13MHz OCXO is rather large in actual manufacturing, the 13MHz output frequencies of different boards differ greatly. Therefore, to ensure an accurate 13MHz reference clock for each board, all the 13MHz clocks are required to be calibrated respectively before the boards start to work. In addition, the 13MHz clocks are required to be calibrated once every year to avoid the 13MHz clock deviation due to clock aging.

1)

Required equipment and environment

One frequency meter, one serial port communication cable and MMI BTS maintenance system.

2)

13MHz clock calibration process Check to ensure the board is in normal service (warm-up end). Connect the frequency meter to the board 13MHz clock port, and the serial port communication cable to the MMI BTS maintenance system control console.

Start MMI control, obtain administration authority and complete the board configuration. Select board management and clock configuration item. Select Internal clock in clock configuration interface, adjust the default DA control value so that the difference between the 13MHz value on the frequency meter and the actual 13MHz is controlled within 0.1Hz.

Select store to Flash Memory and press <OK> in the [CLK configuration] interface. Note: Press Ctrl + Alt + F to perform clock hardware parameter configuration. Exit the configuration item and complete the 13MHz clock calibration. The clock system principles for all Huawei BTS series are basically the same. To get a comprehensive understanding of Huawei BTS clock system signal flow can help a lot for clock system troubleshooting.

V. Huawei BTS clock system signal flow 1)


BTS30 clock system signal flow

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Matching

BTS Wring2

JP3

U5 U7

U6 U8

JP1

SIX TRX JP3

Wring3

TRB

TDU Board
Wring1 BTS
JP4
U2 U4 U1 U3

Wring4
JP2

CMB
JP3

TMU

Figure V.1 BTS30 clock system signal flow


BTS30 clock system signal flow is illustrated in Figure 5-10. The path in the major cabinet is TMU CMU (JP3) TDU (JP2) TDU (JP4 and JP3 Extension cabinet) JP1 TRB (JP3) 6 TRXs in the local cabinet. During the path, signals might pass four wiring points: wiring 1 and wiring 2 (to the extension cabinet), wiring 3 (TDU to TRB) and wiring 4 (from the CMB of the major cabinet to the TDU). The path in the major cabinet is TDU (JP3 or JP4) TDU (JP1) TRB (JP3) the 6 TRX in the local cabinet. During the path, signals might pass three wiring points: wiring 1 and wiring 2 (to the major cabinet and next level of extension cabinet), wiring 3 (to TDU and TRB). The signal flow of BTS312 is similar to that of BTS30. Clock signals are forwarded via TDU.

2)

BTS3001C clock system signal flow

Because BTS3001C cabinets are encapsulated and not allowed to be opened in the field, only clock source and operation problems, no internal signal flow, are described here.

VI. Board indicators of BTS series 1)


Indicators of clock-related boards in BTS3X series

Table 1.1 TMU indicator


Indicator PLL Color Green Meaning Phase discrimination indicator Description ON: free run Flash quickly (4 Hz): pull-in Flash slowly (1 Hz): locked OFF: abnormal Normal state Flash slowly (1 Hz)

2)

BTS3001C clock-related indicator

There is no clock-related indicator in BTS3001C.

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VII. Huawei BTS series clock test points 1)


BTS3X series

The T2MHz and 13MHz test output in TMU is illustrated in Figure VII.1.

PWR RUN LI1 LI2 LI3 LI4 M/S PLL


DBG

T2M FCLK T13M

MMI

Figure VII.1 TMU clock test point 2)


BTS3001C BTS3001C test points are illustrated in Figure VII.1. The 13MHz output point is 13MCLK, and FCLK output point is 2M (output shift is performed by executing custom commands).

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5.2.3 Specifications about BTS Clock System


The requirement about GSM BTS frequency accuracy in GSM specifications is as the following. The frequencies of radio part and baseband part of the BTS must derive from the same signal source. For BTS of any type, no matter whether they support slow rate FH (Frequency Hopping), the absolute frequency error of their transceivers and the relative frequency error between transceivers must be less than 0.05ppm under all test conditions.

5.3 Trouble Handling


5.3.1 Trouble Handling for BSC
I. Trouble handling for reference source 1)
Description

13MCLKF PWRUNACTMODLI POWER

OI
Figure VII.2 BTS3001C O&M cavity (REV.C)
F0 indicator is ON or flashing after GCKS enters normal service. Clock reference source abnormal and Reference source replacement alarms are displayed on the alarm console. Sometimes most of the BTSs clock are out of lock.

ASUO&M S3 MASTER LSB

ON F SLAVE

MSB SLAVE MI

2)

Introduction to indicators

F0 indicator indicates the state of the reference source. OFF: Reference source unavailable and GCKS in free-run state Flash quickly: Reference source available, GCKS in fast pull-in state for about half an hour. Flash slowly: GCKS in locked state (normally working state) ON: Reference source gets lost when GCKS is in locked state, GCKS enters holdover state.

3)

Analysis Remove the cables for the 8K0 and 8K1 reference sources from E3M and check if there are alarms related to reference source and if the BTS has locked the clocks of BSC.

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If after the cables are removed, reference source alarms disappeared and the BTS normally locks the clocks of BSC, reference source fault can be confirmed.

If there is frequency meter available, test the deviation of the output 2MHz clocks in the clock frame before the cable removal and after the cable removal. If the output clock deviation is large before the cable removal, but normal after the removal, reference source fault can be confirmed.

Check board indicator

When F0 indicator is ON, no reference source is available. When F0 is flashing, the reference source is not stable.

4)

Handling process Check whether the cables are correctly and reliably connected. Note that 8K0 and 8K1 come from different offices and are connected to different sockets (JC1 and JC2). IF possible, replace clock input cables to remove the problems caused by the clock input cable fault.

If the reference source fault is confirmed, take the following steps for troubleshooting.

Check the clock generation channels in E3M and TCSM frame. Connect the clock access cables to other E3Ms and TCSM frames to check whether there is E3M or TCSM frame fault. If there is, check whether the E3M interfaces are damaged or whether TCSM frame is not in normal service. Replace E3M or the DRC on the back of the backplane.

If the reference source fault still cannot be removed, test in sequence the MSC CKS output clock, MSM clock and the 8kHz reference source clock input from the BSC CKB.

If the MSC clocks are not accurate, check the reference source and the operating status of the clock frame of the MSC.

If the MSM clock is not accurate, check the E1 cables between BSC and MSC. If there is transmission between BSC and MSC, the transmission exerts great impact on the clocks and has to be tested.

II. Trouble handling for the clock frame 1)


Components of the clock frame

The clock frame is composed of GCKS, CKB and PWC. There are two GCKSs, working in active/standby mode in slot 4 and slot 6.

2)

Description

On the maintenance console, GCKS is displayed red and GCKS indicator works abnormally. Clock-related alarms are displayed on the alarm console.

3)

Analysis

The most probable causes for clock frame fault is GCKS or CKB fault (including DIP switches error). When the above scenario occurs, if the fault is removed after GCKS replacement, check whether the DIP switches are correctly set. If the DIP switches are correctly set, it can be confirmed that the GCKS is faulty. Replace the corresponding GCKS. After GCKS replacement, if the fault still exists, remove the cables for the two

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reference sources in the clock frame and test the CKB output clock (including 2 MHz, 4 MHz, 8 kHz and 32 MHz). If the CKB output clock is abnormal (the waveform of the fault is difficult to obtain and the sampling will be long by using oscillometer), CKB must be faulty. Replace CKB.

III. Trouble handling for the cables 1)


Clock-related cables

(a) Maintenance cables Maintenance cables are used to connect GMCCM and GCKS. GMCCM performs O&M to the two GCKSs through 2 serial ports. One end of the maintenance cable is connected to JB33 on C821MCB (it is inserted from the first pin on the top). Another end of the cable has two connectors, one 4-core connector and one 2-core connector. The 4-core connector is connected to JB21 on CKB (inserted in the pins five pins above the bottom) and the 2-core socket is connected to JB3 on CKB (inserted from the first pin on the top). (b) Clock cables There are two types of clock cables. One is the clock cable for synchronization (differential), which is connected to the fifth port at the back of E3M and inputs synchronization clock source to the clock frame. Another is the clock cable used to transmit the two sets of clocks (32MHz, 8kHz and 4MHz; 32MHz and 8kHz) output by the clock frame to the GCTN and GSNT via corresponding backplane.

2)

Analysis

On the maintenance console, GCKS is displayed red, GCKS CLK indicator flashes slowly and Clock reference source alarm is displayed on the alarm console. The trouble cannot be removed even after GCKS replacement. The F0/REFA indicator on the GCKS is ON, and it might indicate reference source cable fault. GCTN clock fault and GSNT clock fault alarms might be displayed on the alarm console, but no other correlated alarms occur.

3)

Handling process

When GCKS is displayed red, GCKS CLK indicator flashes slowly and the trouble cannot be removed after GCKS replacement, replace the maintenance cables. When Clock reference source fault alarm is reported and the F0/REFA indicator on GCKS is ON, the reference source cables might be faulty. Replace the reference source cables. When GCTN clock fault and GSNT clock fault alarms, but no correlated alarm, are displayed on the alarm console, the CKB output clock cable might be faulty. Replace the CKB output clock cable.

5.3.2 Troubleshooting for BTS


I. Troubleshooting for the reference source 1)
Description

Alarms 13MHz clock out-of-lock, BTS BSIC cannot be unlocked and the cell handover success rate drops, but no other alarms, are reported.

2)

Probable causes

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Refer to Table 1-2.

3)

Handling process

Step 1 On the local MMI maintenance console, check whether the BTS MCK module clock is in free-run state or fast pull-in state. Observe and record the D/A value in the board information displayed. Step 2 Test and record the jittering deviation of the 2MHz output clocks in different BTSs. The jittering deviation within a short time frame should be in the MCK module tracing range, i.e., within +/-5Hz or +/-4Hz. Note that custom messages for clock signal switchover has to be sent through the local MMI maintenance console before the test of 2MHz output clocks in BTS3001C. D4-00-FF-FF-FF-81-00-FF-02-72- [00-FCLK, 01-2MHz] Step 3 Test the BTS 13MHz output clocks and write down the value. Step 4 If the BTS 13MHz output clock is not accurate, set the BTS clock mode as internal clock mode. Adjust the BTS D/A value to enable the BTS enter locked state according to the deviations of the 13MHz clocks. Step 5 If BTS 13MHz output clock is accurate, 13MHz clock out-of-lock might be caused by the reference source fault, which probably is incurred by transmission or BSC clock fault. Step 6: Check whether 13MHz clock out-of-lock occurs to other BTSs of the same BSC. Check whether the 2MHz clock of the BSC is accurate and normal. Step 7 If the BSC clock is accurate, check whether other TS abstraction equipment exist on the transmission channel and whether the transmission equipment clock system is normal.

II. Troubleshooting for field operation errors 1)


Description

The alarms 13MHz clock out-of-lock alarm, BTS BSIC cannot be unlocked, Cell handover success rate drops, but no other alarms, are displayed.

2) 3)

Probable causes Handling process

Refer to Table 1-2. Step 1 On the local MMI maintenance console, right click the MMU and observe whether the clock state in the board information displayed is free-run. Write down the D/A value displayed. Step 2 Set the BTS clock mode as the internal clock mode, test the 13MHz clock output by the BTS with the frequency meter and observe whether the 13MHz output meets the specification requirement. Step 3 If errors occur to the 13MHz clock output by the BTS, manually adjust the D/A value and observe whether the 13MHz output clock varies accordingly. Step 4 If D/A value can be successfully adjusted, it can be confirmed that the errors of D/A value are causes by BTS clock aging or operation mistakes. Re-adjust the D/A value corresponding to the 13MHz BTS. If the adjustment of D/A value cannot according adjust the 13MHz output frequency, boards must be faulty. Replace the boards.

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Detailed troubleshooting measures: under the internal clock mode, adjust the D/A value so that the BTS can output accurate 13MHz clocks and save the D/A value in the Flash Memory of the BTS. Then reset the BTS clock work mode as the external clock mode.

III. Troubleshooting for cables 1)


Description

Clock-related alarms and phase-locked loop alarm occur to the TRXs in all the slots. Repeated loading, TRX communication alarm and removal report occur to the TRXs of all slots. No alarms occur to TMU. TDU indicator and DIP switches are normal.

2) 3)

Probable causes Analysis

Refer to Table 1-2. Instrument required: multimeter Step 1 According to the BTS30 clock system signal flow, check the rack cabling from the transmission source (the TMU in the major BTS) to TRB. Replace the faulty cables if there is any, and observe whether the troubles have been removed. If the troubles cannot be removed, it might be caused by board fault. Remove the board fault accordingly.

IV. Troubleshooting for board fault 1)


Description

Boards are repeatedly reset and loaded due to TMU major clock alarm, TRX frame No. (TS No.) alarm and clock alarm etc. TMU alarm and TRX alarm are most probably caused by board fault. As described in the BTS30 clock system signal flow, TMU is the source of the clock system, CMB, TRB and TDU are the parts the clock signal flow passes and the TRX is the termination of the clock signals. Therefore, TMU, TDU and CMB clock faults will lead to the abnormal working of all TRXs. The TMU fault alarm will be accompanied by TMU clock alarm Therefore, when TMU, TDU and CMB clocks are faulty, all TRXs cannot work normally. TMU fault is usually accompanied with TMU clock alarm, TDU fault will lead to the fault of all TRXs and CMB fault will also lead to TDU fault. When TRB and TRX are faulty, usually clock alarms occur to the TRXs in some slots. Usually board faults can be analyzed and located according to the system clock signal flow.

2) 3)

Probable causes Handling process

Refer to Table 1-1. There are two ways to handle board faults. One is board replacement. Another is

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clock waveform test. The second way requires oscillometer on site to help the test. Test the clock wave form segment by segment according to the clock signal flow to locate the faulty segment. The following describes the process for board replacement. Step 1 Check whether all TRXs are faulty and whether serious clock alarms occur to TMU. If yes, go to Step 2. If No, go to Step 7. Step 2 Replace the board suspected to be faulty with a normal board and observe whether the BTS can normally working. If the BTS can resume normal working, it can be confirmed that TMU is faulty. Replace the faulty TMU. If after TMU replacement, TMU major clock is removed, but TRX alarm cannot, go to Step 3. Step 3 Observe whether the configuration of the rack indicated by TDU indicator is correct. If yes, replace the faulty TDU with a normal TDU working in other racks and observe whether the fault is removed. If yes, go to Step 4. Step 4 It can be confirmed that cabling fault is excluded. Step 5 Replace CMB. Step 6 Replace TRB. Step 7 If faults of some TRXs still cannot be removed, pull put the faulty TRXs and insert them into normally-working TRX slots. Observer if faults still persists. If yes, the TRX must be faulty. If no, TRB corresponding slot or matching problem might happen. Replace TRB boards. For matching problem, pull out, then push in connectors to adjust the clock bus load so that the fault can be removed.

5.4 Examples
5.4.1 Troubleshooting Examples for BSC Clock Fault
I. Call drops during handover due to too large BTS clock frequency deviation
Description Sometimes the call dropped during handover in GSM1800 system. But the signal level was high and there was no interference. Handling process The maintenance personnel found that the BTS frequency deviation was very big according to the onsite test result. The 13MHz output frequency deviation of some BTSs reached 2.5Hz, greatly larger than the international standard 0.65Hz. 8KHZ clock alarms of many BTSs were reported on the alarm console. MSC frequently

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reported Clock software phase lock normal/abnormal alarm, which indicated the inaccuracy of the clock at MSC side. Analysis From the above description, it can be inferred that the instability of BTS clock were the major causes for call drops during handover. Therefore, the maintenance personnel re-adjusted the clock reference source of the MSC to make it stable, the 8kHz input clock error alarm disappeared and the call drop during handover disappeared.

II. BTS clock frequency deviation too big due to configuration error in the clock description table
Description In single module BSC, the maintenance personnel queried the MCK clock of the BTS and found its the frequency deviation was very big. Then tested the clock from the GCTN and found its frequency deviation was also very big. Handling process The maintenance personnel queried the data configuration and found the clock selection in the clock description table wad configured as Multi-module BSC clock load-sharing mode and the GCTN extracted clocks from GOPT. Analysis In the single module BSC, the clock selection should be configured as C&C08B standalone exchange and the GCTN extracted clocks directly from the clock frame. After modifying the configuration, the maintenance personnel tested the clocks from the GCTN and found their frequency deviation very small. They queried the MCK clocks and found the frequency deviation normal.

III. Clock fault due to cable problem from MCB backplane to FIO backplane
Description During the equipment check after an upgrading in an office, the maintenance personnel found clock system alarms were reported and the ENA indicator on GCTN0 in SCP4 was flashing quickly. Handling process The maintenance personnel at first thought it was caused by GCTN fault. But the fault could not be removed after GCTN replacement. They performed GCKS switchover and the system resumed normal. They then replace GCKS0 and switch GCKS0 over as active, but the fault still remained. After repeated verification, it was found that whenever GCKS0 is used, the alarm would be reported. But when the GCKS1 was used, the system would work normally. The maintenance personnel performed GSNT switchover clock cable plug/unplug test and inserted only one GCKS in the frame, but the fault could not be removed. Analysis In the internal cable set of the BSC, the cable from MCB to FIO backplane is disrupted, so GCTN cannot correctly select clocks after clock switchover.

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IV. BSC clock problem due to MSM fault


Description In an office, BTS2.0 was used. After BTS cutover, most of the BTSs were in fast pullin state and crystal oscillator override alarm was reported many times. Handling process The maintenance personnel queried BSC clock board and found it normal. The MOD indicator of GCKS was flashing slowly and GCKS was in locked state. They checked all the boards on the BSC maintenance console and found their state normal. Analysis After analyzing the faulty MSM, the maintenance personnel found that the matching resistance of the E1 Rx/Tx chip of the faulty MSM is damaged. They replaced the damaged resistance and the fault was removed.

V. BTS out of lock because E1 TS integrater cannot transmit the clock in real time
Description In a BSC module, 13MHz clock out-of-lock alarm was displayed at the BTS side. The TMUs of all the BTSs were in free-run state and could not lock BSC clocks. This fault can be temporarily removed by resetting GCKS but cannot be removed from its root cause. Handling process The maintenance personnel checked the E1 channels on E3M 2. They connected TS crossover equipment in one E1 channel. They replaced the clock extraction E1 port of the BSC and extracted the clocks from the E1 that did not pass the TS crossover equipment. The out-of-lock problem of the BTS was removed and the BTS started to trace its upper level clock.

VI. The reference source not available due to too small amplitude of 8k1 reference source
Description After XX BTSs cutover, most of the BTSs were found in fast pull-in state and crystal oscillator override alarm was reported many times. The maintenance personnel checked the BSC clocks and found them normal. They then checked MSC clocks and found the 8kHz 1 reference source abnormal. Handling process The maintenance personnel tested the 2MHz differential signals output from the MSM on the pins at the back of the MSM backplane with an oscillometer and a frequency meter. The square wave pulse voltage was only 68 mV and the frequency was only around 2.048MHz. Analysis The fault was probably caused by too small signal level. After tested with the frequency meter, it was 1.75MHz. After MSM replacement, the clocks resumed normal. Therefore, it can be inferred that the fault was caused by MSM problem.

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VII. Clock fault due to CKB DIP switches setting error


Description During batch GCKS replacement in the office X, the GCKS of the older version worked normally in the slot 6 of the clock frame. But it was displayed faulty after being replaced with the GCKS of the new version. Handling process The maintenance personnel checked the DIP switches on CKB and found the S4 was incorrectly set as ON ON ON OFF. Therefore it was the S4 setting error that caused the abnormal working of new-version GCKS in slot 6. Analysis Under multi-module BSC, the communication between GCKS and GMCCM adopts point to multi-point mode. Since the serial port on GCKS0 in slot 4 in the clock frame is directly connected to the serial port cables communicating with GMCCS, the setting of the DIP switches exerts impact on the serial port communication of GCKS1 in slot 6 instead of that of the GCKS0 in slot 4 in the clock frame.

VIII. Clock fault due to connection problem of clock cables and the backplane
Description In XX local network, there was no voice when calls were connected, and Group0 clock fault alarm was reported to GCTN in AM/CM (Group0 clock refers to the clock signals transmitted from GCKS0 to GCTN or to GSNT. Group1 clock refers to the clock signals from GCKS1 to GCTN or to GSNT). Handling process The maintenance personnel pulled out the active GCKS0 and performed active/standby switchover to the boards. Then the network worked normally. Analysis After test, it was confirmed that the fault was caused by the clock cable connection problem between the CKB and the group0 4MHz clock cable of GCTN 0. Replace the clock cable and the CKB, the fault can be removed.

5.4.2 Troubleshooting Examples for BTS Clock Fault


I. Clock fault because TMU13MHz clock cannot lock th external clock
Description In office deployment, The maintenance personnel found that the BSIC of A BTS could not be unlocked and the TMU of BTS A was in free-run state. In the BSC configuration data, the working state of BTS A was set as Tracing BSC clocks, but the actual state was free-run. The D/A value of TMU OXCO was 1470. Troubleshooting process: The maintenance personnel tested the T2MHz and T13MHz output of the BTS TMU with a frequency meter and found the deviation of the two clocks was very big, as given in the following.

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T2MHz T13MHz

2047996Hz 2048006Hz 12999993Hz 12999994Hz

From the above test result, the clock deviation of the T2MHz was very big and it was necessary to check whether it was poor transmission quality or the TMU 21Q554 chip problem that caused the clock deviation. The maintenance personnel selected a BTS B that was working normally in external clock mode, and then they tested the output of the T2MHz and T13MHz clocks with the frequency meter. T2MHz T13MHz 2047999Hz 2048000Hz 13000000Hz 13000000Hz

They switched the TMU of the BTS B to the BTS A and tested the clock output of TMU with a frequency meter. T2MHz T13MHz 2047993Hz 2048009Hz 13000000Hz 13000000Hz

From the above test, it can be confirmed that the transmission of the BTS B was not stable and the clock deviation was big. But the TMU of BTS B could still lock the external clocks in BTS A and output standard 13MHz clocks. Therefore, though the transmission quality was poor, it was not the cause for the free-run state of the TMU in BTS A. After switching the TMU of BTS A back, they adjusted the D/A value of the OXCO with the frequency meter. They found that the TMU could output standard 13MHz clocks and successfully locked the external clock when the D/A value was 1910. Analysis The following three conclusions can be drawn from the troubleshooting process.

1) 2) 3)

The transmission quality of BTS A is poor, but it is not the cause for the problem that the TMU cannot lock the external clock. The chips of the TMU in BTS A are not damaged, because the TMU can work normally when the D/A value is 1910. The root cause for the fault is that the deviation between the setting of the D/A value of the OXCO in the TMU of BTS A and the actual value is too big (19101470=440).

The maintenance personnel had traced the status of the TMU in BTS A for three weeks and found the value of the phase discriminator stayed around 1910 and the TMU worked normally. This means the fault has been removed.

II. Faults are located segment bu segment accoriding to the signal flow
Description In site X, TRX could not be started normally. Troubleshooting process: The maintenance personnel powered off the BTS, then proceeded in the following procedures.

1)

Replaced the connection cable between CMBJ25 and TRBJC3. But the TRX still could not be started.

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2) 3) 4) 5) 6) 7)

Replaced the TRB and the TRX could be started. But, master clock alarms were reported during the operation. Checked the DIP switches, the cables and the matching connectors of the TDU, CMB and TRB and found no error. Pulled out, then pushed in all TRXs one by one, and powered on them. But the fault could not be removed. Replaced TMU and reset the BTS X. The fault disappeared. Re-installed the replaced TMU and the master clock alarm occurred again. Therefore, it can be confirmed that the TMU was faulty. Replaced the faulty TMU with the normal one and tested the BTS X. The operating status of boards was normal.

Analysis The BTS worked normally after TMU was replaced and master clock alarm occurred to the original TMU. From the fact, it can be inferred that the TMU fault caused the TRX unable to be started normally.

III. Clock fault due to operation errors


Description 13MHz clock out-of-lock alarm was found in many BTSs in X area. Troubleshooting process: The maintenance personnel configured the 13MHz clock under free-run mode at the local end and tested the output T13M of the BTS. They found the output deviation was around 5Hz. They adjusted the D/A value and found the 13MHz clocks working normally under free-run mode. They then configured the clocks of the BTS under Tracing the upper level clock mode and found the BTS normal without any out-of-lock alarm. Analysis The fault was caused by operation errors. The default clock D/A value on the clock O&M interface was 2048, while the D/A value adjusted for the boards was between 1100 and 1600. When the user queried the interface and pressed <OK> to exit the interface, the system would start clock capturing with the default D/A value. Under this case, the output of the 13MHz clocks was around 13MHz+5Hz, 5Hz deviated from the ex-factory 13MHz. The version of many clocks in the BTS in the field was 0407, which usually gave up clock capturing of the reference clocks 4Hz deviated from the value of the 13MHz phase discriminator and adopted free-run clock mode. Thus, the 13MHz clock out-of-lock alarm was reported.

IV. Troubleshooting example 1 for faulty TMU


Description In the BTS in X area, TRX repeatedly loaded the software, TRX communication alarm, TRX micro-processor fault and frame TS alarm was also reported. Troubleshooting process: The maintenance personnel checked the output signal pulse of the 13MHz clocks of the TMU and found them intermittently disruptive. They replaced the TMU and the BTS resumed normal. Analysis

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TMU was damaged and 13MHz clocks were unstable.

V. Troubleshooting example 2 for faulty TMU


Description In X local network, the TRX stayed in downloading state after BAM reset. There were history alarms such as 2166 TRX master clock alarm and 2136, test phase-locked loop alarm, the clock of the TMU was in slave state, and to rest the TMU and TRX from the remote end failed. Troubleshooting process: The maintenance personnel found that the transmission at the local end was normal and the ALM indicator on the TRX was ON. He performed debugging on the MMI and found there was no reset hole beside the RST silk print on the handle bar. He first mistaken that the RST hole was covered by the yellow ESD label. But, he then found that the clock of the TMU was a slave clock and the soft reset cannot be performed. On the local end, there was master clock alarm and E1 local end alarm, and the TRX was still in alarm state after hard reset of TMU at the local end and the TRX repeatedly downloaded software. He replaced the TMU and the BTS resumed normal.

VI. Troubleshooting examples for BTS3001C version fallback


Description The cell handover success rate of BTS3001C microcell in X area drops sharply. Troubleshooting process: The maintenance personnel tested the 13MHz clock output deviation of the BTS with a frequency meter and found it reached around 27Hz. He checked the version of the BTS and found the version of the BTS fell back from 05.0301A to BOOT 03.0301A. He re-activated the software and the fault disappeared. Analysis After version fallback, the versions of the BTS are not matched, so deviation of the BTS clocks occurs.

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