DCIS 2004
Extended Abstracts of the
XIX Conference on Design of Circuits and Integrated Systems
Edited by
Pascal Fouillat María Luisa López Vallejo Jean Tomas
Bordeaux, France November 2426, 2004
DCIS 2004
XIX Conference on Design of Circuits and Integrated Systems
Bordeaux, France November 2426, 2004
Organized by
Laboratoire IXL  ENSEIRB  CNRS UMR5818 UNIVERSITE BORDEAUX 1
Sponsored by
La Région Aquitaine La Communauté Urbaine de bordeaux La Mairie de Bordeaux La Maison du Tourisme de la Gironde
IEEE CAS
Le Club EEA
And
ANSOFT 
CIS 
Mentor Graphics 
Coherent 
ST 
Nasa 
Foreword
On behalf of the DCIS Organizing and Program Committees, we would like to welcome you to the 19 ^{t}^{h} Conference on Design of Circuits and
Integrated Systems (DCIS), held in Bordeaux, France, November 24 ^{t}^{h} 
26 ^{t}^{h} .
The Conference aims at gathering the experts in the field of Microelectronics, and providing a forum to exchange ideas and information on industrial and research results. The 2004 edition of DCIS confirms its international impact with the contribution of 16 countries. Experts in a wide range of areas have decided to participate, leading to a very high number of submitted papers and a reviewing effort shared upon 178 reviewers. The quality of the submissions made the selection very difficult. Following the reviewers recommendations, the program committee accepted 182 papers for oral presentation at the Conference.
This year, the threeday technical program is organized in four parallel tracks and 36 sessions. Two plenary sessions take place with distinguished speakers from STMicroelectronics and the NASA to present the new challenges offered to our community by Software Designed Radio and Space Electronics. A panel session is also scheduled in order to evaluate and discuss altogether the return on experiments from European countries with our new higher educational system according to the
Bologna process. And for the first time this year, a special award will be conferred to honour the best paper from the previous edition of DCIS, in
2003.
DCIS 2004 results from the work of many dedicated volunteers: the authors of the papers, the reviewers, the session organisers, the moderators, the invited speakers, and the sponsors. We would like to thank the ENSEIRB Graduate Engineering School for providing the modern environment abreast of the scientific level of this event. We also would like to use this opportunity to express our gratitude to the members of the IXL Organizing Committee, for all the time and efforts they have offered freely for the great pleasure of our scientific community. We wish you a productive and enjoyable stay in the sweet area of Bordeaux.
Pascal Fouillat General Chairman
Maria Luísa López Vallejo & Jean Tomas Program CoChairs
III
1
Plenary Sessions
Table of Contents
2 
Software Defined Radio : Theory and Applications, Ernesto Perea (STMicroelectronics) 
3 
Space Electronics : a Challenging World for Designers, Christian Poivey & Kenneth LaBel (Goddard Space Flight Center, NASA) 
4 
Panel Discussion 
5 
The Bologna Process : Return on Experiment, Moderator: Prof. Yves Danto (U Bordeaux 1) 
6 
Exhibits 
7 
Microwind : An introduction to nanoscale CMOS cell design. Prof. Etienne SICARD, Sonia BENDHIA (INSA Toulouse) 
8 
ICEmit: Comparing simulated/measured Parasitic Emission of Integrated Circuits. Prof. Etienne SICARD (INSA Toulouse), Amaury SOUBEYRAN (EadsCCR) 
9 
Session 1a : CAD Tools and Optimisation Algorithms 
10 "BNSAT: Representing Boolean Functions in a NonCanonical Form", Joaquín Saiz(Universidad Autónoma de Barcelona), Jordi Cortadella (Universidad Politécnica de Catalunya), Lluís Ribas, Jordi Carrabina (Universidad Autónoma de Barcelona)
11 "SUSANA: a MOSMixedCircuit Simulator Using Logic/ELogic Algorithms Implemented in Python", Tiago Carrisosa , Tiago Félix , Miguel Jerónimo (INESCID/IST), José Soares Augusto (INESCID/FCULDep. Física)
12 "A Distributed Enhanced Genetic Algorithm Kernel Applied to a Circuit/Level Optimization E Design Environment", Manuel Barros (Instituto Politecnico de Tomar), Goncalo Neves (Instituto Superior Tecnico  IST/IT), Jorge Guilherme (Instituto Politecnico de Tomar), Nuno Horta (Instituto Superior TecnicoIST/IT)
13 "A CAD Tool for the Design of RTD Programmable Gates based on MOBILE ", Hector Pettenghi , Maria Jose Avedillo , Jose Maria Quintana (Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica)
14 Session 1b : Data Converter Design
15 "A New CapacitorRatio and Offset Independent Amplifier for Pipelined A/D Converters", Fernando Muñoz Chavero , Antonio Torralba Silgado , Ramón González Carvajal , Bernardo Palomo Vázquez (Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, Spain)
IV
16
"Simulationbased Highlevel Synthesis of Pipeline AnalogtoDigital Converters", Jesús RuizAmaya , José M. de la Rosa, Manuel DelgadoRestituto (Instituto de Microelectrónica de Sevilla, IMSECNM (CSIC))
17 "Digital Background Technique for Gain Error Correction in Pipeline ADCs", Antonio José Ginés Arteaga , Eduardo José Peralías Macías , Adoración Rueda Rueda (Instituto de Microelectónica de Sevilla, Centro Nacional de Microelectrónica)
18 "Mismatch Properties of MOS and Resistors Calibrated Ladder Structures", Rafael Serrano Gotarredona , Teresa SerranoGotarredona, Bernabé LinaresBarranco (IMSECNMCSIC)
19 Session 1c : SiGe Designs
20 "A multistandard SiGe Power Amplifier for GSM900/DCS/PCS/WCDMA applications.", Laurent Leyssenne , JeanMarie Pham , Pierre Jarry , Eric Kerherve (IXL Microelectronics laboratory ), Daniel Saias (ST Microelectronics  Crolles)
21 "A SiGe BiCMOS, Low Noise and Wide Band Amplifier Working at 77 K", Damien Prele , Geoffroy Klisnick , Gérard Sou , Michel Redon (UPMCLISIF), Alain Kreisler (SUPELEC LGEP), Cyrille Boulanger (CNES)
22 "A SiGe Power Amplifier with Dynamic Bias for Efficient Power Control in UMTS/WCDMA Applications", Nathalie Deltimple, Eric Kerherve (IXL Laboratory), Didier Belot (ST Microelectronics), Yann Deval, Pierre Jarry (IXL Laboratory)
23 "A 5GHz SiGe VCO for WLAN using Optimized Spiral Inductors", Amaya Goñi (Applied Microelectronics Research Institute, University of Las Palmas de Gran Canaria, Las Palmas, Spain), Sunil Lalchand Khemchandani , Javier Del Pino, Antonio Hernández (Applied Microelectronics Research Institute and Departamento de Ingeniería Electrónica y Automática, University of Las Palmas de Gran Canaria, Las Palmas, Spain)
24 Session 1d : Built In Self Test
25 "Robustness Improvement of a Ratiometric BuiltIn Current Sensor", Mikaël Cimino , Magali De Matos , Hervé Lapuyade, JeanBaptiste Bégueret, Yann Deval (IXL lab)
26 "A NonIntrusive BuiltIn Sensor for Transient Current Testing of Digital VLSI Circuits ", Bartomeu Alorda , Vicenç Canals , Jaume Segura (Universitat Illes Balears)
27 "BuiltIn Current Sensor using FloatingGate MOS Transistors for LowVoltage Applications ", Alkiviades A. Hatzopoulos , Stilianos Siskos (Aristotle Univ. of Thessaloniki)
28 "Experimental Evaluation of a Builtin Current Sensor for Analog Circuits", Roman Mozuelos , Yolanda Lechuga , Miguel Angel Allende, Mar Martinez , Salvador Bracho (University of Cantabria)
V
29
Session 2a : High Level Modeling
30 "Compact Modeling of a Magnetic Tunnel Junction using VHDLAMS" , JeanBaptiste Kammerer, Luc Hébrard (Laboratoire d'Electronique et de Physique des Systèmes Instrumentaux (LEPSI)), Michel Hehn (Laboratoire de Physique des Matériaux (LPM)), Francis Braun (Laboratoire d'Electronique et de Physique des Systèmes Instrumentaux (LEPSI)), Patrick Alnot (Laboratoire de Physique des Milieux Ionisés et application (LPMI)), Alain Schuhl (Laboratoire de Physique des Matériaux (LPM))
31 "AnalogueSynthesis Tool Development for SwitchedCurrent Systems using VHDLAMS", Nesrine Ksentini, Ahmed Fakhfakh, Mourad Loulou, Nouri Masmoudi (LETI Laboratory, ENIS, SFAX, TUNISIA), Yannick Hervé (CNRSPHASE, Strasbourg, France), JeanJacques Charlot (ENST)
32 "Modeling and simulation of phototransistors using VHDLAMS", Annick Alexandre, Andrea Pinna, Bertrand Granado, Patrick Garda (LISIF  UPMC  PARIS)
33 "Final User Oriented SOC Modeling", Sébastien Snaidero, Yannick Hervé (CNRS/PHASE)
34 "Design and Simulation of MixedMode Optical Systems for PSD Applications", Ricardo Doldán , Eduardo Peralías, Alberto Yúfera, Adoración Rueda (Instituto de Microelectrónica de Sevilla (IMSE)  Centro Nacional de Microelectrónica (CNM))
35 Session 2b : Biometric and Robotic Applications
36 "DSPbased Fuzzy Controllers: Application to Parking an Autonomous Robot", Iluminada Baturone, Francisco J. MorenoVelo, Santiago SánchezSolano (Instituto de Microelectrónica de Sevilla (IMSECNM)), Víctor Blanco , Joaquín Ferruz (Dept. Ingeniería de Sistemas y Automática. Univ. de Sevilla)
37 "Coprocessor of the Ridge Line Following Fingerprint Algorithm", E Canto, N Canyellas (URV), M Lopez (UPC), M Fons, F Fons (URV)
38 "Iris Biometrics Verifiers for Low Cost Identification Tokens", Judith LiuJimenez, Raul SanchezReillo (Universidad Carlos III de Madrid), Carmen SanchezAvila (E.T.S.I. Telecomunicacion (U. P. M.)), Luis Entrena (Universidad Carlos III de Madrid)
39 "Fingerprint Matching Acceleration in Smart Cards", Luis Entrena, Raúl SánchezReillo, Almudena Lindoso, Judith Liu (Universidad Carlos III de Madrid)
40 "Hardware Implementation of the Bresenham Line Generation Algorithm applied to µrobot Movement", Raimon Casanova, Angel Dieguez, Juanjo Lacort, Josep Samitier (Departament d’Electrònica, SIC, Universitat de Barcelona)
41 Session 2c : Industrial Applications
42 "DualPort Serial Arbiter with GSM Modules for Simultaneous Local/Remote Control of RS232based Devices", Eloi Ramon, Lluís Ribas (Universitat Autònoma de Barcelona)
VI
43
"Signal Processing Unit for River Tugboat Telemetry System", Humberto Campanella (Instituto de Microelectrónica de Barcelona IMBCNM / U. del Norte), Mauricio Pardo, Víctor Manotas, Javier Páez (Universidad del Norte (BarranquillaColombia)), Juan Carlos Niebles, David Angulo (Flota Fluvial Carbonera Ltda)
44 "A Sensorless Electronically Controlled Horn for Automobiles", M. Cesar Rodriguez, Cesar Sanz (Universidad Politecnica de Madrid), Jacinto M. Acero, Fernando Nozal (Robert Bosch España S.A.)
45 "Design of LowPower CMOS ReadOut ICs for Large Arrays Cryogenic InfraRed Sensors", Bertrand Misischi, Francisco SerraGraells (Centro Nacional de Microelectrónica  CSIC), Eduardo Casanueva, César Méndez (Indra Sistemas S.A.), Lluís Terés (Centro Nacional de Microelectrónica  CSIC)
46 "A Dynamic Current Mode Logic to Counteract Power Analysis Attacks", François Macé, FrançoisXavier Standaert, Illham Hassoune, JeanDidier Legat, JeanJacques Quisquater (Laboratoire de Microélectronique, UCL, Belgium.)
47 Session 2d : Data Converter Test
48 "Digital Diagnosis of Settling Error in SigmaDelta Modulators ", Gildas Leger (Instituto de Microelectronica de Sevilla (IMSECNM)), Adoración Rueda (Universidad de Sevilla, Instituto de Microelectronica de Sevilla (IMSECNM))
49 "Digital Sigma Delta Oscillator : Design Consideration ", Maher Jridi (Laboratoire IXL), Dominique Dallet (Laboratoire IXL  ENSEIRB), Chiheb Rebai (Institut Supérieur des arts du multimédia de Manouba), Philippe Marchegay (Laboratoire IXL  ENSEIRB)
50 "Optimal Implementation of Linear and Adaptive Filter Bank for ADC Characterization", Fahmi Missaoui (MEDIATRON Laboratory  High School of Communications TUNIS SUP'COM  Tunisie), Dominique Dallet (IXL laboratory  ENSEIRB Bordeaux 1 University), Chiheb Rebai, Adel Ghazel (MEDIATRON Laboratory  High School of Communications TUNIS SUP'COM  Tunisie)
51 "Selection of Test Techniques for HighResolution SigmaDelta Modulators", Oscar Guerra , Sara Escalera, Jose Manuel de la Rosa (IMSECNM), Eric Compaigne, Christophe Galliard (Dolphin Integration), Angel RodríguezVázquez (IMSECNM)
52 "Guidelines for the Design of a SineWave Analyzer for BIST Applications", Manuel J. Barragan, Diego Vazquez, Adoracion Rueda (Instituto de Microelectronica de Sevilla Centro Nacional de Microelectronica (IMSECNM))
53 Session 3a : Digital Signal Processing in FPGA Platforms
54 "Implementing the FFT Algorithm in FPGA Plaforms: a Comparative Study of Parallel Architectures", Miguel Angel Sanchez Marcos, Mario Garrido Galvez, Marisa LópezVallejo, Jesus Grajal de la Fuente (Univ. Politecnica Madrid)
VII
55
"An FPGA Landmine Detection System based on Infrared Images", Fernado Pardo (Universidad de Santiago de Compostela. Santiago. Spain), Marco Balsi (Università La Sapienza. Roma. Italy), Paula López (Fraunhofer Institut für Integrierte Schaltungen. Erlangen. Germany), Diego Cabello (Universidad de Santiago de Compostela. Santiago. Spain)
56 "Implementation of Optimized FFT on Stratix DSP Development Board ", Nouvel Fabienne (IETR)
57 "Comparison of Two Implementations of Scalable Montgomery Coprocessor Embedded in Reconfigurable Hardware", Milos Drutarovsky (Technical Univeristy of Kosice, Slovak Republic), Viktor Fischer (Universite Jean Monnet, SaintEtienne, France), Martin Simka (Technical Univeristy of Kosice, Slovak Republic)
58 "An implementation of a Parallel Architecture for the SelfSorting FFT Algorithm applied to IEEE 802.11a", Ainhoa Cortes, Igone Velez, Juan Francisco Sevillano (CEIT), Andoni Irizar (Universidad de Navarra), Pilar Calvo (CEIT)
59 "Optimized FPGA implementation of Trigonometric Functions with Large Input Argument", Javier Hormigo, Manuel Sanchez, Mario A. Gonzalez, Gerardo Bandera, Julio Villalba (Dept. Computer Architecture. University of Malaga)
60 Session 3b : Sensors and Smart Objects
61 "CMOS Buried Double Junction Active Pixel Sensor For HighSensitivity LowResolution Linear Arrays ", Patrick Pittet, Genaro Carillo, GuoNeng Lu, Loubna Hannati (LENAC Université Claude Bernard)
62 "An Experience on Wireless Networks for Industrial Applications", Emili Lupon, Gabriel Torrens (Departament d'Enginyeria Electrònica, Universitat Politècnica de Catalunya)
63 "Sigma Delta Based Parametrable Sensor Interface, a Design Methodology", Fellah Yasmina, Tixier Thierry, Aubert Alain, Abouchi Nacer (CPE LYON LPM)
64 "An Improved Love Wave Oscillator for Low Concentration Chemical Sensing Application", Nicolas Moll, Corinne Déjous, Dominique Rebière, Jacques Pistré (Laboratoire IXL), Roger Planade (Centre d’Etudes du Bouchet)
65 "Parasitic Hot Electron Effects in Active Pixel Sensors", Stephan Maëstre, Pierre Magnan (Supaero)
66 "RingOscillator Based Temperature Sensor for Deep Submicron CMOS Technologies", Sebastia Bota, Vicens Canals, Josep lluis Rosselló, Jaume Segura (Universitat de les Illes Balears)
67 Session 3c : Bioinspired Circuits
68 "Experiments on Electrical MFHN Neurons", Stéphane Binczak, Sabir Jacquir, Olivier Tarlet, JeanMarie Bilbault (LE2I, CNRS UMR 5158, Université de Bourgogne)
VIII
69
"A Mixed Neuromorphic ASIC for Computational Neurosciences", Sylvain Saighi, Jean Tomas, Yannick Bornat, Sylvie Renaud (Laboratoire IXL)
70 "MixedMode Class AB Neuron Building Blocks: Analysis and Real Application", Guillermo ZatorreNavarro, Nicolas MedranoMarques, Santiago CelmaPueyo (Universidad de Zaragoza)
71 "A DiscreteTime Cellular Neural Network Architecture for a PixelLevel Snake OnChip Implementation", V.M. Brea, D.L. Vilarino, D. Cabello (Dept. of Electronics and Computer Science, University of Santiago de Compostela)
72 "ChargePacket Driven MismatchCalibrated IntegrateandFire Neuron for AddressEvent Representation", Rafael Serrano Gotarredona, Bernabe LinaresBarranco, Teresa Serrano Gotarredona (Instituto de Microelectrónica de Sevilla)
73 "Digital Implementation of a Simplicial Cellular Neural Network", Pablo Echevarria, Victoria Martinez, Jose M. Tarela, Ines del Campo (Universidad del Pais Vasco)
74 Session 3d : Power Electronics : Devices and Systems
75 "Optimization of a High Voltage pChannel Transistor fabricated using a Standard CMOS Process", Amador PérezTomás, Xavier Jordà, Philippe Godignon , Miquel Vellvehí, José Millán (Centre Nacional de Microelectrònica (IMBCNMCSIC))
76 "Digital PhaseShifting for Multiphase Converters", Angel de Castro (Universidad Politecnica de Madrid), Pablo Zumel (Universidad Carlos III de Madrid), Oscar Garcia, Teresa Riesgo (Universidad Politecnica de Madrid)
77 "Electrothermal Characterization of Ultracapacitors used as Power Source in Hybrid Electric Vehicles", Walid Lajnef, JeanMichel Vinassa, Stéphane Azzopardi, Olivier Briat, Eric Woirgard, Christian Zardini (IXL)
78 "Linear Regulators for Lithium Batteries", Peter Spies, Günter Rohmer (Fraunhofer Institute IIS)
79 "Specific Drivers and Integrated 20V Regulated ChargePump for an Autonomous MicroRobot: MiCRoN", Albert Saiz, Pere MiribelCatala, Jordi Brufau, Raimon Casanova, Manel PuigVidal, Josep Samitier (Sic Lab. Electronics Department. Universitat de Barcelona)
80 "AC Current and DC Voltage Sensorless Control of Bidirectional BoostBuck Converter", Touzani Youssef, Toumalet Jean Pierre, Le Bars Pierre, Laurent Alain, Gary Francis (IUT Montluçon)
81 Session 4a : Image Processing
82 "A Study of Trade offs in Interframe Compression MPEG for a Multiprocessor Platform", Antoni Portero (Dept. Informatica Universitat Autonoma de Barcelona), Pol Marchal (IMEC ), Jose Ignacio Gomez, Luis Piñuel (DACYA U.C.M,), Francky Catthoor (IMEC), Jordi Carrabina (Dept. Informatica Universitat Autonoma de Barcelona)
IX
83
"Adviser Coprocessor for Image Compression on FPGA", Antonio Guzman, Marta Beltran (Rey Juan Carlos University)
84 "PowerAware Tuning of Dynamic Memory Management for Embedded RealTime Multimedia Applications", David Atienza (DACYA/Complutense University of Madrid & IMEC vzw), Stylianos Mamagkakis (VLSI CenterDemokritus University), Miguel Peon, Jose Manuel Mendias (DACYA/Complutense University of Madrid), Francky Catthoor (IMEC vzw), Dimitrios Soudris (VLSI CenterDemokritus University)
85 "An IIR Based 2D Adaptive and Predictive Cache for Image Processing", Stéphane Mancini , Nicolas Eveno(LIS  Laboratoire des Images et des Signaux)
86 "Real Time Smart Pixels Processing Array for Mobile Multimedia Applications", Sebastian López, Rafael Calzada, Ayoze Tejera, Jose Fco. López, Roberto Sarmiento (Research Institute for Applied Microelectronics (IUMA))
87 "Adaptation of Altera Stratix DSP Board for Realtime Stereoscopic Image Processing", Pavol Pavelka, Vincent Betheas, Viktor Fischer, Virginie Fresse (Laboratoire Traitement du signal et InstrumentationUniversite Jean Monnet)
88 Session 4b : Embedded Design & System On Chip
89 "On the Performance of ThreeState and Multiplexor Logic Interconnection for Shared Bus SoC Design", Unai Bidarte, Armando Astarloa, José Luis Martín, Jaime Jiménez, Carlos Cuadrado (Universidad del Pais Vasco UPV  Euskal Herriko Unibertsitatea EHU)
90 "Reconfiguration Control for Dynamically Reconfigurable Systems", Ewerson Carvalho, Ney Calazans, Fernando Moraes (Pontifícia Universidade Católica do Rio Grande do Sul  PUCRS), Daniel Mesquita (Universite de Montpellier II (LIRMM))
91 "A SoCbased Architecture coupled with a CMOS Image Sensor for measurements by Image Processing", Lelong Lionel, Motyl Guy, Jacquet Gérard, Bochard Nathalie (Laboratoire Traitement du Signal et Instrumentation )
92 "Simulation of a NoCbased Heterogeneous System Using Ns", Maria del Milagro Bolado Tirado, Pablo Sanchez Espeso (Microelectronics Engineering Group  University of Cantabria)
93 "A ContextSwitch Based Checkpoint and Rollback Scheme", Michele Portolan, Régis Leveugle (TimaCMP Laboratory)
94 "Cyclope: An Integrated Realtime 3D Image Sensor", Tarik graba, Bertrand Granado, Olivier Romain (LISIF  UPMC), Thomas Ea (ISEP), Andrea Pinna, Patrick Garda (LISIF  UPMC)
95 Session 4c : Analog CMOS Design
96 "High Sensitivity and Wide Bandwidth CMOS Transimpedance Amplifier for Optical Receiver Circuit", Mohamed Boutaleb Guermaz, Lyes Bouzerara (Centre de Développement des Technologies Avancées), Hamoudi Escid (Université des Science et de Technologies Houari Boumediene), Mohand Tahar Belaroussi (Centre de Développement des Technologies Avancées)
X
97
"1.5V SquareRoot Domain Magnitude Locked Loop", Carlos A. De La CruzBlas, Antonio LopezMartin, Alfonso Carlosena (Public University of Navarra)
98 
"HighSpeed HighPrecision Analog Rank Order Filter with O(n) complexity in CMOS Technology", Ramon Carvajal (Dpto. de Ingenieria Electronica, Escuela Superior de Ingenieros, Universidad de Sevilla (Spain)), Jaime RamirezAngulo, Gladys Omayra Ducoudray (Klipsch School of Electrical and Computer Engineering, New Mexico State University), Antonio LopezMartin (Dept. of Electrical and Electronic Engineering, Public University of Navarra, Pamplona (Spain)) 
99 
"A Seventh Order Elliptic CMOS Continuous Time GmC Filter for PLC applications", Juan Francisco FernándezBootello, Manuel DelgadoRestituto, Angel RodríguezVázquez (Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica) 
100 
"Tunable GmC Biquadratic Filter Operating in Moderate Inversion", Jaime RamirezAngulo (New Mexico State University), Chandrika Durbha (Biomorphic VLSI, Inc.), Antonio J. Lopez Martin (Public University of Navarra), Ramon G. Carvajal (University of Sevilla) 
101 
"FullyDifferential CMOS Current Conveyor Operating in Moderate Inversion", Antonio J. LopezMartin (Public University of Navarra), Jaime RamirezAngulo, Chandrika Durbha (New Mexico State University), Ramon G. Carvajal (University of Sevilla) 
102 
Session 4d : Radiation Effects and EMC 
103 "Analysis of Transient Fault Emulation Techniques in Platform FPGAs", Marta Portela Garcia, Celia LopezOngil, Mario GarciaValderas, Luis Entrena (Universidad Carlos III of Madrid)
104 "Analysis of input and feedback capacitances effect on low noise preamplifier performance for Xrays silicon strip detectors", Thomas Noulis, Stilianos Siskos (Aristotle University of Thessaloniki (AUTH)), Gerard Sarrabayrouse (Laboratoire d'Analyse et d'Architecture des Systemes (LAAS)  National Center for Scientific Research (CNRS))
105 "A Hardware Approach for SEU Immunity Verification using Xilinx FPGA's", Miguel A. Aguirre, Jonathan N. Tombs, Fernando Muñoz, Vicente R. Baena, Antonio J. Torralba, Leopoldo G. Franquelo (Departamento de Ingeniería Electrónica. Universidad de Sevilla), Agustin FernàndezLéon, Francisco TortosaLopez, Daniel GutiérrezGonzàlez (Data Systems Division, ESTEC/TOSED European Space Agency)
106 "Radiation Hardness Assessment of an ADC for Space Application using a Laser Test Equipment", Vincent Pouget, Pascal Fouillat, Dean Lewis, Frédéric Darracq (IXL  CNRS UMR 5818)
107 "Exploitation of the ICEM Model for Jitter Analysis in an Integrated PLL", JeanLuc Levant (ATMEL Nantes), Mohamed Ramdani, Richard Perdriau (ESEO), M'hamed Drissi (INSA Rennes)
108 "An IPBased ChipLevel EMC Modeling and Prediction Methodology", Richard Perdriau, Mohamed Ramdani (ESEO), JeanLuc Levant (ATMEL Nantes)
XI
109
Session 5a : Devices for High Frequency Circuits
110 "Integrated MOS Varactors in Accumulation Mode for RF Applications", Benito Gonzalez, Javier Garcia (IUMA. Universidad de Las Palmas de Gran Canaria), Iñigo Gutierrez, Nekane Sainz (Escuela de Ingenieros. Universidad de Navarra. TECNUN), Margarita Marrero, Amaya Goñi (IUMA. Universidad de Las Palmas de Gran Canaria)
111 "Embedded Passive Design for High Speed Circuits ", Genevieve Duchamp, Yves Ousten, Bruno Levrier (Lab. IXL  Univ. Bordeaux 1), Philippe Kertesz (Thales Airborne Systems), Steven Heytens (Rogers NV)
112 "Analysis and Applications of MOS Resistive Cells", M. Teresa Sanz, Santiago Celma, Belén Calvo, Juan Pablo Alegre (Universidad de Zaragoza)
113 "Laddertype FBAR Filter Synthesis Methodology", Alexandre Shirakawa, JeanMarie Pham, Pierre Jarry, Eric Kerherve, Elias Hanna (IXL Microelectronics Laboratory)
114 "Study of the Proximity Effect in High Q Inductors with CMOS 0.18 µm Technology", Iosu Cendoya, Nekane Sainz (Tecnun), Jaizki Mendizabal, Roc Berenguer, Unai Alvarado, Andres GarciaAlonso (CEIT)
115 Session 5b : Low Power / Low Voltage : analog circuits (1)
116 "Wireless Battery Charger Chip for SmartCard Applications", Franz Xaver Arbinger, Peter Spies, Guenter Rohmer (Fraunhofer Institut Integrierte Schaltungen)
117 "Lowpower highslewrate railtorail CMOS analog buffer", Ramón G. Carvajal (University of Sevilla), Juan M. Carrillo, J. Francisco DuqueCarrillo (University of Extremadura), Antonio Torralba (University of Sevilla)
118 "1.5V CurrentMode CMOS True RMSDC Converter Based on ClassAB Transconductors", Carlos A. De La Cruz Blas, Antonio LopezMartin, Alfonso Carlosena (Public University of Navarra), Jaime RamirezAngulo (New Mexico State University)
119 "New Lowvoltage High Performance WTA Circuits based on Flipped Voltage Followers", Jaime RamirezAngulo, Gladys Omayra Ducoudray (Klipsch School of Electrical and Computer Engineering, New Mexico State University), Ramon Carvajal (University of Sevilla), Antonio LopezMartin (University of Navarra)
120 "New LowVoltage Fully Programmable CMOS Triangle/Trapezoidal Function Generator Circuit", Megraj Kachare, Jaime RamirezAngulo (Klipsch School of Electrical and Computer Engineering, New Mexico State University), Antonio LopezMartin (Dept. of Electrical and Electronic Engineering, Public University of Navarra, Pamplona (Spain)), Ramon Carvajal (Dpto. de Ingenieria Electronica, Escuela Superior de Ingenieros, Universidad de Sevilla (Spain))
121 "LowVoltage Micropower Integrated CMOS Log Domain Filter", Antonio J. LopezMartin, Carlos A. De La Cruz Blas, Alfonso Carlosena (Public University of Navarra)
XII
122
Session 5c : SOC & Analog Test
123 "An Infrastructure and Application Specific Processor for Testing Analogue and MixedSignal SoCs", Francisco Duarte (INESC Porto), Jose Machado da Silva, Jose Alves, Jose Matos (FEUP, INESC Porto)
124 "Test Planning for MixedSignal SoCs and Analog BIST: a Case Study ", Luigi Carro (Departamento Eng. Elétrica  Universidade Federal do Rio Grande do Sul), Erika Cota, Marcelo Negreiros (Instituto de Informática  Universidade Federal do Rio Grande do Sul), Marcelo Lubaszewski (Instituto de Microelectrónica de Sevilla  Centro Nacional de Microeléctronica), Antonio Andrade Jr. (Departamento Eng. Elétrica  Universidade Federal do Rio Grande do Sul)
125 "BIST XY Zoning Detector based on Quasifloating Gate Structure", Ricard Sanahuja, Victor Barcons, Luz Balado, Joan Figueras (Universitat Politècnica de Catalunya (UPC))
126 "An SC Spectrum Analyzer for Testing Analog Circuits", Miguel A. Domínguez, José L. Ausín (University of Extremadura), Guido Torelli (University of Pavia), J. Francisco DuqueCarrillo (University of Extremadura)
127 "A Test Methodology to Compute Typical LNA Characterization Parameters", Gabriel Pinho (Faculdade de Engenharia da Universidade do Porto), Jose Machado da Silva, Helio Mendonca, Jose Matos (Faculdade de Engenharia da Universidade do Porto  INESC Porto)
128 "Hardware Requirements for Testing MS Circuits based on Multidimensional Lissajous Curves", Emili Lupon, Luz Balado, Lucas García, Joan Figueras (Departament d'Enginyeria Electrònica Universitat Politècnica de Catalunya)
129 Session 5d : RF Building Blocks
130 " Synchronous Oscillator Locked Loop: A New Delay Locked Loop Using Injection Locked Oscillators as Delay Elements.", Franck Badets, Mohamed Benyahia, Didier Belot (STMicroelectronics Central R&D Crolles)
131 "A Fully Integrated Mixer in CMOS 0.35µm Technology for 802.11a WIFI Applications", Roberto Diaz , Ruben Pulido, Amaya GoniIturri (Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Las Palmas, Spain), Sunil Lalchand Khemchandani, Benito Gonzalez (Institute for Applied Microelectronics and Departamento de Ingenieria Electronica y Automatica, University of Las Palmas de Gran Canaria, Las Palmas, Spain), Javier del Pino (Institute for Applied Microelectronics, University of Las Palmas de Gran Canaria, Las Palmas, Spain)
132 "Effect of Mismatch and Delay on the Quadrature CrossCoupled Relaxation Oscillator/Mixer", Luís Bica Oliveira, Jorge R. Fernandes (IST/INESCID)
133 "Highgain LNA in 0.18 µm CMOS Technology for a WLAN Receiver", Iñigo Adin (CEIT), Guillermo Bistué (Tecnun), Carlos Quemada, Hector Solar, Jorge Presa (CEIT), Jon Legarda (Tecnum)
134 "Microwave Low Noise HEMT Gate Mixers ", Faiza Amrouche, Rachid Allam, JeanMarie Paillot (LAIIuniversité de poitiers)
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135
136
"A 2.45GHz Low PhaseNoise CMOS ", Vincent Cheynet de Baupré, Lakhdar Zaid, Wenceslas Rahajandraibe (L2MP  Polytech), Gilles Bas (STMicroelectronics)
Session 6a : New Architectures & Rapid Prototyping and Debugging
137 "100 MHz Floating Point Processing Unit – A Feasibility Study ", Mauro Castelli, Erwin Ofner (Carinthia Tech Institute)
138 "A Linear Sorter Core based on a Programmable Register File", Lluís Ribas, David Castells, Jordi Carrabina (Universitat Autònoma de Barcelona (UAB))
139 "Rapid Prototyping Environment for CMOS Camera IC and Systems Design", Enric Pons (Universitat Autonoma de Barcelona), Jose Luis Merino, Lluis Teres (Centre Nacional de Microelectronica), Jordi Carrabina (Universitat Autonoma de Barcelona)
140 "Advances in Realtime Hardware Debugging using the UNSHADES System", J. Tombs, M.A. Aguirre Echanove, F. Muñoz, V. Baena, A. Torralba (Universidad de Sevilla)
141 Session 6b : SigmaDelta Modulator Design (1)
142 "A 330 MHz Tunable ContinuousTime Bandpass SigmaDelta A/D Converter for Direct Conversion of Radio Signals", David Bisbal, Jacinto San Pablo, Jesús Arias, Luis Quintanilla, José Vicente, Juan Barbolla (Universidad de Valladolid)
143 "A New Method for the HighLevel Synthesis of ContinuousTime Cascaded SigmaDelta Modulators", Ramón Tortosa, José M. de la Rosa, Angel RodríguezVázquez, Francisco V. Fernández (Instituto de Microelectrónica de Sevilla, IMSECNM (CSIC))
144 "Modeling AllMOS LogDomain SigmaDelta A/D Converters", Xavier Redondo (Centre Nacional de Microelectrònica, CSIC), Jofre Pallarès (Barcelona International R&D Core, CNMEpson), Francisco SerraGraellls (Centre Nacional de Microelectrònica, CSIC)
145 "A DualBand SigmaDelta Modulator for GSM/WCDMA Receivers", Ana Rusu, Babita Roslind Jose, Mohammed Ismail, Hannu Tenhunen (Royal Institute of Technology (KTH))
146 Session 6c : Analog Test
147 "Probabilistic and SimulationBased MaskedBIST Implementation" , Fernando Guerreiro (INESCID ), José Miguel Fernandes (Schindler, SA), Marcelino Santos, Arlindo Oliveira, Isabel Teixeira, Paulo Teixeira (IST / INESCID)
148 "Experimental Analysis of Transient Current Test Based on dIDD Variations in S2I Memory Cells", Yolanda Lechuga, Roman Mozuelos, Miguel Angel Allende, Mar Martinez, Salvador Bracho (Microelectronics Engineering Group (University of Cantabria))
149 "Testing of RF Systems by Zoning the Constellation Diagram", Daniel Arumí Delgado, Rosa Rodríguez Montañés, Joan Figueras (Universitat Politècnica de Catalunya)
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150
"On the Minimum Number of Measurements for Single Fault Diagnosis in Linear Circuits", Jose Soares Augusto (INESCID/FCUL  Physics Dept.)
151 Session 6d : Mixed Signal Circuits for RF Applications
152 "Digitally Programmable UHF Transconductor in Digital CMOS Technologies", Aranzazu Otin, Santiago Celma, Concepcion Aldea (Electronic Design Group.University of Zaragoza)
153 "A MixedSignal ASIC for FMDCSK Modulation", Manuel DelgadoRestituto, Antonio J. Acosta, Angel RodríguezVázquez (Instituto de Microelectrónica de Sevilla, IMSECNM (CSIC))
154 "A Multifunctional Approach of Frequency Synthesizer dedicated to the next Multistandard Smart Objects", Christophe Rougier, JeanBaptiste Begueret, Hervé Lapuyade, Yann Deval (IXL Laboratory), Angelo Malvasi (ACCO)
155 "A Local Oscillator with a Reconfigurable Direct Digital Synthesis System", João Gonçalves, Jorge R. Fernandes (I.S. Técnico/INESCID)
156 Session 7a : Analog Design Methods
157 "Optimization Design of Stacking Voltage Triplers for Capacitive Load", Ming Zhang, Nicolas Llaser, Dariga Meekhun (University of south paris)
158 "Design Considerations of a Frequency Synthesizer for a MixedSignal BuiltInSelfTest Application", Africa Luque, Diego Vazquez, Adoracion Rueda (Instituto de Microelectronica de Sevilla)
159 "Analog IC Design With A Library Of Parameterized Device Generators", Vincent Bourguet, Laurent de Lamarre, MarieMinerve Louerat (University of Paris VI, LIP6ASIM Laboratory)
160 "An Accurate Algorithm for Transistor Sizing in Analog CMOS Design", Pablo RodizObaya, Juan J. RodriguezAndina (Universidad de Vigo), Jaime RamirezAngulo (New Mexico State University)
161 "Optimizing SI Class AB Memory Cells", Mourad Fakhfakh, Mourad Loulou, Nouri Masmoudi (LETIENIS Sfax Tunisia)
162 "The Importance of Microwave Approach for High Frequency MOS Analog Designers", Gilles Petit, Richard Kielbasa (Service des Mesures, Supélec), Vincent Petit (Thales Airborne Systems)
163 Session 7b : New Synchronisation schemes and Asynchronous Circuits
164 "Secured Structures for Secured Asynchronous QDI Circuits" , Alin Razafindraibe, Philippe Maurine, Michel Robert (LIRMM), Fraidy Bouesse, Bertrand Folco, Marc Renaudin (TIMA)
165 "Definition of P/N Width Ratio for CMOS Standard Cell Library ", Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne (LIRMM)
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166
"DPA on Quasi Delay Insensitive Asynchronous Circuits: Concrete Results", Fraidy Bouesse, Marc Renaudin (TIMA Laboratory ), Bruno Robisson, Edith Beigne (CEA Grenoble), PierreYvan Liardet, Solenn Prevosto (STMicroelectronics, ZI Rousset)
167 "Four Phase Alternating Latches Clocking Scheme for CMOS Sequential Circuits", David Guerrero, Manuel Jesús Bellido, Jorge Juan Chico, Alejandro Millán, Paulino Ruiz de Clavijo, Enrique Ostua (Instituto de Microelectrónica de SevillaCentro Nacional de Microelectrónica/Departamento de Tecnología ElectrónicaUniversidad de Sevilla)
168 "A Memoryless Clock Domain Adaptation Unit IP", Roberto EsperChaín, Félix Tobajas, Francisco González, Rubén Arteaga, Roberto Sarmiento (Instituto Universitario de Microelectrónica Aplicada)
169 "Synchronization of Sequential Circuits using the Asynchronous Wave Pipelining Technique", Stephan Hermanns, Sorin Alexander Huss (Integrated Circuits and Systems, Darmstadt University of Technology)
170 Session 7c : Failure Analysis & Reliabiliy
171 "Flash Memory Cell: Threshold Voltage Sensibility to Geometry", Bertrand Saillet (STMicroelectronics), JeanMichel Portal (L2MPPolytech), Didier Née (STMicroelectronics)
172 "Modeling the Influence of Time Skew on Crosstalk Induced Delay in Submicron CMOS Technologies", Jose L Rossello, Jaume Segura (Universitat de les Illes Balears)
173 "RC onchip Interconnect Performance Revisited", Philippe Maurine, Nadine Azemard, Daniel Auvergne (LIRMM)
174 "Scalable Substrate Modeling based on 3D Physical Simulation", Sebastien Fregonese (IXL), Didier Celi (ST MICROELECTRONICS), Thomas Zimmer, Cristell Maneux, Pierre Yvan Sulima (IXL)
175 "Extraction of MOSFET Parameters Using FourierSpace Techniques ", Rodrigo Picos (University of Balearic Islands), Miquel Roca (University of Balearic Islands), Benjamin Iñiguez (Universitat Rovira i Virgili), Eugenio GarciaMoreno (University of Balearic Islands)
176 "Impact of Deterministic WithinDie Variation on the Circuit Performance in Nanoscale Semiconductor Manufacturing", Munkang Choi, SeyedAbdollah Aftabjahani, Cheng Jia, Linda Milor (Georgia Institute of Technology)
177 Session 7d : Low Power / Low Voltage : analog circuits (2)
178 "A LowDropout Voltage Regulator for Biomedical Integrated Systems", Rui Martins, Francisco Vaz (University of Aveiro/IEETA)
179 "A Lowvoltage, Low Power Widelinear Range Subthreshold OTA ", Aimad El mourabit, GuoNeng Lu, Patrick Pittet (LENAC, Université Claude Bernard  Lyon1)
180 "A Low Voltage I/O Interface for High Speed Buses in GaAs Technology", Roberto Esper Chaín, Félix Tobajas, Roberto Sarmiento (Instituto de Microelectrónica Aplicada)
XVI
181
"New Low Voltage ClassAB CMOS Unity Gain Buffer and Current Mirror", Antonio Torralba, Ramón G. Carvajal, Mariano Jiménez, Fernando Muñoz (Universidad de Sevilla (SPAIN)), Jaime RamírezAngulo (New Mexico State University, USA)
182 "New Lowvoltage Class AB/AB CMOS OpAmp with RailtoRail Input/Output Swing", MilindSubhash Sawant, Shanta Thoutam, Jaime RamirezAngulo (New Mexico State University), Antonio LopezMartin (Universidad Publica de Navarra), Ramon G. Carvajal (Escuela Superior de Ingenieros Universidad de Sevilla)
183 "A New Family of LowVoltage PowerEfficient Class AB CMOS OTAs", Sushmita Baswa (New Mexico State University), Antonio J. LopezMartin (Public University of Navarra), Jaime RamirezAngulo (New Mexico State University), Ramon G. Carvajal (University of Sevilla)
184 Session 8a : SigmaDelta Modulator Design (2)
185 "ContinuousTime SigmaDelta Modulator with Exponential Feedback for Reduced Jitter Sensitivity ", Jacinto San Pablo, David Bisbal, Luis Quintanilla, Jesus Arias, Lourdes Enriquez, Juan Barbolla (Universidad de Valladolid)
186 "Implementation of an RTZ code for feedback DAC on a SigmaDelta Modulator", Jofre Pallarès, Xavier Redondo (Institut de Microelectrònica de BarcelonaCNM, Spain), Justo Sabadell (Barcelona Branch Office, Epson Europe Electronics, GmbH), Francesc Serra Graells (Institut de Microelectrònica de BarcelonaCNM, Spain)
187 "ExcessLoop delay reduction on LowOSR HighSpeed Multibit ContinuousTime Sigma Delta Modulators", Susana Paton (Universidad Carlos III), Thomas Poetscher, Antonio Di Giandomenico, Klaus Kolhaupt (Infineon Technologies), Luis Hernandez (Universidad Carlos III), Andreas Wiesbauer (Infineon Technologies)
188 "Discrete Invariant Set Algorithm for Sigma Delta Modulators Dynamics Analysis", David Camarero de la Rosa, VanTam Nguyen, JeanFrançois Naviner, Patrick Loumeau (Ecole Nationale Supérieure des Télécommunications.)
189 Session 8b : Digital Test
190 "Optimization of Digitally Coded Test Vectors for MixedSignal Components", Ahcène Bounceur, Salvador Mir, Emmanuel Simeu (TIMA Laboratory)
191 "Improving the Efficiency of Arithmetic BIST by Combining Targeted and General Purpose Patterns", Salvador Manich, Lucas García, Luz Balado, Josep Rius, Rosa Rodriguez, Joan Figueras (DEEUPC)
192 "Automatic Verification of RTLevel Microprocessor Cores Using Behavioral Specifications: a Case Study", Ernesto Sanchez, Matteo Sonza Reorda, Giovanni Squillero (Politecnico di Torino), Raoul Velazco (TIMACMP Laboratory)
193 "Solving the State Justification Problem using MILP for RTL Specifications", H. Navarro, Juan A. MontielNelson, J. Sosa, José C. García (IUMA, Institute for Applied Microelectronics)
XVII
194
Session 8c : IPbased design
195 "Hiding Technique for Intellectual Property Protection on FPGAs", Luis Parrilla, Encarnacion Castillo, Antonio Garcia, Antonio Lloris (Universidad de Granada)
196 "Rapid Integration of IPs in System on Chips", Salim Ouadjaout (M3Systems), Dominique Houzet (IETR INSA Rennes)
197 "Block Constraints Budgeting in TimingDriven Hierarchical Flow", Olivier Omedes (CADENCE DESIGN SYSTEMS), Michel Robert (LIRMM UMR CNRS Montpellier II), Mohamed Ramdani (ESEO Angers)
198 "Flexible HW/SW Implementation of MPEG Systems using FPGA Platforms", Oscar Navas, Antoni Portero, David Novo, Jordi Carrabina, Jordi Escrig, Martí Bonamusa (Universitat Autònoma Barcelona)
199 Session 8d : Low Power Digital Design
200 "Analytical Estimation of Node Activity in Ripple Carry binary Adders", Antonio Calomarde, Antonio Rubio (Universitat Politècnica de Catalunya)
201 "Increase in Energy Consumption due to Multiple Transitions in Coupled Lines", Eugeni Isern, Miquel Roca, Francesc Moll (Universitat Politecnica Catalunya UPC)
202 "Power Characterization of RAMs. An Experimental Approach.", Javier Rellán, José L. Ayala, Marisa LópezVallejo (Departamento de Ingeniería Electrónica (Universidad Politécnica de Madrid))
203 "Optimization Protocol based on Performance Metric", Xavier Michel, Alexandre Verle, Nadine Azemard, Philippe Maurine, Daniel Auvergne (LIRMM)
204 Session 9a : Logic and Architectural Synthesis
205 "Assertion Checking of Cyclic Behavioral Descriptions", Iñigo Ugarte, Pablo Sanchez (University of Cantabria)
206 "Behavioural Synthesis for Low Power Applying Operation Transformations", Maria Carmen Molina, Rafael RuizSautua, Jose Manuel Mendias, Roman Hermida (Universidad Complutense de Madrid)
207 "Clock Cycle Length Minimization by Arrival Time Aware Scheduling", Rafael RuizSautua, Maria Carmen Molina, Jose Manuel Mendias (Universidad Complutense de Madrid)
XVIII
208
Session 9b : Communications Systems
209 "An Efficient Priority Queuing System for High Speed Network Processors with QoS Support", Félix B. Tobajas, Valentín De Armas (Instituto Universitario de Microelectrónica Aplicada (IUMA) / Departamento de Ingeniería Electrónica y Automática (DIEA)), Néstor Cruz(IUMA), Roberto EsperChaín (IUMA / DIEA), Rubén Arteaga (IUMA), Roberto Sarmiento (IUMA / DIEA)
210 "Optimizations in DVBRCS Turbo Decoder based on Trellis Structure", Jesus M. Perez Llano, Victor Fernandez Solorzano (Cantabria University)
211 "Implementation of a 2.5Gbps ATM over SDH Transceiver with Add/Drop on a VirtexII", Rubén Arteaga Mesa, Roberto EsperChaín Falcón, Oscar Tubío Araújo, Félix Tobajas Guerrero, Valentín De Armas Sosa, Roberto Sarmiento Rodríguez (Instituto Universitario de Microelectrónica Aplicada (IUMA))
212 "ITUCompliant Macrocells for Dual Tone Multiple Frequency Transmission and Reception", Arturo Purroy, Isidro Urriza (Universidad de Zaragoza)
213 "Evaluation of a PHM Scheduler Implementation", Francisco Javier GonzálezCastaño (Departamento de Ingeniería Telemática, Universidad de Vigo), Enrique SotoCampos (Departamento de Tecnología Electrónica, Universidad de Vigo), Rafael AsoreyCacheda (Departamento de Ingeniería Telemática, Universidad de Vigo), Cristina LópezBravo (Departamento de Tecnologías de la Información y las Comunicaciones, Universidad Politécnica de Cartagena), José FariñaRodríguez, Juan José RodríguezAndina (Departamento de Tecnología Electrónica, Universidad de Vigo)
214 Session 9c : System Level Design
215 "XML Specification and Tools for Automatic SoC Generation", Màrius Montón, Oriol Font, Jaume Joven (Universitat Autonoma de Barcelona), Pere Garcia (EPSON Electronics Europe), Lluís Terés (Centro Nacional de Microelectronica), Jordi Carrabina (Universitat Autonoma de Barcelona)
216 "Generic Programming with abstract parametrized components", Fernando Rincón, Jesús Barba, Juan Carlos López, Juan Pablo Rozas (University of CastillaLa Mancha)
217 "System Level Design using SystemC: a Case Study of Block Turbo Decoder", Erwan Piriou, Christophe Jego, Patrick Adde, Michel Jezequel (ENSTBretagne)
218 "ObjectOriented Hardware/Software CoSimulation Using SystemC", Ana Mª Cardells, JuanJosé Noguera (Hewlett Packard BPO Spain), Lluís Terés (Centre Nacional de Microelectrònica)
219 "Comparing Design Flows for Structural System Level Specifications facing FPGA Platforms", David Castells, Marius Monton, Ramon Pla, David Novo, Antoni Portero, Oscar Navas (Universitat Autonoma Barcelona)
220 Session 9d : Noise in Electronics
221 "Minimum Noise Figure Comparison of YParameter Based Bipolar Noise Models.", Juan Carlos Milena, Manuel Sanchez, Juan Miguel Lopez (Universitat Politècnica de Catalunya), Antonio J. Garcia (Universidad de Santiago de Compostela)
XIX
222
"Spectral Characterization of the Digital Noise", Miguel Angel Méndez Villegas, José Luis González Jiménez, Diego Mateo Peña, José Antonio Rubio Solá (Universitat Politècnica de Catalunya)
223 "On the Relation between Digital Circuitry Characteristics and Power Supply Noise Spectrum in MixedSignal CMOS IC", Miguel Ángel Méndez, José Luis González, Enrique Barajas, Diego Mateo, Antonio Rubio (Electronic Engineering Department, Universitat Politècnica de Catalunya)
XX
Conference Committees
Steering Committee
Daniel Auvergne Salvador Bracho del Pino Rafael Burriel Lluna Fulvio Corno Joan Figueras Pàmies José Epifanio da Franca Leopoldo García Franquelo Eugenio García Moreno Miguel A. Hernández y Coll José Luis Huertas Díaz Juan Carlos López López Antonio Núñez Ordóñez Emilio Olías Ruiz Michel Renovell Armando Roy Yarza Antonio Rubio Solá José A.R. Silva Matos Antonio J. Torralba Silgado Javier Uceda Antolín
LIRMM, F U. de Cantabria, E CeDInt, U. Politécnica Madrid. E Politecnico Torino, I U. Politécnica Catalunya, E Inst. Superior Técnico, P U. de Sevilla, E U. Illes Balears, E Siemens A.G. Munich, D CNM Sevilla, E U. CastillaLa Mancha, E U. Las Palmas G. Canaria, E U. Carlos III, E LIRMM, F U. de Zaragoza, E U. Politécnica de Catalunya, E U. Porto, P U. de Sevilla, E U. Politécnica Madrid, E
General Chair
Pascal Fouillat
ENSEIRB
Programme CoChairs
Maria Luisa López Vallejo
Jean Tomas
U.Politécnica de Madrid
U. Bordeaux 1
Local Organizing Committee
Stéphane Azzopardi Dominique Dallet Régis Devreese Isabelle Dufour Hervé Lapuyade Nicolas Moll Sylvain Saïghi Patrick Villesuzanne
Valérie Cauhapé Yann Deval Geneviève Duchamp Eric Kerhervé Nathalie Malbert Sylvie Renaud Angélique Tételin JeanMichel Vinassa
Local Secretariat Valérie Cauhapé Laboratoire IXL Université Bordeaux 1 351 Cours de la Libération 33405 Talence Cedex  FRANCE Tel: +33 (0) 540 002 807 Fax: +33 (0) 556 371 545
dcis2004@ixl.fr
Registration and Hotel accomodation Dominique Aurieres SUD CONGRES CONSEIL  DCIS'04 166 cours du Maréchal Galliéni  33400 Talence – FRANCE Fax : +33 (0) 556 249 948 dominique.aurieres@wanadoo.fr
XXI
Reviewers
Abouchi,N. Acosta Jiménez,A.J. Aguiar,R.L. Aguirre Echanove,M.A. Alarcón,E. Alcubilla,R. Alexandre,A. Alexandres Fernández,S. Alves,J.C. Amendola,G. Aragonés,X. Arapoyanni,A. Aubepart,F. Aubry,J.F. Augusto,J. Auvergne,D. Ayala,J.L. Azcondo,F.J. Badets,F. Ballester Merelo,F.J. Barthelemy,H. Bausells,J. Begueret,J.B. Belhaire,E. Bellido Diaz,M.J. Bota,S. Bourdel,S. Bracho,S. Burriel,R. Campo,E. Canas Ferreira,J. Capraro,S. Carmona,R. Carrera Usiabaga,A. Celma,S. Charlot,B. Chatelon,J.P. Crand,S. Dallet,D. Dejous,C. Del Rio Fernandez,R. Deltimple,N. Deval,Y. Dilillo,L. Dualibe,C. Duchamp,G. Dufour,I.
Erwin,O. Farina Rodriguez,J. Fernandez,A. Ferreiros,J. Ferrer,C. Figueras,J. Fischer,V. Fouillat,P. Garcia Franquelo,L. Garcia Moreno,E. Garda,P. Girard,P. Granado,B. Hebrard,L. Hermida,R. Hernandez,A. Herve,Y. Houzet,D. Isern,E. Izpura,I. Jacquemod,G. Kerherve,E. Landrault,C. Lapuyade,H. Levant,J.L. Leveugle,R. Levi,H. Lewis,D. Lewis,N. Linan Cembrano,G. Lopez Nozal,L.A. Lopez Vallejo,M. Lopez,C. Lopez,J.C. LopezVillegas,J.M. Lorenz,M.G. Louerat,M.M. Luxey,C. Machado da Silva,J. Madrenas,J. Mancini,S. Maneux,C. Manich,S. Marc,F. Martin,J.L. Martinez Salamero,L. Martinez,M. Mengibar,L.
XXII
Meresse,A. Mieyeville,F. Mir,S. Molina,M.C. MontielNelson,J.A. Moreno Arostegui,J.M. Moya,F. Moya,J.M. Navarro,D. Naviner,J.F. Nebel,W. Nouet,P. O'Connor,I. Olías Ruiz,E. Oliver,J. OrtizConde,A. Ousten,Y. Pérez Verdú,B. Petit,G. Petrashin,P. Pinna,A. Pissaloux,E. Psychalinos,C. Quero,J. Ramdani,M. Rebiere,D. Renaud,S. Renovell,M. Ribas,L. Ribeiro Alves,G. Rincon,F. Rius Vázquez,J. Robert,M. Roca,M. Rodríguez Andina,J.J. Rodríguez,R. Romain,O. Roy,A. Rubio,A. Rueda Rueda,A. Samitier,J. Sanchez Espeso,P.P. Sandoval Hernández,F. Santos,D.M. Santos,H. Santos,M. Sauerer,J. Silva,M.
Sinclair,D. 
Trullemans,A.M. 
Vergos,H.T. 
Stechele,W. 
Tsiatouhas,Y. 
Vidal,F. 
Taris,T. 
Vaz,J. 
Vieira dos Santos,J.M. 
Texeira,I. 
Vázquez García de la 
Villar,E. 
Toledo,L. 
Vega,D. 
Vinassa,J. 
Tomas,J. 
Velazco,R. 
Zimmer,T. 
Torres,L. 
Verdier,F. 
XXIII
Plenary Sessions
Software Defined Radio : Theory and Applications
Ernesto Perea
STMicroelectronics
A brief overview of Software Defined Radio (SDR) principle yields the required characteristics for some of the key building blocks. Although the analogtodigital converter appears to be a severe bottleneck as expected, the huge bit stream the system has to deal with generates the strongest constraints on the Digital Signal Processor. It is demonstrated that a sampledanalog signal processing approach can solve this problem – and initiates others.
Space Electronics : a Challenging World for Designers
Christian Poivey & Kenneth LaBel
Goddard Space Flight Center, NASA
Christian Poivey will address in his talk the concern of Radiation effects for the design of space electronics systems. He will describe first the radiation environment and how this environment affects electronics parts and embedded systems. A special focus will be given on CMOS devices. Then, examples of radiation effects on spacecraft will be presented. The talk will end with a short description of hardening by design methods for CMOS electronics devices.
DCIS 2004
 3 
Panel Discussion
Panel Discussion
The Bologna Process : Return on Experiment
Moderator:
Prof. Yves Danto (U Bordeaux 1)
Participants:
Prof. Olivier Bonnaud (U. Rennes 1)
Prof. Fausto Fantini (U. de Modena)
Prof. López Barrio (U. Madrid)
Prof. José Silva Matos (U. Porto)
Prof. João Paulo Teixeira (U. Lisboa)
DCIS 2004
 5 
Exhibits
Microwind
An introduction to nanoscale CMOS cell design
Etienne SICARD Professor, INSA 135 av de Rangueil, 31077 Toulouse France etienne.sicard@insatlse.fr www.microwind.org
Sonia BENDHIA Senior Lecturer, INSA 135 av de Rangueil, 31077 Toulouse France sonia.bendhia@insatlse.fr
Abstract: Microwind is a friendly windowsbased tool for designing and simulating microelectronic CMOS cells at layout level. The tool features full editing facilities, various views (MOS characteristics, 2D cross section, 3D process viewer), and a high performance builtin analog simulator. Microwind aims at illustrating the technology scale down, the major improvements allowed by nanoscale technologies, as well as main substrate options (buried layer, SOI, RF). The nchannel and pchannel MOS devices, simple/double/triple oxide, simple/doublegate, are illustrated and simulated based on BSIM4 models. Basic cells such as Inverters, logic gates, complex gates, arithmetic blocs, latches can be designed, simulated and optimized in a very efficient way with Microwind. A specific effort has been dedicated to the handling of static, dynamic, nonvolatile and magnetic memories. Furthermore, radiofrequency analog cells, such as mixers, voltagecontrolled oscillators, fast phaselockloops and power amplifiers are also illustrated by Microwind. Finally, input/output interfacing principles, electrostatic discharge protections, pad structure, and package are also covered through numerous examples. Technologies ranging from 1µm down to 65nm are supported. The tool runs on Windows 98, 2000, NT, and XP. Microwind is used in more than 500 Universities around the world and in industry training centers. The tool has proven very efficient in the illustration of CMOS technology and design principles, either for teachers during their lecture or for students realizing integrated logic or analog functions as practical training.
Figure 1: Main layout design window
Figure 2: Analog simulation (PLL)
Figure 3: 3D view of the process (90nm)
Figure 4: Tutorial on MOS device (BSIM4)
Free copies of the complete package+ manual will be available at DCIS'04.
DCIS 2004
 7 
ICEmit
Comparing simulated/measured Parasitic Emission of Integrated Circuits
Etienne SICARD INSALesia Toulouse, France etienne.sicard@insatlse.fr
Amaury SOUBEYRAN EadsCCR Suresnes, France amaury.soubeyran@eads.net
Abstract: ICEmit is a Windowsbased environment for the simulation of parasitic emission of integrated circuits. The tool consists of a dedicated schematic editor, an IBIS translator, a core activity evaluator, an analog SPICE simulator and a dedicated postprocessor. The IBIS translator gives information about the input/output characteristics and the package and supply model. The core activity evaluator translates the integrated circuit specification into a current source which aims at modeling the core switching noise and onchip decoupling. The analog simulation is performed by WinSpice, and a post processing features an immediate comparison of predicted and measured spectrum in frequency domain. ICEmit handles a set of standards for integrated circuit modeling, emission modeling and test setups. ICEmit can be downloaded from www.icemc.org. The tool has been used to modelize successfully the parasitic emission of 16bit, 32bit microcontrollers, Xilinx programmable devices as well as dedicated ASICs, within the range 1MHz2GHz.
The freeware runs on Windows 95,98, NT, XP.
Figure 1: Schematic editor window
Figure 3:IBIS loader (Xlinx VirtexII Bga 896)
Figure 2: Core activity evaluator
Figure 4: Simulated/measured emission (16bit µc)
Free copies of the package and the manual will be available at DCIS'04. ICemit has been developped within MEDEA+ "Mesdie" project A509
DCIS 2004
 8 
Session 1a
CAD Tools and Optimisation Algorithms
Wednesday nov. 24 9h00 10h00, Lacanau Room
Chairs
Lluis Ribas (U. Autonòma de Catalunya) Eugeni Isern (U. de les Illes Balears)
BNSAT: Representing Boolean Functions in a NonCanonical Form
J. Saiz, J. Cortadella*, L. Ribas, J. Carrabina Computer Science Department, Universitat Autònoma de Barcelona, Bellaterra, Spain {Joaquin.Saiz Lluis.Ribas Jordi.Carrabina}@uab.es *Software Department, Univ. Politècnica de Catalunya, Barcelona, Spain, jordicf@lsi.upc.es
M ODERN SAT solvers, which implement improved variants of the DavisPutnam algorithm, can determine the satisfiability of large CNF formulae in a few seconds. This fact has
favoured the development of noncanonical methods of representing Boolean functions. In this paper, we introduce BNSAT, a new package that implements a noncanonical representation of Boolean functions. The central idea behind BNSAT is representing a Boolean function F as a composition of small functions f _{i} . The main data structure employed in BNSAT is a cyclic directed graph with specific features, resembling a Boolean network. Each nonterminal vertex has an nvariable function f
associated to it. Functions f _{i} are represented by means of BDDs, and BDD variables are shared among several vertices. As a consequence, a BDD node can be used in the representation of the functions f _{i} of different vertices. Such reusing of BDD nodes involves a great saving of memory. Two parameters, the maximum number of fanin nodes and the maximum number of BDD nodes, control the size of the functions f _{i} . BNSAT package can compute the usual Boolean operations. The most intuitive way of doing a binary operation among two Boolean functions F _{1} and F _{2} is by operating the BDDs of the vertices that represent those functions. However, limits imposed by the aforementioned parameters can be exceeded. To avoid this problem, one of the operands (or both) can be replaced by a BDD variable. It gives rise to four different methods of implementing a binary operation. Different strategies have been studied in order to determine the satisfiability of a Boolean function F represented with BNSAT. By the time being, the strategy that best performs consists of a specific method of translation into CNF formulae in conjunction with the use of a SAT solver, Zchaff. The translation into CNF format is based on the use of ESPRESSO. We have tested BNSAT on some common combinational circuit benchmarks in BLIF format.
It can be seen that the combination of BNSAT and Zchaff outperforms the combination of Zchaff and
a direct BLIFCNF translator in most cases. In the short term, we are going to implement
Quantification Boolean Formulae, which are widely used in formal verification algorithms. Some of these algorithms (for instance, reachability analysis) will be implemented in order to explore the efficiency of BNSAT in the field of formal verification.
DCIS 2004
 10 
SUSANA: a MOSMixedCircuit Simulator Using Logic/ELogic Algorithms implemented in Python
Tiago Carrisosa (*), Tiago F´elix (*), Miguel Jer´onimo (*), J. Soares Augusto (*,**)
(*) INESCID, R. Alves Redol, 9, 1000029 Lisboa, Portugal (**) Physics Dept, Fac. Ciˆencias da Univ. de Lisboa
In this paper we describe the simulator SUSANA (”Alternative Numerical Algorithmsbased Simulator”), based on the ELogic ^{1} simulation approach and implemented in Python/wxPython. ELogic, an eventdriven simulation algorithm, traditionally used in digital MOS circuits simulation, is also suitable for simulating analogue and mixed circuits. SUSANA was applied to large digital ISCAS85 benchmark circuits. Several improvements have been added to standard ELogic, such as the implementation of a logic simulator to obtain initial conditions before starting ELogic simulation of digital circuits. The precision of simulation can be controlled by the user through the number of discrete states (voltages) allowed for the circuit nodes. The smaller the number of states, the faster the simulation but, also, in this case the simulation error becomes larger. ∆V , the voltage diﬀerence between adjacent states, controls their number. The use of a very high level programming language (Python) permitted the rapid development, test and debugging of a quite complex circuit simulator and of the associated visual input and data analysis components. Examples, results and a description of the simulation environment are presented in the full paper. The eﬃciency of SUSANA when compared to Spice, despite being written in Python, is clearly shown in table 1. In the simulation of the ALU shown in ﬁg. 1 a speedup of 12X was observed.
SIMULATOR 
TIME (s) 
REL. SPEED 
Spice SUSANA (∆V =0.25 V) 
4557 
1 
380 
12 
Table 1: ALU simulation run times in Spice and in SUSANA
The simulation of pulse propagation in a chain of 1000 inverters has shown a speedup of 168X due, in part, to the use of a digital simulator to initialize correctly the ’digital’ values.
Figure 1: Simulation of ALU C3540 with SUSANA (∆V = 0.25 V).
^{1} R. Saleh, S.J. Jou and A. R. Newton, MixedMode Simulation and Analog Multilevel Simulation, Boston, Massachusetts:
Kluwer Academic Publishers, 1994.
DCIS 2004
 11 
A Distributed Enhanced Genetic Algorithm Kernel Applied to a Circuit/Level Optimization EDesign Environment
^{1}^{,}^{2} M. Barros, ^{2} G. Neves, ^{1} J. Guilherme and ^{2} N. Horta
^{1} IPT – Inst. Pol. de Tomar Qt. do Contador – Est. de Serra 2300313 Tomar, Portugal
^{2} IST/IT  Centre for Microsystems Av. Rovisco Pais, 1 1049001 Lisboa, Portugal
Emails: fmbarros@ipt.pt, gneves@gcsi.ist.utl.pt, jorge.guilherme@ipt.pt, n.horta@ieee.org
T HIS paper presents a distributing implementation of a circuit/systemlevel optimization EDesign environment (fig.1) based on an enhanced modified genetic algorithm kernel. First, we discuss the main features of the optimization kernel such as automatic search space decomposition, premature convergence prevention procedures and the ability to optimize a broad range of circuits based on either an equationbased approach or an simulationbased approach, using Spicelike simulators. Then, a simple, inexpensive and efficient distributed processing method applied to the serial genetic algorithm is described. Finally, the achieved increase on optimization efficiency, compared to the standard genetic algorithm implementation, as well as the validity of the proposed approach, is demonstrated by a multiobjective, multiconstraint optimization of some well known circuits.
DCIS 2004
Figure 1. EDesign FrontEnd.
 12 
A CAD Tool for the Design of RTD Programmable Gates based on MOBILE ^{1}
Héctor Pettenghi, María J. Avedillo, and José M. Quintana
Instituto de Microelectrónica de Sevilla, CNM, Sevilla, SPAIN Email: {hector, avedillo, josem}@imse.cnm.es
Resonant Tunnelling Diodes (RTDs) exhibit a negative differential resistance (NDR) region in their cur rentvoltage characteristics which can be exploited to significantly increase the functionality implemented by a single gate in comparison to MOS and bipolar technologies, thus reducing circuit complexity. Because of these attractive features they are receiving much attention as device elements for circuit applications. How ever there is a wide gap between research on the device development and automatic tools to design circuits using them, which can limit the success of this emergent technology. This paper presents a CAD tool for the design of complex programmable logic blocks (able to implement a set of functions) using RTDs. Starting from a functional speciﬁcation, it generates a sized netlist implementing it. The derived circuits exploit the MOBILE operating principle but increase the logic complexity which can be implemented with a single gate by rising the number of negative differential resistance devices connected in series, and by the simul taneous implementation of functions with such structure. The tool is based on the maximization of the number of functions which are simultaneously realized (minimization of number of control variables), and in the formulation of the design problem as a mixed integer linear problem (MILP) with a suitable cost function which allows minimizing the circuit complexity in terms of device counts. From the solution, the sized circuit and the control combination for selecting each function are derived. Figure 1(a), despicts the circuit derived for a 2 input programmable gate that implements the functions NAND, OR and EXOR. Simulation results in the figure 1(b) show correct operation. The proposed tool can be useful in translating the attractive features of RTDs to the circuit level.
Vbias
1. This effort was partially supported by the EU QUDOS project IST 200132358.
DCIS 2004
 13 
Session 1b
Data Converter Design
Wednesday nov. 24 9h00 10h00, Bordeaux Room
Chairs
Dominique Dallet (E.N.S.E.I.R.Bordeaux) Josep Samitier (U. de Barcelona)
A New CapacitorRatio and Offset Independent Amplifier for Pipelined A/D Converters
F. Muñoz, R.G. Carvajal, A. Torralba, B. Palomo
Departamento de Ingeniería Electrónica, Universidad de Sevilla
T HE mismatch of ratio capacitors used in the residue amplifier of the first pipelined stages limits the resolution in highresolution pipelined AnalogtoDigital Converters (ADC). In this paper, a new
residue amplifier which is inherently insensitive to capacitor mismatch and amplifier offset is presented. Using a fourphase switched capacitor circuit, the proposed technique (shown in figure 1) senses and compensates the mismatch capacitor error.
Although other ratioindependent residue amplifiers have been proposed in the literature, the technique proposed here is, in the authors’ knowledge, the only one which allows an operational amplifier to be shared between two successive pipelined stages, providing, in addition, cancellation of the amplifier offset. Simulation results show the potentiality of the proposed technique for the design of very lowpower highresolution pipelined converters.
DCIS 2004
 15 
Simulationbased Highlevel Synthesis of Pipeline AnalogtoDigital Converters
Jesús RuizAmaya, José M. de la Rosa and Manuel DelgadoRestituto
Instituto de Microelectrónica de Sevilla IMSECNM (CSIC) Ed. CNMCICA, Av. Reina Mercedes s/n, 41012 Sevilla, SPAIN. Email: {ruizjrosamandel}@imse.cnm.es ^{*}
T HIS paper presents a toolbox for the simulation, optimization and highlevel synthesis of pipeline
AnalogtoDigital Converters (ADCs) in MATLAB. The embedded simulator uses SIMULINK Ccoded Sfunctions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPUtime up to 2 orders of magnitude as compared with previous approaches – based on the use of SIMULINK elementary blocks. Moreover, Sfunctions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioural models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a designoriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK platform by using the MATLAB engine library, so that the optimization core runs in background while MATLAB acts as a computation engine. The implementation on the MATLAB platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer
to browse through all steps of the simulation, synthesis and postprocessing of results. In order to illustrate the capabilities of the toolbox, a 0.13 m CMOS 12bit@80MS/s A/D interface for power line communications is synthesized and highlevel sized. Different experiments show the effectiveness of the proposed methodology.
^{*} This work has been supported by the MEDEA+ (A110 MIDAS) Project.
DCIS 2004
 16 
Digital Background Technique for Gain Error Correction in Pipeline ADCs
Antonio J. Ginés, Eduardo J. Peralías and Adoración Rueda Instituto de Microelectónica de Sevilla (España), Centro Nacional de Microelectrónica
IGHspeed high resolution for communications needs good performance of the analogue blocks in data
converters as well as selfcorrection/selfcalibrating techniques. In the particular case of Pipeline
ADCs, correction techniques can improve the linearity of subADCs dealing with the transition errors, but for
H
resolution greater than 10 bits, a calibration technique is still necessary. Moreover, even for lower resolutions
calibration can relax the analogue block specification, and therefore, should be considered as an additional
design variable.
There exist foreground calibration techniques that need the interruption of the normal converter operation
to start a calibration cycle. Normally, the error measurements are obtained just after power is turned on. Thus,
any miscalibration, environmental change such as temperature, power supply or component aging cannot be
overcome if the system works continuously. However, background calibration allows that, performing error
measurements during the ADC operation.
This paper presents a new digital technique for background calibration of gain errors in Pipeline ADCs.
The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration
(SUC) and the global gain error associated to the least signiﬁcant stages. This process is performed without
interruption of the conversion and without reduction of the dynamic rate. The proposed system (Fig. 1a) uses
a stage with two inputoutput characteristics depending on the value of a digital pseudorandom noise signal
N[i] to modulate the output residue of the SUC and to estimate the calibration code by an adaptive averaging
process. The proposed method introduces no signiﬁcant modiﬁcations in the analogue blocks of the Pipeline
ADCs making this technique a very promising alternative for the background calibration of the nonlinearity
associated to the gain errors due to the capacitor mismatches and limited OPAMP gain. Simulation results
(Fig. 1b) have probed the stability of the algorithm and the tracking capability for fast gain error changes con
sidering errors in both the subADC of the SUC and the backend stages.
Fig. 1. a) Schematic of the tworesidue stage ; b) Simulation results
DCIS 2004
 17 
Mismatch Properties of MOS and Resistors Calibrated Ladder Structures
Rafael SerranoGotarredona, Teresa SerranoGotarredona, and Bernabé LinaresBarranco Instituto de Microelectrónica de Sevilla (IMSECNMCSIC), Ed. CICA, Av. Reina Mercedes s/n, 41012 Sevilla, SPAIN. Phone: 34955056666, Fax: 34955056686, Email:
bernabe@imse.cnm.es.
T HE mismatch behavior of MOS and resistor based calibrated ladder structures, used in arrays of
DACs, is studied theoretically and experimentally. It is found that the calibrated DAC worst case output current standard deviation is approximately 1/3 that of its individual components. MOS experimental measurements illustrate the discussed mismatch behavior. Directions on how to design ladder DACs for a target precision are provided.
DCIS 2004
 18 
Session 1c
SiGe Designs
Wednesday nov. 24 9h00 10h00, St Emilion Room
Chairs
JeanBaptiste Bégueret (U. Bordeaux 1) JeanMichel Fournier (E.N.S.E.R.Grenoble)
A multistandard SiGe Power Amplifier for GSM900/DCS/PCS/WCDMA applications
Laurent Leyssenne, JeanMarie Pham, Pierre Jarry, Eric Kerhervé, Daniel Saias*, Didier Belot*
IXL laboratory  UMR 5818  ENSEIRB University of Bordeaux  France
*ST Microelectronics  Crolles  France
EmailAddresses: leyssen@ixl.fr  pham@ixl.fr
A N original multistandard integrated power amplifier is presented for communication systems. It consists
of two subamplifiers in parallel, each one being devoted to a specific frequency range, either the 900MHz bandwidth (GSM), or the 1700/2000MHz bandwidth (DCS/PCS/WCDMA). These circuits are to be implemented with a SiGe BiCMOS technology. Part of the challenge lies in the integration of both amplifiers on the same chip and in the reconfigurability of the PCS/DCS/WCDMA amplifier in terms of linearity, power added efficiency, and output power, via control bits. The architectures of both amplifiers are respectively described in figure1. This work was done in the framework of a complete transceiver design. That’s why some extra functionalities such as sleepmode and bypass mode had to be integrated for convenience purpose with the upstream frequency synthesizer. The simulations were carried out in the Cadence environment, with the SpectreRF simulator, and their results are as follows:
The GSM power amplifier is able to provide a 26.5 dBm output power and a 46% PAE with a 5dBm input power.
The linear output power and the PAE of the “2GHz” power amplifier were respectively simulated to be 32dBm and 39% with a 5dBm input power in the UMTS mode. In DCS/PCS mode, the maximum output power is 33dBm and the amplifier features a PAE above 30% for input power values down to –5dBm.
Fig 1: Block diagrams of both the singleended GSM switchingmode amplifier, and the reconfigurable DCS/PCS/WCDMA power amplifier
DCIS 2004
 20 
A SiGe BiCMOS, Low Noise and Wide Band Amplifier Working at 77 K
D. Prêle ^{(}^{1}^{)} , G. Klisnick ^{(}^{1}^{)} , G. Sou ^{(}^{1}^{)} , M. Redon ^{(}^{1}^{)} , A. Kreisler ^{(}^{2}^{)} , C. Boulanger ^{(}^{3}^{)}
^{(}^{1}^{)} Laboratoire des Instruments et Systèmes d’Ile de France UPMCP6, 4 place Jussieu, 75252 Paris cedex 05, France Email: prele@lis.jussieu.fr
^{(}^{2}^{)} Laboratoire de Génie Electronique de Paris UMR 8507 CNRS, SupélecP6/P11, 11 rue JoliotCurie, 91192 GifsurYvette cedex, France Email: Alain.Kreisler@supelec.fr
^{(}^{3}^{)} Centre National d’Etudes Spatiales 18 avenue Edouard Belin, 31055 Toulouse cedex, France Email: cyrille.boulanger@cnes.fr
A specific readout circuit operating at cryogenic temperature, has been investigated to process the lowlevel signals delivered by highTc superconducting (YBaCuO Tc~85 K) hot electron
bolometers. An ASIC has been designed, including a low noise and wide band (quasi DC to 1 GHz) amplifier, operating from room temperature down to 77K. This amplifier has been successfully tested at liquid nitrogen temperature (Fig. 1). The vicinity between sensor and processing electronics allows to reduce parasitic noises due to connecting leads and improves the compactness of the overall detector. This experiment shows that it is possible to realise, with SiGe BiCMOS technology, an ASIC designed for processing, in a cryogenic environment, the signal delivered by a YBaCuO hot electron bolometer on a large frequency scale.
Figure 1. Cryogenic amplifier on the PCB and its cryostat.
DCIS 2004
 21 
A SiGe Power Amplifier with Dynamic Bias for Efficient Power Control in UMTS/WCDMA Applications
Nathalie Deltimple ^{1} , Eric Kerhervé ^{1} , Didier Belot ^{2} , Yann Deval ^{1} and Pierre Jarry ^{1} ^{1} IXL Laboratory, CNRS UMR 5818, CNRS FR 2648, ENSEIRB – Bordeaux1 University, 351 cours de la Libération, 33405 Talence Cedex, France, ^{2} ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France email: deltimple@ixl.fr
P OWER AMPLIFIERS (PAs) are the most power consuming components in portable equipment so
achieving high power added efficiency (PAE) PAs are deeply expected. Moreover, in WCDMA systems, where a nonconstante envelop modulation is used, the handset rarely transmits the signal at maximum power, so it is important to reduce the power consumption at low transmitted powers. An integrated twostage power amplifier operating at 1.95 GHz frequency range is proposed. The PA uses 2.5 V supply voltage and was designed using 0.25µm SiGe BiCMOS technology from ST Microelectronics. The linear gain is 24 dB and the output 1 dB compression point (CP1) is 26.2 dBm. The amplifier achieves a maximum PAE of 54%. In order to fulfill UMTS/WCDMA requirements, especially on linearity, the output power is 24 dBm in a linear ClassA operation, with a 32.4% PAE. By acting on the twostage bias circuits, the amplifier is able to shift dynamically the CP1 at constant power gain according to input power level. Thanks to this, greater PAE is achieved at low input power level. For instance, if the PA is backedoff by 6 dB and 11.4 dB from its CP1, PAE is equal to 15.6% and 5.1% respectively. In order to enhance PAE, the driver stage bias circuit is used to shift the CP1 to lower level, as shown in Figure 1, whereas the power stage bias circuit realizes the gain compensation, then PAE reached is 27.1% and 13% respectively. The circuit designed with a SiGe quarter micron technology from STMicroelectronics is still in progress, the layout is depicted in Figure 2. With a CP1 dynamic controlled, this PA paving the way to reconfigurable PA well suited to multimode multi band transceivers.
Figure 1: Output power as a function of the input signal level for different driver stage bias conditions
Figure 2: Layout of the integrated UMTS/WCDMA Power Amplifier
DCIS 2004
 22 
A 5 GHz SiGe VCO for WLAN Using Optimized Spiral Inductors
A. GoniIturri, S. L. Khemchandani, J. del Pino, A. Hernandez Institute for Applied Microelectronics of Las Palmas de Gran Canaria University, Spain. aiturri@iuma.ulpgc.es
T HE low fabrication cost and high packing density makes Silicon the most suitable material to
choose in many RF IC applications. The devices requirements cannot be fulfilled in many cases without the use of onchip inductors. However, standard integrated inductors suffer from their poor quality factor due to the low resistivity silicon substrate. In this work, silicon integrated standard spiral inductors are studied and some guidelines to optimized the performance are deduced. A highquality factor inductor library on a 0.35 µm SiGe technology at 5 GHz has been designed using electromagnetic simulations. The inductors, designed with no changes in the process technology or postprocessing techniques, reach values up to 10 nH. As an application, a completely integrated LC voltage controlled oscillator (VCO) according to the IEEE 802.11a WLAN standard has been designed. The achieved phase noise is 113 dBc/Hz at 1 MHz offset, and the power consumption is 116 mW. The total VCO area, shown in Figure 1, is 0.424 mm ^{2} . This work demonstrates the feasibility of a low cost silicon technology for the design of 5 GHz band circuits.
DCIS 2004
Figure 1. VCO layout
 23 
Session 1d
Built In Self Test
Wednesday nov. 24 9h00 10h00, Auditorium
Chairs
Michel Renovell (L.I.R.M.Montpellier) Joao Paulo Teixeira (INESCLisboa)
Robustness Improvement of a Ratiometric BuiltIn Current Sensor
Mikaël Cimino, Magali De Matos, Hervé Lapuyade, JeanBaptiste Bégueret and Yann Deval
Laboratoire IXL, Bordeaux, France, cimino@ixl.fr
I N this paper we present a new builtin current sensor (BICS) dedicated to monitor the current of analog and mixedsignal building blocks. His principle is the same as the initial ratiometric BICS
presented by Yvan Maidon and al. in the ninety’s. This initial BICS was first designed to operate under a 3.3 Volt power supply, as the CMOS technology used to implement the circuit was a 0.6 µm one. His output range presented a good linearity but an important technology dispersion. The new version of the BICS (figure1) uses a design methodology that allows to dramatically reduce the dispersion (from 70% to 8.5% of the output range). We have first adapted the initial version of the BICS to a 130 nm VLSI CMOS technology, and have substituted the classical current mirrors by low voltage bootstrap cascode ones. This design approach allows a 1.2 Volt power supply and reduces the channel length modulation effect. At last, we added to the BICS degenerative resistors that prevent the circuit from thermal burst and improve its robustness. The new BICS here presented appears to be robust enough to be implemented in mass production mixedsignal integrated circuits such as System on Chip (SOC) solutions, in which testability is of major importance.
I
meas
^{I} meas
40/ 0.5
40/ 0.5
100 100
A NonIntrusive BuiltIn Sensor for Transient Current Testing of Digital VLSI Circuits
B.Alorda, V. Canals and J. Segura Univ. de les Illes Balears, Dept. Fisica, Cra. Valldemossa, km. 7.5, 07071 Palma de Mallorca, Spain Fax: +34 –971 173 426. Tel: +34 –971 172 506. email: tomeu.alorda@uib.es
W E propose and evaluate a nonintrusive builtin monitor to facilitate the implementation of
transient current based testing of digital CMOS VLSI circuits. The monitor measures the transient current idd(t) by sensing the voltage drop at an inductance coupled to the magnetic field produced by the power supply transient current. Designed in 0.18 m CMOS technology, the sensor proposed has two blocks. The transducer circuit senses the transient current and provides a voltage waveform, while a second module amplifies the voltage waveform and computes the transient current waveform Idd(t). Simulation results, using an elaborated CUT model, demonstrate the performance of the new transceiver element.
DCIS 2004
 26 
BuiltIn Current Sensor using FloatingGate MOS Transistors for LowVoltage Applications
A.A. Hatzopoulos ^{(}^{1}^{)} , S. Siskos ^{(}^{2}^{)}
Aristotle University of Thessaloniki 54124 Thessaloniki GREECE (1) Dept. of Electrical and Computer Eng., Electronics Lab., alkis@vergina.eng.auth.gr (currently Visiting Professor at the Katholieke Universiteit Leuven, Belgium) (2) Dept. of Physics, Electronics Lab., siskos@surf.physics.auth.gr
In recent years Floating Gate MOS Transistors (FGT) have found many applications. In case where the input terminal is divided in two parts, the FGT can be used as a variable threshold transistor, when the first input is used as the signal input of the device and the second is used to control the threshold voltage. Supply current testing, known as I _{D}_{D}_{Q} testing in CMOS digital circuits, has been recognized for over 25 years now as an advantageous method supplementary to the conventional logic testing. It can reveal defects that are missed by logic testers. Various designs have been proposed in the last decade, especially for builtin current testing circuits. A major problem with all builtin current sensors (BICS) is their influence to the normal operation and performance of the CUT. The voltage drop across the current sensing device is a considerable drawback of the BICS. In this work the application of floating gate transistors in the design of a BICS is proposed. The important benefit from this application is that the voltage drop across the sensing device can be reduced to almost zero value, while preserving adequate linearity for the current monitoring. This linearity makes the proposed BICS also appropriate for analog and mixedsignal circuit testing. The proposed BICS structure is given in fig. 1. For two input gates it is shown that for the FGTs it
2 . With proper selection of the coupling ratio w _{2} and using a
is:
K
2
w V
1
GS
1
w V
2
GS
2
V
T
I
D
K
2
w V
1
GS
1
2
. Since
corresponding bias voltage V _{G}_{S}_{2} , we can have:
the value of V _{D}_{S}_{1} is kept quite low for the range of the I _{D} current under consideration, the voltage degradation of the CUT supply will be minimal, making this structure suitable for low voltage builtin current sensing applications. The mirrored current in FGT2 can be converted to a voltage by the use of a loading transistor. This voltage output, followed by an appropriate buffer or a latch, may be directly used as a fault indicating flag. The mirrored current can be downscaled for power saving by scaling the sizes of the floatinggate transistors. The proposed FGTBICS structure of fig. 1 has been simulated, utilizing various circuits as a CUT. The relation between Vout of the BICS and the supply current of a simple opamp circuit in a voltage inverting configuration with a 10k load as a CUT is plotted in fig. 2, showing very good linearity.
w
2
V
GS
2
V 0
T
, which results in:
I
D
Fig. 2. BICS voltage output versus supply current of an inverting opamp configuration as the a CUT.
Experimental Evaluation of a Builtin Current Sensor for Analog Circuits
R. Mozuelos, Y. Lechuga, M.A. Allende, M. Martínez, and S. Bracho Microelectronics Engineering Group, University of Cantabria Avda. Los Castros s/n, 39005, Santander, Spain {roman, yolanda, allende, martinez, bracho}@teisa.unican.es
T HIS paper presents the experimental characterization of a builtin current sensor (BICS) for
analog circuits. The BICS gives greater specific weight to the higher frequency components of the current waveform. Thus, an inductive rather than a resistive load has been used to carry out the conversion of the sampled current to voltage. The circuit has been fabricated with the Austria Micro System (AMS) 0.6 micron technology. The test approach relies on obtaining a copy of the supply current by means of the integration of additional transistors within the current mirrors of the CUT. In this way, the sensor overcomes the drawback of impacting the effective voltage supply seen by the CUT and consequently degrading the circuit performance if the sensor were placed in series with the supply/ground node. The proposed BICS gives an output that reflects the dynamic power supply consumption of the CUT. This signal has been digitized by a simple window comparator made of logical gates. The key parameter is the width of the pulse at the sensor output. Thus, a low cost counter or an integrator can easily do the signal postprocessing and the result will be compared with either the one obtained from simulation or the one obtained from a golden circuit. Finally, the sensor has been coupled to a transconductance amplifier in order to experimentally validate the structural test approach. Together with the fault free circuit, three parametric faults were implemented. The discrimination between them can be easily done by means of the measured value of the pulse width at the BICS output.
DCIS 2004
Figure 1. BICS die photograph
 28 
Session 2a
High Level Modeling
Wednesday nov. 24 10h30 11h45, Lacanau Room
Chairs
Hervé Lévi (U. Bordeaux 1) Francisco Moya (U. de CastillaLa Mancha)
Compact Modeling of a Magnetic Tunnel Junction Using VHDLAMS
JeanBaptiste Kammerer, Luc Hébrard, Michel Hehn, Francis Braun, Patrick Alnot and Alain Schuhl
C URRENTLY, the lack of compact magnetic tunnel junction (MTJ) model is a truly limiting factor for the design of spintronics circuits. In this paper, we present a compact MTJ model written in VHDLAMS. This behavioral model is based on the StonerWohlfarth model and takes most of the important phenomena such as magnetic coupling, capacitance, and magnetizations dependent conductance into account. The method employed to model a two layers magnetic tunnel junction is detailed. Applications of this model such as the simulation of the operation of a MRAM cell and of a magnetometer are also presented.
DCIS 2004
 30 
AnalogueSynthesis Tool Development for SwitchedCurrent Systems using VHDLAMS
Nesrine KSENTINI ^{1}^{,}^{3} , Ahmed FAKHFAKH ^{1} , Mourad LOULOU ^{1} , Nouri MASMOUDI ^{1} Yannick HERVE ^{2} , JeanJacques CHARLOT ^{3} ^{1} LETIENIS, Sfax, Tunisia, ahmed.fakhfakh@isecs.rnu.tn ^{2} CNRSPHASE, Strasbourg, France ^{3} ENSTCOMELEC, Paris, France
T HIS contribution presents a methodology, based on VHDLAMS modeling, for synthesis and
optimization of systems designed with the switchedcurrent technique (SI). This methodology has been implemented in Simplorer Software environment and allows a reduction of simulation runtime and a characterization of SI systems at a high level of the hierarchical design methodology.
DCIS 2004
 31 
Modeling and simulation of phototransistors using VHDLAMS
A. Alexandre, A. Pinna, B. Granado, P. Garda Laboratoire des Instruments et Systèmes d’Ile de France, Case 252 Université Pierre et Marie Curie, 4 place Jussieu, F75252 Paris Cedex 05 email : alexan@lis.jussieu.fr , granado@lis.jussieu, pinna@lis.jussieu, garda@lis.jussieu
T O develop Systems On Chip for imaging, models of photodetectors for APS cells are needed.
The mainly used photodetectors are photodiodes but it is possible to realize APS cells with phototransistors. Next complete models of vertical and lateral phototransistors are presented. They are based on a physical approach which leads to an electrical model. These models were implemented by using VHDLAMS language. The simulations of these structures give the spectral response of these
components and are in good agreement with the usual results.
DCIS 2004
 32 
Final User oriented SoC modeling
Sébastien SNAIDERO, Yannick HERVE sebastien.snaidero@ensps.ustrasbg.fr, herve@erm1.ustrasbg.fr Laboratoire ERMPHASE, ENSPS, Parc d’Innovation, BP 10413, F67400 ILLKIRCH
V VHDLAMS and other Hardware Description Languages (HDLs) are no longer used only by modeling specialists. There are thus people who are simple users of models designed by others and do not know a word about languages. The new simulation software meets the demand with their new graphical user interface (GUI). They allow the development of simple and fast models easy to use for industries as well as in depth models for physical studies and laboratories. To meet the demand of both this new type of users and the developers, the new software needs some qualities that are hard to gather. For the user side: intuition, simplicity and convenience must hide the difficulties inherent in the complexity and varieties of languages without impoverish the power of the HDLs. For developers, a powerful model creation tool that brings a substantial implementation of the various languages it accepts is required. It must of course allow interfacing models of these different languages. As developers remain the only ones able to create models from scratch, they must watch over using datasheets parameters for their models to guarantee their widest possible use. The developers on the one side and the users on the other side both require tools adapted to their needs. The current effort of simulation software corporations is to build extremely powerful and convenient tools that work for both users and developers. As the abstraction level of our designs is increasing up to describe whole systems, it is important to notice that the tools have to and will still have to advance the same way to provide userfriendly graphical representations of the objects we wish to design.
DCIS 2004
A complete channel of the module
 33 
Design and Simulation of MixedMode Optical Systems for PSD Applications
Ricardo Doldán, Eduardo Peralías, Alberto Yúfera and Adoración Rueda Instituto de Microelectrónica de Sevilla (IMSE), Centro Nacional de Microelectrónica (CNM), Av. Reina Mercedes s/n. Edificio CICA. 41012. Sevilla. SPAIN. emails: {rdoldan, peralias, yufera, rueda}@imse.cnm.es
T HIS work describes an optical Position Sensing Detection (PSD) algorithm. A mixedsignal
model of a photodetector cell for electrical simulation has been developed, including the complete dynamic model for a photodiode. It is shown how standard simulators employed in electrical environments can be adapted to describe devices included in optical based system. This enables it to perform complex system characterizations including optical and electrical parts using the same environment (Spectre), and to extend the mixedmode simulation concept to a wider field than non electrical systems. A system simulation application for Position Sensing Detection (PSD) with a resolution in the micrometer range is reported along the paper.
DCIS 2004
 34 
Session 2b
Biometric and Robotic Applications
Wednesday nov. 24 10h30 11h45, St Emilion Room
Chairs
Rachid Bouchakour (E.P.U. de Marseille) Jacques Pistre (E.N.S.E.I.R.Bordeaux)
DSPbased Fuzzy Controllers: Application to Parking an Autonomous Robot
Iluminada Baturone ^{1} , Francisco J. MorenoVelo ^{1} , Santiago SánchezSolano ^{1} , Víctor Blanco ^{2} , and Joaquín Ferruz ^{2} ^{1} Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica (IMSE CNM), Sevilla, SPAIN, email: {lumi, velo, santiago}@imse.cnm.es ^{2} Departamento de Ingeniería de Sistemas y Automática, Universidad de Sevilla, Sevilla, SPAIN, email: {vmblanco, ferruz}@cartuja.us.es
F UZZY controllers are used in many applications because of their rapid design by translating
heuristic knowledge, robustness against perturbations, and smoothness in the control action. However, their direct implementation requires parallel processing and special operators (such as fuzzification or defuzzification) which are not available at standard digital signal processors (DSPs). The novel idea followed in this paper is to translate the fuzzy rule bases of a fuzzy controller into non fuzzy ones that can be implemented easily by using the relational and logical operators, the standard ifthen conditional statements, and the addition and multiplication operators available at a DSP. This is done by using hierarchical structures and adequate membership functions, connective operators, and inference methods. The parking problem of an autonomous robot (Figure 1) is described to illustrate this design process. Experimental results (Figure 2) show the efficiency of the designed fuzzy controller embedded into a standalone card based on a fixedpoint DSP from Texas Instruments.
Figure 1. The autonomous robot Romeo 4R.
DCIS 2004
 36 
y ^{y}
Figure 2. Example of experimental results.
Coprocessor of the Ridge Line Following Fingerprint Algorithm
E. Cantó, N. Canyellas, M. López, M. Fons, F. Fons
Universitat Rovira i Virgili (URV), Department of Electronic, Electrical and Automatic Control Engineering Av. Paisos Catalans 26, 43007 Tarragona (phone: 977558522; fax: 977559605; email: ecanto@etse.urv.es).
F ingerprintbased automatic recognition systems are rapidly growing on a wide shell of applications.
Most of biometrics authentication systems are implemented on high performance computer based platforms executing a set of complex algorithms implemented on software. Those solutions cannot be applied to lowcost embedded systems, based in microprocessors without floatingpoint arithmetic unit. The use of fingerprint biometrics coprocessors is still a young field. A great majority of commercial fingerprint OEM modules are based on embedded high performance 32bit processors or DSPs In this article we present a biometrics coprocessor to speed up the ride line following minutiae extraction algorithm. It covers the minutiae extraction stage, the one with higher computational requirements. In our work we use the MaioMaltoni ridge line following algorithm ^{1} because it permits minutiae extraction directly from the grayscale fingerprint image, it is computationally less expensive than others, and it can be rewritten to be implemented without floating point operations. In order to develop an efficient hardware implementation of the coprocessor, in terms of lowcost and highspeed, floatingpoint computations used on the algorithm have been substituted by fixedpoint computations, among other substituted complex functions. It has also been adopted a pipelined scheme to reduce the critical pathdelay and to execute several steps in parallel, to increase the clock frequency and throughput.
The execution of the steps performed by the coprocessor running at 50MHz, is 14.4 s, while the time devoted by an ARM7TDMI processor at the same clock speed to execute the same computation tasks, was 211 s averaged. The overall execution time of the algorithm running in the ARM with the coprocessor is reduced from 700ms to 215ms, that is a reduction of about 70%.
^{1} Maio, D.; Maltoni, D. “Direct GrayScale Minutiae Detection In Fingerprints” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol 19, No. 1. January 1997
DCIS 2004
 37 
Iris Biometrics Verifiers for Low Cost Identification Tokens
Judith LiuJimenez ^{a} , Raul SanchezReillo ^{a} , Carmen SanchezAvila ^{b} , Luis Entrena ^{a} ^{a} Dpto de Tecnologia Electronica, Grupo de Microelectronica, Universidad Carlos III de Madrid, c/ Butarque 15, 28911 Leganes (Madrid), Spain, Email: {jliu, rsreillo,
entrena}@ing.uc3m.es
^{b} Dpto. de Matematica Aplicada a las Tecnologias de la Informacion, E.T.S.I. Telecomunicacion, Universidad Politecnica de Madrid, Ciudad Universitaria, 28040 Madrid, Spain, Email: csanchez@mat.upm.es
T HE use of biometrics is increasing everyday, as security is becoming one of the most important
concerns in Information society. In Biometrics, one of the most promising techniques is iris recognition, which presents lower error rates than other biometrics techniques. One of the processes in
a biometric system is the verification or matching between data obtained and a template previously
stored. This process can be done on centralized systems, such as a central database, or in a distributed
way, using identification tokens. When developing new identification tokens, computational cost and processing time should be reduced, to provide cheaper devices, which could allow a viable solution in
a commercial system. The authors, in this paper, develop different implementations of low cost
biometric verifiers, to be included in identification tokens. The biometric technique chosen for that issue has been iris recognition, and therefore, the verification technique has been based in Hamming Distance.
DCIS 2004
 38 
Fingerprint Matching Acceleration in Smart Cards ^{1}
Luis Entrena, Raúl SánchezReillo, Almudena Lindoso, Judith Liu Departamento de Tecnología Electrónica Universidad Carlos III de Madrid {entrena, rsreillo, alindoso, jliu}@ing.uc3m.es
T HE increasing demand for pervasive security poses a challenge in achieving robust
authentication at very low cost. Biometrics is the only way to perform a real user authentication,
but has a high computational cost. In this work we study the integration of fingerprint biometrics in
smart cards. Since commercial smart cards use low performance microprocessors, fingerprint
verification may take up to several seconds, which is unacceptable for practical applications. On the
other hand, simply moving to a more powerful processor will result in an important cost penalty and
will not solve the performance bottleneck.
In order to speedup fingerprint verification, we identify the most critical operations of an efficient
fingerprint matching algorithm. These include the computation of euclidean distance, radial angle and
element matching. Then, we propose an extended instruction set that can be implemented with low
hardware overhead. With this extension, the total time required to complete fingerprint matching is
reduced more than 60% and accounts to less than a second for medium size minutia sets. An improved
instruction for element matching, termed vector matching, is also proposed that provides larger speed
up. Final results using vector matching allow to perform fingerprint verification in a fraction of a
second for large minutiae sets.
^{1} This work was supported in part by the Ministerio de Ciencia y Tecnología (Spain) under Project TIC2003
01793
DCIS 2004
 39 
Hardware implementation of the Bresenham line generation algorithm applied to µrobot movement
R. Casanova, A. Diéguez, J. Lacort J. Samitier Departament d’Electrònica, SIC, Universitat de Barcelona, C/Martí Franquès 1, E08028, Barcelona, Spain. Email: casanova@el.ub.es,
A digital waveform generator for the movement control of an autonomous microrobot is presented. The circuit is able to generate trapezoidal and sawtooth signals with programmable amplitude, period and phase. These control waveforms are used to actuate over a bimorphic locomotion unit. As the robot has to be capable to operate with nanometric resolution, waveforms must be generated with great precision. Waveforms are generated by using the Bresenham algorithm in order to deal with integer operations. The circuit has been designed with the 0.35µm C35b4 technology of AMS.
DCIS 2004
 40 
Session 2c
Industrial Applications
Wednesday nov. 24 10h30 11h45, Auditorium
Chairs
Franck Badets (STMicroelectronics) Daniel Auvergne (L.I.R.M.Montpel
Dualport serial arbiter with GSM modules for simultaneous local/remote control of RS232based devices
Eloi Ramon ^{1} , and Lluís Ribas ^{2} , Member, IEEE ^{1} Electronics, and ^{2} Computer Science Departments, Universitat Autònoma de Barcelona (UAB), Cerdanyola, Spain, {Eloi.Ramon, Lluis.Ribas}@UAB.es
_{S} ERIAL communications are extensively used within the electronics industry due to its relative simplicity and low hardware overhead. One of the most popular serial communications standard in use is certainly the RS232. There are many devices that can be controlled by RS232 ports at home and, especially, in industrial applications. Remote control and/or monitoring of such devices enables users to access these devices from anywhere. Particularly, providers of such devices or related services can remotely monitor their functionality and yield, and take actions accordingly. SMS (Short Message Service) was introduced as a GSM (Global System for Mobile Communications) service in 1992. In the last years, SMS have been widely used in remote control due to its ubiquity, area coverage, cost and ease of use. Despite the increase in GSM/GPRS modules in the market, most industrial applications are still using SMS as a communication protocol. In this paper we present a module to both extend the serial communications port for other devices or protocol adapters and to allow remote control by SMS messaging. In order not to interfere with local applications, it is interesting that RS232 device ports are kept connected to local application hosts. Consequently, there should be a module that, apart from having 2 serial ports, is capable of transmitting information wirelessly. Unfortunately, the RS232 serial protocol is a pointtopoint communication one, thus the introduction of a thirdparty port necessarily requires the participation of an arbiter that resolves the conflicts and sets the appropriate connections. The arbiter has been implemented on a SonyEricsson GR47 module, as well as its application specific queue reading/writing functions. The application presented has been used in an industrial appliance designed for MAM Electrónica to remotely control UPS systems in order to monitor charger status, battery status and condition, utility status, et cetera.
DCIS 2004
 42 
Signal Processing Unit for River Tugboat Telemetry System
Mauricio Pardo ^{1} , Víctor Manotas ^{1} , Juan Carlos Niebles ^{2} , Javier Páez ^{1} , David Angulo ^{2} , Humberto Campanella ^{1}^{,} ^{3}
1 Universidad del Norte, Barranquilla, Colombia, email: mpardo@uninorte.edu.co 2 Flota Fluvial Carbonera Ltda, Barranquilla, Colombia 3 Centro Nacional de Microelectrónica (IMBCNM), Barcelona, Spain _{h}_{c}_{a}_{m}_{p}_{a}_{n}_{e}_{@}_{c}_{n}_{m}_{.}_{e}_{s}
T HIS article describes the design and implementation of a complete signal acquisition system
intended for use in telemetry systems for river tugboats. Specifically, the design aspects of the signal processing unit are covered. A complete prototype was built, installed and put into operation in
a tugboat of the fleet of a fluvial transportation company in Northern Colombia (Flota Fluvial
Carbonera Ltda). System functionality was mainly synthesized on an Altera’s FPGA, taking great advantage on rapid prototyping. Field measurements are reported, making detail in the fuel volume calculation, which demonstrated to be more accurate than previous method.
As an industrial application, this system represents an innovation for the company’s operation. Specifically, a method to estimate fuel level and volume is proposed. This method does not require installation of neither 3D angular sensors nor complex calculation to compensate measurements due to swell or navigation conditions. A single sensor was installed in each one of the fuel tanks achieving less difference with real dumped fuel than previous method.
The telemetry system is composed by hardware and software components. The hardware component
is an acquisition and processing unit. The second component is a network management application,
totally tailored in C++ for this telemetry application and conformed by three main software modules. Processed data is transmitted to the company’s network operation center using a satellite link.
Processing
Figure 1. Standalone enclosure with the acquisition and signal processing hardware
DCIS 2004
 43 
A Sensorless Electronically Controlled Horn for Automobiles
M. César Rodríguez, César Sanz Universidad Politécnica de Madrid, Spain (e mail: mcesar@sec.upm.es)
Jacinto M. Acero, Fernando Nozal Robert Bosch España S.A.
T HIS paper describes a new kind of sensorless electronically controlled horn for automobiles.
The main benefits of this new horn over the classical electromechanical counterparts are: a much longer lifetime, a lower level of generated electromagnetic interference, a better behavior against aging and stress, the avoidance of the adjusting operation during manufacturing and its multifunction
capabilities. To fulfil all these targets we have substituted the electromechanical breaker of previous designs by a solid state switch controlled by a microprocessor on board the horn. In order to detect the resonance condition of the horn we use a novel technique based on the analysis of the current across the coil (as seen in the figure), avoiding the need for any soundlevel, position or motion sensor. The lifetime of these new horns is, at least, forty times that of previous breaker horns. The level of generated EMI for these new horns is much lower than previous electromechanical designs. These new horns can fulfil the requirements of both 95/54 EC directive and CISPR 25 standard, whereas the breaker horns cannot. As the horn is now selfadjusting, its behavior against aging and stress is better, as it can compensate for these factors dynamically. This selfadjusting operation also allowed the avoidance of the expensive trimming operation during fabrication. We have also developed a multifunction horn capable of producing different kinds of sound at the command of the vehicle’s electronic control unit. Both kinds of horns were assembled using the very same machinery as previous breaker horns and serve as perfect spare parts for them.
Figure 1. Proposed sensorless control circuitry
DCIS 2004
 44 
Design of LowPower CMOS ReadOut ICs for Large Arrays Cryogenic InfraRed Sensors
B. Misischi ^{1} , F. SerraGraells ^{1} , E. Casanueva ^{2} , C. Méndez ^{2} and L. Terés ^{1}
bertrand.misischi@cnm.es , paco.serra@cnm.es , ecasanueva@indra.es , cmendez@indra.es and lluis.teres@cnm.es
^{1} Institut de Microelectrònica de Barcelona, CNM, CSIC (Spain) ^{2} Indra Sistemas S.A. (Spain)
T HIS paper describes a complete design methodology for a low power cryogenic design readout integrated circuit (ROIC) of large arrays of infrared (IR) detectors. The presented methodology
includes IR sensor modeling, MOSFET modeling at cryogenic temperature, circuit design, physical veriﬁcation strategies and the systemonchip realization. Also, novel lowpower and compact CMOS circuits are proposed to implement all the required basic building blocks, from the active pixel sensor (APS) to the composition of the output video signal. The resulting high performance 500 ×12 array and 60ns/pixel systemonchip, capable of capturing highresolution and realtime infrared images, like 640 ×500@100fps, has been designed for a standard 0.35µm CMOS technology from AMS.
Figure 1: Simpliﬁed schematic (left) and layout including bumping pads (right) of the APS cell, and landscape view of the complete ROIC layout including bonding pads (bottom).
DCIS 2004
 45 
A Dynamic Current Mode Logic to Counteract Power Analysis Attacks
F. Mace, F.X. Standaert, I. Hassoune, J.D. Legat, J.J. Quisquater UCL Crypto Group, Microelectronics Laboratory (DICE), Université Catholique de Louvain (UCL), Belgium mace,standaert,hassoune,legat,quisquater@dice.ucl.ac.be
S INCE their publication in 1998, power analysis attacks have attracted significant attention
within the cryptographic community. So far, they have been successfully applied to different kinds of implementations (eg: smart cards, ASICs, FPGAs) of cryptographic algorithms. To protect such devices against power analysis attacks, it has been proposed to use a dynamic and differential logic style for which the power consumption does not depend on the data handled. In this paper, we suggest to use the Dynamic Current Mode Logic to counteract power analysis. The resulting circuits exhibit similar resistance to the previously published proposals but significantly reduce the power delay product. We also demonstrate that certain criteria previously used to evaluate the resistance against power analysis have no cryptographic relevance.
DCIS 2004
 46 
Session 2d
Data Converter Test
Wednesday nov. 24 10h30 11h45, Bordeaux Room
Chairs
François Marc (U. Bordeaux 1) Joan Figueras (U. Politècnica de Catalunya)
Digital Diagnosis of Settling Error in Modulators
Gildas Leger, Adoración Rueda Instituto de Microelectrónica de Sevilla (IMSECNM), Universidad de Sevilla Edificio CICA, c/ Tarifa s/n, 41012SEVILLA, SPAIN. email: leger@imse.cnm.es, tlf: 34 95 505 66 66
F IRST and second order sigmadelta modulators are commonly used in cascaded structures to
achieve high resolution analogtodigital converters. While these modulators are gaining more and more resolution, they become harder to test. Embedded test solutions and BuiltIn SelfTest (BIST) techniques are faced to important issues to ensure the test stimulus precision or the test data acquisition. This makes functional test a tricky path to follow. For almost all systems, and in particular for modulators, a behavioural model where the principal noidealities are quantified is usually used to settle highlevel design specifications and realize high level simulations. Designers know that to reach a given precision they have to guarantee a number of parameters like amplifier DC gain, amplifier slewrate and bandwidth, capacitor switching noise level, integrator output range, etc. Hence, from a test viewpoint it can be assumed that the principal causes of unexpected performance decrease should be related to these highlevel design specifications. In other words, if a modulator is not performing as expected it is likely that some highlevel parameter have been brought out of specification. It is thus of utmost interest to diagnose and measure these parametric faults. This paper presents a simple and fully digital test technique able to evaluate amplifiers settling error in second and first order modulators. These settling errors are related to amplifier gainbandwidth product and slewrate, which are part of the above mentioned set of high level design specifications. Actually, they are known to be a source of nonlinearity. The realistic simulations presented in this paper exhibit good matching with theory and show very promising results as the integrator settling error can be determined with good precision. It is also shown that the settling error can directly be related to a precision loss, which enables a functional interpretation of the test signature.
DCIS 2004
 48 
Digital Sigma Delta Oscillator : Design Considerations
Maher Jridi ^{∗} , Chiheb Rebai ^{†} , Dominique Dallet ^{∗} , Sylvain Engels ^{‡} , Laurent Dugoujon ^{§}
^{∗} Laboratoire IXL
UMR CNRS 5818
ENSEIRB
Univerist´e Bordeaux 1
351 cours de la lib´eration, 33405 Talence CEDEX
France
Telephone: +33 5 4000 6540, Email: [jridi,dallet]@ixl.fr
^{†} Institut Sup´erieur des arts du multim´edia de Manouba
Campus universitaire Manouba, 2010
Tunisie
Telephone: +216 71 602 050, Email : chiheb.rebai@voila.fr ^{‡} STMicroelectronics  850, rue Jean Monnet, F38926 Crolles Cedex Telephone: +33 4 76 92 50 26, Email : sylvain.engels@st.com ^{§} STMicroelectronics  12, rue Jules Horowitz BP217, 38019 Grenoble Telephone: +33 4 76 58 62 54, Email : laurent.dugoujon@st.com
This work is deployed in the context of Analog to Digital test Converters where a precise sinusoidal sources is needed. A promising solution to this challenge, a digital Lossless Discrete Integrator (LDI) resonator combined with a 1bit Delta Sigma modulator and simulation results has been yet presented. This present article proposes a new methodology enabling us to go towards ASIC using the same parameters of FPGA implementation. As summarized later, the digital source is build using digital hardware: digital registers, adders, multiplexers and shifters. The work presented will be divided into three parts: this paper ﬁrst reviews the fundamentals of DeltaSigma modulator based signal generation (Section II): ﬁrst of all we talk about the digital resonator and its drawbacks. Then we detail the principle of Sigma Delta attenuator where we emulate the multiplier operator by Sigma Delta modulator and a multiplexer. This oscillator has to generate a precise 1bit signal to test the ADC. To perform the SNR, we need to increase the modulator order. A problem of stability can appears if the modulator quantiﬁer is on only one bit. Schreier seems found an empirical methodology to resolve this. Section III brieﬂy outlines the material FPGA implementation. The simulation results will be presented to validate our preferences to the selected LDI structure and the simulation parameters. The difﬁculties of this part consist on the data ﬂow where we used a ﬁxedpoint precision. Section IV describes the circuit. The layout schema will be shown in the end of this paper.
DCIS 2004
 49 
Optimal implementation of linear and adaptive filter bank for ADC characterization
^{1} F. Missaoui, ^{2} D. Dallet, ^{1} C. Rebai, ^{1} A. Ghazel
^{1} – MEDIATRON Laboratory – Ecole Supérieure de Communication (SUP’COM) 2088 Cité Technologique des Communication, Tunis, TUNISIE
^{2} – Laboratoire IXL – UMR CNRS 5818 – ENSEIRB – Univeristé Bordeaux 1, 351 cours de la libération, 33405 Talence CEDEX – France, tel : 33 5 4000 2632, dallet@ixl.fr
I N this paper we present a linear and an adaptive filter bank employed to decompose the
signal in its main spectral components in the field of ADC characterization. Both structures are based on band pass LDI filter (Lossless Digital Integrator) which is known for its efficient implementation. From real acquisitions, we show the efficiency of linear structure to obtain an estimation of the main spectral parameters. Nevertheless, if the input frequency is not the expected one, we have to use an adaptive structure to track the fundamental component. In this way, we can estimate the spectral parameters related to the ADC performances. These two architectures were simulated in floating point precision. This paper shows the design
consideration to take into account for the implantation in fixed point precision: the data flow for the linear structure and the latency problem for the adaptive one.
u(n)
e(n)
out
Figure. Adaptive structure for ADC spectral parameters estimation.
DCIS 2004
 50 
Selection of test techniques for highresolution modulators
Oscar Guerra*, Sara Escalera*, Jose M. de la Rosa*, Eric Compaigne ^{+} , Christophe Galliard ^{+} and Angel RodríguezVázquez* (guerra, escalera, jrosa, angel@imse.cnm.es; eco, cga@dolphin,fr) *Instituto de Microelectrónica de Sevilla (IMSECNMCSIC) Av. Reina Mercedes, 41012Sevilla, SPAIN. Tlfno.: 955056666 Fax:955056686 ^{+} Dolphin Integration B.P. 65 ZIRST F38242 Meylan, France
The objective of this paper is to select the best test techniques for their application to highresolution modulators. As the selection process is quite complex, a decision matrix has been created in order evaluate the efficiency of the different techniques in term of their cost. This cost could then be used as a reference to determine the efficiency of the different test techniques compared to the standard methodologies. The decision matrix presented in the chart below is a tool that has been created for the TAMES2 project in order to evaluate the efficiency of the different test techniques in term of cost. For each test technique, it is required to fill in the decision matrix with all the parameter values. Then, a cost is auto matically computed. The resulting "Weighted cost" allows to determine if the technique is cost effective or not. For the case of the sensor interface under study ^{1} , the key point of test is to cover both static and dynamic measure ments. Concerning dynamic requirements, the following measurements have to be performed:
• Signal over Noise Ratio: the estimated test time for this FFT is 0.3 s.
• Total Harmonic Distortion: the estimated test time for this FFT ranges is 0.6 s.
• Efficient number of bits: is obtained automaticaly from the FFT that is used to test the SNR or the THD. Thus, no additional time (unless some negligible computational time) has to be added to the total test time. Then, for the case of static measurements, the following test measurements have to be performed:
• Integral non linearity, differential non linearity: the computational time for this test is 65s using the standard histo gram test.
• Static gain and and offset can be calculated from the data achieved for the INL with an almost negligible post processing time. Thus, no additional time is devoted to this task. After a detailed study of all the potential test techniques capable of dealing with highresolution converters, the cho sen test techniques for the Sensor interface have been the following:
FFTINL. In order to test the static behavior of the A/D converter, the FFT coefficients resulting after the application of the FFT test can be used to generate the coefficients of a polynomial that is the "smoothed" version of the DNL.
Hierarchicalbased. This technique has been fully explained in other paper ^{2} . The basic idea here is to test the impact that the extra test circuitry and some specific reconfiguration scheemes have on the circuit performance.
Waveletbased. This technique is based on the application of the wavelet transform to the output of the converter when it is excited using a sine wave. Information about the instantaneous ENOB, SNR and INL can be obtained using less samples than those required for the standard Histogram technique.
In the paper, these techniques will be compared to two reference test methods, the standard FFT to test the dynamic characteristics of the converter and the standard histogram test to measure its static characteristics.
1.J. M. GarcíaGonzález, S. Escalera, J. M. de la Rosa, F. Medeiro, O. Guerra, B. PérezVerdú and A. RodríguezVázquez, “Design and Implementation of a 0.35 m CMOS Programmablegain 21 Cascade Modulator for Automotive Sensors”, Pro ceedings XIX Design of Circuits and Integrated Circuits Conference, pp. 114119, 2003.
2.O. Guerra, J. Ruiz, J. M. de la Rosa, F. Medeiro and A. RodríguezVázquez, “A decomposition methodology to test highreso lution modulators” Proc. 9th International MixedSignal Testing Workshop, pp. 6570, 2003
DCIS 2004
 51 
Guidelines for the Design of a SineWave Analyzer for BIST Applications
Manuel J. Barragán, Diego Vázquez and Adoración Rueda Instituto de Microelectrónica de Sevilla – Centro Nacional de Microelectrónica (IMSECNM) Universidad de Sevilla Avda Reina Mercedes s/n, Edif. CICA/CNM, 41012 Sevilla (SPAIN) email: {manuelj, dgarcia, rueda}@imse.cnm.es
T HIS paper presents some guidelines for the design of an onchip analyzer for extracting, in the
digital domain, the main characteristic parameters of an analog sinewave signal. The analyzer, reported elsewhere ^{1} , is based on a doublemodulation, squarewave and sigmadelta, altogether with a simple digital processing algorithm. We discuss the specifications required for the analog part of the analyzer and describe an areaefficient implementation of the digital part. In addition, we show simulations results which demonstrate the validity of the proposed guidelines, while the simplicity and the robustness of the circuitry make it very suitable for BIST applications.
^{1} D. Vazquez, G. Huertas, G. Leger, A. Rueda, and J. L. Huertas, “A Method for Parameter Extraction of Analog SineWave Signals for MixedSignal BuiltInSelfTest Applications”, IEEE Design and Test in Europe (DATE04), Paris, France, Feb. 2004.
DCIS 2004
 52 
Session 3a
Digital Signal Processing in FPGA Platforms
Wednesday nov. 24 14h15 15h45, Lacanau Room
Chairs
Lionel Torres (L.I.R.M.Montpellier) Lluis Teres (IMBCNM)
Implementing the FFT Algorithm on FPGA Platforms:
A Comparative Study of Parallel Architectures ^{*}
M. A. Sánchez ^{1} , M. Garrido ^{1} , M. LópezVallejo ^{1} and J. Grajal ^{2}
^{1} Dept. Ingeniería Electrónica, ^{2} Dept. SSR, ETSIT, UPM, Madrid, Spain,
^{1} {masanchez, mariog, marisa}@die.upm.es
^{2} jesus@gmr.ssr.upm.es
I N this paper we present an in depth analysis of the implementation of different FFT architectures
in FPGA platforms. The target applications are radar processing systems and wideband digital receivers, what enforces hard constraints in processing speed. Thus, parallel pipelined architectures of the FFT have to be used. In particular, feedback and feedforward architectures are analized in detail, studying the variations of results with a set of key design parameters: radix, word length, number of points or the effect of truncation. Additionally, the impact due to the implementation in programmable devices will be considered when designing and analyzing the different architectures. Two alternative structures have been studied: feedback and feedforward architectures. They provide very diverse results in terms of area and performance, what results in different applications of the proposed architectures. In this way, feedback structures can be used for long Npoint FFTs, because of their small area, while feedforward architectures are better suited for applications with hard realtime constraints due to their better speed. Figure 1 depicts the results of area and speed obtained for different implementations of feedback (FB) and feedforward (FF) implementations.
Figure 1. Area and perfomance results of feedback (FB) and feedforward (FF) architectures for 16, 64, 256 and 1024 points
^{*} This work was supported by the Spanish Ministry of Science and Technology under contract TIC200307036.
DCIS 2004
 54 
An FPGA landmine detection system based on infrared images
F.Pardo*, M. Balsi**, P. López*** and D. Cabello* *Dept. Electrónica y Computación. Univ. de Santiago de Compostela, Spain. **Dipartimento di Ingegneria Elettronica. Università La Sapienza. Italy. ***Fraunhofer Instituf für Integrierte Schaltungen. Erlangen. Germany.
fpardo@usc.es balsi@uniroma1.it lop@iis.fraunhofer.de diego@dec.usc.es
H umanitarian deminining has become an important issue in regions where an army conflict has
occurred. The detection of small plastic mines can not be done using classical detection techniques, such as metal detectors, because their metal content is null or very low. The use of infrared
images of the soil is an efficient technique to detect this kind of mines ^{1} . This approach is based on thermal modeling of the heat transfer processes in the soil and at the soilair interface. This is used to characterize the soil thermal response to a given stimulus, also known as the thermal signature. Perturbations on the expected signature constitute reliable indicatives of the presence of mines, due to the different thermal properties of the soil and the mine. The detection of the mines is divided into two steps; in the first step a comparison between the real data and the data obtained in the simulation of the thermal model is made. In the simulation process we first assume that there are no mines present. The differences between the real data and the simulated data give us indicatives of the presence of unexpected objects. The second step is an inverse problem, in which the thermal model must be run for multiple soil configurations, representing different possible depths of burial and different types of
targets (mine, stone
the nature of the unexpected targets. Several soil configurations (nature and position of the object) must be run in order to detect with high precision the position and nature of the unexpected patterns.
This detection scheme is a very long timeconsuming process on a personal computer. In this work an architecture of a system which simulates the thermal model is projected onto an FPGA in order to reduce the computing time. The system is formed by four memory banks, a processing element, a unit that generate the addresses that must be loaded/uploaded from the memory and an element that generates the required control signals. The pipelined structure of the design lets to update several nodes in parallel. In the current implementation a reduction factor in the computing time of 15 is achieved.
).
The nearest configuration to the real data gives us the estimated position and
^{1} P. López. “Detection of Ladmines from Measured Infrared Images using Thermal Modeling of the soil”. PhD, Univ. Santiago de Compstela, Spain, April 2003.
DCIS 2004
 55 
Implementation of Optimized FFT on Stratix DSP Development Board
Fabienne NOUVEL, IETR/INSA20 avenue des Buttes de Coesmes35043 RENNES. France, fabienne.nouvel@insarennes.fr
T his paper deals with the comparison of two FFT/IFFT cores implementations on the Altera Stratix Component.
As FPGAs are particularly well suited to highspeed and regular functions, they can perform DSP functions, answering both the need for flexibility and high performances. The FFT, FIR, DCT, … DSP functions are iterative and need high level pipeline, space and time parallelism. However, FPGA architecture must be optimized in order to increase the performances of the cores, including MAC ( Multiply Accumulate) hard blocks. Using wired blocks, the DSP functions run faster.
In the first part of this paper, the studied DSP board is presented, by mean of the Stratix component, connected to SRAM, converters DAC and ADC.
The FFT core is studied in order to perform a high speed MultiCarrier modulation
/demodulation (MC). In fact, this one is easily carried out in the digital domain by performing
IFFT and FFT operations. In the receiver, after direct FFT, the received sequence is
"equalized" in the frequency domain. Nowadays, MC combined with spread spectrum is
undoubtedly a high potential candidate for the air interface of the 4G cellular networks.
The two IFFT/FFT IP cores are presented and compared : the Altera FFT MegaCore function is a
parameterizeable IP core. It uses an inplace mixed radix 4 and 2 decimation in frequency
architecture, and implements any transform length that is a power of 2. The Jaguar II is a
variable FFT/IFFT core up to 1024 points. Available as a softcore, it is parameterized to
allow up to 32bits of resolution (32 Inphase / 32 Quadrature).
The two cores have been implemented, taking into account the specific architecture of the Sratix component. The results show that the Altera FFT core runs faster than the Jaguar core and used less resources (both DSP blocks and memories). Neither, the Jaguar requires less cycles than Altera. Indeed, a 1024 points FFT with a 45 MHz system clock is performed in only 29 s with the Jaguar
core, compared with the 130 s with Altera, which means a ratio of 4. This lowest clock system will result in a lowest power consumption.
DCIS 2004
 56 
Comparison of Two Implementations of Scalable Montgomery Coprocessor Embedded in Reconfigurable Hardware
Miloš Drutarovský ^{(}^{1}^{)} , Viktor Fischer ^{(}^{2}^{)} and Martin Simka ^{(}^{1}^{)} , ^{(}^{1}^{)} Department of Electronics and Multimedia Communications, Technical University of Kosice, Park Komenského 13, 04120, Kosice, Slovak Republic, {Milos.Drutarovsky,Martin.Simka}@tuke.sk ^{(}^{2}^{)} Laboratoire Traitement du Signal et Instrumentation, Unité Mixte de Recherche CNRS 5516, Université Jean Monnet, 10, rue Barrouin, 42000 SaintEtienne, France, fischer@univstetienne.fr
HIS paper presents a comparison of two possible approaches for the efficient implementation of
a scalable ^{1} Montgomery Modular Multiplication (MM) coprocessor on modern Field Programmable Logic Devices (FPLDs). The first implementation uses a data path based on traditionally used redundant CarrySave Adders (CSA), the second one exploits standard Carry Propagate Adder (CPA) with fast carry chain logic not yet used in fully scalable designs. Both implementations use large embedded memory blocks available in recent FPLDs. Speed and logic requirements comparisons are performed on the optimized designs. The issues of targeting a design specifically for a FPLD are considered taking into account the underlying architecture imposed by the target FPLD technology. It is shown that carrysave adder is not an optimal building block for constrained scalable MM coprocessor in modern Altera FPLDs. The proposed implementation method can also be applied for FPLDs from other vendors since it uses building blocks generally available in modern FPLDs – high speed dualport embedded memories and fast carrypropagated logic.
T
q
x
i
i
Figure 1. Block diagrams of analyzed CSA and CPA based processing elements
^{1} A.F. Tenca, C.K. Koc, “A scalable architecture for modular multiplication based on Montgomery’s algorithm”. IEEE Transactions on Computers , vol. 52, no. 9, pp. 12151221, Sept. 2003.
DCIS 2004
 57 
An implementation of a Parallel Architecture for the SelfSorting FFT Algorithm applied to IEEE 802.11a
Ainhoa Cortés* , Igone Vélez* , Pilar Calvo* , Juan F. Sevillano † and Andoni Irizar †. * CEIT Research Center, Department of Electronics and Communications, Spain. † Universidad de Navarra, Department of Electrical and Electronic Engineering, Spain.
I N this paper we present an implementation of a parallel architecture for the SelfSorting (SS) Fast
Fourier Transform Algorithm that optimizes the processing rate for the IEEE 802.11a standard. Two
structures have been developed in the radix2 Butterfly to improve the architecture. In order to analyze the
dependence of the FFT on the bitwidth of the input data and of the twiddle factors, the SNR of our module
has been studied.
The resulting design is parameterizable, regular and modular, presenting constant geometry. The total
processing time required is
for a number of points N=r ^{n} , where r is the radix and n
represents the number of the stages to process the FFT, computed using Q=r ^{u} processors.
The SS algorithm was implemented on a processor column (PEs). The data flow between PEs, by using
eight processors in parallel to execute a FFTradix 2, is shown in figure 1. In table I we compare the
processing time of our design with other architectures for different clock frequencies. As IEEE 802.11a
needs 4 s as processing time, the Parallel Architecture presented here fulfils the timing specifications.
(2
nN
rQ
) log
r N
Table I. Comparison with other architectures
CLK (MHz) 
Processing time ( s) 

Fast64 ^{1} 
50 
2.82 
64Xilinx ^{2} 
50 
3.84 
Cobra ^{3} 
40 
5.55 
64Point ^{4} 
40 
3.2 
64Point 
100 
1.3 
Parallel SS 
50 
2.22 
Parallel SS 
40 
2.775 
Parallel SS 
100 
1.11 
^{1} L. Fanucci, M. Forliti, and P. Terreni, “Fast: FFT ASIC automated synthesis”, INTEGRATION, the VLSI journal, vol. 33, pp. 230234, 2000.
^{2} “Xilinx Product Specification: HighPerformance 64point complex FFT/IFFT V1.0.5”.
^{3} T. Chen and L. Zhu, “COBRA: A 100 MOPS singlechip programmable and expandable FFT”, IEEE Transactions Very Large Scale Integration (VLSI) Systems, vol. 7, nº 2, pp. 174182, 1999.
^{4} Tiong Jiu Ding, John V. McCanny and Yi Hu, “Rapid Design of Application Specific FFT Cores”, IEEE Trans. on Signal Processing, vol. 47, nº 5, pp. 13711381, May 1999.
DCIS 2004
 58 
Optimized FPGA implementation of trigonometric functions with large input argument
Javier Hormigo, Manuel Sanchez, Mario A. Gonzalez, Gerardo Bandera, and Julio Villalba Dept. of Computer Architecture, University of Malaga, Spain, hormigo@ac.uma.es
T RIGONOMETRIC function evaluation is widely used many current scientific applications such as
digital signal processing, image processing, simulation of physic phenomena, etc. An initial range reduction is required to perform forward trigonometric functions when the input angle is too large. The most usual method for range reduction involves two consecutive multiplications. The first one allows obtaining a scaled version of the reduced input angle, and the second one calculates the correct value for the reduced input argument. The CORDIC algorithm is a wellknown method for computing trigonometric functions. For the sine and cosine computation, a vector (1, 1/k) is rotated over the input angle, using iterative rotations over a fix set of given elementary angles, which are stored in a lookup table. In this paper, a new range reduction technique which is optimized for the CORDIC algorithm is proposed. To directly operate over the scaled version of the reduced input angle, the elementary angles are scaled by the same factor, before store them in the lookup table. Thus, the computation of the second multiplication is avoided. The designs based on our proposal require a classical CORDIC module where the table contains scaled elementary angles. Two basic implementation alternatives are considered: wordserial and pipeline implementation. Both alternatives have been implemented in FPGA to verify the improvement obtained with our proposal. For the wordserial implementation, the experimental results show a speedup of about 32% with the similar hardware cost. For the pipeline case, the classic approach requires about 32% more CLBs with similar cycle time and large latency.
DCIS 2004
 59 
Session 3b
Sensors and Smart Objects
Wednesday nov. 24 14h15 15h45, St Emilion Room
Chairs
Isabelle Dufour (CNRSIXL) Salvador Manich (U. Politècnica de Catalunya)
CMOS Buried Double Junction Active Pixel Sensor For HighSensitivity LowResolution Linear Arrays
P. Pittet, G. Carrillo, G.N. Lu, L. Hannati LENAC, Université Lyon 1, Villeurbanne, France, Patrick.Pittet@lenac.univlyon1.fr
I N this paper, we present the study and design of a CMOS active pixel sensor (APS) for a high
detectivity, lowresolution linear array, which is intended to be used as part of biochemical
microanalysis systems for imaging and spectrophotometric purposes. The proposed CMOS APS
implements a large buried double pn junction photodetector (BDJ) and charge sensitive regulated
cascode amplifiers. One benefit of using a BDJ photodetector rather than a simple photodiode is that
the former has two junctions for collecting carriers, thus providing higher sensitive response. Another
advantage of employing a BDJ detector is that it can be used as a wavelengthsensitive device, which
may be helpful for selectivity achievements in biochemical analysis applications.
The detector of the APS has an area of 100 µm x 300 µm. To deal with its inherent junction
capacitances related to its size, we propose a pixel circuitry integrating charge sensitive regulated
cascode amplifiers. This allows the use of integration capacitors much lower than the detector’s
parasitic capacitances, thus achieving much higher conversion ratio (160nV/e ^{} ) compared to
conventional architectures.
Time domain analysis and simulations are performed for dominant noise source identification and
quantification. At a supply voltage down to 3V, the proposed APS has a dynamic range larger than
60dB. For an integration time of 200ms, the detectivity of the proposed APS is evaluated to be 3.9 10 ^{1}^{2}
cm Hz ^{}^{½} W ^{}^{1} for the well channel and 2.3 10 ^{1}^{2} cm Hz ^{}^{½} W ^{}^{1} for the diffusion channel.
Figure 1 a) schematic and b) layout of the 0.8µm CMOS BDJ APS
DCIS 2004
 61 
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