Facultatea de Electronic, Telecomunicaii i Tehnologia Informaiei

Proiect de semestru la disciplina Sisteme Digitale

Automat de stare

Nume student Dulamita Cosmina Alexandra Grupa 2125

Descrierea structural a automatului de stare

library IEEE; use IEEE.std_logic_1164.all; entity fsm_cnt is end entity; architecture structural of fsm_cnt is signal a, inD, inC, inB, inA, inck, inCln: std_logic; signal outQ: std_logic_vector (3 downto 0); component nr74163 is port( A, B, C, D: in std_logic; clk, Cln: in std_logic; Q: out std_logic_vector(3 downto 0) ); end component; begin U1: nr74163 port map (A => inA, B => inB, C => inC, D => inD, clk => inck, Cln => inCln, Q => outQ); inD <= (not outQ(3)) or (outQ(1)); inC <= outQ(3); inB <= outQ(2) or outQ(1); inA <= outQ(0) or outQ(2); gen_clock: process begin inck <= '0'; wait for 1 ns; inck <= '1'; wait for 1 ns; end process; gen_A: process begin a <= '0'; wait for 20 ns; a <= '1'; wait for 20 ns; end process; gen_Cln: process begin inCln <= '1'; wait for 1 ns; inCln <= '0'; wait for 2 ns; inCln <= '1'; wait; end process; end structural;

Testbench automat
library ieee; use ieee.std_logic_1164.all; entity testautomat is end testautomat; architecture testbench of testautomat is component automatstare port( A, B, C, D: in std_logic; clk, Cln: in std_logic; Q: out std_logic_vector(3 downto 0) ); end component; signal a, inD, inC, inB, inA, inck, inCln: std_logic; signal outQ: std_logic_vector (3 downto 0); begin

U1: autom port map ( A=>inA, B=>inB, C=>inC, D=>inD, clk=>inclk, Cln=>inCln, Q => outQ); gen_inA: process begin inck <= '0'; wait for 15 ns; inck <= '1'; wait for 15 ns; end process; gen_Cln: process begin inCln <= '20'; wait for 10 ns; inCln <= '0'; wait for 20 ns; inCln <= '10'; wait; end process; inA <= '0'; wait for 1 ns; inA <= '1'; wait for 1 ns; end process ; gen_inB: process; begin inB<= '0'; wait for 1.3 ns; inB<='1'; wait for 1.3 ns;

end process; gen_inC: process begin inC<= '0'; wait for 2 ns; inC<= '1'; wait for 2 ns; end process; gen_inD: process begin inD<='0'; wait for 3 ns; inC<= '1'; wait for 3 ns; end process; end testbench;

Descriere comportamentala Bistabil D

library IEEE; use IEEE.std_logic_1164.all; entity DFF is port (Preset: in Bit; Clear: in Bit; Clock: in Bit; Data: in Bit; Q: out Bit; QBar: out Bit); end DFF; architecture Dataflow of DFF is signal A ,B ,C ,D: Bit; signal QInt, QBarInt: Bit; begin A <= not (Preset and D and B) after 1 ns; B <= not (A and Clear and Clock) after 1 ns; C <= not (B and Clock and D) after 1 ns; D<= not ( C and Clear and Data) after 1 ns; QInt <= not (Preset and B and QBarInt ) after 1 ns; QBarInt <= not (QInt and Clear and C) after 1 ns; Q <= QInt; QBar <= QBarInt; end;

Testbench Bistabil D
library IEEE; use IEEE.std_logic_1164.all; entity DFF is port (Preset: in Bit; Clear: in Bit; Clock: in Bit; Data: in Bit; Q: out Bit; QBar: out Bit); end DFF; architecture Dataflow of DFF is signal A ,B ,C ,D: Bit; signal QInt, QBarInt: Bit; begin A <= not (Preset and D and B) after 1 ns; B <= not (A and Clear and Clock) after 1 ns; C <= not (B and Clock and D) after 1 ns; D<= not ( C and Clear and Data) after 1 ns; QInt <= not (Preset and B and QBarInt ) after 1 ns; QBarInt <= not (QInt and Clear and C) after 1 ns; Q <= QInt; QBar <= QBarInt; end;library IEEE; use IEEE.std_logic_1164.all; entity DFF is port (Preset: in Bit; Clear: in Bit; Clock: in Bit; Data: in Bit; Q: out Bit; QBar: out Bit); end DFF; architecture Dataflow of DFF is signal A ,B ,C ,D: Bit; signal QInt, QBarInt: Bit; begin A <= not (Preset and D and B) after 1 ns; B <= not (A and Clear and Clock) after 1 ns; C <= not (B and Clock and D) after 1 ns; D<= not ( C and Clear and Data) after 1 ns; QInt <= not (Preset and B and QBarInt ) after 1 ns; QBarInt <= not (QInt and Clear and C) after 1 ns; Q <= QInt; QBar <= QBarInt; end;

Descrierea comportamentala MUX 8:1

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX8_1 IS PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DOUT:OUT STD_LOGIC); END MUX8_1; ARCHITECTURE BEH123 OF MUX8_1 IS BEGIN PROCESS(DIN,SEL) BEGIN CASE SEL IS WHEN"000"=>DOUT<=DIN(0); WHEN"001"=>DOUT<=DIN(1); WHEN"010"=>DOUT<=DIN(2); WHEN"011"=>DOUT<=DIN(3); WHEN"100"=>DOUT<=DIN(4); WHEN"101"=>DOUT<=DIN(5); WHEN"110"=>DOUT<=DIN(6); WHEN"111"=>DOUT<=DIN(7); WHEN OTHERS=> DOUT<='Z'; END CASE; END PROCESS; END BEH123;