Objective

To give students more detail and give more knowledge about the JFET and how JFET work. Learn more effective and practically about JFET transistor. Know how to use the JFET in electronic circuit.

INTRODUCTION

For the field- effect transistor, the relationship between input and output quantities is nonlinear due to the squared term in Shockleys equation. Linear relationship result in straight line when plotted on a graph of one variable versus the other, whereas nonlinear functions result in curves as obtained for the transfer characteristics of a JFET. The nonlinear relationship between ID and VGS can complicate the mathematical approach to the dc analysis of FET configurations. A graphical approach may limit solutions to tenths-place accuracy, but it is a quicker method for most FET amplifiers. Since the graphical approach is in general the most popular, the analysis of this chapter will have a graphical orientation rather than use direct mathematical techniques. Another distinct difference between the analysis of BJT and FET transistor is that: The input controlling variable for a BJT transistor is a current level, whereas for the FET a voltage is the controlling variable. In both cases, however, the controller variable on the output side is a current level that also defines the important voltage levels of the output circuit. The general relationships that can be applied to dc analysis of all FET amplifiers are IG = 0A And ID = IS For JFETS and the depletion-type MOSFETs and MESFETs, Shockleys equation is applied to relate the input and output quantities : ID = IDSS(1-VGS/VP)^2 For enhancement-type MOSFERs and MESFETs, the following equations is applicable : ID = k(VGS-VT)^2 It is particularly important to realize that all of the equations above are for the device only! They do not change with each network configuration so long as the device is in the active region. The network simply defines the level of current and voltage associated with the operating point through its own set of equations. In reality, the dc solution of BJT and FET networks is the solution of simultaneous equations established by the device and the network. The solution can be determined using a mathematical or graphical approach-a fact to be demonstrated by the first few networks to be analyzed.

PART A:Answer all question

Q1.

The self-bias configuration eliminate the need for _________ dc supplies

(a) two (b) three (c) zero (d) one Answer: (a )

Q2.

For dc analysis,the capacitor can again be replace by ____________ and the resistor RG replaced by a ____________ equivalent since IG = 0 A.

(a) short circuit ; open circuit (b) open circuit ;open circuit (c) open circuit ; short circuit (d) short circuit ; short circuit Answer: (c)

Q3.

Which of following are true of a self bias configuration compared to a fixed-bias configuration?

(a) VGS is function of the output current ID (b) A resistor RS is added (c) One of the dc supplies is eliminated 2

(d) All of the above Answer: (d)

Q4.

Which one of following represents the voltage level of VGS in a self-bias configuration?

(a) VP (b) VGS(off) (c) VG (d) VS Answer: (d)

Q5.

In a certain self-bias circuit,RD = 3.3k,IDSS = 8mA, VP = -6 V,VDS = 8.82 V, VDD = 20V and IDQ = 2.6 mA,RS is

(a) 2.0 k (b) 1.0 k (c) 2.0 k (d) 1.5 k

Answer: ( b )

PART B : SHORT ANSWER Fill in the blanks as appropriate

1.The JFET is ________________________(a unipolar device and a voltage-contolled device)

2.The channel of a JFET is between the________________________(drain and source)

3.A JFET always operates with__________________________ (the gate-to-source pn junction reverse-biased)

4.The constant-current region of an FET lies between_______________________ (cuttoff and saturation)

5.At cutoff,the JFET channel is____________________________ (completely closed by the depletion region)

6.The self-bias configuration eliminates the need for ________________________ (two dc supplies)

7.All voltages with a single subscript define a voltage from a specified point to ground_______________________(ground)

8.The analysis of p-channel FET is same as thataplied to n-channel FET except for the fact that all the voltages will have the_____________________(opposite polarity) and the current the_________________________(opposite direction)

Part c: answer all question Covalent and intrinsic Material 1.Describe the atomic structure of copper and discuss why it is a good conductor and how its structure is different from that of silicon. The atomic number of copper is 29, which means it has 29 protons in the middle and 29 electrons moving around the outside. (The 29 negative charges of the electrons and the 29 positive charges of the protons balance out, so the atom is neutral when all of its electrons are in place.) Copper has two electrons in the innermost shell, eight in the next shell, eighteen in the third shell, and one in the fourth shell. This means that the first three shells each have as many electrons as they can hold, and the fourth shell has one lonely electron. (The fourth shell can hold up to 32 electrons.) Because this one lonely electron is all by itself in the outer shell, it can easily separate from the rest of the atom and go roaming around, which makes copper a very good conductor. The atomic number of silicon is 14, which means it has 14 protons in the middle and 14 electrons moving around the outside. Silicon has two electrons in the innermost shell, eight in the next shell, and four in the third shell. This means that the first two shells are completely full, and the third shell has four electrons, out of the 18 that can fit in the third shell of an atom. Something about having four electrons in that outer shell makes the shell more stable than copper's outer shell with its one lonely electron, so the electrons in the silicon atom don't wander off as easily. Since the silicon atom has a fairly firm grip on its electrons, silicon is not as good a conductor as copper is. Energy Level. 2. If 48 eV of energy is required to move a charge through a potential difference of 12 V, determine the charge involved. W = QV Q = W/V Q = 48/12 = 4 coulomb

Extrinsic Material: n-Type and p-Type Materials. 3. Describe the difference between n-type and p-type semiconductor materials. N-type material is created by introducing impurity element that have five valence electron (pentavalent), such as antimony, arsenic, and phosphorus. Diffused impurities with five valence electron are called donor atoms. P-type material is forming by doping a pure germanium or silicon crystal with impurity atoms having three valence electron. The elements most frequently used for this purpose are boron, gallium, and indium. The diffused impurities with three valence electrons are called acceptor atoms.

Semiconductor Diode. 4. Describe in your own word the condition established by forward- and reverse-bias conditions on a p-n junction diode and how the resulting current affected. Forward bias is established by applying the positive potential to the p-type material and the negative potential to the n-type material. The force will push the electrons in the n-type material and the hole in the p-type material to recombine with the ions near the boundary and reduce the width of the depletion region. Reverse bias is establish by applying positive terminal is connected n-type material and negative terminal is connected to p-type material. This resulting a wide depletion region until its to wide to lets the electrons and hole to cross over the depletion region.

Ideal versus Practical 5. Describe on your own word the meaning of word ideal as applied to a device or a system. IDEAL theory means that the device or system is working perfectly without any interference from anything. Whether it means from the device itself or the surrounding area. IDEAL device or system also means that, its what we really needed to see the maximum output of the device or what its limits when its operationally.

PART D : calculations Question...

Figure 1 1. Refer to figure Q1 determine, if IDSS = 8 mA and VP = -5 V. a) Plot the tranfer curve on the graph paper provided.
b) Given the Q-point for the circuit. VGSQ = -1.8 mA and VD = 12 V, determine the

values of RD and RS.

Figure 2 2. For the network of the figure 2 determine: a. VGSQ and IDQ. b. VDS, VD and VS.

Figure 3 3. Given the measurement VS = 1.7 V for the network of figure 3, determine: a. IDQ. b. VGSQ. c. IDSS. d. VD. e. VDS.

Figure 4 4. For the network of figure 4, determine: a. ID. b. VDS. c. VD. d. VS.

Figure 5 5. Find Vs for the network of figure 5.

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Conclusions
1. A fixed-bias configuration has, as the label implies, a fixed dc voltage from gate to source to establish the operating point. 2. The nonlinear relationship between the gate-to-source voltage and teh drain current of a JFET requires that a graphical or mathematical solution (involving the solutions of two simulaneous equations ) be used to determine the quiescent point of operation. 3. All voltages with a single subscript define a voltage from a specified point to ground. 4. The self-bias configuration is determine by an equation for VGS that will always pass through the origin. Any other point determined by the biasing equation will establish a straight line to represent the biasing network. 5. For the voltage-divider biasing configuration, one can always assume that the gate current is 0 A to permit an isolation of the voltage-divider network from the output section. The resulting gate-to-ground voltage will always be positive for an n-channel JFET and negative for pchannel JFET. Increasing values of Rs result in lower quiescent values of ID and more negative values of VGS for an n-channel JFET. 6. The method of analysis applied to depletions-type MOSFETs is the same as applied to JFETs, with the only difference being a possible operating point with an ID level above the IDSS value. 7. The characteristics and method of analysis applied to enhancement-type MOSFETs are entirely different from those of JFETs and deplition-type MOSFETs. For values fo VGS less than the threshold value, the drain current is 0A. 8. When analyzing networks with a variety of devices, first work with the region of the network that will provide a voltage or current level using the basic relationship associated with those devices. Then use that level and the appropriate equations to find other voltage or current levels of the network in the surrounding region of the system. 9. The design process often requires finding a resistance level to establish the desired voltage or current level. With this in mind, remember that a resistance level is defined by the voltage across the resistor divider by the current through the resistor. In the design process, both of these quantities are often available for a particular resisitive element. 10. The ability to troubleshoot a network requires a clear, firm understanding of the terminal behavior of each of the devices in the network. That knowlegde will provide an estimate of the working voltage levels of specific points of the network, which can be checked with a voltmeter. The ohmmeter sections of a multimeter is particularly helpful in ensuring that there is a true connection between all the elements of the network. 11. The analysis of P-channel FETs is the same as that applied to n-channel FETs except for the fact that all the voltage will have the opposite polarity and the current the opposite dircetion.

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