Layout and EMC

• Buck & Boost layout

• EMC filter for DC/DC
• EMC test results (Conducted&Radiated)

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 4-Layer PCB – Layer Placement

Undesired Desired

Layer #1 – Power Component Layer #1 – Power Component

Layer #2 – Small Signal Layer #2 – GND

Layer #3 – GND Layer #3 – Small Signal

Layer #4 – Small signal / controller Layer #4 – Small signal / controller

Power

Signal

GND
PCB capacitance
High current loop
Pulsating current loop
• Place ground or DC voltage layer between power layer and
small signal layer

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 Small Signal Traces on Reference Layer
• If the small signal traces have to be routed on the reference
layer, use short traces with proper direction:
Desired Undesired
Reference Layer Reference Layer

current

current

PWM IC MOSFET

Coupled AC
current return path

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 Parasitic Inductance in the Current Paths
Trace Inductance and Example Layout (Buck)
VIN+

ST LF
ST
SB SW
SW
VIN+ D
CHF

CHF
SB D PGND

0.1uF – 10uF Minimize this loop area!

Ceramic Capacitor
PGND

• Minimize loop between HF capacitor and MOSFETs

• It is desirable to keep CHF, top FET and bottom FET on the same layer
• Use multiple vias for power connection

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 Separate the input / output grounds

ST
LF
CIN CHF
ESRo

PCB SB R
Impedance
Co Vo

- + - + - + Top Layer

PCB Insulation Layer

Internal GND Layer

Via
impedance
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Step-down Layout Example from LT3481 data sheet

SW

IN

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 Boost Converter Current Paths

Continue Current
High dv/dt node Pulsating Current
LF SW D
Vo+
Vo
VIN
CIN CHF C
o
SB
Load

PGND

• Minimize the critical pulsating current loop on the output side

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 Output Noise Decoupling Capacitor (Boost)

LF SW D LF SB SW

CHF Vo+
SB
CHF
PGND

0.1uF – 10uF
Minimize Ceramic Capacitor
PGND this loop
area
(a) (b)

• Minimize the critical pulsating current loop on the output side

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Boost Layout Example from LT3489 data sheet

SW

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 Land Patterns of Power Components
Undesired Desired

+ -
C R/C/D/L

+ -

C R/C/D/L

FET

Connected Via Connected Via

• Use wide / short copper trace for power components

• Use multiple vias for inter-layer connections
• Avoid improper use of “thermal relief”
• Minimize resistance and inductance
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 Examples of a 2-Phase DC/DC Power Stage
Air Flow For dual output, split here

GND D Vo
Vo L2
QB1 QB1 Vin
CHF1
Cout Rsen2
SW1
QT1
Rsen1
L1
Cout
CIN Cout CIN
GND D
GND GND Cout
VIN L2 CHF1 QB1 QB1
Rsen2
QT2 SW1
SW2 QT1
Cout Rsen1
CHF2 QB2 QB2
GND D L1

Internal Internal
GND Layer GND Layer

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Layout of Dual Output 2-Phase Buck with Dual SO8 FETs
Rsen1
Vo1
L1
SW1
Cout
D1

CIN
VIN
CIN

GND
D2 Cout
SW2
L2
Vo2

Rsen2

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Decoupling Capacitor and Separated Grounds

LTC3729
Local GND under controller
RUN/SS
R SEN1+ TG1
RSENSE C
R SEN1- SW1
C EAIN

SGND Island
BG1

ITH INTVCC
C C
SGND PGND
VDIFF BG2
PGND
SW2
Plane
R SEN2- TG2
RSENSE C
R SEN2+

Shortest Distance

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 Signal Ground and Power Ground

• Components connected to following pins use SGND:

- EAIN, RUN/SS, ITH, UVADJ, PHAMD, PLLIN, PLLFTR, FCB, CLKOUT

•Components connected to following pins use PGND:

- BOOST, +5V, PGND

•The SGND and PGND can be tied together underneath the IC.

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 QFN Package Controller Layout
Example
LTC3731
PGND
SGND

SGND

INTVCC C
PGND

PGND

Vias
Vias

• Exposed SGND pad must be soldered to PCB

• Use multiple vias to connect SGND pad to both SGND
and PGND layers
• PGND pin also connects to SGND pad underneath the IC

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 Gate Driver Traces
LTC3729
Route together
BOOST1 QT
TG1

SW1

INTVCC
BG1

QB

C If no GND plane present

Route BG1-return as
PGND separate trace
Automatically coupled AC
ground return current

PGND
Plane

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 IC Signal Trace Width
Following are the trace width values we use in
Polyphase demo board:

20 mils – TG, BG, SW

25 mils - +5V, Vcc, PGND

15 mils – Current sensing, feedback, ITH, etc.

10 mils – Short traces that directly connected to IC pads

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 Current Sensing Traces

RSENSE
LF
Vo+
Direct trace connection.
Do NOT use via.

LTC3729
This via should NOT
touch any other internal Vo+
R SENSE- copper plane.
C
R SENSE+

• Kelvin sensing of the current signal

• Keep current sensing traces away from noisy traces / copper
area or use ground layer for shielding.

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 Sensitive Traces and Noisy Traces
• Most sensitive traces:
Current sensing (SENSE+/-), EAIN, ITH, SGND

-Sense+ / - traces for each channel should be routed together

With minimum trace spacing. The filter capacitor should be as close to
IC pins as possible. The filter resistor should be close to filter capacitor.
- Keep sensitive traces away from noisy traces.

• Sensitive traces:
Vos+/-, DIFFOUT, PLLFTR, CLKOUT
-CLKOUT is a sensitive trace but it is also a noisy trace. So keep it away from
other small signal sensitive traces.

• Most noisy traces:

SW, TG, BOOST, BG
-Keep them away from sensitive traces.
-Avoid overlapping between large SW copper area and sensitive traces in two
neighborhood layers.
- For each channel, route the SW and TG trace together with minimum space.

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 Summary - Layout Checklist
• Plan of the layout:
– Location of the supply / load / bulk capacitors
– # of layers / layer placement / copper thickness
• Power stage layout:
– Power component placement
– Power component land patterns
– Identify pulsating current paths
– Decouple capacitor close to MOSFET
– Short / wide copper trace and multiple vias for high current
• Controller circuit layout:
– Decoupling capacitors close to pins
– Separate signal / power grounds
– Current sensing
– De-couple sensitive and noisy traces
– Gate driver traces
– Select proper trace width

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What is wrong on this board?

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EMC filter and test results

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 Conducted Emission
#1 Problem to solve with DC/DC converter
Optimum antenna needs λ/4 loop size @100MHz -> 75cm in air
In PCB FR4 (εr=4.7) -> ~35cm
For strong radiation the cable is needed => do not let noise
enter the cable!!!
EN55022 c (q-peak) & d (average) Class B Limits

0.15 -0.5MHz: 66-56dBµV(Q-pk) 56-46dBµV(∅∅)

0.5 -5MHz: 56dBµV(Q-pk) 46dBµV(∅ ∅)
5 -30MHz: 60dBµV(Q-pk) 50dBµV(∅ ∅66dBµV
)

0dBm ≡ 107dBµV in 50Ω System 60dBµV

56dBµV
7dBm ≡ 114dBµV

0.15 0.5 5 30 MHz

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LISN: Line Impedance Stabilization Network
Provides a defined impedance between DUT
And power source

L1
V+DUT
5µ
C1
V1
100n Vout

R1
50 V-DUT
Supply
AC 1

Use this for checking input ripple in your own lab.

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 Conducted Emission set-up
LISN

DUT

LISN
DUT Load load box

Load resistor

Tests performed at HST Elektronik www.HST-elektronik.de

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 Radiated Emission set-up
Antenna 3m distance

PSU
DUT

Cable from supply

Antenna for horizontal and vertical
measurements (plot of the worse shown)

Plot shows the PEAK scan from 30MHz-1GHz;

Limit line is Q-Peak (120kHz band width)
Chamber without absorber – harder test condition due to reflections

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LT3493EDCB Demo Board
24V to 3.3V@1A
Conducted Emission Q-peak
0.15-30MHz
average

Test without EMC filter:

Peak 88dBµV @ 748kHz
→ 38dB above limit

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 LT3493EDCB Demo Board
Bead: 220Ω@100MHz
24V to 3.3V@1A 3.3µF 10µH
Conducted Emission
24V PSU
0.15-30MHz And LT3493
Test with additional L=10uH, LISN 750kHz
C=3.3uF 50V 1210 input filter: 1µF
Filter gives approx.: 10nF
Peak 41.5dBµV @748kHz 3.3V
20log (Xc/(Xc + X_L)) ~ -50dB
8.5dB below limit 1A load

47dB lower

10uH
Bead: 220Ω

3.3uF 50V 1210 X5R

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In time domain:LT3493 input ripple

Ripple at
Connector with
filter

Ripple at IC

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 LT3493EDCB Demo Board
Radiated Emission 30MHz-1GHz 3m distance peak scan
24V to 3.3V@1A
5022-f3 Q-peak limit
48.5dBµV/m
41.5dBµV/m

Reference: no DUT
5022f Q-peak limit for 3m(120kHz):
30 -230MHz: 41.5dBµV/m
230MHz –1GHz: 48.5dBµV/m

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 LT3481EMSE Demo Board
24V to 3.3V@2A fsw=500kHz
Conducted Emission 0.15-30MHz
Test without EMC filter:
Peak 82dBµV
→ 26dB above limit

66dBµV
56dBµV
46dBµV

Linear Technology Applications

LT3481EMSE Demo Board
High ESR Elco to
24V to 3.3V@2A fsw=500kHz Ferrite bead Damp cable
Conducted Emission 0.15-30MHz
Radiated Emission 30MHz-1GHz
Test with additional L=10uH,
C=3.3uF 50V 1210 input filter

Peak=42dBµV/m ∅=32dBµV/m
Peak & ∅ 14dB below limit
Conducted Emission
Radiated Emission

10dB attenuator in software

Result should be 10dB lower
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LTC3827-1 Demo Board
Conducted Emission 0.15-30MHz
24V to 3.3V@4.4A & 8.5V@2.5A 35W
No EMC-filter: pk 82,7dBµV ∅80dBµV @380kHz

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 LTC3827-1 Demo Board
Conducted Emission 0.15-30MHz Input
24V to 3.3V@4.4A & 8.5V@2.5A 35W + -

10nF
Filter: L_f=10uH; C_f=2x 4.7µF
bead
Pk: 41dBµV ∅37.3dBµv @380kHz
L_f

C_f

No beads in both outputs

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LTC3827 input ripple

Ripple at connector
With filter

Ripple without
Filter. Low due to
Anti-phase switching

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LTC3827-1 Demo Board Ω
4.7Ω
24V to 3.3V@4.4A & 8.5V@2.5A
Radiated Emission 30MHz – 1GHz

5022-f3 Q-peak limit

48.5dBµV/m
41.5dBµV/m

Boost-pin resistor can

slow down rising edge: Quasi-peak results:
43.9MHz: 28.5dBµV/m
157MHz: 35.3dBµV/m 94.4MHz: 34,5dBµV/m
Reduction of 2-5dB possible 157MHz: 39.3dBµV/m

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 Layout example for LT1940EFE with EMC filters
Filter cap
Output 1 through vias

ferite
Low frequency
Filter Out1
1µF..10µF
SW1
GND
1µH .. 15µH

High f filter: Lf
Ferite
100Ω@100MHz
Vin Input
SW2
Through via
Several C Out2 GND
100pF
10nF ferite
100nF

Output 2 through vias Filter cap

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 Complete Step-Down with EMI filter

Input filter: L2,C10

FB1,C9,C11 Output filter:
FB2,C5,C12

U1,D1,C3 form the high frequency loop

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LT3480 DC1212A-A 5V/2A demo board
Vin 6.3V – 38V with transients up to 60V

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 Output filter

Input filter

Output

Input

GND frame for optional shielding

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Layer 2: GND plane under DC/DC
with slit to separate the shielding Output
return current from the system GND

Input

Output
Input & Output routed in L3.

Input

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 150kHz to 30MHz Conductive Emission

90dBµV 100dBµV

90dBµV

50dBµV
50dBµV

With EMC filter W/O EMC filter

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 LT3480 12V to 5V@2A 3m Radiated Emission
Qasi-peak (120kHz) results:
45.7MHz: 24.0dBµV/m
93.6MHz: 20.5dBµV/m
121.4MHz: 21.5dBµV/m Peak scan result
141.5MHz: 18.2dBµV/m

Reference peak scan

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 LT3480 24V to 5V@2A 3m Radiated Emission
Qasi-peak (120kHz) results:
43.7MHz: 28.5dBµV/m
56.0MHz: 23.8dBµV/m
95.3MHz: 24.2dBµV/m

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Regulatory agencies perform EMC testing in fixed, well
defined bandwidths according to the CSPIR 16-1
specification.

Frequency Band Measurement Bandwidth

(-6dB bandwidth)
Band A 220Hz
9kHz to 150kHz
Band B 9kHz
150kHz to 30MHz
Bands C and D 120kHz
30MHz to 1GHz

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 Spread Spectrum Frequency Modulation

Instantaneous frequency variation by much more

than the measurement BW LTC6908 clock chip
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