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CHAPTER 4

4.1

66

(a) T 1 = B'C, T 2 = A'B, T 3 = A + T 1 = A + B'C, T 4 = D T 2 = D (A'B) = A'BD' + D(A + B') = A'BD' + AD + B'D F 1 = T 3 + T 4 = A + B'C + A'BD' + AD + B'D With A + AD = A and A + A'BD' = A + BD':

F 1 = A + B'C + BD' + B'D Alternative cover: F 1 = A + CD' + BD' + B'D

F 2 = T 2 + D' = A'B + D'

ABCD

T 1

T 2

T 3

T 4

F 1

F 2

0000

0

0

0

0

0

1

0001

0

0

0

1

1

0

0010

1

0

1

0

1

1

0011

1

0

1

1

1

0

0100

0

1

0

1

1

1

0101

0

1

0

0

0

1

0110

0

1

0

1

1

1

0111

0

1

0

0

0

1

1000

0

0

1

0

1

1

1001

0

0

1

1

1

0

1010

1 0

0

1

1

1

1011

1 1

0

1

1

0

1100

0

0

1

0

1

1

1101

0

0

1

1

1

0

1110

0

0

1

0

1

1

1111

0

0

1

1

1

0

CD
CD
 

C

   

00

01

11

10

AB

A

00

01

11

10

M 0 M 1 M 3 M 2 1 1 M 4 M 5 M
M 0
M 1
M 3
M 2
1 1
M 4
M 5
M 7
M 6
1 1
1 1
M
M 12
M 13
15
M 14
1 1
M 8
M 9
M
11
M 10
1 1
1 M M 12 M 13 15 M 14 1 1 M 8 M 9 M

D

F 2 = A'B + D'

B

A

CD C 00 01 11 10 M 0 M 1 M 3 M 2 00
CD
C
00
01
11
10
M 0
M 1
M 3
M 2
00
1
1 1
M
M 5
M
M 6
4
7
01
1
1
M
M
12
M 13
15
M 14
11
1
1
1
1
M 8
M 9
M 11
M 10
10
1 1
1
1

D

B

F 1 = A + B'C+ B'D + BD'

B10 1 1 1 1 D B F 1 = A + B'C+ B'D + BD'

D

F 1 = A + CD' + B'D + BD'

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

67

4.2

 
 
 

F(A, B, C, D) = ((AD)(A+ BC))

 

= AD + (A+ BC)

= AD + A (BC)

= AD + AB+ AC

 

C 1 (A, B, C, D) = ((AD) (A+ BC))

 

= (AD)+ (A+ BC)

= (A + D) + A (BC)

= A + D+ AB+ AC

= A (1 + B+ C) + D

= A + D

4.3

(a) Y i = (A i S' + B i S)E' for i = 0, 1, 2, 3

(b) 1024 rows and 14 columns

4.4

(a)

F(A, B, C)

=

(0, 1, 2, 7)

4.4 (a) F ( A , B , C ) = (0, 1, 2, 7) Simplified

Simplified SOP form:

F(A, B, C)

= AC+ AB+ ABC

= A(B+ C) + ABC

= A(BC) + ABC

= A XNOR (BC)

= A (BC)

A ′ ( BC ) ′ + ABC = A XNOR ( BC ) = A

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

(b)

F(A, B, C) = (1, 3, 5, 7)

(b) F ( A , B , C ) = (1, 3, 5, 7) Simplified SOP

Simplified SOP form:

F(A, B, C) = C C

F

4.5

x

y

z

A

B

C

0

0

0

0

1

0

0

0

1

0

1

1

0

1

0

1

0

0

0

1

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

0

1

1

0

1

0

1

1

1

1

1

1

0

 

A

=

(2, 5, 6, 7)

1 1 1 1 0   A = (2, 5, 6, 7) A = xz +

A

= xz + yx

B

= (0, 1, 3, 4, 7)

A = xz + yx ′ B = (0, 1, 3, 4, 7) = y ′

=

yz+ yz + xz

= (y z) + xz

C

=

(1, 4, 6)

z = ( y ⊕ z ) + x ′ z C = (1, 4, 6)

= xz+ xyz

68

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

69

69 4.6 xyz F 000 0 001 0 010 0 011 1 100 0 101 1

4.6

xyz

F

000

0

001

0

010

0

011

1

100

0

101

1

110

1

111

1

x

A

y yz x 00 01 11 10 m m m m x 0 1 3
y
yz
x
00
01
11
10
m
m
m
m
x
0
1
3
2
0
1 z
y
m
m
m
m
z
4
5
7
6
1
1
1 x
1
y
3 2 0 1 z y m m m m z 4 5 7 6 1

z

F = xz + yz + xy

module Prob_4_6 (output F, input x, y, z); assign F = (x & z) | (y & z) | (x & y); endmodule

F = (x & z) | (y & z) | (x & y); endmodule F Digital

F

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.7

(a)

ABCD

wxyz

0000

0000

0001

0001

0011

0010

0010

0011

0110

0100

0111

0101

0101

0110

0100

0111

1100

1000

1101

1001

1111

1010

1110

1011

1010

1100

1011

1101

1001

1110

1000

1111

CD C CD C AB 00 01 11 10 00 01 11 10 m m
CD
C
CD
C
AB
00
01
11
10
00
01
11
10
m
m
m
m
m
m
m
m
0
1
3
2
0
1
3
2
00
00
m
m
m
m
m
m
m
m
4
5
7
6
4
5
7
6
01
01
1
1
1
1
B
m
m
m
m
m
m
m
m
12
13
15
14
12
13
15
14
11
1
1
1 11
1
A
A
m
m
m
m
m
m
m
m
8
9
11
10
8
9
11
10
10
1
1
1 10
1
1
1
1
1
D
D
x = AB' + A'B = A
B
w = A
CD C AB 00 01 11 10 m m m m 0 1 3 2
CD
C
AB
00
01
11
10
m
m
m
m
0
1
3
2
00
1
1
m
m
m
m
4
5
7
6
01
1
1
m
m
m
m
12
13
15
14
11
1
1
A
m
m
m
m
8
9
11
10
10
1
1
13 15 14 11 1 1 A m m m m 8 9 11 10 10

D

B

y = A'B'C A'BC' + ABC + AB'C'

= A'(A B) + A(B C)' = A B C = X C A w
=
A'(A
B) + A(B
C)'
=
A
B
C
=
X
C
A
w
x
B
y
C
z
D
CD
CD

AB

00

A

01

11

10

C

B C = X C A w x B y C z D CD AB 00
 

00

 

01

 

11

 

10

m

0

m

1

 

m

3

m

2

   

1

   

1

m

4

m

5

 

m

7

m

6

 

1

   

1

 

m

12

m

13

 

m

15

m

14

   

1

   

1

m

8

m

9

 

m

11

m

10

 

1

   

1

 
 

D

 
 

D

z = A = y

B C D
B
C
D

B

B

70

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

(b)

module Prob_4_7(output w, x, y, z, input A, B, C, D); always @ (A, B, C, D) case ({A, B, C, D})

4'b0000:

{w, x, y, z} = 4'b0000;

4'b0001:

{w, x, y, z} = 4'b1111;

4'b0010:

{w, x, y, z} = 4'b1110;

4'b0011:

{w, x, y, z} = 4'b1101;

4'b0100:

{w, x, y, z} = 4'b1100;

4'b0101:

{w, x, y, z} = 4'b1011;

4'b0110:

{w, x, y, z} = 4'b1010;

4'b0111:

{w, x, y, z} = 4'b1001;

4'b1000:

{w, x, y, z} = 4'b1000;

4'b1001:

{w, x, y, z} = 4'b0111;

4'b1010:

{w, x, y, z} = 4'b0110;

4'b1011:

{w, x, y, z} = 4'b0101;

4'b1100:

{w, x, y, z} = 4'b0100;

4'b1101:

{w, x, y, z} = 4'b0011;

4'b1110:

{w, x, y, z} = 4'b0010;

4'b1111:

{w, x, y, z} = 4'b0001;

endcase

endmodule

Alternative model:

module Prob_4_7(output w, x, y, z, input A, B, C, D); assign w = A; assign x = A ^ B); assign y = x ^ C; assign z = y ^ D; endmodule

71

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

72

4.8 (a) The 8-4-2-1 code (Table 1.5) and the BCD code (Table 1.4) are identical for digits 0 – 9.

(b)

8421

Gray

ABCD

wxyz

0000

0000

0001

0001

0010

0011

0011

0010

0100

0110

0101

0111

0110

0101

0111

0100

1000

1100

1001

1101

CD
CD

AB

00

A

01

11

10

C

11 10
11
10

00 01

m

0

m

1

m

3

m

2

m

4

m

5

m

7

m

6

m

12

m

13

m

15

m

14

m m 8 9 1 1
m
m
8
9
1
1
 

m

11

m

10

m 14 m m 8 9 1 1   m 11 m 10 D w =

D

w = AB'C'

CD
CD

AB

00

A

01

11

10

C

m 11 m 10 D w = AB'C' CD AB 00 A 01 11 10 C

11

10

00

01

m

0

m

1

m m 3 2 1 1
m
m
3
2
1
1
 
m m 4 5 1 1
m
m
4
5
1
1
 

m

7

m

6

m

12

m

13

m

15

m

14

m

8

m

9

m

11

m

10

 

D

 

y = A'BD' + A'B'D

CD C 00 01 11 10 m m m m 0 1 3 2 00
CD
C
00
01
11
10
m
m
m
m
0
1
3
2
00
m
m
m
m
4
5
7
6
01
1
1
1
1
B
B
m
m
m
m
12
13
15
14
11
A
m
m
m
m
8
9
11
10
10
1
1
D
x = AB'C' + A'B
C
AB CD
00
01
11
10
m
m
m
m
0
1
3
2
00
1
1
m
m
m
m
4
5
7
6
01
1
1
B
B
m
m
m
m
12
13
15
14
11
1
A
m
m
m
m
8
9
11
10
10
m m 12 13 15 14 11 1 A m m m m 8 9 11

D

z = A'C'D + BC'D + A'CD'

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.9

ABCD

a

b

 

c

d

 

e

f

g

 

0000

1

1

 

1

1

 

1

1

0

0001

0

1

1

0

0

0

0

0010

1

1

0

1

1

0

1

0011

1

1

1

1

0

0

1

0100

0

1

1

0

0

1

1

0101

1

0

1

1

0

1

1

0110

1

0

1

1

1

1

1

0111

1

1

1

0

0

0

0

1000

1

1

1

1

1

1

1

1001

1

1

1

1

0

1

1

   

C

   
CD
CD
 

01

 

11

10

 

00

00 m 0 1
00
m
0
1

m

1

m

3

m 2 1 m 6 1
m
2
1
m
6
1

01

m

4

m

5

m

7

 

m

12

m

13

m

15

m

14

11

     
 

m

9

m

11

m

10

10

     

AB

A

m 8 1
m
8
1
11 m 10 10       AB A m 8 1 D e = A'CD'

D

e = A'CD' + B'C'D'

73

CD C CD C AB AB 00 01 11 10 00 01 11 10 m
CD
C
CD
C
AB
AB
00
01
11
10
00
01
11
10
m
m
m
m
m
m
m
m
0
1
3
2
0
1
3
2
00
1
1
1
00
1
1
1
1
m
m
m
m
m
m
m
m
4
5
7
6
4
5
7
6
01
1
1
1
01
1
1
B
B
m
m
m
m
m
m
m
m
12
13
15
14
12
13
15
14
11
11
A
A
m
m
m
m
m
m
m
m
8
9
11
10
8
9
11
10
10
1
1
10
1
1
D
D

a = A'C + A'BD + B'C'D' + AB'C'

b = A'B' + A'C'D' + A'CD + AB'C'

CD C CD C AB AB 00 01 11 10 00 01 11 10 m
CD
C
CD
C
AB
AB
00
01
11
10
00
01
11
10
m
m
m
m
m
m
m
m
0
1
3
2
0
1
3
2
00
1
1
1
00
1
1
1
m
m
m
m
m
m
m
m
4
5
7
6
4
5
7
6
01
1
1
1
1
01
1
1
B
B
m
m
m
m
m
m
m
m
12
13
15
14
12
13
15
14
11
11
A
A
m
m
m
m
m
m
m
m
8
9
11
10
8
9
11
10
10
1
1
10
1
1
D
D

B

c = A'B + A'D + B'C'D' + AB'C'

d = A'CD' + A'B' C+ B'C'D' + AB'C' + A'BC'D

CD C AB 00 01 11 10 m m m m 0 1 3 2
CD
C
AB
00
01
11
10
m
m
m
m
0
1
3
2
00
1
m
m
m
m
4
5
7
6
01
1
1
1
m
m
m
m
12
13
15
14
11
A
m
m
m
m
8
9
11
10
10
1
1
m 12 13 15 14 11 A m m m m 8 9 11 10 10

D

B

f = A'BC' + A'C'D' + A'BD + AB'C'

CD
CD

AB

00

A

01

11

10

C

+ A'BD + AB'C' CD AB 00 A 01 11 10 C 11 10 00 01

11

10

00

01

m

0

m

1

   
 
m m 4 5 1 1
m
m
4
5
1
1
m m 3 2 1 1 m m 7 6 1
m
m
3
2
1
1
m
m
7
6
1
 

m

12

m

13

m

15

m

14

m m 8 9 1 1
m
m
8
9
1
1
 

m

11

m

10

 

D

B

g = A'CD' + A'B'C + A'BC' + AB'C'

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.10

ABCD

wxyz

0000

0000

0001

1111

0010

1110

0011

1101

0100

1100

0101

1011

0110

1001

0111

1000

1000

1000

1001

0111

1010

0110

1011

0101

1100

0100

1101

0011

1110

0010

1111

0001

CD C CD C AB 00 01 11 10 00 01 11 10 m m
CD
C
CD
C
AB
00
01
11
10
00
01
11
10
m
m
m
m
m
m
m
m
0
1
3
2
0
1
3
2
00
1 1
1 00
1
1
1
m
m
m
m
m
m
m
m
4
5
7
6
4
5
7
6
01
1
1 1
1 01
1
B
m
m
m
m
m
m
m
m
12
13
15
14
12
13
15
14
11
11
1
A
A
m
m
m
m
m
m
m
m
8
9
11
10
8
9
11
10
10
1
10
1
1
1
D
D

B

w = A'(B + C + D) + AB'C'D'

= A (B + C + D) CD C AB 00 01 11 10 m
= A
(B + C + D)
CD
C
AB
00
01
11
10
m
m
m
m
0
1
3
2
00
1
1
m
m
m
m
4
5
7
6
01
1
1
m
m
m
m
12
13
15
14
11
1
1
A
m
m
m
m
8
9
11
10
10
1
1
D
y =
CD' + C'D = C
D

x = B'(C + D) + CB'D'

= B (C + D) CD C AB 00 01 11 10 m m m
= B
(C + D)
CD
C
AB
00
01
11
10
m
m
m
m
0
1
3
2
00
1 1
m
m
m
m
4
5
7
6
01
1 1
B
B
m
m
m
m
12
13
15
14
11
1 1
A
m
m
m
m
8
9
11
10
10
1 1
13 15 14 11 1 1 A m m m m 8 9 11 10 10

D

z = D

74

For a 5-bit 2's complementer with input E and output v:

v = E

5-bit 2's complementer with input E and output v: v = E (A + B +

(A + B + C + D)

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.11

(b)

(a)

A

3

A 2

A 1

A 0

 

x

y

 

x

y

 

x

y

 

x

y

Half Adder

Half Adder

Half Adder

Half Adder

C

S

C

S

C

S

C

S

     
     
 
     
 
     
 
     

1

S C S C S C S       1 Note: 5-bit output A 3

Note: 5-bit output

A 3

1

A

2

1

A

1

1

A

0

1

 

x

y

 

x

y

 

x

y

 

x

y

Full Adder

Full Adder

Full Adder

Half Adder

B

D

B

D

B

D

B

D

     
     
 
     
 
     
 
     

75

Note: To decrement the 4-bit number, add -1 to the number. In 2's complement format ( add F h ) to the number. An attempt to decrement 0 will assert the borrow bit. For waveforms, see solution to Problem 4.52.

4.12

x

y

Diff.

Bout

0

0

0

0

0

1

1

0

1

0

1

1

1

1

0

0

0 1 1 0 1 0 1 1 1 1 0 0 Diff. = x ′

Diff. = xy + xy

x y

= x y

Bout = xy

Bin

Diff.

Bout

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

0

0

0

0

0

0

0

1

1

1

0

1

0

1

0

0

1

1

0

0

1

0

0

1

1

1

0

1

0

1

1

1

0

0

0

1

1

1

1

1

0 1 1 1 0 0 0 1 1 1 1 1 Bout = xy ′

Bout = xy+ yBin + xBin

Diff.

= x(y Bin)

+ x (y Bin)

76

= x y Bin

Bout

= (1, 4, 5, 7)

⊕ Bin) 76 = x ⊕ y ⊕ Bin Bout = (1, 4, 5, 7) 4.13

4.13

Sum

C

V

(a)

1101

0

1

(b)

0001

1

1

(c)

0100

1

0

0 1 (b) 0001 1 1 (c) 0100 1 0 Digital Design With An Introduction to

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.14

4.15

4.16

(d)

1011

0

1

(e)

1111

0

0

xor

AND

OR

XOR

10

+

5

+

5

+

10

= 30 ns

C 4

S 0

S 1

= C 13 + P 3 C 3

= C 13 + P 3 (C 12 + P 2 C 11 + P 2 P 1 C 10 + P 2 P 1 P 0 C 10 )

= C 13 P 3 C 12 + P 3 P 2 C 11 + P 3 P 2 P 1 C 10 + P 3 P 2 P 1 P 0 C 0

= P 0 C 0

= P 1 C 1

Using S i = P i C i

S

2

= P 2 C 2

S

3

= P 3 C 3

(a)

(C'G' i + p' i )'

= (C i + G i )P i = G i P i + P i C i = A i B i (A i + B i ) + P i C i

= A i B i + P i C i = G i + P i C i

= A i B i + (A i + B i )C i = A i B i + A i C i + B i C i = C i+1

4.17

(P i G' i ) C i

(b)

= (A i + B i )(A i B i )'

= (A' i B i + A i B' i )

C i = (A i + Bi)(A' i + B' i )

C i = A i

B i

C i = S i

C i

Output of NOR gate = (A 0 + B 0 )' = P' 0 Output of NAND gate = (A 0 B 0 )' = G' 0

S 1 = (P 0 G' 0 )

C 0

C 1 = (C' 0 G' 0 + P' 0 )'

as defined in part (a)

(a)

(C' i G' i + P' i )' = (C i + G i )P i = G i P i + P i C i = A i B i (A i + B i ) + P i C i

77

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

= A i B i + P i C i = G i + P i C i

= A i B i + (A i + B i )C i = A i B i + A i C i + B i C i = C i+1

(P i G' i )C i = (A i + B i )(A i B i )'C i = (A i + B i )(A' i + B' i )C i = (A' i B i + A i B' i )C i = A i B i C i = S i

(b)

Output of NOR gate = (A 0 + B 0 )' = P' 0

Output of NAND gate = (A 0 B 0 )' = G' 0

S 0 = (P 0 G' 0 )C 0 C 1 = (C' 0 G' 0 + P' 0 )'

as defined in part (a)

78

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.18

Inputs

Outputs

ABCD

wxyz

 

0000 1001

0001 1000

0010

0111

0011

0110

0100

0101

0101

0100

0110

0011

0111

0010

1000

0001

1001

0000

d(A, b, c, d) = (10, 11, 12, 13, 14, 15)

79

CD C CD C AB AB 00 01 11 10 00 01 11 10 m
CD
C
CD
C
AB
AB
00
01
11
10
00
01
11
10
m
m
m
m
m
m
m
m
0
1
3
2
0
1
3
2
00
1
1
00
1
1
m
m
m
m
m
m
m
m
4
5
7
6
4
5
7
6
01
01
1
1
B
B
m
m
m
m
m
m
m
m
12
13
15
14
12
13
15
14
11
x
x
x
x
11
x
x
x
x
A
A
m
m
m
m
m
m
m
m
8
9
11
10
8
9
11
10
10
x
x
10
x
x
D
D
w = A'B'C'
x = BC' + B'C = B
C
CD C 00 01 11 10 m m m m 0 1 3 2 00
CD
C
00
01
11
10
m
m
m
m
0
1
3
2
00
1 1
m
m
m
m
4
5
7
6
01
1 1
B
B
m
m
m
m
12
13
15
14
11
x
x
x
x
m
m
m
m
8
9
11
10
10
x
x
D
D
y = C
z = D'

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.19

4.20

4.21

B 3

B 2

B 1

B 0

Mode = 0 FOR Add Mode = 1 for Subtract

9's Complementer (See Problem 4.18)
9's Complementer
(See Problem 4.18)
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Select = 1

 

Select = 0

 

Quadruple 2 x 1 MUX

 
 
   
   
   
   
 
Select A 3 A 2 A 1 A 0
Select
A 3
A 2
A 1
A 0

C in

BCD Adder (See Fig. 4.14)

Combine the following circuit with the 4-bit binary multiplier circuit of Fig. 4.16. A C
Combine the following circuit with the 4-bit binary multiplier circuit of Fig. 4.16.
A
C 6
C 5
C 4
C 3
C 2
3
B
B
B
B
3
2
1
0
C
out
4-bit Adder
Augend
D 7
D 6
D 5
D 4
D 3
D 2

C 1

4-bit Adder Augend D 7 D 6 D 5 D 4 D 3 D 2 C

D 1

Two 4-bit numbers are A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0 To Check unequal:

C 0

B 3 B 2 B 1 B 0 To Check unequal: C 0 D 0 80

D 0

80

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.22

4.23

4.22 4.23 x = ( A 3 ⊕ B 3 ) + ( A 2 ⊕

x = (A 3 B 3 ) + (A 2 B 2 ) + (A 1 B 1 ) + (A 0 B 0 )

81

XS-3 Binary ABCD wxyz 0011 0000 0100 0001 0101 0010 0110 0011 0111 0100 1000
XS-3
Binary
ABCD
wxyz
0011
0000
0100
0001
0101
0010
0110
0011
0111
0100
1000
0101
1001
0110
1010
0111
1011
1000
1100
1001
CD
C
CD
C
AB
AB
00
01
11
10
00
01
11
10
x
m
m
m
m
m 0
m 1
m 3
0
1
3
2
00
x x
00
X
X
X
m
m
m
m
m 4
m 5
m 7
m 6
4
5
7
6
01
01
1
B
B
m
m
m
m
m
m
m 12
m 13
15
14
12
13
15
14
11
1 x
x 11
x
x
x
x
A
A
m
m
m
m
m
m
m 8
m 9
11
10
8
9
11
10
10
1 10
1
1
1
D
D
w = AB + ACD
x = B'C' + B'D' + BCD
y = C'D + CD'
z = D'
D0 = A1'A0' = (A1 + A0)'
D1 = A1'A0 = (A1 + A0')'
(NOR)
D0' = (A1'A0')'
D1' = (A1'A0)'
(NAND)
(NOR)
(NAND)

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

82

D2 = A1A0' = (A1' + A0)' D3 = A1A0 = (A1' + A0)' (NOR)
D2 = A1A0' = (A1' + A0)'
D3 = A1A0 = (A1' + A0)'
(NOR)
D2' = (A1A0')'
D0' = (A1A0)'
(NAND)
(NOR)
(NAND)
A
1
D 0 = (A 1 + A 0 + E' )' = A' 1 A' 0 E
A
0
D 1 = (A 1 + A' 0 + E' )' = A' 1 A 0 E
D 2 = (A' 1 + A 0 + E' ) = A 1 A' 0 E
D 3 = (A' 1 + A' 0 + E' )' = A 1 A 0 E
E
E A 1 A 0 D 0 ' = (A 1 + A 0 +
E A 1
A 0
D 0 ' = (A 1 + A 0 + E' ) = (A' 1 A' 0 E)'
D 0
D 1 ' = (A 1 + A' 0 + E' ) = (A' 1 A 0 E)'
D 1
D2' = (A 1 ' + A 0 + E' ) = (A 1 A 0 'E)'
D 2
D 3 ' = (A 1 ' + A 0 ' + E' ) = (A 1 A 0 E)'
D 3

4.24

2421

Decimal

[Using Table 1.5]

ABCD

0000

0001

0010

0011

0100

1011

1100

1101

1110

1111

D 0 = ABCDD 1 = ACD D 2 = ACDD 3 = ACD D 4 = AB D 5 = ABD 6 = ACDD 7 = ACD D 8 = ACDD 9 = BCD

D

D

D

D

D

D

D

D

D

0

1

2

3

4

5

6

7

8

D9

′ D 9 = BCD D D D D D D D D D 0 1

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.25

4.26

A 0

A 1

A 2

A 3

A 4

E

8 3 x 8 D 0 - D 7 Decoder E 8 3 x 8
8
3
x 8
D 0 - D 7
Decoder
E
8
3
x 8
D 8 - D 15
Decoder
E
0
0
2
1
2
x 4
Decoder
2
8
3
x 8
1
2
D 16 - D 23
Decoder
3
E
E
8
3
x 8
D 24 - D 31
Decoder
E

83

0 A 0 2 4 2 x 4 D 0 - D 3 1 Decoder
0
A 0
2
4
2
x 4
D 0 - D 3
1
Decoder
A 1
2
E
0
2
4
2
x 4
D 4 - D 7
1
Decoder
2
E
0
0
A 2
2
1
2
x 4
Decoder
0
2
2
4
2
x 4
1
A 3
2
D 8 - D 11
1
Decoder
3
2
E
E
E
0
2
4
2
x 4
D 12 - D 15
1
Decoder
2
E

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.27 F 1 (A, B, C) = (2, 4, 6) F 2 (A, B, C) = (3, 5, 7) F 3 (A, B, C) = (0, 2, 3, 4, 7)

84

(3, 5, 7) F 3 ( A , B , C ) = (0, 2, 3,
4.28 F 1 =xy + xz′ + yz′ = (2, 4, 6, 7) F 2
4.28 F 1 =xy + xz′ + yz′ = (2, 4, 6, 7)
F 2 = xz + xy + yz = (3, 5, 6, 7)
(a)
F 3 = y′z + x′y′z′ + xy =
(0, 1, 5, 6, 7)
(b)
F 1 = z′ + xy = (0, 2, 4, 6, 7)
F 2 = yz + x′y + y′z′ = (0, 2, 3, 4, 7)
F 3 = (x′ + y)z + xy′z = (0, 2, 5, 6)
(0, 2, 3, 4, 7) F 3 = (x′ + y)z + xy′z = (0, 2,

Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved.

4.29

D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

x

y

z

0 0

0

0

0

0

0

0

-

-

-

1 0

0

0

0

0

0

0

0

0

0

- 1

0

0

0

0

0

0

0

0

1

- -

1

0

0

0

0

0

0

1

0

- -

-

1

0

0

0

0

0

1

1

- -

-

-

1

0

0

0

1

0

0

- -

-

-

-

1

0

0

1

0

1

- -

-

-

-

-

1

0

1

1

0

- -

-

-

-

-

-

1

1

1

1

x = D 7 + D 7 (D 6 + D 6 (D 5 + D 5 (D 4 )))

y = D 7 + D 7 (D 6 + D 4 D 5 D 6 (D 3 + D 3 (D 2 )))

z = D 7 + D 7 D 6 (D 5 +