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Anna University Chennai 60 0025 B.E./B.Tech. Degree Examination, May/June 2012 Sixth Semester Electronics And Communication Engineering EC 2354/EC 64 VLSI DESIGN (Common To PTEC 2354 VLSI DESIGN For B.E. (Part Time) Fifth Semester Electronics And Communication Engineering Regulation 2009 ) (Regulation 2008) Time : Three Hours Max:100 Marks Answer All Questions Part-A (10 X 2 = 20) Www.Technical4u.com 1. Draw The Iv Characteristics Of Mos Transistor.

m o c Model 3. Draw The Equivalent Circuit Structure Of Level 1 Mosfet . In Spice. 4u l a 4. Brief About The Variation Of Fringing Fieldic Factor With The Interconnect n Geometry. h c e 5. Compare Cmos Combinational Logic T Gates With Reference To The . Equivalent N-Mos Depletion Load wLogic With Reference To The w Area Requirement. W
2. Brief The Different Operating Regions Of Mos System. 6. What Are The Advantage Of Using A Pseudo N-Mos Gate Instead Of A Full Cmos Gate 7. What Are The Factors That Cause Timing Failures? 8. What Are The Advantage Of A Single Stuck At Fault? 9. With Component Instantitation, Write A Vhdl Program For A Buffer. 10. Write A Note On Transport Delay

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Www.Technical4u.com Part-B (10 X 2 = 20) 11. (A) Discuss In Detail About: (1) Full-Custom Mask Layout Design (8) (2) Cmos Inverter Layout Design (8) [Or] (B) (I) With A Neat Diagram Discuss In Detail About Dc Transfer Characteristics Of Cmos. (8) (Ii) Write A Short Notes On The Following Along With The Mask View (I) Oxide Related Capacitance (4) (Ii) Junction Capacitance (4) 12. (A) (I) Obtain An Expression For Level 2 Model Equation Of Mosfet In Spice. (8) (Ii) Discuss In Detail About: (1) Variation Of Mobility With Electric Field.

l a c Modes. (2) Variation Of Channel Length In Saturation i n (3) Saturation Of Carrier Velocity. (8) h c e [Or] T . (B)(I) How Do The Spice Mosfet Model Account For The Parasitic w w Device Capacitances?(8) W
(Ii) Explain The Charecterization Of Circuits.(8) 13. (A) (I)For A Two Input Nand Gate Derive An Expression For The Drain Current. (8) (Ii) Draw A Cmos Nor2 Gate And Its Complementary Operation With Necessary Equations. (4) (Iii) Obtain A Cmos Logic Design Realizing The Boolean Function

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Z=A(D+E)+Bc (8) [Or] (B) (I) Draw A Circuit Diagram Of The Cmos Sr Latch And Explain In Detail. (8) (Ii) Along With The Necessary Input And Output Waveforms Of The Cmos Dff Negative Edge Triggered Master Slave D Flip Flop. (8) 14. (A) (I) Explain Indetail About Partition And Mux Testing With Necessary Example And Diagram. (8) (Ii) Explain The Principle Of Silicon Debug. (8) [Or] (B) (I) Elaborate The Scan Based Techniques. (8) (Ii) Discuss In Detail About: (I) Pseudo Random Pattern Generator. (4) (Ii) Output Response Analyser. (4)

l a 15. (A) Using Mixed Level Mode Write A Vhdlic Program For A n (I) Comparator. (8) h c e (Ii) D Flip Flop. (8) T . w [Or] w (B) With All The Three Types Of Modeling Write A Vhdl Program For A W
(I) Decoder (8) (Ii) Full Adder. (8) Www.Technical4u.com

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