Sie sind auf Seite 1von 1422

DL135/D Rev.

7, Apr-2001

Power MOSFETs

Power MOSFETs

DL135/D Rev. 7, Apr2001

SCILLC, 2001 Previous Edition 1996 All Rights Reserved

EZFET, MiniMOS & SMARTDISCRETES are trademarks of Semiconductor Components Industries, LLC (SCILLC). ChipFET is a trademark of Vishay Siliconix. FETKY is a trademark of International Rectifier Corporation. Micro8 is a trademark of International Rectifier.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION


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Table of Contents

Power MOSFET Numeric Data Sheet Listing and Selector Guide


Page Numeric Data Sheet Listing . . . . . . . . . . . . . . . . . . . . . . . . . 5 Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ChipFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SO8 MiniMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SO8 FETKY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 EZFET SO8 Power MOSFETs . . . . . . . . . . . . . . . . 10 Micro8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TSSOP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SOT23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SC70/SOT323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SC88/SOT363 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TO220AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TO247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TO264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SMARTDISCRETES . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TO92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IGBTs Insulated Gate Bipolar Transistors . . . . . . . . 17

Chapter 1: Power MOSFETs


Page Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 2: Abstracts
Application Note Abstracts . . . . . . . . . . . . . . . . . . . . . . . 1399

Chapter 3: Case Outlines and Package Dimensions


Case Outlines and Package Dimensions . . . . . . . . . . 1405

Chapter 4: Index
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415

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Power MOSFET Numeric Data Sheet Listing

Chapter 1: Power MOSFET Data Sheets


Device Function Page NGD15N41CL . . . . . . . . . . . . . . . Ignition IGBT 15 Amps, 410 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 NIB64045L . . . . . . . . . . . . . . . . . SMARTDISCRETESt 52 Amps, 40 Volts Self Protected with Temperature Sense NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . 23 NIMD6302R2 . . . . . . . . . . . . . . . . SMARTDISCRETESt 5 Amps, 30 Volts Self Protected with Current Sense NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . . 27 NTD20N03L27 . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 NTD20N06 . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 NTD3055094 . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 NTD3055L104 . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts, Logic Level NChannel DPAK . . . . . . . . . . . . . . . . . 37 NTD32N06 . . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 NTD32N06L . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts, Logic Level NChannel DPAK . . . . . . . . . . . . . . . . . 44 NTD4302 . . . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 NTGS3433T1 . . . . . . . . . . . . . . . . MOSFET 3.3 Amps, 12 Volts PChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 NTGS3441T1 . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts PChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 NTGS3443T1 . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts PChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 NTGS3446 . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts NChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 NTGS3455T1 . . . . . . . . . . . . . . . . MOSFET 3.5 Amps, 30 Volts PChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 NTHD5902T1 . . . . . . . . . . . . . . . . Dual NChannel 30 V (DS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 NTHD5903T1 . . . . . . . . . . . . . . . . Dual PChannel 2.5 V (GS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 NTHD5904T1 . . . . . . . . . . . . . . . . Dual NChannel 2.5 V (GS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NTHD5905T1 . . . . . . . . . . . . . . . . Dual PChannel 1.8 V (GS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 NTHS5402T1 . . . . . . . . . . . . . . . . NChannel 30 V (DS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 NTHS5404T1 . . . . . . . . . . . . . . . . NChannel 2.5 V (GS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 NTHS5441T1 . . . . . . . . . . . . . . . . PChannel 2.5 V (GS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 NTHS5443T1 . . . . . . . . . . . . . . . . PChannel 2.5 V (GS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 NTHS5445T1 . . . . . . . . . . . . . . . . PChannel 1.8 V (GS) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 NTMD3P03R2 . . . . . . . . . . . . . . . Power MOSFET 3.05 Amps, 30 Volts Dual PChannel SO8 . . . . . . . . . . . . . . . . . . . 120 NTMD6N02R2 . . . . . . . . . . . . . . . Power MOSFET 6.0 Amps, 20 Volts NChannel Enhancement Mode Dual SO8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 NTMD6P02R2 . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 20 Volts PChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 120 NTMD7C02 . . . . . . . . . . . . . . . . . . Power MOSFET 9.5 Amps, 20 Volts (NCh) 4 Amps, 20 Volts (PCh) Complementary SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 NTMS10P02R2 . . . . . . . . . . . . . . Power MOSFET 10 Amps, 20 Volts PChannel EnhancementMode Single SO8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 NTMS3P03R2 . . . . . . . . . . . . . . . Power MOSFET 3.05 Amps, 30 Volts PChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . 150 NTMS4N01R2 . . . . . . . . . . . . . . . Power MOSFET 4.2 Amps, 20 Volts NChannel EnhancementMode Single SO8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 NTMS4P01R2 . . . . . . . . . . . . . . . Power MOSFET 4.5 Amps, 12 Volts PChannel EnhancementMode Single SO8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 NTMS5P02R2 . . . . . . . . . . . . . . . Power MOSFET 5.4 Amps, 20 Volts PChannel EnhancementMode Single SO8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 NTMSD2P102LR2 . . . . . . . . . . . . FETKYt Power MOSFET and Schottky Diode Dual SO8 Package . . . . . . . . . . . . . . . 178 NTMSD3P102R2 . . . . . . . . . . . . . FETKYt PChannel EnhancementMode Power MOSFET and Schottky Diode Dual SO8 Package . . . . . . . . . . . . . . . . . . . . . . . . 188 NTMSD3P303R2 . . . . . . . . . . . . . FETKYt PChannel EnhancementMode Power MOSFET and Schottky Diode Dual SO8 Package . . . . . . . . . . . . . . . . . . . . . . . . 198 NTP27N06 . . . . . . . . . . . . . . . . . . Power MOSFET 27 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . . 208 NTP45N06 . . . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . . 210 NTP45N06L . . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 60 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . . . 215 NTP75N0306 . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts NChannel TO220 and D2PAK . . . . . . . . . . . . . . 220 NTP75N03L09 . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts NChannel TO220 and D2PAK . . . . . . . . . . . . . . 225 http://onsemi.com
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Power MOSFET Numeric Data Sheet Listing (continued)


Device Function Page NTQD6866 . . . . . . . . . . . . . . . . . . Power MOSFET 5.8 Amps, 20 Volts NChannel TSSOP8 . . . . . . . . . . . . . . . . . . . . . . . 230 NTTD1P02R2 . . . . . . . . . . . . . . . . Power MOSFET 1.45 Amps, 20 Volts PChannel Enhancement Mode Dual Micro8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 NTTD2P02R2 . . . . . . . . . . . . . . . . Power MOSFET 2.4 Amps, 20 Volts Dual PChannel Micro8t . . . . . . . . . . . . . . . . . 241 NTTS2P02R2 . . . . . . . . . . . . . . . . Power MOSFET 2.4 Amps, 20 Volts Single PChannel Micro8t . . . . . . . . . . . . . . . . 248 NTTS2P03R2 . . . . . . . . . . . . . . . . Power MOSFET 2.48 Amps, 30 Volts PChannel Enhancement Mode Single Micro8 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 NTUD01N02 . . . . . . . . . . . . . . . . . Power MOSFET 100 mAmps, 20 Volts Dual NChannel SC88 . . . . . . . . . . . . . . . . . . . 262 2N7000 . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 60 Volts NChannel TO92 . . . . . . . . . . . . . . . . . . 264 2N7002LT1 . . . . . . . . . . . . . . . . . . Power MOSFET 115 mAmps, 60 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 267 BS107 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 250 mAmps, 200 Volts NChannel TO92 . . . . . . . . . . . . . . . . . 271 BS108 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 250 mAmps, 200 Volts, Logic Level NChannel TO92 . . . . . . 275 BS170 . . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 500 mAmps, 60 Volts NChannel TO92 . . . . . . . . . . . . . . . . . . 277 BSS123LT1 . . . . . . . . . . . . . . . . . Power MOSFET 170 mAmps, 100 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . 280 BSS138LT1 . . . . . . . . . . . . . . . . . Power MOSFET 200 mAmps, 50 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 284 BSS84LT1 . . . . . . . . . . . . . . . . . . . Power MOSFET 130 mAmps, 50 Volts PChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 289 MGP15N35CL . . . . . . . . . . . . . . . Ignition IGBT 15 Amps, 350 Volts NChannel TO220 and D2PAK . . . . . . . . . . . . . . . . 293 MGP15N40CL . . . . . . . . . . . . . . . Ignition IGBT 15 Amps, 410 Volts NChannel TO220 and D2PAK . . . . . . . . . . . . . . . . 301 MGP19N35CL . . . . . . . . . . . . . . . Ignition IGBT 19 Amps, 350 Volts NChannel TO220 and D2PAK . . . . . . . . . . . . . . . . 309 MGSF1N02ELT1 . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 316 MGSF1N02LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 320 MGSF1N03LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 30 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 324 MGSF1P02ELT1 . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts PChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 328 MGSF1P02LT1 . . . . . . . . . . . . . . Power MOSFET 750 mAmps, 20 Volts PChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 332 MGSF2P02HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts PChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . 336 MGSF3442VT1 . . . . . . . . . . . . . . Power MOSFET 4 Amps, 20 Volts NChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . 344 MGSF3454VT1 . . . . . . . . . . . . . . Power MOSFET 4 Amps, 30 Volts NChannel TSOP6 . . . . . . . . . . . . . . . . . . . . . . . . . . 349 MLD1N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 1 Amp, 62 Volts, Logic Level NChannel DPAK . . . . . 354 MLP1N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 1 Amp, 62 Volts, Logic Level NChannel TO220 . . . 360 MLP2N06CL . . . . . . . . . . . . . . . . . SMARTDISCRETES MOSFET 2 Amps, 62 Volts, Logic Level NChannel TO220 . . 366 MMBF0201NLT1 . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 372 MMBF0202PLT1 . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts PChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 377 MMBF1374T1 . . . . . . . . . . . . . . . Small Signal MOSFET 50 mAmps, 30 Volts NChannel SC70/SOT323 . . . . . . . . . . 382 MMBF170LT1 . . . . . . . . . . . . . . . . Power MOSFET 500 mAmps, 60 Volts NChannel SOT23 . . . . . . . . . . . . . . . . . . . . . . 384 MMBF2201NT1 . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts NChannel SC70/SOT323 . . . . . . . . . . . . . . 388 MMBF2202PT1 . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 20 Volts PChannel SC70/SOT323 . . . . . . . . . . . . . . . 392 MMDF1300 . . . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts Complementary SO8, Dual . . . . . . . . . . . . . . . . . . . 396 MMDF1N05E . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 50 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . . 399 MMDF2C01HD . . . . . . . . . . . . . . Power MOSFET 2 Amps, 12 Volts Complementary SO8, Dual . . . . . . . . . . . . . . . . . . . 404 MMDF2C02E . . . . . . . . . . . . . . . . Power MOSFET 2.5 Amps, 25 Volts Complementary, SO8, Dual . . . . . . . . . . . . . . . . . 416 MMDF2C02HD . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts Complementary SO8, Dual . . . . . . . . . . . . . . . . . . . 427 MMDF2C03HD . . . . . . . . . . . . . . Power MOSFET 2 Amps, 30 Volts Complementary SO8, Dual . . . . . . . . . . . . . . . . . . . 439 MMDF2N02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 451 MMDF2N05ZR2 . . . . . . . . . . . . . . Power MOSFET 2 Amps, 50 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 459 MMDF2P01HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 12 Volts PChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 468 MMDF2P02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 25 Volts PChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 477 MMDF2P02HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts PChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 485 MMDF2P03HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 30 Volts PChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 494 MMDF3N02HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 503 MMDF3N03HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 30 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 512 MMDF3N04HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 40 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 521 MMDF3N06HD . . . . . . . . . . . . . . Power MOSFET 3 Amps, 60 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 531 MMDF3N06VL . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 60 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 540 MMDF4N01HD . . . . . . . . . . . . . . Power MOSFET 4 Amps, 20 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 542 http://onsemi.com
6

Power MOSFET Numeric Data Sheet Listing (continued)


Device Function Page MMDF5N02Z . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 551 MMDF6N03HD . . . . . . . . . . . . . . Power MOSFET 6 Amps, 30 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 560 MMDF7N02Z . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 20 Volts NChannel SO8, Dual . . . . . . . . . . . . . . . . . . . . . . . 569 MMDFS2P102 . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts PChannel SO8, FETKYt . . . . . . . . . . . . . . . . . . . 579 MMDFS6N303 . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 30 Volts NChannel SO8, FETKYt . . . . . . . . . . . . . . . . . . . 589 MMFT2406T1 . . . . . . . . . . . . . . . . Power MOSFET 700 mAmps, 240 Volts NChannel SOT223 . . . . . . . . . . . . . . . . . . . . 605 MMFT2955E . . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts PChannel SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . 610 MMFT2N02EL . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts NChannel SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . 619 MMFT3055V . . . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts NChannel SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . 628 MMFT3055VL . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 60 Volts NChannel SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . 637 MMFT5P03HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 30 Volts PChannel SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . 646 MMFT960T1 . . . . . . . . . . . . . . . . . Power MOSFET 300 mAmps, 60 Volts NChannel SOT223 . . . . . . . . . . . . . . . . . . . . . 656 MMSF10N02Z . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 20 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 MMSF10N03Z . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 30 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 MMSF1308 . . . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 MMSF1310 . . . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 30 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 MMSF2P02E . . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 20 Volts PChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 MMSF3300 . . . . . . . . . . . . . . . . . . Power MOSFET 11.5 Amps, 30 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . 705 MMSF3P02HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts PChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 MMSF5N02HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 20 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 MMSF5N03HD . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 30 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 MMSF7N03HD . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 MMSF7N03Z . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 30 Volts NChannel SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 MPF930 . . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 2 Amps, 35, 60, 90 Volts NChannel TO92 . . . . . . . . . . . . . . . 761 MTB1306 . . . . . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts, Logic Level NChannel D2PAK . . . . . . . . . . . . . . . 765 MTB20N20E . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 200 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . 772 MTB23P06V . . . . . . . . . . . . . . . . . Power MOSFET 23 Amps, 60 Volts PChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 781 MTB29N15E . . . . . . . . . . . . . . . . . Power MOSFET 29 Amps, 150 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . 790 MTB30N06VL . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts, Logic Level NChannel D2PAK . . . . . . . . . . . . . . . 798 MTB30P06V . . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts PChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 807 MTB36N06V . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 816 MTB40N10E . . . . . . . . . . . . . . . . . Power MOSFET 40 Amps, 100 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . 825 MTB50N06V . . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 834 MTB50N06VL . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts, Logic Level NChannel D2PAK . . . . . . . . . . . . . . . 843 MTB50P03HDL . . . . . . . . . . . . . . Power MOSFET 50 Amps, 30 Volts, Logic Level PChannel D2PAK . . . . . . . . . . . . . . . 852 MTB52N06V . . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 862 MTB52N06VL . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts, Logic Level NChannel D2PAK . . . . . . . . . . . . . . . 871 MTB55N06Z . . . . . . . . . . . . . . . . . Power MOSFET 55 Amps, 60 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 880 MTB60N05HDL . . . . . . . . . . . . . . Power MOSFET 60 Amps, 50 Volts, Logic Level NChannel D2PAK . . . . . . . . . . . . . . . 885 MTB60N06HD . . . . . . . . . . . . . . . Power MOSFET 60 Amps, 60 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 895 MTB75N03HDL . . . . . . . . . . . . . . Power MOSFET 75 Amps, 25 Volts, Logic Level NChannel D2PAK . . . . . . . . . . . . . . . 905 MTB75N05HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 50 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 915 MTB75N06HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 60 Volts NChannel D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . 922 MTD1302 . . . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 MTD15N06V . . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 MTD15N06VL . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 MTD20N03HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts, Logic Level NChannel DPAK . . . . . . . . . . . . . . . . 960 MTD20N06HD . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 MTD20N06HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts, Logic Level NChannel DPAK . . . . . . . . . . . . . . . . 980 MTD20P03HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 30 Volts, Logic Level PChannel DPAK . . . . . . . . . . . . . . . . 990 MTD20P06HDL . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts, Logic Level PChannel DPAK . . . . . . . . . . . . . . . 1000 MTD2955V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts PChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 MTD3055V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 MTD3055VL . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 http://onsemi.com
7

Power MOSFET Numeric Data Sheet Listing (continued)


Device Function Page MTD3302 . . . . . . . . . . . . . . . . . . . Power MOSFET 18 Amps, 30 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 MTD4N20E . . . . . . . . . . . . . . . . . . Power MOSFET 4 Amps, 200 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 MTD5P06V . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 60 Volts PChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057 MTD6N20E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 200 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 MTD6P10E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 100 Volts PChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 MTD9N10E . . . . . . . . . . . . . . . . . . Power MOSFET 9 Amps, 100 Volts NChannel DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 MTDF1N02HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts NChannel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . . 1093 MTDF1N03HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 30 Volts NChannel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . . 1104 MTDF2N06HD . . . . . . . . . . . . . . . Power MOSFET 2 Amps, 60 Volts NChannel Micro8t, Dual . . . . . . . . . . . . . . . . . . . . 1115 MTP10N10E . . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 100 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . 1123 MTP10N10EL . . . . . . . . . . . . . . . . Power MOSFET 10 Amps, 100 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . 1130 MTP12P10 . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 100 Volts PChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . 1136 MTP1302 . . . . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 30 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1141 MTP1306 . . . . . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 30 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1148 MTP15N06V . . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1155 MTP15N06VL . . . . . . . . . . . . . . . . Power MOSFET 15 Amps, 60 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . . 1161 MTP20N06V . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1167 MTP20N15E . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 150 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . 1173 MTP20N20E . . . . . . . . . . . . . . . . . Power MOSFET 20 Amps, 200 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . 1175 MTP23P06V . . . . . . . . . . . . . . . . . Power MOSFET 23 Amps, 60 Volts PChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1181 MTP27N10E . . . . . . . . . . . . . . . . . Power MOSFET 27 Amps, 100 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . 1187 MTP2955V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts PChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1193 MTP29N15E . . . . . . . . . . . . . . . . . Power MOSFET 29 Amps, 150 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . 1199 MTP3055V . . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1213 MTP3055VL . . . . . . . . . . . . . . . . . Power MOSFET 12 Amps, 60 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . . 1219 MTP30N06VL . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . . 1225 MTP30P06V . . . . . . . . . . . . . . . . . Power MOSFET 30 Amps, 60 Volts PChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1231 MTP36N06V . . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1237 MTP40N10E . . . . . . . . . . . . . . . . . Power MOSFET 40 Amps, 100 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . 1243 MTP50N06V . . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1249 MTP50N06VL . . . . . . . . . . . . . . . . Power MOSFET 42 Amps, 60 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . . 1255 MTP50P03HDL . . . . . . . . . . . . . . Power MOSFET 50 Amps, 30 Volts, Logic Level PChannel TO220 . . . . . . . . . . . . . 1261 MTP52N06V . . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1268 MTP52N06VL . . . . . . . . . . . . . . . . Power MOSFET 52 Amps, 60 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . . 1274 MTP5P06V . . . . . . . . . . . . . . . . . . Power MOSFET 5 Amps, 60 Volts PChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . . 1280 MTP60N06HD . . . . . . . . . . . . . . . Power MOSFET 60 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1286 MTP6P20E . . . . . . . . . . . . . . . . . . Power MOSFET 6 Amps, 200 Volts PChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1293 MTP75N03HDL . . . . . . . . . . . . . . Power MOSFET 75 Amps, 25 Volts, Logic Level NChannel TO220 . . . . . . . . . . . . . 1299 MTP75N05HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 50 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1306 MTP75N06HD . . . . . . . . . . . . . . . Power MOSFET 75 Amps, 60 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1313 MTP7N20E . . . . . . . . . . . . . . . . . . Power MOSFET 7 Amps, 200 Volts NChannel TO220 . . . . . . . . . . . . . . . . . . . . . . . . 1320 MTSF1P02HD . . . . . . . . . . . . . . . Power MOSFET 1 Amp, 20 Volts PChannel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . . 1326 MTSF3N02HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 20 Volts NChannel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . 1337 MTSF3N03HD . . . . . . . . . . . . . . . Power MOSFET 3 Amps, 30 Volts NChannel Micro8t . . . . . . . . . . . . . . . . . . . . . . . . . 1348 MTW32N20E . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 200 Volts NChannel TO247 . . . . . . . . . . . . . . . . . . . . . . . 1359 MTW32N25E . . . . . . . . . . . . . . . . Power MOSFET 32 Amps, 250 Volts NChannel TO247 . . . . . . . . . . . . . . . . . . . . . . . 1365 MTW35N15E . . . . . . . . . . . . . . . . Power MOSFET 35 Amps, 150 Volts NChannel TO247 . . . . . . . . . . . . . . . . . . . . . . . 1371 MTW45N10E . . . . . . . . . . . . . . . . Power MOSFET 45 Amps, 100 Volts NChannel TO247 . . . . . . . . . . . . . . . . . . . . . . . 1377 MTY55N20E . . . . . . . . . . . . . . . . . Power MOSFET 55 Amps, 200 Volts NChannel TO264 . . . . . . . . . . . . . . . . . . . . . . . 1383 VN0300L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 60 Volts NChannel TO92 . . . . . . . . . . . . . . . . . 1389 VN2222LL . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 150 mAmps, 60 Volts NChannel TO92 . . . . . . . . . . . . . . . . . 1391 VN2406L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 240 Volts NChannel TO92 . . . . . . . . . . . . . . . . 1394 VN2410L . . . . . . . . . . . . . . . . . . . . Small Signal MOSFET 200 mAmps, 240 Volts NChannel TO92 . . . . . . . . . . . . . . . . 1396

http://onsemi.com
8

Power MOSFET Selector Guide

Table 1. ChipFET Case 1206A


V(BR)DSS (Volts) Min 30 20 Max RDS(on) @ VGS 10 V () 0.035 0.085 8 4.5 V () 0.055 0.143 0.03 0.075 0.060 (Note 7.) 0.065 0.155 0.035 0.09 2.5 V () 0.045 0.0134 0.083 0.110 0.260 0.047 0.13 1.8 V () 0.062 0.18 ID (cont) Amps (Note 8.) 6.7 3.9 7.2 4.2 5.3 4.7 2.9 7.1 4.1 Device (Note 3.) NTHS5402T1 NTHD5902T1 NTHS5404T1 NTHD5904T1 NTHS5441T1 NTHS5443T1 NTHD5903T1 NTHS5445T1 NTHD5905T1 PD (Notes 1. & 2.) (Watts) Max 1.3 1.1 1.3 1.1 1.3 1.3 1.1 1.3 1.1 Page No. 95 80 106 90 109 112 85 114 95

Configuration Single NChannel Dual NChannel Single NChannel Dual NChannel Single PChannel Single PChannel Dual PChannel Single PChannel Dual PChannel

Table 2. SO-8 (MiniMOS) Case 75106


V(BR)DSS (Volts) Min 60 50 40 30 Max RDS(on) @ VGS 10 V () 0.100 0.300 0.080 0.030 0.015 0.0125 0.040 0.028 0.085 0.070 0.035 0.085 0.070/0.200 25 20 0.100/0.210 0.025 0.250 0.075 4.5 V () 0.130 (Note 5.) 0.200 0.500 0.100 0.039 0.019 0.020 0.050 0.040 0.115 0.075 0.050 0.125 0.075/0.300 0.160/0.375 0.040 0.045 0.400 0.095 0.033 0.014 2.7 V () 0.055 2.5 V () 0.048 0.020 ID (cont) Amps 3.3 3.3 1.5 3.4 7.0 10.0 11.5 6.5 8.2 3.05 4.1 6.0 3.05 4.1 3.0/2.0 8.2 4.0 2.5 5.6 5.4 10.0 Device (Note 4.) MMDF3N06VLR2 MMDF3N06HDR2 MMDF1N05ER2 MMDF3N04HDR2 MMSF1308R2 MMSF1310R2 MMSF3300R2 MMSF5N03HDR2 MMSF7N03HDR2 NTMS3P03R2 MMDF3N03HDR2 MMDF6N03HDR2 NTMD3P03R2 MMDF2C03HDR2 MMDF1300R2 MMSF5N02HDR2 NTMS4N01R2 MMSF2P02ER2 MMSF3P02HDR2 NTMS5P02R2 NTMS10P02R2 PD (Notes 1. & 2.) (Watts) Max 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 2.5 2.5 2.0 2.0 2.0 2.0 1.8 2.5 2.5 2.5 2.5 2.5 2.5 Configuration (Note 6.) Dual NChannel Dual NChannel Dual NChannel Dual NChannel Single NChannel Single NChannel Single NChannel Single NChannel Single NChannel Single PChannel Dual NChannel Dual NChannel Dual PChannel Complementary Complementary Single NChannel Single NChannel Single PChannel Single PChannel Single PChannel Single PChannel Page No. 540 531 399 521 681 689 705 733 742 150 512 560 120 439 396 724 157 697 715 171 143

1. 2. 3. 4. 5. 6. 7. 8.

TC = 25C See Data Sheet for Applicable Mounting Configuration. Available in Tape and Reel only. T1 suffix = 3000 per reel. Available in Tape and Reel only. R2 suffix = 2500 per reel. VGS = 5.0 V Data for all Complementary Devices listed as Nch/Pch. VGS = 3.6 V t 5 sec

Devices listed in bold, italic are ON Semiconductor preferred devices.

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9

Power MOSFET Selector Guide (continued)

Table 2. SO-8 (MiniMOS) Case 75106 (continued)


V(BR)DSS (Volts) Min 20 Max RDS(on) @ VGS 10 V () 0.100 0.090 0.250 0.160 0.100/0.250 0.090/0.160 12 4.5 V () 0.200 0.035 0.100 0.400 0.180 0.033 0.200/0.400 0.100/0.180 0.024/0.074 0.045 0.180 0.045/0.180 2.7 V () 0.048 0.055 0.220 2.5 V () 0.049 0.050 ID (cont) Amps 3.6 6.5 3.8 2.5 3.3 7.8 3.6 3.8 7.0 5.1 3.4 5.2 Device (Note 11.) MMDF2N02ER2 NTMD6N02R2 MMDF3N02HDR2 MMDF2P02ER2 MMDF2P02HDR2 NTMD6P02R2 MMDF2C02ER2 MMDF2C02HDR2 NTMD7C02R2 NTMS4P01R2 MMDF2P01HDR2 MMDF2C01HDR2 PD (Notes 9. & 10.) (Watts) Max 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.5 2.0 2.0 Configuration (Note 12.) Dual NChannel Dual NChannel Dual NChannel Dual PChannel Dual PChannel Dual PChannel Complementary Complementary Complementary Single PChannel Dual PChannel Complementary Page No. 451 127 503 477 485 120 416 427 141 164 468 404

Table 3. SO8 FETKY Case 75106


V(BR)DSS (Volts) Min 30 Max RDS(on) @ VGS 10 V () 0.035 0.085 20 0.160 0.085 4.5 V () 0.050 0.125 0.180 0.090 0.125 2.7 V () 0.130 2.5 V () 0.15 ID (cont) Amps 6.0 3.05 3.3 2.4 3.0 Device (Note 11.) MMDFS6N303R2 NTMSD3P303R2 MMDFS2P102R2 NTMSD2P102LR2 NTMSD3P102R2 PD (Notes 9. & 10.) (Watts) Max 2.0 2.0 2.0 2.0 2.0 Page No. 589 198 579 178 188

Configuration Dual NChannel/ Schottky Dual PChannel/ Schottky Dual PChannel/ Schottky Dual PChannel/ Schottky Dual PChannel/ Schottky

Table 4. EZFET SO8 Power MOSFETs with Zener Gate Protection Case 75106
V(BR)DSS (Volts) Min 50 30 20 Max RDS(on) @ VGS 10 V () 0.3 0.03 0.013 4.5 V () 0.04 0.018 0.015 0.04 0.027 2.7 V () 0.019 0.05 2.5 V () 0.035 ID (cont) Amps 2.0 7.5 10 10 5.0 7.0 Device (Note 11.) MMDF2N05ZR2 MMSF7N03ZR2 MMSF10N03ZR2 MMSF10N02ZR2 MMDF5N02ZR2 MMDF7N02ZR2 PD (Notes 9. & 10.) (Watts) Max 2.0 2.5 1.6 2.5 2.0 2.0 Page No. 459 751 671 662 551 569

Configuration Dual NChannel Single NChannel Single NChannel Single NChannel Dual NChannel Dual NChannel

9. TC = 25C 10. See Data Sheet for Applicable Mounting Configuration. 11. Available in Tape and Reel only. R2 suffix = 2500 per reel. 12. Data for all Complementary Devices listed as Nch/Pch.

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Power MOSFET Selector Guide (continued)

Table 5. Micro8 Case 846A02


V(BR)DSS (Volts) Min 60 30 Max RDS(on) @ VGS 10 V () 0.22 0.04 0.085 0.12 20 4.5 V () 0.26 0.06 0.135 0.16 0.04 0.16 0.09 0.12 0.16 0.090 2.7 V () 0.05 0.19 0.13 0.16 0.25 0.130 2.5 V () ID (cont) Amps 1.5 5.7 2.5 2.0 6.1 1.8 2.4 2.8 1.45 2.4 Device (Note 15.) MTDF2N06HDR2 MTSF3N03HDR2 NTTS2P03R2 MTDF1N03HDR2 MTSF3N02HDR2 MTSF1P02HDR2 NTTS2P02R2R2 MTDF1N02HDR2 NTTD1P02R2 NTTD2P02R2 PD (Notes 13. & 14.) (Watts) Max 1.25 1.79 1.79 1.25 1.79 1.8 0.78 1.25 1.25 1.25 Page No. 1115 1348 255 1104 1337 1326 248 1093 234 241

Configuration Dual NChannel Single NChannel Single PChannel Dual NChannel Single NChannel Single PChannel Single PChannel Dual NChannel Dual PChannel Dual PChannel

Table 6. SOT-223 Case 318E04


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () 2.5 V () ID (cont) Amps 0.7 0.25 1.7 1.5 0.3 1.6 Device (Note 16.) PD (Notes 13. & 14.) (Watts) Max 1.5 0.8 2.0 2.0 0.8 0.8 Page No.

NChannel
240 200 60 6.0 14 0.13 1.7 20 0.14 0.15 10 MMFT2406T1/T3 MMFT107T1/T3 MMFT3055VT1/T3 MMFT3055VLT1/T3 MMFT960T1 MMFT2N02ELT1 605 599 628 637 656 619

PChannel
60 30 0.3 0.1 1.2 5.2 MMFT2955ET1/T3 MMFT5P03HDT3 0.8 3.13 610 646

Table 7. TSOP6 Case 318G02


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () 2.5 V () ID (cont) Amps 4.2 4.0 5.8 Device (Note 17.) PD (Notes 13. & 14.) (Watts) Max 2.0 2.0 1.6 Page No.

NChannel
30 20 0.065 0.095 0.07 0.045 0.095 0.055 MGSF3454VT1 MGSF3442VT1 NTGS3446T1 349 344 73

PChannel
30 20 0.100 0.175 12 0.170 0.09 0.065 0.28 .075 0.090 .095 0.135 0.100 3.5 3.3 4.4 1.3 3.3 NTGS3455T1 NTGS3441T1 NTGS3443T1 MGSF2P02HDT1 NTGS3433T1 2.0 2.0 2.0 2.0 2.0 76 61 67 336 57

13. TC = 25C 14. See Data Sheet for Applicable Mounting Configuration. 15. Available in Tape and Reel only. R2 suffix = 4000 per reel. 16. Available in Tape and Reel only. T1 suffix = 1000 per reel, T3 suffix = 4000 per reel. 17. Available in Tape and Reel only. T1 suffix = 3000 per reel.

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Power MOSFET Selector Guide (continued)

Table 8. TSSOP8 Case 318G02


V(BR)DSS (Volts) Min 20 Max RDS(on) @ VGS 10 V () 4.5 V () 0.03 (Note 23.) 0.020 2.7 V () 0.027 2.5 V () 0.04 ID (cont) Amps 5.8 6.2 Device (Note 20.) NTQD6866R2 NTQS6463R2 PD (Notes 18. & 19.) (Watts) Max 1.6 1.05 Page No. 230 232

Configuration Dual NChannel Single PChannel

Table 9. SOT23 Case 31808


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.5 V () ID (cont) Amps 0.17 0.50 0.115 0.20 0.75 0.75 0.3 0.75 Device (Note 21.) PD (Notes 18. & 19.) (Watts) Max 0.225 0.225 0.225 0.225 0.4 0.4 0.225 0.4 Page No.

NChannel
100 60 50 30 20 6.0 5.0 7.5 0.1 0.09 1.0 3.5 @ 5.0 V 0.145 0.13 1.4 0.085 7.0 @ 2.75 0.115 BSS123LT1/T3 MMBF170LT1/T3 2N7002LT1/T3 BSS138LT1/T3 MGSF1N03LT1 MGSF1N02LT1 MMBF0201NLT1 MGSF1N02ELT1 280 384 267 284 324 320 372 316

PChannel
50 20 0.35 1.4 10 @ 5.0 V 0.26 0.5 3.5 0.5 0.13 0.75 0.75 0.3 BSS84LT1 MGSF1P02ELT1 MGSF1P02LT1 MMBF0202PLT1 0.225 0.4 0.4 0.225 289 328 332 377

Table 10. SC70 / SOT323 Case 41902


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps Device (Note 22.) PD (Notes 18. & 19.) (Watts) Max VGS (Volts) Min Page No.

NChannel
30 20 1.0 50 1.4 0.10 0.30 MMBF1374T1 MMBF2201NT1 0.10 0.15 1.0 1.0 382 388

PChannel
20 2.2 3.5 0.30 MMBF2202PT1 0.15 1.0 392

Table 11. SC88 / SOT363 Case 419B01


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps Device (Note 22.) PD (Notes 18. & 19.) (Watts) Max VGS (Volts) Min Page No.

NChannel
20 10 0.1 NTUD01N02 0.15 0.5 262

18. TC = 25C 19. See Data Sheet for Applicable Mounting Configuration. 20. Available in Tape and Reel only. R2 suffix = 4000 per reel. 21. Available in Tape and Reel only. T1 suffix = 3000 per reel, T3 suffix = 10,000 per reel. 22. Available in Tape and Reel only. T1 suffix = 3000 per reel. 23. VGS = 4.0 V

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Power MOSFET Selector Guide (continued)

Table 12. DPAK Case 369A13 (TO252)


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () ID (cont) Amps Device (Note 26.) PD (Notes 24. & 25.) (Watts) Max Page No.

N-Channel
200 1.2 0.07 100 60 0.25 0.094 0.15 0.12 0.045 0.046 0.026 30 0.022 0.010 0.010 0.104 0.18 0.085 0.045 0.028 0.035 0.027 0.013 4.0 6.0 9.0 12 12 12 12 15 15 20 20 20 32 32 20 20 20 20 30 MTD4N20E MTD6N20E MTD9N10E NTD3055094 NTD3055L104 MTD3055V MTD3055VL MTD15N06V MTD15N06VL MTD20N06HD MTD20N06HDL NTD20N06 NTD32N06 NTD32N06L MTD20N03HDL MTD1302 NTD20N03L27 NTD4302 MTD3302 40 50 40 36 36 48 48 55 60 40 40 60 60 60 74 74 74 62 96 1048 1066 1084 35 37 1019 1028 942 951 970 980 33 39 44 960 932 29 49 1037

P-Channel
100 60 0.66 0.45 0.20 30 0.175 0.099 6.0 5.0 12 15 19 MTD6P10E MTD5P06V MTD2955V MTD20P06HDL MTD20P03HDL 50 40 60 72 75 1075 1057 1010 1000 990

24. TC = 25C 25. See Data Sheet for Applicable Mounting Configuration. 26. Also available in Tape and Reel. T4 suffix = 2500 per reel.

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Power MOSFET Selector Guide (continued)

Table 13. D2PAK Case 418B03 (TO264)


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () ID (cont) Amps Device (Note 29.) PD (Notes 27. & 28.) (Watts) Max Page No.

N-Channel
200 150 100 60 0.16 0.07 0.04 0.04 0.026 0.028 0.022 0.016 0.014 0.010 50 0.0095 30 0.0065 0.0065 25 0.05 0.028 0.032 0.025 0.014 0.009 0.009 20 29 40 32 30 45 45 42 42 52 52 55 60 75 75 60 75 75 75 75 MTB20N20E MTB29N15E MTB40N10E MTB36N06V MTB30N06VL NTB45N06 NTB45N06L MTB50N06V MTB50N06VL MTB52N06V MTB52N06VL MTB55N06Z MTB60N06HD MTB75N06HD MTB75N05HD MTB60N05HDL MTB1306 NTB75N0306 NTB75N03L09 MTB75N03HDL 125 125 169 90 90 120 120 125 125 165 188 136 125 125 125 150 150 150 150 125 772 790 825 816 798 210 215 834 843 862 871 880 895 922 915 885 765 220 225 905

P-Channel
60 0.12 0.08 30 0.025 23 30 50 MTB23P06V MTB30P06V MTB50P03HDL 90 125 125 781 807 852

27. TC = 25C 28. See Data Sheet for Applicable Mounting Configuration. 29. Also available in Tape and Reel. T4 suffix = 800 per reel.

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Power MOSFET Selector Guide (continued)

Table 14. TO-220AB Case 221A09


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () ID (cont) Amps PD (Note NO TAG) (Watts) Max Page No.

Device

N-Channel
200 0.70 0.16 150 0.07 0.13 100 0.25 0.07 0.04 60 0.150 0.12 0.085 0.046 0.04 0.026 0.028 0.022 0.014 0.01 50 30 0.0095 0.022 0.0065 0.0065 25 0.22 0.18 0.085 0.05 0.028 0.032 0.025 0.029 0.0085 0.009 0.009 7.0 20 29 20 10 27 40 10 12 12 15 15 20 27 32 30 45 45 42 42 52 52 60 75 75 42 75 75 75 75 MTP7N20E MTP20N20E MTP29N15E MTP20N15E MTP10N10E MTP27N10E MTP40N10E MTP10N10EL MTP3055V MTP3055VL MTP15N06V MTP15N06VL MTP20N06V NTP27N06 MTP36N06V MTP30N06VL NTP45N06 NTP45N06L MTP50N06V MTP50N06VL MTP52N06V MTP52N06VL MTP60N06HD MTP75N06HD MTP75N05HD MTP1302 MTP1306 NTP75N0306 NTP75N03L09 MTP75N03HDL 50 125 125 112 75 104 169 40 48 48 55 60 60 74 90 90 120 120 125 125 165 165 150 150 150 74 150 150 150 150 1320 1175 1199 1173 1123 1187 1243 1130 1213 1219 1155 1161 1167 208 1237 1225 210 215 1249 1255 1268 1274 1286 1313 1306 1141 1148 220 225 1299

P-Channel
500 200 100 60 6.0 1.0 0.30 0.45 0.20 0.12 0.08 30 0.025 2.0 6.0 12 5.0 12 23 30 50 MTP2P50E MTP6P20E MTP12P10 MTP5P06V MTP2955V MTP23P06V MTP30P06V MTP50P03HDL 75 75 75 40 60 90 125 125 1207 1293 1136 1280 1193 1181 1231 1261

30. TC = 25C

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Power MOSFET Selector Guide (continued)

Table 15. TO-247 (Isolated Mounting Hole) Case 340K01


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps PD (Note 31.) (Watts) Max Page No.

Device

N-Channel
250 200 150 100 0.08 0.075 0.05 0.035 32 32 35 45 MTW32N25E MTW32N20E MTW35N15E MTW45N10E 250 180 180 180 1365 1359 1371 1377

Table 16. TO-264 Case 340G02


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps PD (Note 31.) (Watts) Max Page No.

Device

N-Channel
200 0.028 55 MTY55N20E 300 1383

Table 17. SMARTDISCRETES


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 5.0 V () 2.7 V () Function Device PD (Notes 31. & 32.) (Watts) Max Page No.

TO-220AB
62 (Clamped) 0.75 0.40 Current Limit, ESD Current Limit, ESD MLP1N06CL MLP2N06CL 40 40 360 366

DPAK
62 (Clamped) 0.75 Current Limit, ESD MLD1N06CLT4 (Note 33.) 40 354

D2PAK 5 Lead
40 V 0.02 Temp Sense, ESD, Overvoltage Protect NIB64045L 115 23

SO8
30 V 0.05 Current Mirror, ESD Protect NIMD6302R2 (Note 34.) 20 27

31. TC = 25C 32. See Data Sheet for Applicable Mounting Configuration. 33. Available in Tape and Reel only. T4 suffix = 2500 per reel. 34. Available in Tape and Reel only. R2 suffix = 2500 per reel.

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Power MOSFET Selector Guide (continued)

Table 18. TO-92


V(BR)DSS (Volts) Min Max RDS(on) @ VGS 10 V () 4.5 V () 2.7 V () ID (cont) Amps PD (Note 35.) (Watts) Max Page No.

Device

N-Channel
240 10 6.0 200 14 6.0 90 60 2.0 7.5 5.0 5.0 1.7 1.2 35 1.4 1.4 8.0 @ 2.8 V 6.0 3.3 @ 5 V 10 @ 2.5 V 10 @ 2.5 V 10 @ 2.5 V 28 @ 2.6 V 0.2 0.2 0.25 0.25 0.25 2.0 0.15 0.5 0.2 2.0 0.2 2.0 2.0 VN2410L VN2406L BS108 BS107 BS107A MPF990 VN2222LL BS170 2N7000 MPF960 VN0300L MPF930 MPF930A 0.35 0.35 0.35 0.35 0.35 1.0 0.4 0.35 0.35 1.0 0.35 1.0 1.0 1396 1394 275 271 271 761 1391 277 264 761 1389 761 761

Table 19. Ignition IGBTs Insulated Gate Bipolar Transistors


V(BR)CES (Volts) Min Max VCE(on) @ VGE 4.0 V IC = 6.0 A 4.5 V IC = 10 A IC (pulse) Amps IC (cont) Amps PD (Notes 35. & 36.) (Watts) Max Page No.

Device

TO-220AB
400 V (Clamped) 350 V (Clamped) 1.6 1.6 1.6 1.9 1.9 1.8 50 50 50 15 15 19 MGP15N40CL MGP15N35CL MGP19N35CL 150 150 166 301 293 309

D2PAK
400 V (Clamped) 350 V (Clamped) 1.6 1.6 1.6 1.9 1.9 1.8 50 50 50 15 15 19 MGB15N40CLT4 (Note 37.) MGB15N35CLT4 (Note 37.) MGB19N35CLT4 (Note 37.) 150 150 166 301 293 309

DPAK
410 V (Clamped) 1.7 2.1 50 15 NGD15N41CLT4 (Note 38.) 96 21

35. TC = 25C 36. See Data Sheet for Applicable Mounting Configuration. 37. Available in Tape and Reel only. T4 suffix = 800 per reel. 38. Available in Tape and Reel only. T4 suffix = 2500 per reel.

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CHAPTER 1 MOSFET Data Sheets

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20

NGD15N41CL Product Preview Ignition IGBT 15 Amps, 410 Volts


NChannel DPAK
This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and OverVoltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. Ideal for CoilonPlug Applications DPAK Package Offers Smaller Footprint and Increased Board Space GateEmitter ESD Protection Temperature Compensated GateCollector Voltage Clamp Limits Stress Applied to Load Integrated ESD Diode Protection New Cell Design Increases Unclamped Inductive Switching (UIS) Energy Per Area ShortCircuit Withstand Capability Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices Low Saturation Voltage High Pulsed Current Capability Optional Gate Resistor (RG) and GateEmitter Resistor (RGE)
MAXIMUM RATINGS (55C TJ 175C unless otherwise noted)
Rating CollectorEmitter Voltage CollectorGate Voltage GateEmitter Voltage Collector CurrentContinuous @ TC = 25C Operating and Storage Temperature Range Symbol VCES VCER VGE IC TJ, Tstg Value 440 440 15 15 55 to 175 Unit VDC VDC VDC ADC C TBD = Specific Device Code

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15 AMPS 410 VOLTS VCE(on) @ 10 A = 2.1 V MAX


C

RG RGE

MARKING DIAGRAM

DPAK CASE 369A STYLE 2

TBD

ORDERING INFORMATION
Device NGD15N41CL NGD15N41CLT4 Package DPAK DPAK Shipping 75 Units/Rail 2500/Tape & Reel

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

21

March, 2001 Rev. 2

Publication Order Number: NGD15N41CL/D

NGD15N41CL
UNCLAMPED COLLECTORTOEMITTER AVALANCHE CHARACTERISTICS (55C TJ 175C)
Characteristic Single Pulse CollectortoEmitter Avalanche Energy VCC = 50 V, VGE = 5 V, Pk IL = 16 A, L = 1.8 mH, Starting TJ = 25C VCC = 50 V, VGE = 5 V, Pk IL = 15 A, L = 1.8 mH, Starting TJ = 150C Symbol EAS 225 200 Value Unit mJ

THERMAL CHARACTERISTICS
Thermal Resistance, Junction to Ambient DPAK RJA TL 100 275 C/W C Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds

ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)


Characteristic Symbol Test Conditions Min Typ Max Unit

OFF CHARACTERISTICS
CollectorEmitter Clamp Voltage Zero Gate Voltage Collector Current BVCES ICES IC = 2 mA TJ = 40C to 175C VCE = 300 V, VGE = 0, TJ = 25C VCE = 300 V, VGE = 0, TJ = 150C Reverse CollectorEmitter Leakage Current GateEmitter Clamp Voltage Gate Resistor (Optional) Gate Emitter Resistor (Optional) IECS BVGES RG RGE VCE = 24 V IG = 5 mA 380 10 10 410 70 440 40 200 1.0 16 26 mA VDC k VDC ADC

ON CHARACTERISTICS*
Gate Threshold Voltage Threshold Temperature Coefficient (Negative) CollectortoEmitter OnVoltage CollectortoEmitter OnVoltage VGE(th) VCE(on) VCE(on) IC = 1 mA VGE = VCE IC = 6 A, VGE = 4 V IC = 10 A, VGE = 4.5 V, TJ = 150C 1.0 1.4 4.4 2.1 1.8 2.1 VDC mV/C VDC VDC

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance CISS COSS CRSS VCC = 15 V VGE = 0 V f = 1 MHz 700 60 6.0 pF

SWITCHING CHARACTERISTICS*
TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time *Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. td(off) tf td(on) tr VCC = 300 V, IC = 10 A RG = 1 k, L = 300 H VCC = 10 V, IC = 6.5 A RG = 1 k, RL = 1 4.0 10 1.0 4.0 Sec Sec

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NIB6404-5L
Preferred Device

Product Preview SMARTDISCRETESt 52 Amps, 40 Volts


Self Protected with Temperature Sense NChannel D2PAK
SMARTDISCRETES devices are an advanced series of Power MOSFETs which utilize ON Semiconductor s latest MOSFET technology process to achieve the lowest possible onresistance per silicon area while incorporating additional features such as clamp diodes. They are capable of withstanding high energy in the avalanche and commutation modes. The avalanche energy is specified to eliminate guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. This new SMARTDISCRETES device features integrated GatetoSource diodes for ESD protection, and GatetoDrain clamp for overvoltage protection. Also, this device integrates a sense diode for temperature monitoring. Ultra Low RDS(on) Provides Higher Efficiency IDSS Specified at Elevated Temperature Avalanche Energy Specified Overvoltage Protection Temperature Sense Diode ESD Human Body Model Discharge Sensitivity Class 3
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage GatetoSource Voltage Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (Note 1.) (VDD = 25 Vdc, VGS = 5.0 Vdc, IL(pk) = 25 A, L = 1.4 mH, RG = 10 k) Drain Current Continuous @ TA = 25C Continuous @ TA = 140C Single Pulse (tpv10 s) Total Power Dissipation (t 10 seconds) Linear Derating Factor Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1.) Symbol VDSS VDGR VGS TJ, Tstg EAS Value 40 40 "10 55 to +175 450 Unit Vdc Vdc Vdc C mJ TBD = Specific Device Code

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52 AMPERES 40 VOLTS RDS(on) = 20 m


D T2

G T1 S

MARKING DIAGRAM

D2PAK CASE 936D PLASTIC

TBD

ORDERING INFORMATION
Device NIB64045L Package D2PAK Shipping TBD

Adc ID ID IDM PD @ TA = 25C RJC RJA 52 25 200 115 0.76 1.3 80 W W/C C/W

Preferred devices are recommended choices for future use and best overall value.

1. Measured while surface mounted to an FR4 board using the minimum recommended pad size. Typical value is 64C/W.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

23

February, 2001 Rev. 1

Publication Order Number: NIB64045L/D

NIB64045L
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc, 55C < TJ < 175C) Temperature Coefficient (Negative) GatetoSource Clamp Voltage (Note 2.) (VGS = 0 Vdc, IG = 20 Adc) Zero Gate Voltage Drain Current (VDS = 35 Vdc, VGS = 0 Vdc) (VDS = 15 Vdc, VGS = 0 Vdc) (VDS = 35 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 5.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 1.0 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 2.) (VGS = 5.0 Vdc, ID = 20 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) (Note 2.) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 32 Vdc, ID = 25 Adc, VGS = 5.0 Vdc) (Note 2.) (VDD = 32 Vdc, ID = 25 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 10 ) (Note 2.) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 25 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Charge TEMPERATURE SENSE DIODE CHARACTERISTICS Forward (Reverse) OnVoltage Temperature Coefficient (Negative) Forward Voltage Hysteresis (IF(R) = 250 Adc) (Note 2.) (IF(R) = 250 Adc, TJ = 125C) IF(R) = 250 Adc, TJ = 160C IF(R) = 125 Adc to 250 Adc VAC(ACR) VFTC Vhys 715 1.57 25 743 570 1.71 37 775 1.85 50 mVdc mV/C mVdc (IS = 20 Adc, VGS = 0 Vdc) (Note 2.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.876 0.746 60 29 32 80 1.2 pC Vdc ns 16 263 149 345 29 6.0 16 2.0 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1720 525 120 pF VGS(th) 1.0 RDS(on) gFS TBD 1.7 4.5 18 34 2.0 20 Vdc mV/C m mhos V(BR)DSS 40 V(BR)GSS IDSS IGSS 1.1 0.2 4.0 0.02 100 2.0 20 1.0 Adc 10 51 7.0 13 55 20 Vdc mV/C Vdc Adc Symbol Min Typ Max Unit

2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperatures.

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24

NIB64045L
TYPICAL ELECTRICAL CHARACTERISTICS
50 I D, DRAIN CURRENT (AMPS) 45 40 35 30 25 20 15 10 5.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) RDS(on), DRAINTOSOURCE RESISTANCE (mW) RDS(on), DRAINTOSOURCE RESISTANCE (mW) VGS = 2.5 V 3.0 V TJ = 25C 40 5.0 V 4.5 V 4.0 V I D, DRAIN CURRENT (AMPS) 3.5 V 35 30 25 20 15 10 5.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS, GATETOSOURCE VOLTAGE (VOLTS) TJ = 175C 25C 55C

Figure 1. OnRegion Characteristics


50 45 40 35 30 25 20 15 10 5.0 0 0 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) 55C 25C TJ = 175C

Figure 2. Transfer Characteristics


50 45 40 35 30 25 20 15 10 5.0 0 0 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) TJ = 25C 4.0 V 5.0 V 10 V VGS = 3.0 V 3.5 V

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (C) VGS = 5.0 V ID = 20 A C, CAPACITANCE (pF)

4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 5.0 10 15 20 Coss Crss 25 30 Ciss VGS = 0 V f = 1.0 MHz TJ = 25C

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. Capacitance Variation

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25

NIB64045L
TYPICAL ELECTRICAL CHARACTERISTICS
5000 4500 C, CAPACITANCE (pF) 4000 3500 3000 2500 2000 1500 1000 500 0 0 2.0 4.0 6.0 8.0 10 VGS, GATETOSOURCE VOLTAGE (VOLTS) VDS = 0 V f = 1 MHz TJ = 25C Coss 20 Ciss IS, SOURCE CURRENT (A) 18 16 14 12 10 8.0 6.0 4.0 2.0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCETODRAIN VOLTAGE (VOLTS) TJ = 175C 25C

Figure 7. Capacitance Variation


VFTC, TEMPERATURE COEFFICIENT (mV/C)

Figure 8. Diode Forward Voltage versus Current


1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 50 0 50 100 150 TJ, JUNCTION TEMPERATURE (C) IF(R) = 250 mA

1.0 VF, FORWARD VOLTAGE (V) 0.9 IF(R) = 500 mA 0.8 250 mA 0.7 125 mA 0.6 0.5 50 mA 0.4 0.3 100 25 mA 50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (C)

Figure 9. Sense Diode Forward Voltage Variation with Temperature

Figure 10. Sense Diode Temperature Coefficient Variation with Temperature

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26

NIMD6302R2 Product Preview SMARTDISCRETESt 5 Amps, 30 Volts


Self Protected with Current Sense NChannel SO8, Dual
SMARTDISCRETES devices are an advanced series of Power MOSFETs which utilize ON Semiconductor s latest MOSFET technology process to achieve the lowest possible onresistance per silicon area while incorporating smart features. They are capable of withstanding high energy in the avalanche and commutation modes. The avalanche energy is specified to eliminate guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. This new SMARTDISCRETES device features an integrated GatetoSource clamp for ESD protection. Also, this device features a sense FET for current monitoring. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life IDSS Specified at Elevated Temperature Avalanche Energy Specified Current Sense FET ESD Protected, Main FET and SENSEFET
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in this specification is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. SOIC8 CASE 751 STYLE 19

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5.0 AMPERES 30 VOLTS RDS(on) = 50 m


Drain

Gate

Sense

Main FET

Source Sense

Source Main

MARKING DIAGRAM
Source 1 Gate 1 Source 2 Gate 2 1 2 3 4 (Top View) TBD = Specific Device Code TBD 8 7 6 5 Mirror 1 Drain 1 Mirror 2 Drain 2

MAIN MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 MW) GatetoSource Voltage Single Pulse DraintoSource Avalanche Energy (Note 1.) (VDD = 25 Vdc, VGS = 10 Vdc, VDS = 20 Vdc, IL = 15 Apk, L = 10 mH, RG = 25 ) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C (Note 1.) Single Pulse (tpv10 s) Symbol VDSS VDGR VGS EAS Value 30 30 "16 250 Unit Vdc Vdc Vdc mJ

ORDERING INFORMATION
Device NIMD6302R2 Package SOIC8 Shipping TBD

ID 6.5 Adc ID 4.4 Adc IDM 33 Apk Maximum Power Dissipation (TA = 25C) PD TBD W 1. Switching characteristics are independent of operating junction temperatures
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

27

February, 2001 Rev. 1

Publication Order Number: NIMD6302R2/D

NIMD6302R2
MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 2.) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 25C) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 125C) Forward Transconductance (Note 2.) (VDS = 6.0 Vdc, ID = 15 Adc) (VDS = 15 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS (Note 3.) Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 6.0 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDD = 6.0 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) Forward OnVoltage (Notes 2., 3.) Reverse Recovery Time (Note 3.) (IS = 3.0 3 0 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge (Note 3.) MIRROR MOSFET CHARACTERISTICS (TJ = 25C unless otherwise noted) Main/Mirror MOSFET (VDS = 6.0 Vdc, IDmain = 25 mA) Current Ratio (VDS = 6.0 Vdc, IDmain = 25 mA, TA = 125C) Main/Mirror Current Ratio Variation versus Current and Temperature GateBody Leakage Current (VDS = 6.0 Vdc, IDmain = 25 mA, TA = 25 to 125C) VDS = 0 Vdc, VGS = 3.0 Vdc (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) trr ta tb QRR VSD S 0.76 0.62 24.7 13 12 0.018 mC ns Vdc 8.4 24 18 5.0 11.3 2.8 1.9 2.2 nC ns (VDS = 6.0 6 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 380 272 93 600 350 200 pF VGS(th) RDS(on) gFS 7.4 5.5 50 TBD mhos 1.0 5.0 2.0 Vdc mV/C m V(BR)DSS 30 IDSS IGSS 22 10 100 32 Adc 35 30 Vdc mV/C Adc Symbol Min Typ Max Unit

IRAT

192 192 7.5

200 200 3.0

208 208 +7.5

IDRAT

IGSS

100

nAdc

2. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperatures.

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28

NTD20N03L27 Power MOSFET 20 Amps, 30 Volts


NChannel DPAK
This logic level vertical power MOSFET is a general purpose part that provides the best of design available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The draintosource diode has a ideal fast but soft recovery.
Features http://onsemi.com

UltraLow RDS(on), single base, advanced technology SPICE parameters available Diode is characterized for use in bridge circuits IDSS and VDS(on) specified at elevated temperatures High Avalanche Energy Specified ESD JEDAC rated HBM Class 1, MM Class A, CDM Class 0 Power Supplies Inductive Loads PWM Motor Controls Replaces MTD20N03L in many applications

20 AMPERES 30 VOLTS RDS(on) = 27 m


NChannel D

Typical Applications
G S

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25_C Continuous @ TA = 100_C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25_C Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5 Vdc, L = 1.0 mH, IL(pk) = 24 A, VDS = 34 Vdc) Thermal Resistance JunctiontoCase JunctiontoAmbient JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 30 30 "20 "24 20 16 60 74 0.6 1.75 55 to 150 288 Adc Apk Watts W/C W C mJ 1 Gate 2 Drain Unit Vdc Vdc Vdc 1 2 3 20N3L Y WW 4 CASE 369A DPAK STYLE 2 = Device Code = Year = Work Week

MARKING DIAGRAM

YWW 20N3L

PIN ASSIGNMENT
4 Drain

TJ, Tstg EAS

C/W RJC RJA RJA TL 1.67 100 71.4 260 C

3 Source

ORDERING INFORMATION
Device NTD20N03L27 NTD20N03L271 NTD20N03L27T4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size and repetitive rating; pulse width limited by maximum junction temperature.

Semiconductor Components Industries, LLC, 2001

29

January, 2001 Rev. 0

Publication Order Number: NTD20N03L27/D

NTD20N03L27
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ =150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 2.) (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) Static DraintoSource OnResistance (Note 2.) (VGS = 5.0 Vdc, ID = 20 Adc) (VGS = 5.0 Vdc, ID = 10 Adc, TJ = 150C) Forward Transconductance (Note 2.) (VDS = 5.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 15 Adc, Ad VGS = 10 Vdc) (Note 2.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (Note 2.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS =15 15 Adc, Adc VGS = 0 Vdc, Vdc dlS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. trr ta tb QRR VSD 1.0 0.9 23 13 10 0.017 1.15 C ns Vdc (VDD = 20 Vdc, ID = 20 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) (Note 2.) td(on) tr td(off) tf QT Q1 Q2 17 137 38 31 13.8 2.8 6.6 25 160 45 40 18.9 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1005 271 87 1260 420 112 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 0.48 0.40 21 0.54 mhos 28 23 31 27 Vdc 1.6 5.0 2.0 Vdc mV/C m V(BR)DSS 30 IDSS IGSS 10 100 100 nAdc 43 Vdc mV/C Adc Symbol Min Typ Max Unit

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30

NTD20N03L27
40 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDS, DRAINTOSOURCE VOLTAGE (V) TJ = 25C VGS = 3 V VGS = 2.5 V VGS = 10 V VGS = 8 V VGS = 4 V VGS = 4.5 V VGS = 5 V VGS = 3.5 V VGS = 6 V 40 36 32 28 24 20 16 12 8 4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 TJ = 100C TJ = 25C TJ = 55C VDS > = 10 V

VGS, GATETOSOURCE VOLTAGE (V)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 2 5 8 12 15 18 22 25 28 32 35 38 ID, DRAIN CURRENT (AMPS) TJ = 25C TJ = 55C VGS = 5 V TJ = 100C

0.03

TJ = 25C VGS = 5 V

0.025

0.02 VGS = 10 V

0.015

0.01 0 4 8 12 16 20 24 28 32 36 40 ID, DRAIN CURRENT (AMPS)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance vs. Drain Current and Temperature


1.6 ID = 10 A VGS = 5 V IDSS, LEAKAGE (nA) 100 1000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V TJ = 125C

1.4

1.2

TJ = 100C 10

0.8

0.6 50

1 25 0 25 50 75 100 125 150 0 3 6 9 12 15 18 21 24 27 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (V)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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31

NTD20N03L27
VGS, GATETOSOURCE VOLTAGE (V) 2500 VGS VDS C, CAPACITANCE (pF) 200 12 10 8 VGS 6 4 2 0 Q1 Q2 Q

1500 Ciss

1000 Coss Crss 0 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 23 25

500

ID = 20 A TJ = 25C 0 2 4 6 8 10 12 14

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (V)

Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge

1000 IS, SOURCE CURRENT (AMPS)

20 18 16 14 12 10 8 6 4 2 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGS = 0 V TJ = 25C

t, TIME (ns)

100

tr tf td(off)

10

td(on) VDS = 20 V ID = 20 A VGS = 5.0 V TJ = 25C 1 10 RG, GATE RESISTANCE () 100

VSD, SOURCETODRAIN VOLTAGE (V)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance


EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 350

Figure 10. Diode Forward Voltage vs. Current

ID = 24 A 300 250 200 150 100 50 0 25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Avalanche Energy vs. Starting Junction Temperature

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32

NTD20N06 Advance Information Power MOSFET 20 Amps, 60 Volts


NChannel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous Nonrepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH, IL(pk) = 18.4 A, VDS = 60 Vdc) Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1.) JunctiontoAmbient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "20 "30 Adc 20 10 60 60 0.40 1.88 1.36 55 to 175 170 Unit Vdc Vdc Vdc 1 2 3

20 AMPERES 60 VOLTS RDS(on) = 46 m


NChannel D

Typical Applications

G S 4 4

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)

CASE 369A DPAK (Bent Lead) STYLE 2 NTD20N06 Y WW

CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week

Apk W W/C W W C mJ

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain YWW NTD 20N06 1 Gate 2 Drain 3 Source 1 Gate 2 Drain YWW NTD 20N06

TJ, Tstg EAS

C/W RJC RJA RJA TL 2.5 80 110 260 C

3 Source

ORDERING INFORMATION
Device NTD20N06 NTD20N061 NTD20N06T4 Package DPAK DPAK Straight Lead DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Semiconductor Components Industries, LLC, 2001

33

March, 2001 Rev. 3

Publication Order Number: NTD20N06/D

NTD20N06
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 3.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (Note 3.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 3.) (VGS = 10 Vdc, ID = 10 Adc) Static DraintoSource OnVoltage (Note 3.) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) Forward Transconductance (Note 3.) (VDS = 7.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 20 Adc, Ad VGS = 10 Vdc) (Note 3.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 20 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. (IS = 20 Adc, VGS = 0 Vdc) (Note 3.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR 1.0 0.87 42.9 33 9.9 0.084 1.2 C Vdc ns (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (Note 3.) td(on) tr td(off) tf QT Q1 Q2 9.5 60.5 27.1 37.1 21.2 5.6 7.3 20 120 60 80 30 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 725 213 58 1015 300 120 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 0.78 1.57 13.2 1.10 mhos 37.5 46 Vdc 2.91 6.9 4.0 Vdc mV/C m V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 71.7 79.4 Vdc mV/C Adc Symbol Min Typ Max Unit

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34

NTD3055-094 Advance Information Power MOSFET 12 Amps, 60 Volts


NChannel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Lower RDS(on) Lower VDS(on) Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits
1 2 3

12 AMPERES 60 VOLTS RDS(on) = 94 m


NChannel D

Typical Applications
G S 4 4

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH IL(pk) = 11 A, VDS = 60 Vdc) Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1.) JunctiontoAmbient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "20 "30 12 10 45 48 0.32 2.1 1.5 55 to +175 61 Adc Apk W W/C W W C mJ Unit Vdc Vdc Vdc

CASE 369A DPAK (Bent Lead) STYLE 2 NTD3055094 Y WW

CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain YWW NTD 3055094 1 Gate 2 Drain 3 Source 1 Gate 2 Drain YWW NTD 3055094

TJ, Tstg EAS

RJC RJA RJA TL

3.13 71.4 100 260

C/W

3 Source

ORDERING INFORMATION
Device NTD3055094 Package DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).
This document contains information on a new product. Specifications and information herein are subject to change without notice.

DPAK NTD30550941 Straight Lead NTD3055094T4 DPAK

Semiconductor Components Industries, LLC, 2001

35

March, 2001 Rev. 1

Publication Order Number: NTD3055094/D

NTD3055094
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 3.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (Note 3.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 3.) (VGS = 10 Vdc, ID = 6.0 Adc) Static DraintoSource OnVoltage (Note 3.) (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) Forward Transconductance (Note 3.) (VDS = 7.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 12 Adc, Ad VGS = 10 Vdc) (Note 3.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 12 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. (IS = 12 Adc, VGS = 0 Vdc) (Note 3.) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR 0.94 0.82 33.1 24 8.9 0.047 1.15 C Vdc ns (VDD = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc, RG = 9.1 ) (Note 3.) td(on) tr td(off) tf QT Q1 Q2 7.7 32.3 25.2 23.9 10.9 3.1 4.2 15 70 50 50 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 323 107 34 450 150 70 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 0.85 0.77 6.7 1.35 mhos 84 94 Vdc 2.9 6.3 4.0 Vdc mV/C mOhm V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 68 54.4 Vdc mV/C Adc Symbol Min Typ Max Unit

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36

NTD3055L104 Advance Information Power MOSFET 12 Amps, 60 Volts, Logic Level


NChannel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Lower RDS(on) Lower VDS(on) Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits
1 2 3

12 AMPERES 60 VOLTS RDS(on) = 104 m


NChannel D

Typical Applications
G S 4 4

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH IL(pk) = 11 A, VDS = 60 Vdc) Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1.) JunctiontoAmbient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "15 "20 12 10 45 48 0.32 2.1 1.5 55 to +175 61 Adc Apk W W/C W W C mJ Unit Vdc Vdc Vdc

CASE 369A DPAK (Bent Lead) STYLE 2 NTD3055L104 Y WW

CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain YWW NTD 3055L104 1 Gate 2 Drain 3 Source 1 Gate 2 Drain YWW NTD 3055L104

TJ, Tstg EAS

RJC RJA RJA TL

3.13 71.4 100 260

C/W

3 Source

ORDERING INFORMATION
Device NTD3055L104 Package DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).
This document contains information on a new product. Specifications and information herein are subject to change without notice.

DPAK NTD3055L1041 Straight Lead NTD3055L104T4 DPAK

Semiconductor Components Industries, LLC, 2001

37

March, 2001 Rev. 1

Publication Order Number: NTD3055L104/D

NTD3055L104
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 3.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (Note 3.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 3.) (VGS = 5.0 Vdc, ID = 6.0 Adc) Static DraintoSource OnVoltage (Note 3.) (VGS = 5.0 Vdc, ID = 12 Adc) (VGS = 5.0 Vdc, ID = 6.0 Adc, TJ = 150C) Forward Transconductance (Note 3.) (VDS = 8.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 12 Adc, Ad VGS = 5.0 Vdc) (Note 3.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 12 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. (IS = 12 Adc, VGS = 0 Vdc) (Note 3.) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR 0.95 0.82 35 21 14 0.04 1.2 C Vdc ns (VDD = 30 Vdc, ID = 12 Adc, VGS = 5.0 Vdc, RG = 9.1 ) (Note 3.) td(on) tr td(off) tf QT Q1 Q2 9.2 104 19 40.5 7.4 2.0 4.0 20 210 40 80 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 316 105 35 440 150 70 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 0.98 0.86 9.1 1.50 mhos 89 104 Vdc 1.6 4.2 2.0 Vdc mV/C mOhm V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 70 62.9 Vdc mV/C Adc Symbol Min Typ Max Unit

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38

NTD32N06 Power MOSFET 32 Amps, 60 Volts


NChannel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Smaller Package than MTB36N06V Lower RDS(on) Lower VDS(on) Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits

32 AMPERES 60 VOLTS RDS(on) = 26 m


NChannel D

Typical Applications

G 4 4 1 2 3 Value 60 60 "20 "30 32 22 90 93.75 0.625 2.88 1.5 55 to +175 313 Adc Apk W W/C W W C mJ 1 Gate YWW NTD 32N06 2 Drain 3 Source 1 Gate 2 Drain Unit Vdc Vdc Vdc VGS VGS ID ID IDM PD CASE 369A DPAK (Bent Lead) STYLE 2 NTD32N06 Y WW T S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (Note 3.) (VDD = 50 Vdc, VGS = 10 Vdc, L = 1.0 mH, IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 ) Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1.) JunctiontoAmbient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR

2 3

CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week = MOSFET

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain YWW NTD 32N06

TJ, Tstg EAS

C/W RJC RJA RJA TL 1.6 52 100 260 C

3 Source

ORDERING INFORMATION
Device NTD32N06 NTD32N061 NTD32N06T4 Package DPAK DPAK Straight Lead DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). 3. Repetitive rating; pulse width limited by maximum junction temperature.
Semiconductor Components Industries, LLC, 2001

39

March, 2001 Rev. 1

Publication Order Number: NTD32N06/D

NTD32N06
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 4.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Note 4.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 4.) (VGS = 10 Vdc, ID = 16 Adc) Static DraintoSource OnVoltage (Note 4.) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 32 Adc) (VGS = 10 Vdc, ID = 16 Adc, TJ = 150C) Forward Transconductance (Note 4.) (VDS = 6 Vdc, ID = 16 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 32 Adc, Ad VGS = 10 Vdc) (Note 4.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (Note 4.) (IS = 32 Adc, VGS = 0 Vdc) (Note 4.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) (IS = 32 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. VSD 0.89 0.96 0.75 52 37 14.3 0.095 1.0 C Vdc (VDD = 30 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (Note 4.) td(on) tr td(off) tf QT Q1 Q2 10 84 31 93 33 6.0 15 25 180 70 200 60 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1231 346 77 1725 485 160 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 0.417 0.680 0.633 21.1 0.62 mhos 21 26 Vdc 2.8 7.0 4.0 Vdc mV/C mOhm V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 70 41.6 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

trr ta tb QRR

ns

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40

NTD32N06

60 VGS = 10 V ID, DRAIN CURRENT (AMPS) 50 40 30 20 10 0 VGS = 4.5 V VGS = 4 V ID, DRAIN CURRENT (AMPS) VGS = 6 V VGS = 6.5 V VGS = 7 V VGS = 5.5 V VGS = 8 V VGS = 5 V

60 VDS > = 10 V 50 40 30 20 10 0 0 1 2 3 4 3 3.4 3.8 4.2 4.6 5 5.4 5.8 6.2 6.6 7 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS) TJ = 25C TJ = 100C TJ = 55C

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.038 VGS = 10 V TJ = 100C

0.024 0.023 0.022 VGS = 10 V 0.021 0.02 VGS = 15 V 0.019 0.018 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS)

0.034 0.03

0.026 0.022 0.018 0.014 0.01 0 10 20 30 40 50 60 TJ = 25C

TJ = 55C

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1 0.8 0.6 50 25 10 0 25 50 75 100 125 150 175 10000 ID = 16 A VGS = 10 V IDSS, LEAKAGE (nA) 1000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V TJ = 150C

TJ = 125C 100 TJ = 100C

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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41

NTD32N06
VGS, GATETOSOURCE VOLTAGE (VOLTS)

3200 2800 C, CAPACITANCE (pF) 2400 2000 1600 1200 800 400 0 10

VDS = 0 V Ciss

VGS = 0 V

TJ = 25C

12 QT VGS

10 8 6 4 2 0 0

Crss Ciss

Q1 Q2

Coss Crss 5 VGS 0 VDS 5 10 15 20 25

ID = 32 A TJ = 25C 4 8 12 16 20 24 28 32 36

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation


1000 IS, SOURCE CURRENT (AMPS) VDS = 30 V ID = 32 A VGS = 10 V t, TIME (ns) 32 28 24 20 16 12 8 4 0 0.6

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge


VGS = 0 V TJ = 25C

100

tr tf td(off) td(on)

10

10 RG, GATE RESISTANCE ()

100

0.64 0.68 0.72 0.76

0.8

0.84 0.88

0.92 0.96

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance


EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 1000 ID, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C RDS(on) Limit Thermal Limit Package Limit 350 300 250 200 150 100 50 0 25

Figure 10. Diode Forward Voltage vs. Current

ID = 32 A

100

dc 10 10 ms 1 ms 100 s Mounted on 3 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating,10 s max 0.1 0.1 1 10 100

50

75

100

125

150

175

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature

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42

NTD32N06
10 Normalized to RJC at Steady State

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.1

0.01 0.00001

0.0001

0.001

0.01 t, TIME (s)

0.1

10

Figure 13. Thermal Response

10 r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board

0.1

0.01 0.00001

0.0001

0.001

0.01

0.1 t, TIME (s)

10

100

1000

Figure 14. Thermal Response

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43

NTD32N06L Power MOSFET 32 Amps, 60 Volts, Logic Level


NChannel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Smaller Package than MTB30N06VL Lower RDS(on) Lower VDS(on) Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits

32 AMPERES 60 VOLTS RDS(on) = 28 m


NChannel D

Typical Applications
G S

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (Note 3.) (VDD = 50 Vdc, VGS = 5 Vdc, L = 1.0 mH, IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 ) Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 1.) JunctiontoAmbient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "15 "20 32 22 90 93.75 0.625 2.88 1.5 55 to +175 313 Adc Apk W W/C W W C mJ Unit Vdc Vdc Vdc 1 2 3 4 CASE 369A DPAK STYLE 2

MARKING DIAGRAM
YWW NTD 32N06L

NTD32N06L Y WW T

= Device Code = Year = Work Week = MOSFET

PIN ASSIGNMENT
4 Drain

TJ, Tstg EAS

C/W RJC RJA RJA TL 1.6 52 100 260 C

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device NTD32N06L NTD32N06L1 NTD32N06LT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). 3. Repetitive rating; pulse width limited by maximum junction temperature.
Semiconductor Components Industries, LLC, 2001

44

March, 2001 Rev. 0

Publication Order Number: NTD32N06L/D

NTD32N06L
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 4.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Note 4.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 4.) (VGS = 5 Vdc, ID = 16 Adc) Static DraintoSource OnResistance (Note 4.) (VGS = 5 Vdc, ID = 20 Adc) (VGS = 5 Vdc, ID = 32 Adc) (VGS = 5 Vdc, ID = 16 Adc, TJ = 150C) Forward Transconductance (Note 4.) (VDS = 6 Vdc, ID = 16 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 32 Adc, Ad VGS = 5 Vdc) (Note 4.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (Note 4.) (IS = 32 Adc, VGS = 0 Vdc) (Note 4.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) (IS = 32 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. VSD 0.89 0.95 0.74 56 31 25 0.093 1.0 C Vdc (VDD = 30 Vdc, ID = 32 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) (Note 4.) td(on) tr td(off) tf QT Q1 Q2 12.8 221 37 128 23 4.5 14 30 450 80 260 50 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1214 343 87 1700 480 180 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 0.48 0.78 0.61 27 0.67 mhos 23.7 28 Vdc 1.7 4.8 2.0 Vdc mV/C mOhm V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 70 62 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

trr ta tb QRR

ns

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45

NTD32N06L

60 VGS = 10 V ID, DRAIN CURRENT (AMPS) 50 40 30 20 10 0 VGS = 6 V VGS = 3.5 V VGS = 8 V VGS = 3 V VGS = 5 V VGS = 4 V ID, DRAIN CURRENT (AMPS) VGS = 4.5 V

60 VDS > = 10 V 50 40 30 20 10 0 1.8

TJ = 25C TJ = 100C 2.2 2.6 3 TJ = 55C 3.4 3.8 4.2 4.6 5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.042 VGS = 5 V

0.042 0.038 0.034 0.03 0.026 0.022 0.018 0.014 0.01 0 10 20 TJ = 55C TJ = 100C TJ = 25C VGS = 10 V

0.038 0.034 0.03 TJ = 25C TJ = 100C

0.026 0.022 0.018 0.014 0.01 0 10 20

TJ = 55C

30

40

50

60

30

40

50

60

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1 0.8 0.6 50 25 10 0 25 50 75 100 125 150 175 ID = 16 A VGS = 5 V 10000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V IDSS, LEAKAGE (nA)

TJ = 150C

1000 TJ = 125C

100 TJ = 100C

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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46

NTD32N06L
VGS, GATETOSOURCE VOLTAGE (VOLTS)

4000 3600 C, CAPACITANCE (pF) 3200 2800 2400 2000 1600 1200 800 400 0 10

VDS = 0 V Ciss Crss

VGS = 0 V

TJ = 25C

6 5 4 3 2 1 0 0 ID = 32 A TJ = 25C 4 8 12 16 20 24 Q1 QT VGS Q2

Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation


1000 IS, SOURCE CURRENT (AMPS) VDS = 30 V ID = 32 A VGS = 5 V t, TIME (ns) tr 100 tf 32 28 24 20 16 12 8 4 0 0.6

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge


VGS = 0 V TJ = 25C

td(off)

td(on) 10 1 10 RG, GATE RESISTANCE () 100

0.64 0.68 0.72 0.76

0.8

0.84 0.88

0.92 0.96

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance


EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 1000 ID, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C RDS(on) Limit Thermal Limit Package Limit 350

Figure 10. Diode Forward Voltage vs. Current

ID = 32 A 300 250 200 150 100 50 0 25 50 75 100 125 150 175

100

dc 10 10 ms 1 ms 100 s 1 Mounted on 3 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating,10 s max 0.1 0.1 1 10 100 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature

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47

NTD32N06L
10 Normalized to RJC at Steady State

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.1

0.01 0.00001

0.0001

0.001

0.01 t, TIME (s)

0.1

10

Figure 13. Thermal Response

10 r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board

0.1

0.01 0.00001

0.0001

0.001

0.01

0.1 t, TIME (s)

10

100

1000

Figure 14. Thermal Response

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48

NTD4302 Power MOSFET 18.5 Amps, 30 Volts


NChannel DPAK
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS Specified at Elevated Temperature SO8 Mounting Information Provided

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18.5 AMPERES 30 VOLTS 10 m @ VGS = 10 V


NChannel D

Applications

DCDC Converters Low Voltage Motor Control Power Management in Portable and Battery Powered Products:
i.e., Computers, Printers, Cellular and Cordless Telephones, and PCMCIA Cards
1 2 3

G S 4

12

CASE 369A DPAK (Bend Lead) STYLE 2

CASE 369 DPAK (Straight Lead) STYLE 2

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain YWW T 4302 1 Gate 4302 Y WW T 2 Drain 3 Source = Device Code = Year = Work Week = MOSFET 1 Gate 4 Drain YWW T 4302

3 Source 2 Drain

ORDERING INFORMATION
Device NTD4302 NTD43021 NTD4302T4 Package DPAK DPAK Straight Lead DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2001

49

March, 2001 Rev. 1

Publication Order Number: NTD4302/D

NTD4302
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Pulsed Drain Current (Note 5.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 5.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 5.) Thermal Resistance JunctiontoAmbient (Note 4.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 5.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 17 Apk, L = 5.0 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. 2. 3. 4. 5. Symbol VDSS VGS RJA PD ID IDM RJA PD ID ID IDM RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 30 20 1.3 96 30 90 25 5.0 18.5 11.5 60 67 1.87 11.3 7.1 36 120 1.04 8.4 5.3 28 55 to 150 722 260 Unit Vdc Vdc C/W Watts Amps Amps C/W Watts Amps Amps Amps C/W Watts Amps Amps Amps C/W Watts Amps Amps Amps C mJ C

TL Mounted on Heat Sink, Steady State. Mounted on 2 square FR4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), Time 10 seconds. Mounted on 2 square FR4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), Steady State. Minimum FR4 or G10 PCB, Steady State. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.

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50

NTD4302
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 A) Positive Temperature Coefficient Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Negative Temperature Coefficient Static DrainSource OnState Resistance (VGS = 10 Vdc, ID = 18.5 Adc) (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge g (VDS = 24 Vd Vdc, ID = 2.0 2 0 Ad Adc, VGS = 10 Vdc) BODYDRAIN DIODE RATINGS (Note 6.) Diode Forward OnVoltage (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 18.5 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery y Time (IS = 2.3 2 3 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 6. Indicates Pulse Test: Pulse Width = 300 sec max, Duty Cycle 2%. 7. Switching characteristics are independent of operating junction temperature. VSD trr ta tb Qrr 0.75 0.88 0.65 39 20 19 0.043 1.0 65 C ns Vdc (VDD = 24 Vdc, ID = 18.5 Adc, VGS = 10 Vdc, Vdc RG = 2.5 ) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, Vdc RG = 2.5 ) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, Vdc RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf td(on) tr td(off) tf QT Qgs (Q1) Qgd (Q2) 11 15 85 55 11 13 55 40 15 25 40 58 55 5.5 15 20 25 130 90 20 20 90 75 80 nC ns ns ns (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 1 0 MHz) Ciss Coss Crss 2050 640 225 2400 800 310 pF VGS(th) 1.0 RDS(on) gFS 0.0078 0.0078 0.010 20 0.010 0.010 0.013 Mhos 1.9 3.8 3.0 Vdc V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 25 Vdc mV/C Adc Symbol Min Typ Max Unit

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51

NTD4302
50 ID, DRAIN CURRENT (AMPS) 60 VDS > = 10 V ID, DRAIN CURRENT (AMPS) 50 40 30 20 10 0 TJ = 25C TJ = 100C TJ = 55C

VGS = 4 V VGS = 4.4 V VGS = 4.6 V VGS = 5 V VGS = 7 V VGS = 10 V

TJ = 25C VGS = 3.8 V

40

30

20

VGS = 3.4 V VGS = 3.2 V VGS = 3.0 V

10 0 0 0.5 1

VGS = 2.8 V

1.5

2.5

VDS, DRAINTOSOURCE VOLTAGE (V)

VGS, GATETOSOURCE VOLTAGE (V)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

RDS(on), DRAINTOSOURCE RESISTANCE ()

0.1

RDS(on), DRAINTOSOURCE RESISTANCE ()

ID = 10 A TJ = 25C

0.015

TJ = 25C

0.075

VGS = 4.5 V 0.01

0.05

VGS = 10 V

0.005

0.025

0 0 2 4 6 8 10 VGS, GATETOSOURCE VOLTAGE (V)

0.00E+00

1.00E+01

2.00E+01

3.00E+01

4.00E+01

5.00E+01

6.00E+01

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GateToSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 1.6 ID = 18.5 A VGS = 10 V 10000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V TJ = 150C

1.4

1.2

IDSS, LEAKAGE (nA)

1000

100

TJ = 100C

10

0.8 0.6 50

1 25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (V)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current vs. Voltage

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52

NTD4302
60 VDS = 0 V 50 C, CAPACITANCE (pF) Ciss 40 30 20 10 0 10 Crss VGS 0 VDS 10 Coss VGS = 0 V TJ = 25C 12.5 QT VD 30 VDS, DRAINTOSOURCE VOLTAGE (V) 1 VGS, GATETOSOURCE VOLTAGE (V)

10

25

7.5 VGS 5 Q1 Q2

20

Crss

Ciss

15

2.5 ID = 2 A TJ = 25C 0 10 20 30 40 50 Qg, TOTAL GATE CHARGE (nC)

10

20

30

0 60

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (V)

Figure 7. Capacitance Variation

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge

1000 IS, SOURCE CURRENT (AMPS) VDD = 24 V ID = 18.5 A VGS = 10 V t, TIME (ns)

25

VGS = 0 V TJ = 25C

20

15

100 tf td(off) tr td(on) 10 1 10 RG, GATE RESISTANCE () 100

10

0 0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (V)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance

Figure 10. Diode Forward Voltage vs. Current

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53

NTD4302
100 ID , DRAIN CURRENT (AMPS) 100 ms di/dt VGS = 10 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 1 ms IS trr ta tp IS 100 tb TIME 0.25 IS

10

10 ms dc

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Diode Reverse Recovery Waveform

1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE DUTY CYCLE 100 10 1 0.1 0.01 SINGLE PULSE 1E-05 1E-04 1E-03 1E-02 D = 0.5 0.2 0.1 0.05 0.02 0.01

MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT

P(pk) t2 DUTY CYCLE, D = t1/t2 1E-01 t, TIME (seconds) 1E+00 t1

RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+02 1E+03

1E+01

Figure 13. Thermal Response Various Duty Cycles

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54

NTD4302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 14 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 14. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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55

NTD4302
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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56

NTGS3433T1 Product Preview MOSFET -3.3 Amps, -12 Volts


PChannel TSOP6
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Miniature TSOP6 Surface Mount Package
Applications

http://onsemi.com

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones, and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted.)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds Symbol VDSS VGS RJA Pd ID IDM Pd ID RJA Pd ID IDM Pd ID TJ, Tstg TL Value 12 "8.0 62.5 2.0 3.3 20 1.0 2.35 128 1.0 2.35 14 0.5 1.65 55 to 150 260 Unit Volts Volts C/W Watts Amps Amps Watts Amps C/W Watts Amps Amps Watts Amps C C

3.3 AMPERES 12 VOLTS 75 mW @ VGS = 4.5 V


PChannel 1 2 5 6 DRAIN

3 GATE 4 SOURCE

MARKING DIAGRAM
3 2

TSOP6 CASE 318G STYLE 1

433 x

433 x

= Device Code = Date Code

1. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. 2. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state.

PIN ASSIGNMENT
Drain Drain Source
6 5 4

Drain Drain Gate

ORDERING INFORMATION
Device NTGS3433T1
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package TSOP6

Shipping 3000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

57

December, 2000 Rev. 0

Publication Order Number: NTGS3433T1/D

NTGS3433T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 3. & 4.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 8 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 8 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +8.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DrainSource OnState Resistance (VGS = 4.5 Vdc, ID = 3.3 Adc) (VGS = 2.5 Vdc, ID = 2.9 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 3.3 Adc) DYNAMIC CHARACTERISTICS Total Gate Charge GateSource Charge GateDrain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Reverse Recovery Time BODYDRAIN DIODE RATINGS Diode Forward OnVoltage (IS = 1.7 Adc, VGS = 0 Vdc) VSD 0.80 0.90 1.5 Vdc Vdc (IS = 1.7 Adc, dlS/dt = 100 A/s) (VDD = 1 10 0 Vdc, ID = 1 1.0 .0 Adc, VGS = 4.5 Vdc, Rg = 6.0 W) td(on) tr td(off) tf trr 20 20 110 100 30 30 30 120 115 ns ns (VDS = 5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) (VDS = 10 Vdc, Vd VGS = 4.5 4 5 Vdc, Vd ID = 3.3 Adc) Qtot Qgs Qgd Ciss Coss Crss 7.0 2.0 3.5 550 450 200 15 pF nC VGS(th) 0.50 RDS(on) gFS 7.0 0.055 0.075 0.075 0.095 mhos 0.70 1.50 W Vdc V(BR)DSS 12 IDSS IGSS IGSS 100 100 nAdc 1.0 5.0 nAdc Adc Vdc Symbol Min Typ Max Unit

Diode Forward OnVoltage (IS = 3.3 Adc, VGS = 0 Vdc) VSD 3. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 4. Class 1 ESD rated Handling precautions to protect against electrostatic discharge is mandatory.

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58

NTGS3433T1
12 ID, DRAIN CURRENT (AMPS) 10 8 6 4 TJ = 25C 2 VGS = 1.5 V 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) VGS = 5 V VGS = 2.5 V VGS = 3 V VGS = 3.5 V VGS = 4 V VGS = 4.5 V VGS = 2 V 20 18 16 14 12 10 8 6 4 2 0 0.5 1 1.5 2 2.5 3 3.5 4 TJ = 125C VDS 10 V TJ = 55C TJ = 25C

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8 ID = 3.3 A TJ = 25C

0.3 TJ = 25C 0.25 0.2 0.15 0.1 VGS = 4.5 V 0.05 0 VGS = 2.5 V

10

12

14

16

18

20

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance vs. GatetoSource Voltage

Figure 4. OnResistance vs. Drain Current and Gate Voltage

1.6 ID = 3.3 A VGS = 4.5 V

1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) Ciss Coss Crss 0 2.5 5 7.5 10 12.5 15 17.5 20 VGS = 0 V TJ = 25C

1.4

1.2

0.8

0.6 50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. Capacitance Variation

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59

NTGS3433T1
VGS, GATETOSOURCE VOLTAGE (VOLTS) 6 5 4 3 Qgs 2 1 0 Qgd TJ = 25C ID = 3.3 A 0 2 4 6 8 10 10 IS, SOURCE CURRENT (AMPS) 9 8 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 TJ = 25C TJ = 150C VGS = 0 V

QT

Qg, TOTAL GATE CHARGE (nC)

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 7. GatetoSource and DraintoSource Voltage vs. Total Charge


NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 1 Duty Cycle = 0.5

Figure 8. Diode Forward Voltage vs. Current

0.2 0.1 0.1 0.05 0.02 0.01 0.1 1E04 1E03 Single Pulse 1E02 1E01 1E+00 1E+01 1E+02 1E+03

SQUARE WAVE PULSE DURATION (sec)

Figure 9. Normalized Thermal Transient Impedance, JunctiontoAmbient

20 16 POWER (W)

12

4 0 0.01

0.10

1.00 TIME (sec)

10.00

100.00

Figure 10. Single Pulse Power

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60

NTGS3441T1 Power MOSFET 1 Amp, 20 Volts


PChannel TSOP6
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Miniature TSOP6 Surface Mount Package
Applications

http://onsemi.com

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones, and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds Symbol VDSS VGS RJA Pd ID IDM RJA Pd ID IDM RJA Pd ID IDM TJ, Tstg TL Value 20 "8.0 244 0.5 1.65 10 128 1.0 2.35 14 62.5 2.0 3.3 20 55 to 150 260 Unit Volts Volts C/W Watts Amps Amps C/W Watts Amps Amps C/W Watts Amps Amps C C
4 5 6 3

1 AMPERE 20 VOLTS RDS(on) = 90 mW


PChannel 1 2 5 6

MARKING DIAGRAM
2

TSOP6 CASE 318G STYLE 1

441 W

1. Minimum FR4 or G10PCB, operating to steady state. 2. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state. 3. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds.

441 W

= Device Code = Work Week

PIN ASSIGNMENT
Drain Drain Source
6 5 4

Drain Drain Gate

ORDERING INFORMATION
Device NTGS3441T1 Package TSOP6 Shipping 3000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

61

November, 2000 Rev. 1

Publication Order Number: NTGS3441T1/D

NTGS3441T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 4. & 5.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +8.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DrainSource OnState Resistance (VGS = 4.5 Vdc, ID = 3.3 Adc) (VGS = 2.5 Vdc, ID = 2.9 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 3.3 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS Diode Forward OnVoltage Diode Forward OnVoltage (IS = 1.6 Adc, VGS = 0 Vdc) (IS = 3.3 Adc, VGS = 0 Vdc) VSD VSD trr 0.88 0.98 30 1.2 60 Vdc Vdc ns (VDS = 10 Vdc, Vd VGS = 4.5 4 5 Vdc, Vd ID = 3.3 Adc) (VDD = 2 20 0 Vdc, ID = 1 1.6 .6 Adc, VGS = 4.5 Vdc, Rg = 6.0 W) td(on) tr td(off) tf Qtot Qgs Qgd 13 23.5 27 24 6.2 1.3 2.5 25 45 50 45 14 ns ns ns ns nC nC nC (VDS = 5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 480 265 100 pF pF pF VGS(th) 0.45 RDS(on) gFS 6.8 0.069 0.117 0.090 0.135 mhos 1.05 1.50 W Vdc V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 1.0 5.0 nAdc Adc Vdc Symbol Min Typ Max Unit

Reverse Recovery Time (IS = 1.6 Adc, dIS/dt = 100 A/s) 4. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 5. Handling precautions to protect against electrostatic discharge is mandatory.

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62

NTGS3441T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 ID, DRAIN CURRENT (AMPS)

TJ = 25C

VGS = 2.7 V ID, DRAIN CURRENT (AMPS) VGS = 2.5 V VGS = 3 V VGS = 3.5 V VGS = 4 V VGS = 4.5 V VGS = 6 V VGS = 2 V

20

VDS> = 10 V TJ = 25C TJ = 55C TJ = 100C

16

12

2 VGS = 10 V 0 0 0.4 0.8 1.2 1.6 2 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS = 1.5 V

0 0.4

0.8

1.2

1.6

2.4

2.8

3.2

3.6

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


0.4 RDS(on), DRAINTOSOURCE RESISTANCE () ID = 3.3 A TJ = 25C 0.3 0.28

Figure 2. Transfer Characteristics

RDS(on), DRAINTOSOURCE RESISTANCE ()

TJ = 25C 0.24 0.2 0.16 0.12 0.08 0.04 0 0 4 8 12 16 20 ID, DRAIN CURRENT (AMPS) VGS = 4.5 V VGS = 2.5 V

0.2

0.1

0 2 3 4 5 6 7 8 VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance vs. GatetoSource Voltage

Figure 4. OnResistance vs. Drain Current and Gate Voltage

100 RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 1.4 ID = 3.3 A VGS = 4.5 V IDSS, LEAKAGE (nA) 10

VGS = 0 V TJ = 125C

1.2

TJ = 100C

TJ = 25C

0.8

0.6 50

0.1 25 0 25 50 75 100 125 150 0 4 8 12 16 20 TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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63

NTGS3441T1
TYPICAL ELECTRICAL CHARACTERISTICS
1200 8

Ciss C, CAPACITANCE (pF) 900

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS = 0 V

VGS = 0 V

TJ = 25C

6 QT 4 Qgs 2 Qgd VDD = 20 V ID = 3.3 A TJ = 25C

600

Crss Ciss

300

Coss Crss

0 8 4 VGS 0 4 VDS 8 12 16 20

0 0 2 4 6 8 Qg, TOTAL GATE CHARGE (nC)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation


VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 50 ID = 250 A 10 IS, SOURCE CURRENT (AMPS)

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge

VGS = 0 V TJ = 25C 8

25

25

50

75

100

125

150

0 0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

TJ, JUNCTION TEMPERATURE (C)

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Gate Threshold Voltage Variation with Temperature

Figure 10. Diode Forward Voltage vs. Current

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64

NTGS3441T1
TYPICAL ELECTRICAL CHARACTERISTICS
20

16 POWER (W)

12

0 0.01

0.10

1.00 TIME (sec)

10.00

100.00

Figure 11. Single Pulse Power

NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE

1 Duty Cycle = 0.5

0.2 0.1 0.1 0.05 0.02 0.01 1E03 Single Pulse 1E02 1E01 1E+00 1E+01 1E+02 1E+03

0.01 1E04

SQUARE WAVE PULSE DURATION (sec)

Figure 12. Normalized Thermal Transient Impedance, JunctiontoAmbient

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65

NTGS3441T1 INFORMATION FOR USING THE TSOP6 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.094 2.4

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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66

NTGS3443T1 Power MOSFET 2 Amps, 20 Volts


PChannel TSOP6
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Miniature TSOP6 Surface Mount Package
Applications

http://onsemi.com

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones, and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds Symbol VDSS VGS RJA Pd ID IDM RJA Pd ID IDM RJA Pd ID IDM TJ, Tstg TL Value 20 "12 244 0.5 2.2 10 128 1.0 3.1 14 62.5 2.0 4.4 20 55 to 150 260 Unit Volts Volts C/W Watts Amps Amps C/W Watts Amps Amps C/W Watts Amps Amps C C
4 5 6 3

2 AMPERES 20 VOLTS RDS(on) = 65 mW


PChannel 1 2 5 6

MARKING DIAGRAM
2

TSOP6 CASE 318G STYLE 1

443 W

1. Minimum FR4 or G10PCB, operating to steady state. 2. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state. 3. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds.

443 W

= Device Code = Work Week

PIN ASSIGNMENT
Drain Drain Source
6 5 4

Drain Drain Gate

ORDERING INFORMATION
Device NTGS3443T1 Package TSOP6 Shipping 3000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

67

November, 2000 Rev. 1

Publication Order Number: NTGS3443T1/D

NTGS3443T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 4. & 5.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DrainSource OnState Resistance (VGS = 4.5 Vdc, ID = 4.4 Adc) (VGS = 2.7 Vdc, ID = 3.7 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 4.4 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS Diode Forward OnVoltage Reverse Recovery Time (IS = 1.7 Adc, VGS = 0 Vdc) VSD trr 0.83 30 1.2 Vdc ns (IS = 1.7 Adc, dIS/dt = 100 A/s) 4. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 5. Handling precautions to protect against electrostatic discharge is mandatory. (VDS = 10 Vdc, Vd VGS = 4.5 4 5 Vdc, Vd ID = 4.4 Adc) (VDD = 2 20 0 Vdc, ID = 1 1.0 .0 Adc, VGS = 4.5 Vdc, Rg = 6.0 W) td(on) tr td(off) tf Qtot Qgs Qgd 10 18 30 31 7.5 1.4 2.9 25 45 50 50 15 ns ns ns ns nC nC nC (VDS = 5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 565 320 120 pF pF pF VGS(th) 0.60 RDS(on) gFS 8.8 0.058 0.082 0.092 0.065 0.090 0.100 mhos 0.95 1.50 W Vdc V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 1.0 5.0 nAdc Adc Vdc Symbol Min Typ Max Unit

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68

NTGS3443T1
TYPICAL ELECTRICAL CHARACTERISTICS
8 VGS = 5 V ID, DRAIN CURRENT (AMPS) 6 TJ = 25C VGS = 3 V VGS = 4.5 V VGS = 4 V VGS = 3.5 V VGS = 2 V ID, DRAIN CURRENT (AMPS) VGS = 2.5 V 8 VDS = 10 V 6

4 TJ = 25C 2 TJ = 125C

2 VGS = 1.5 V 0 0 0.4 0.8 1.2 1.6 2 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ = 55C 1.8 2.2 2.6 3

0 0.6

1.4

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE (OHMS) RDS(on), DRAINTOSOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 ID = 4.4 A TJ = 25C

0.16 TJ = 25C 0.14 0.12 0.1 0.08 VGS = 4.5 V 0.06 0.04 VGS = 2.5 V VGS = 2.7 V

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance vs. GatetoSource Voltage

Figure 4. OnResistance vs. Drain Current and Gate Voltage

1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 50 ID = 4.4 A VGS = 4.5 V

100

TJ = 125C TJ = 100C

IDSS, LEAKAGE (nA)

10

TJ = 25C

0.1 VGS = 0 V

0.01 25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C)

12

16

20

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature http://onsemi.com


69

Figure 6. DraintoSource Leakage Current vs. Voltage

NTGS3443T1
TYPICAL ELECTRICAL CHARACTERISTICS
1200 VGS, GATETOSOURCE VOLTAGE (VOLTS) 1000 C, CAPACITANCE (pF) 800 600 400 Coss 200 Crss 0 0 2 4 6 8 10 12 14 16 18 20 0 0 1 2 3 4 5 Ciss TJ = 25C VGS = 0 V 5 QT 4 VGS

Q1

Q2

2 TJ = 25C ID = 4.4 A 6 7 8

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge


4

VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 50 ID = 250 A IS, SOURCE CURRENT (AMPS)

VGS = 0 V 3

TJ = 150C

2 TJ = 25C 1

25

25

50

75

100

125

150

0 0.3

0.4

0.5

0.6

0.7

0.8

0.9

TJ, JUNCTION TEMPERATURE (C)

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Gate Threshold Voltage Variation with Temperature

Figure 10. Diode Forward Voltage vs. Current

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70

NTGS3443T1
TYPICAL ELECTRICAL CHARACTERISTICS
20

16 POWER (W)

12

0 0.01

0.10

1.00 TIME (sec)

10.00

100.00

Figure 11. Single Pulse Power

NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE

1 Duty Cycle = 0.5

0.2 0.1 0.1 0.05 0.02 0.01 1E03 Single Pulse 1E02 1E01 1E+00 1E+01 1E+02 1E+03

0.01 1E04

SQUARE WAVE PULSE DURATION (sec)

Figure 12. Normalized Thermal Transient Impedance, JunctiontoAmbient

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71

NTGS3443T1 INFORMATION FOR USING THE TSOP6 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.094 2.4

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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72

NTGS3446T1 Power MOSFET 5.3 Amps, 20 Volts


NChannel TSOP6
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS Specified at Elevated Temperature

http://onsemi.com

5.3 AMPERES 20 VOLTS RDS(on) = 45 mW


NChannel Drain 1 2 5 6

Applications

Power Management in portable and batterypowered products, i.e.


computers, printers, PCMCIA cards, cellular and cordless Lithium Ion Battery Applications Notebook PC

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating DraintoSource Voltage GateSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp t 10 s) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp t 10 s) Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol VDSS VGS RJA Pd ID IDM RJA Pd ID IDM TJ, Tstg TL Value 20 12 62.5 2.0 5.3 25 128 1.0 3.7 20 55 to 150 260 Unit Vdc Vdc C/W Watts Amps Amps C/W Watts
4

Gate 3

Source 4

MARKING DIAGRAM
3 2

TSOP6 CASE 318G STYLE 1 = Device Code = Work Week

446 W

Amps Amps C C

446 W

PIN ASSIGNMENT
Drain Drain Source 6 5 4

1. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. 2. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state.

1 2 3 Drain Drain Gate

ORDERING INFORMATION
Device NTGS3446T1 Package TSOP6 Shipping 3000 Tape & Reel

Semiconductor Components Industries, LLC, 2001

73

March, 2001 Rev. 2

Publication Order Number: NTGS3446/D

NTGS3446T1
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Collector Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 85C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage ID = 0.25 mA, VDS = VGS Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 5.3 Adc) (VGS = 2.5 Vdc, ID = 4.4 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 5.3 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vd Vdc, ID = 5.3 5 3 Ad Adc, VGS = 4.5 Vdc) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 3.) (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 85C) Reverse Recovery Time (IS = 1.7 1 7 Adc, Adc VGS = 0 Vdc, Vdc diS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature. trr ta tb QRR VSD 0.74 0.66 20 11 9.0 0.01 1.1 C ns Vdc (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) td(on) tr td(off) tf QT Qgs Qgd 9.0 12 35 20 8.0 2.0 2.0 16 20 60 35 15 nC ns (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 510 200 60 750 350 100 pF VGS(th) 0.6 RDS(on) gFS 36 44 12 45 55 mhos 0.85 2.5 1.2 Vdc mV/C mW V(BR)DSS 20 IDSS IGSS(f) IGSS(r) 1.0 25 100 100 nAdc 22 Vdc mV/C Adc Symbol Min Typ Max Unit

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74

NTGS3446T1
RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 t, TIME (ns) 1.2 1 0.8 0.6 0.4 50 1 VDD = 10 V ID = 1.0 A VGS = 4.5 V 25 0 25 50 75 100 125 150 1 10 RG, GATE RESISTANCE () 100 ID = 5.3 A VGS = 4.5 V 100 tf td(off) tr 10 td(on)

TJ, JUNCTION TEMPERATURE (C)

Figure 1. OnResistance Variation with Temperature

Figure 2. Resistive Switching Time Variation vs. Gate Resistance

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75

NTGS3455T1 Product Preview MOSFET -3.5 Amps, -30 Volts


PChannel TSOP6
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Miniature TSOP6 Surface Mount Package
Applications

http://onsemi.com

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones, and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted.)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Drain Current Continuous @ TA = 25C Pulsed Drain Current (Tp t 10 S) Maximum Operating Power Dissipation Maximum Operating Drain Current Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes for 10 Seconds Symbol VDSS VGS RJA Pd ID IDM Pd ID RJA Pd ID IDM Pd ID TJ, Tstg TL Value 30 "20.0 62.5 2.0 3.5 20 1.0 2.5 128 1.0 2.5 14 0.5 1.75 55 to 150 260 Unit Volts Volts C/W Watts Amps Amps Watts Amps C/W Watts Amps Amps Watts Amps C C

3.5 AMPERES 30 VOLTS 100 mW @ VGS = 10 V


PChannel 1 2 5 6 DRAIN

3 GATE 4 SOURCE

MARKING DIAGRAM
3 2

TSOP6 CASE 318G STYLE 1

455 x

455 x

= Device Code = Date Code

1. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), t t 5.0 seconds. 2. Mounted onto a 2 square FR4 board (1 sq. 2 oz. cu. 0.06 thick single sided), operating to steady state.

PIN ASSIGNMENT
Drain Drain Source
6 5 4

Drain Drain Gate

ORDERING INFORMATION
Device NTGS3455T1
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package TSOP6

Shipping 3000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

76

December, 2000 Rev. 0

Publication Order Number: NTGS3455T1/D

NTGS3455T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Notes 3. & 4.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 20.0 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +20.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DrainSource OnState Resistance (VGS = 10 Vdc, ID = 3.5 Adc) (VGS = 4.5 Vdc, ID = 2.7 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 3.5 Adc) DYNAMIC CHARACTERISTICS Total Gate Charge GateSource Charge GateDrain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Reverse Recovery Time BODYDRAIN DIODE RATINGS Diode Forward OnVoltage (IS = 1.7 Adc, VGS = 0 Vdc) VSD 0.90 1.0 1.2 Vdc Vdc (IS = 1.7 Adc, dlS/dt = 100 A/s) (VDD = 2 20 0 Vdc, ID = 1 1.0 .0 Adc, VGS = 10 Vdc, Rg = 6.0 W) td(on) tr td(off) tf trr 10 15 20 10 30 20 30 35 20 ns ns (VDS = 5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) (VDS = 15 Vdc, Vd VGS = 10 Vdc, Vd ID = 3.5 Adc) Qtot Qgs Qgd Ciss Coss Crss 9.0 2.5 2.0 480 220 60 13 pF nC VGS(th) 1.0 RDS(on) gFS 6.0 0.094 0.144 0.100 0.170 mhos 1.87 3.0 W Vdc V(BR)DSS 30 IDSS IGSS IGSS 100 100 nAdc 1.0 5.0 nAdc Adc Vdc Symbol Min Typ Max Unit

Diode Forward OnVoltage (IS = 3.5 Adc, VGS = 0 Vdc) VSD 3. Indicates Pulse Test: P.W. = 300 sec max, Duty Cycle = 2%. 4. Class 1 ESD rated Handling precautions to protect against electrostatic discharge is mandatory.

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77

NTGS3455T1
20 ID, DRAIN CURRENT (AMPS) VGS = 10 V VGS = 9 V VGS = 8 V VGS = 7 V VGS = 5 V VGS = 6 V ID, DRAIN CURRENT (AMPS) 20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 TJ = 25C TJ = 125C TJ = 55C

16

12

VGS = 4 V

TJ = 25C 0 0.5 1 1.5 2 2.5

VGS = 3 V 3 3.5 4

0 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.3 0.25 0.2 0.15 0.1 0.05 0 ID = 3.5 A TJ = 25C

0.3 TJ = 25C 0.25 0.2 0.15 VGS = 10 V 0.1 0.05 0 VGS = 4.5 V

10

10

12

14

16

18

20

VGS, GATETOSOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance vs. GatetoSource Voltage

Figure 4. OnResistance vs. Drain Current and Gate Voltage

1.6 ID = 3.5 A VGS = 10 V C, CAPACITANCE (pF)

700 VGS = 0 V TJ = 25C 500 Ciss 300 Coss 100 Crss 100 25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) 0 5 10 15 20 25 30

1.4

1.2

0.8

0.6 50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. Capacitance Variation

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78

NTGS3455T1
VGS, GATETOSOURCE VOLTAGE (VOLTS) 12 11 QT 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 Qgs Qgd TJ = 25C ID = 3.5 A 10 12 10 IS, SOURCE CURRENT (AMPS) VGS = 0 V 8 TJ = 150C

10

4 TJ = 25C 2

0.2

0.4

0.6

0.8

1.2

1.4

Qg, TOTAL GATE CHARGE (nC)

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 7. GatetoSource and DraintoSource Voltage vs. Total Charge


NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 1 Duty Cycle = 0.5

Figure 8. Diode Forward Voltage vs. Current

0.2 0.1 0.1 0.05 0.02 0.01 0.1 1E04 1E03 Single Pulse 1E02 1E01 1E+00 1E+01 1E+02 1E+03

SQUARE WAVE PULSE DURATION (sec)

Figure 9. Normalized Thermal Transient Impedance, JunctiontoAmbient

20 16 POWER (W)

12

4 0 0.01

0.10

1.00 TIME (sec)

10.00

100.00

Figure 10. Single Pulse Power

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79

NTHD5902T1 Product Preview Dual N-Channel 30 V (D-S) MOSFET


http://onsemi.com
D1 D2

G1

G2

PRODUCT SUMMARY
VDS (V) 30 rDS(on) () 0.085 @ VGS = 10 V 0.143 @ VGS = 4.5 V ID (A) "3.9 "3.0

S1 NChannel MOSFET

S2 NChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "3.9 "2.8 IDM IS PD 2.1 1.1 TJ, Tstg 1.1 0.6 C 1.8 "10 0.9 "2.9 "2.1 A A W 5 secs 30 "20 Steady State Unit V V A ChipFET CASE 1206A STYLE 2

PIN CONNECTIONS
D1 D1 D2 D2
8 7 6 5 1 2 3 4

S1 G1 S2 G2

55 to +150

MARKING DIAGRAM

1. Surface Mounted on 1 x 1 FR4 Board. A6

A6 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHD5902T1

Semiconductor Components Industries, LLC, 2000

80

December, 2000 Rev. 0

Publication Order Number: NTHD5902T1/D

NTHD5902T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot Steady State Symbol RthJA 50 90 RthJF 30 60 110 40 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "20 V VDS = 24 V, VGS = 0 V VDS = 24 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS w 5.0 V, VGS = 10 V VGS = 10 V, ID = 2.9 A VGS = 4.5 V, ID = 2.2 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 0.9 A, di/dt = 100 A/s VDD = 15 V, RL = 15 ID ^ 1.0 1 0 A, A VGEN = 10 V, V RG = 6 VDS = 15 V V, VGS = 10 V V, ID = 2.9 A 5.0 0.8 1.0 7.0 12 12 7.0 40 7.5 11 18 18 11 80 ns nC gfs VSD VDS = 15 V, ID = 2.9 A IS = 0.9 A, VGS = 0 V 1.0 10 0.072 0.120 20 0.8 "100 1.0 5.0 0.085 0.143 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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81

NTHD5902T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 VGS = 10 thru 5 V 8 ID,Drain Current (A) ID,Drain Current (A) 10

4V

4 125C 2 25C TC = 55C 4 5

3V

0.5

1.0 1.5 2.0 2.5 VDS, DraintoSource Voltage (V)

3.0

1 2 3 VGS, GatetoSource Voltage (V)

Figure 1. Output Characteristics

Figure 2. Transfer Characteristics

0.20 r DS(on),OnResistance ( )

400 300 VGS = 4.5 V C, Capacitance (pF)

0.15

Ciss

0.10 VGS = 10 V 0.05

200

Coss 100 Crss 0 4 8 12 16 VDS, DraintoSource Voltage (V) 20

0 0 2 4 6 ID, Drain Current (A) 8 10

Figure 3. OnResistance vs. Drain Current

Figure 4. Capacitance

10 VGS,GatetoSource Voltage (V) VDS = 15 V ID = 2.9 A r DS(on),OnResistance ( ) (Normalized)

1.8 1.6 1.4 1.2 1.0 0.8 0.6 50 VGS = 10 V ID = 2.9 A

2 3 Qg, Total Gate Charge (nC)

25

0 25 50 75 100 TJ, Junction Temperature (C)

125

150

Figure 5. Gate Charge

Figure 6. OnResistance vs. Junction Temperature

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82

NTHD5902T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 rDS(on), OnResistance ( ) 0.20

I S, Source Current (A)

0.15 ID = 2.9 A 0.10

TJ = 150C

TJ = 25C

0.05

0 0 0.2 0.4 0.6 0.8 1.0 VDS, DraintoSource Voltage (V) 1.2

2 4 6 8 VGS, GatetoSource Voltage (V)

10

Figure 7. SourceDrain Diode Forward Voltage

Figure 8. OnResistance vs. GatetoSource Voltage


50

0.4 0.2 V GS (th), Varience (V) ID = 250 A Power (W) 0.0 0.2 0.4 0.6 0.8 50

40

30

20

10

25

25 50 75 TJ, Temperature (C)

100

125

150

0 104

103

102

10 1 1 Time (sec)

10

100

600

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

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83

NTHD5902T1
TYPICAL ELECTRICAL CHARACTERISTICS
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 103 102 10 1 1 Square Wave Pulse Duration (sec) PDM t1 t2 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM TA = PDMZthJA(t) 4. Surface Mounted 10 100 600

0.01 104

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 Square Wave Pulse Duration (sec) 1 10

Figure 12. Normalized Thermal Transient Impedance, JunctiontoFoot

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84

NTHD5903T1 Product Preview Dual P-Channel 2.5 V (G-S) MOSFET


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S1 S2

G1

G2

PRODUCT SUMMARY
VDS (V) rDS(on) () 0.155 @ VGS = 4.5 V 20 0.180 @ VGS = 3.6 V 0.260 @ VGS = 2.5 V ID (A) "2.9 "2.7 "2.2

D1 PChannel MOSFET

D2 PChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "2.9 "2.1 IDM IS PD 2.1 1.1 TJ, Tstg 1.1 0.6 C 1.8 "10 0.9 "2.1 "1.5 A A W 5 secs Steady State Unit V V A D1 D1 D2 D2

ChipFET CASE 1206A STYLE 2

20 "12

PIN CONNECTIONS

8 7 6 5

1 2 3 4

S1 G1 S2 G2

MARKING DIAGRAM

55 to +150

1. Surface Mounted on 1 x 1 FR4 Board.

A7

A7 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHD5903T1

Semiconductor Components Industries, LLC, 2000

85

December, 2000 Rev. 0

Publication Order Number: NTHD5903T1/D

NTHD5903T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 50 90 RthJF 30 60 110 40 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "12 V VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS v 5.0 V, VGS = 4.5 V VGS = 4.5 V, ID = 2.1 A VGS = 3.6 V, ID = 2.0 A VGS = 2.5 V, ID = 1.7 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 0.9 A, di/dt = 100 A/s VDD = 10 V, RL = 10 ID ^ 1.0 10A A, VGEN = 4 4.5 5V V, RG = 6 5V VDS = 10 V V, VGS = 4 4.5 V, ID = 2.1 A 3.0 0.9 0.6 13 35 25 25 40 6.0 20 55 40 40 80 ns nC gfs VSD VDS = 10 V, ID = 2.1 A IS = 0.9 A, VGS = 0 V 0.6 10 0.130 0.150 0.215 5.0 0.8 "100 1.0 5.0 0.155 0.180 0.260 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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86

NTHD5903T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 3.5 V VGS = 5 thru 4 V 8 ID,Drain Current (A) I D,Drain Current (A) 3V 6 2.5 V 4 2V 2 1.5 V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, DraintoSource Voltage (V) 3.0 0 0 0.5 3.5 1.0 1.5 2.0 2.5 3.0 VGS, GatetoSource Voltage (V) 4.0 8 25C 6 125C 10 TC = 55C

Figure 1. Output Characteristics

Figure 2. Transfer Characteristics

0.4 r DS(on),OnResistance ( )

600 500 C, Capacitance (pF)

0.3

VGS = 2.5 V

400 300 200 100

Ciss

0.2

VGS = 3.6 V VGS = 4.5 V

0.1

Coss Crss 0 4 8 12 16 VDS, DraintoSource Voltage (V) 20

0 0 2 4 6 ID, Drain Current (A) 8 10

Figure 3. OnResistance vs. Drain Current

Figure 4. Capacitance

5 VGS,GatetoSource Voltage (V) VDS = 10 V ID = 2.1 A r DS(on),OnResistance ( ) (Normalized)

1.6 VGS = 4.5 V ID = 2.1 A

1.4

1.2

1.0

0.8

0.5

1.0

1.5

2.0

2.5

3.0

0.6 50

25

Qg, Total Gate Charge (nC)

0 25 50 75 100 TJ, Junction Temperature (C)

125

150

Figure 5. Gate Charge

Figure 6. OnResistance vs. Junction Temperature

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87

NTHD5903T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 rDS(on), OnResistance ( ) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 1 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VDS, DraintoSource Voltage (V) 1.4 0 1 2 3 4 VGS, GatetoSource Voltage (V) 5 ID = 2.1 A

I S, Source Current (A)

TJ = 150C

TJ = 25C

Figure 7. SourceDrain Diode Forward Voltage

Figure 8. OnResistance vs. GatetoSource Voltage


50

0.4 0.3 V GS (th), Varience (V) ID = 250 A Power (W) 0.2 0.1 0.0 0.1 0.2 50

40

30

20

10

25

25 50 75 TJ, Temperature (C)

100

125

150

0 104

103

102

10 1 1 Time (sec)

10

100

600

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

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88

NTHD5903T1
TYPICAL ELECTRICAL CHARACTERISTICS
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 103 102 10 1 1 Square Wave Pulse Duration (sec) PDM t1 t2 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM TA = PDMZthJA(t) 4. Surface Mounted 10 100 600

0.01 104

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 Square Wave Pulse Duration (sec) 1 10

Figure 12. Normalized Thermal Transient Impedance, JunctiontoFoot

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89

NTHD5904T1 Product Preview Dual N-Channel 2.5 V (G-S) MOSFET


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D1 D2

G1

G2

PRODUCT SUMMARY
VDS (V) 20 rDS(on) () 0.075 @ VGS = 4.5 V 0.134 @ VGS = 2.5 V ID (A) "4.2 "3.1

S1 NChannel MOSFET

S2 NChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "4.2 "3.0 IDM IS PD 2.1 1.1 TJ, Tstg 1.1 0.6 C A2 1.8 "10 0.9 "3.1 "2.2 A A W 5 secs 20 "12 Steady State Unit V V A ChipFET CASE 1206A STYLE 2

PIN CONNECTIONS
D1 D1 D2 D2
8 7 6 5 1 2 3 4

S1 G1 S2 G2

MARKING DIAGRAM

55 to +150

1. Surface Mounted on 1 x 1 FR4 Board.

A2 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHD5904T1

Semiconductor Components Industries, LLC, 2000

90

December, 2000 Rev. 0

Publication Order Number: NTHD5904T1/D

NTHD5904T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 50 90 RthJF 30 60 110 40 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "12 V VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS w 5.0 V, VGS = 4.5 V VGS = 4.5 V, ID = 3.1 A VGS = 2.5 V, ID = 2.3 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 0.9 A, di/dt = 100 A/s VDD = 10 V, RL = 10 ID ^ 1.0 1 0 A, A VGEN = 4.5 4 5 V, V RG = 6 VDS = 10 V V, VGS = 4.5 4 5 V, V ID = 3.1 A 4.0 0.6 1.3 12 35 19 9.0 40 6.0 18 55 30 15 80 ns nC gfs VSD VDS = 10 V, ID = 3.1 A IS = 0.9 A, VGS = 0 V 0.6 10 0.065 0.115 8.0 0.8 "100 1.0 5.0 0.075 0.143 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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91

NTHD5904T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 VGS = 5 thru 3 V 8 ID,Drain Current (A) 2.5 V D,Drain Current (A) 8 10 TC = 55C 25C

125C

4 2V 2 1.5 V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, DraintoSource Voltage (V) 3.0

I 2 0 0

0.5

1.0 1.5 2.0 2.5 3.0 VGS, GatetoSource Voltage (V)

3.5

Figure 1. Output Characteristics

Figure 2. Transfer Characteristics

0.30 r DS(on),OnResistance ( ) 0.25 C, Capacitance (pF) 0.20 0.15 0.10 0.05 0 0 2 4 6 8 10 ID, Drain Current (A) VGS = 2.5 V VGS = 4.5 V

600 500 Ciss 400 300 200 100 0 0 4 8 12 16 VDS, DraintoSource Voltage (V) 20 Coss Crss

Figure 3. OnResistance vs. Drain Current

Figure 4. Capacitance

5 VGS,GatetoSource Voltage (V) VDS = 10 V ID = 3.1 A r DS(on),OnResistance ( ) (Normalized)

1.6 VGS = 4.5 V ID = 3.1 A

1.4

1.2

1.0

0.8

2 3 1 Qg, Total Gate Charge (nC)

0.6 50

25

0 25 50 75 100 TJ, Junction Temperature (C)

125

150

Figure 5. Gate Charge

Figure 6. OnResistance vs. Junction Temperature

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92

NTHD5904T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 rDS(on), OnResistance ( ) 0.20

I S,Source Current (A)

0.15 ID = 3.1 A 0.10

TJ = 150C

TJ = 25C

0.05

0 0 0.2 0.4 0.6 0.8 1.0 VDS, DraintoSource Voltage (V) 1.2

1 2 3 4 VGS, GatetoSource Voltage (V)

Figure 7. SourceDrain Diode Forward Voltage

Figure 8. OnResistance vs. GatetoSource Voltage

0.4 0.2 V GS (th), Varience (V) 0.0 0.2 0.4 0.6 0.8 50 ID = 250 A Power (W)

50

40

30

20

10

25

25 50 75 100 TJ, Temperature (C)

125

150

0 104

103

102

10 1 1 Time (sec)

10

100

600

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

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93

NTHD5904T1
TYPICAL ELECTRICAL CHARACTERISTICS
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 103 102 10 1 1 Square Wave Pulse Duration (sec) PDM t1 t2 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM TA = PDMZthJA(t) 4. Surface Mounted 10 100 600

0.01 104

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 Square Wave Pulse Duration (sec) 1 10

Figure 12. Normalized Thermal Transient Impedance, JunctiontoFoot

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94

NTHD5905T1 Product Preview Dual P-Channel 1.8 V (G-S) MOSFET


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S1 S2

G1

G2

PRODUCT SUMMARY
VDS (V) rDS(on) () 0.090 @ VGS = 4.5 V 8.0 0.130 @ VGS = 2.5 V 0.180 @ VGS = 1.8 V ID (A) "4.1 "3.4 "2.9

D1 PChannel MOSFET

D2 PChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "4.1 "2.9 IDM IS PD 2.1 1.1 TJ, Tstg 1.1 0.6 C 1.8 "10 0.9 "3.0 "2.2 A A W 5 secs Steady State Unit V V A D1 D1 D2 D2

ChipFET CASE 1206A STYLE 2

8.0 "8.0

PIN CONNECTIONS
S1 G1 S2 G2

8 7 6 5

1 2 3 4

MARKING DIAGRAM

55 to +150

1. Surface Mounted on 1 x 1 FR4 Board.

A9

A9 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHD5905T1

Semiconductor Components Industries, LLC, 2000

95

December, 2000 Rev. 0

Publication Order Number: NTHD5905T1/D

NTHD5905T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 50 90 RthJF 30 60 110 40 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "8.0 V VDS = 6.4 V, VGS = 0 V VDS = 6.4 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS v 5.0 V, VGS = 4.5 V VGS = 4.5 V, ID = 3.0 A VGS = 2.5 V, ID = 2.5 A VGS = 1.8 V, ID = 1.0 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 0.9 A, di/dt = 100 A/s VDD = 4.0 V, RL = 4 ID ^ 1.0 10A A, VGEN = 4 4.5 5V V, RG = 6 0V 5V VDS = 4 4.0 V, VGS = 4 4.5 V, ID = 3.0 A 5.5 0.5 1.5 10 45 30 10 30 9.0 15 70 45 15 60 ns nC gfs VSD VDS = 5.0 V, ID = 3.0 A IS = 0.9 A, VGS = 0 V 0.45 10 0.075 0.110 0.150 7.0 0.8 "100 1.0 5.0 0.090 0.130 0.180 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

http://onsemi.com
96

NTHD5905T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 VGS = 5 thru 3 V 8 ID,Drain Current (A) 2V D,Drain Current (A) 2.5 V 8 10 TC = 55C 25C

125C

4 1.5 V 1V 0 0 0.5 1.0 1.5 2.0 2.5 VDS, DraintoSource Voltage (V) 3.0

0.5

1.0 1.5 2.0 2.5 VGS, GatetoSource Voltage (V)

3.0

Figure 1. Output Characteristics


0.30 r DS(on),OnResistance ( ) 0.25 0.20 0.15 0.10 0.05 0 0 2 4 6 ID, Drain Current (A) 8 10 VGS = 2.5 V VGS = 4.5 V C, Capacitance (pF) VGS = 1.8 V 1000

Figure 2. Transfer Characteristics

800 Ciss 600

400 Coss 200 Crss 0 0 4 8 12 16 VDS, DraintoSource Voltage (V) 20

Figure 3. OnResistance vs. Drain Current


5 VGS,GatetoSource Voltage (V) r DS(on),OnResistance ( ) (Normalized) 1.6

Figure 4. Capacitance

1.4

VGS = 4.5 V ID = 3 A

1.2

1.0

0.8

2 3 4 Qg, Total Gate Charge (nC)

0.6 50

25

0 25 50 75 100 TJ, Junction Temperature (C)

125

150

Figure 5. Gate Charge

Figure 6. OnResistance vs. Junction Temperature

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97

NTHD5905T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 rDS(on), OnResistance ( ) 0.25

I S, Source Current (A)

0.20

ID = 3 A

TJ = 150C

0.15

0.10

TJ = 25C 1

0.05

0 0 0.2 0.4 0.6 0.8 1.0 VDS, DraintoSource Voltage (V) 1.2 1.4

1 2 3 4 VGS, GatetoSource Voltage (V)

Figure 7. Source Diode Forward Voltage

Figure 8. OnResistance vs. GatetoSource Voltage


50

0.4 0.3 V GS (th), Varience (V) 0.2 0.1 0.0 ID = 250 A Power (W)

40

30

20

0.1 0.2 50

10

25

25 50 75 100 TJ, Temperature (C)

125

150

0 104

103

102

10 1 1 Time (sec)

10

100

600

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

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98

NTHD5905T1
TYPICAL ELECTRICAL CHARACTERISTICS
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 103 102 10 1 1 Square Wave Pulse Duration (sec) PDM t1 t2 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM TA = PDMZthJA(t) 4. Surface Mounted 10 100 600

0.01 104

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 Square Wave Pulse Duration (sec) 1 10

Figure 12. Normalized Thermal Transient Impedance, JunctiontoFoot

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99

NTHS5402T1 Product Preview N-Channel 30 V (D-S) MOSFET


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D

PRODUCT SUMMARY
VDS (V) 30 rDS(on) () 0.035 @ VGS = 10 V 0.055 @ VGS = 4.5 V ID (A) "6.7 "5.3

S NChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "6.7 "4.8 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 C A6 2.1 "20 1.1 "4.9 "3.5 A A W 5 secs 30 "20 Steady State Unit V V A D D D S
8 7 6 5 1 2 3 4

ChipFET CASE 1206A STYLE 1

PIN CONNECTIONS

D D D G

MARKING DIAGRAM

55 to +150

1. Surface Mounted on 1 x 1 FR4 Board.

A6 = Specific Device Code

ORDERING INFORMATION
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Device NTHS5402T1

Package ChipFET

Shipping 3000/Tape & Reel

Semiconductor Components Industries, LLC, 2000

100

December, 2000 Rev. 0

Publication Order Number: NTHS5402T1/D

NTHS5402T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 40 80 RthJF 15 50 95 20 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "20 V VDS = 24 V, VGS = 0 V VDS = 24 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS w 5.0 V, VGS = 10 V VGS = 10 V, ID = 4.9 A VGS = 4.5 V, ID = 3.9 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 1.1 A, di/dt = 100 A/s VDD = 15 V, RL = 15 ID ^ 1.0 1 0 A, A VGEN = 10 V, V RG = 6 VDS = 15 V V, VGS = 10 V V, ID = 4.9 A 13 1.3 3.1 10 10 25 10 30 20 15 15 40 15 60 ns nC gfs VSD VDS = 10 V, ID = 4.9 A IS = 1.1 A, VGS = 0 V 1.0 20 0.030 0.045 15 0.8 "100 1.0 5.0 0.035 0.055 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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101

NTHS5402T1
TYPICAL CHARACTERISTICS
20 VGS = 10 thru 5 V 16 ID,Drain Current (A) 4V ID,Drain Current (A) 20

16

12

12

8 3V 4

8 TC125C 4 25C TC = 55C

0.5

1.0 1.5 2.0 2.5 VDS, DraintoSource Voltage (V)

3.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS, GatetoSource Voltage (V)

Figure 1. Output Characteristics

Figure 2. Transfer Characteristics

0.10 r DS(on),OnResistance ( )

1200 1000 C, Capacitance (pF) Ciss 800 600 400 200 Crss 0 0 4 8 12 ID, Drain Current (A) 16 20 0 6 12 18 24 VDS, DraintoSource Voltage (V) 30 Coss

0.08

0.06

VGS = 4.5 V VGS = 10 V

0.04

0.02

Figure 3. OnResistance vs. Drain Current

Figure 4. Capacitance

10 VGS,GatetoSource Voltage (V) VDS = 15 V ID = 4.9 A r DS(on),OnResistance ( ) (Normalized)

1.6 VGS = 10 V ID = 4.9 A

1.4

1.2

1.0

0.8

6 9 Qg, Total Gate Charge (nC)

12

15

0.6 50

25

0 25 50 75 100 TJ, Junction Temperature (C)

125

150

Figure 5. Gate Charge

Figure 6. OnResistance vs. Junction Temperature

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102

NTHS5402T1
TYPICAL CHARACTERISTICS
20 rDS(on), OnResistance ( ) TJ = 150C I S, Source Current (A) 10 0.10

0.08 ID = 4.9 A 0.06

0.04

TJ = 25C

0.02

0 0 0.2 0.4 0.6 0.8 1.0 VSD, SourcetoDrain Voltage (V) 1.2

2 4 6 8 VGS, GatetoSource Voltage (V)

10

Figure 7. SourceDrain Diode Forward Voltage

Figure 8. OnResistance vs. GatetoSource Voltage

0.4 0.2 V GS (th), Varience (V) ID = 250 A 0.0 Power (W)

50

40

30

0.2 0.4 0.6 0.8 50

20

10

25

25 50 75 100 TJ, Temperature (C)

125

150

0 103

102

10 1

1 Time (sec)

10

100

600

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

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103

NTHS5402T1
TYPICAL CHARACTERISTICS
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 1 Square Wave Pulse Duration (sec) PDM t1 t2 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80C/W 3. TJM TA = PDMZthJA(t) 4. Surface Mounted 10 100 600

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5

0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 Square Wave Pulse Duration (sec) 1 10

Figure 12. Normalized Thermal Transient Impedance, JunctiontoFoot

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104

NTHS5402T1
80 mm 18 mm 25 mm 68 mm 80 mm

28 mm 26 mm 26 mm

28 mm

Figure 13.

Figure 14.

BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 13. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 14 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.

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105

NTHS5404T1 Product Preview N-Channel 2.5 V (G-S) MOSFET


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D

PRODUCT SUMMARY
VDS (V) 20 rDS(on) () 0.030 @ VGS = 4.5 V 0.045 @ VGS = 2.5 V ID (A) "7.2 "5.9

S NChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "7.2 "5.2 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 C 2.1 "20 1.1 "5.2 "3.8 A A W D S 5 secs 20 "12 Steady State Unit V V A D D

ChipFET CASE 1206A STYLE 1

PIN CONNECTIONS

8 7 6 5

1 2 3 4

D D D G

MARKING DIAGRAM

55 to +150

1. Surface Mounted on 1 x 1 FR4 Board.

A2

A2 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHS5404T1

Semiconductor Components Industries, LLC, 2000

106

December, 2000 Rev. 0

Publication Order Number: NTHS5404T1/D

NTHS5404T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 40 80 RthJF 15 50 95 20 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "12 V VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS w 5.0 V, VGS = 4.5 V VGS = 4.5 V, ID = 5.2 A VGS = 2.5 V, ID = 4.3 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 1.1 A, di/dt = 100 A/s VDD = 10 V, RL = 10 ID ^ 1.0 1 0 A, A VGEN = 4.5 4 5 V, V RG = 6 VDS = 10 V V, VGS = 4.5 4 5 V, V ID = 5.2 A 12 2.4 3.2 20 40 40 15 30 18 30 60 60 23 60 ns nC gfs VSD VDS = 10 V, ID = 5.2 A IS = 1.1 A, VGS = 0 V 0.6 20 0.025 0.038 20 0.8 "100 1.0 5.0 0.030 0.045 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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107

NTHS5404T1
80 mm 18 mm 25 mm 68 mm 80 mm

28 mm 26 mm 26 mm

28 mm

Figure 1.

Figure 2.

BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 1. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 2 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.

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108

NTHS5441T1 Product Preview P-Channel 2.5 V (G-S) MOSFET


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S

PRODUCT SUMMARY
VDS (V) rDS(on) () 0.055 @ VGS = 4.5 V 20 0.06 @ VGS = 3.6 V 0.083 @ VGS = 2.5 V ID (A) "5.3 "5.1 "4.3

D PChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "5.3 "3.8 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 C 2.1 "20 1.1 "3.9 "2.8 A A S W 5 secs Steady State Unit V V A D D D

ChipFET CASE 1206A STYLE 1

20 "12

PIN CONNECTIONS

8 7 6 5

1 2 3 4

D D D G

MARKING DIAGRAM

55 to +150

1. Surface Mounted on 1 x 1 FR4 Board.

A3

A3 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHS5441T1

Semiconductor Components Industries, LLC, 2000

109

December, 2000 Rev. 0

Publication Order Number: NTHS5441T1/D

NTHS5441T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 40 80 RthJF 15 50 95 20 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "12 V VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS v 5.0 V, VGS = 4.5 V VGS = 3.6 V, ID = 3.7 A VGS = 2.5 V, ID = 3.1 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 1.1 A, di/dt = 100 A/s VDD = 10 V, RL = 10 ID ^ 1.0 10A A, VGEN = 4 4.5 5V V, RG = 6 VDS = 10 V V, VGS = 4 4.5 5V V, ID = 3.9 A 11 3.0 2.5 20 35 65 45 30 22 30 55 100 70 60 ns nC gfs VSD VDS = 10 V, ID = 3.9 A IS = 1.1 A, VGS = 0 V 0.6 20 0.050 0.070 12 0.8 "100 1.0 5.0 0.06 0.083 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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110

NTHS5441T1
80 mm 18 mm 25 mm 68 mm 80 mm

28 mm 26 mm 26 mm

28 mm

Figure 1.

Figure 2.

BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 1. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 2 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.

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111

NTHS5443T1 Product Preview P-Channel 2.5 V (G-S) MOSFET


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S

PRODUCT SUMMARY
VDS (V) RDS(on) () 0.065 @ VGS = 4.5 V 20 0.074 @ VGS = 3.6 V 0.110 @ VGS = 2.5 V ID (A) "4.9 "4.6 "3.8

D PChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "4.9 "3.5 IDM IAS PD 2.5 1.3 TJ, Tstg 1.3 0.7 C 2.1 "15 1.1 "3.6 "2.6 A A W 5 secs Steady State Unit V V A D D D S

ChipFET CASE 1206A STYLE 1

20 "12

PIN CONNECTIONS

8 7 6 5

1 2 3 4

D D D G

MARKING DIAGRAM

55 to +150

A4

1. Surface Mounted on 1 x 1 FR4 Board. A4 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHS5443T1

Semiconductor Components Industries, LLC, 2001

112

January, 2001 Rev. 1

Publication Order Number: NTHS5443T1/D

NTHS5443T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 40 80 RthJF 15 50 95 20 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "12 V VDS = 16 V, VGS = 0 V VDS = 16 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (N t 3 (Note 3.) ) ID(on) rDS(on) S( ) VDS v 5.0 V, VGS = 4.5 V VGS = 4.5 V, ID = 3.6 A VGS = 3.6 V, ID = 3.3 A VGS = 2.5 V, ID = 2.7 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time SourceDrain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = 1.1 A, di/dt = 100 A/s VDD = 10 V, RL = 10 ID ^ 1.0 10A A, VGEN = 4 4.5 5V V, RG = 6 5V VDS = 10 V V, VGS = 4 4.5 V, ID = 3.6 A 9.0 2.2 2.2 15 30 50 35 30 14 25 45 75 50 60 ns s nC gfs VSD VDS = 10 V, ID = 3.6 A IS = 1.1 A, VGS = 0 V 0.6 15 0.056 0.065 0.095 10 0.8 "100 1.0 5.0 0.065 0.074 0.110 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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113

NTHS5445T1 Product Preview P-Channel 1.8 V (G-S) MOSFET


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S

PRODUCT SUMMARY
VDS (V) rDS(on) () 0.035 @ VGS = 4.5 V 8.0 0.047 @ VGS = 2.5 V 0.062 @ VGS = 1.8 V ID (A) "7.1 "6.2 "5.7

D PChannel MOSFET

MAXIMUM RATINGS (TA = 25C unless otherwise noted)


Rating DrainSource Voltage GateSource Voltage Continuous Drain Current (TJ = 150C) (Note 1.) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "7.1 "5.2 IDM IS PD 2.5 1.3 TJ, Tstg 1.3 0.7 C 2.1 "20 1.1 "5.2 "3.7 A A W 5 secs Steady State Unit V V A D D D S

ChipFET CASE 1206A STYLE 1

8.0 "8.0

PIN CONNECTIONS
8 7 6 5 1 2 3 4

D D D G

MARKING DIAGRAM

55 to +150

1. Surface Mounted on 1 x 1 FR4 Board.

A5

A5 = Specific Device Code

ORDERING INFORMATION
Device
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package ChipFET

Shipping 3000/Tape & Reel

NTHS5445T1

Semiconductor Components Industries, LLC, 2001

114

January, 2001 Rev. 1

Publication Order Number: NTHS5445T1/D

NTHS5445T1
THERMAL CHARACTERISTICS
Characteristic Maximum JunctiontoAmbient (Note 2.) t v 5 sec Steady State Maximum JunctiontoFoot (Drain) Steady State Symbol RthJA 40 80 RthJF 15 50 95 20 C/W Typ Max Unit C/W

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic Static Gate Threshold Voltage GateBody Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS SS VDS = VGS, ID = 250 A VDS = 0 V, VGS = "8.0 V VDS = 6.4 V, VGS = 0 V VDS = 6.4 V, VGS = 0 V, TJ = 85C OnState Drain Current (Note 3.) DrainSource OnState Resistance (Note 3.) ID(on) rDS(on) S( ) VDS v 5.0 V, VGS = 4.5 V VGS = 4.5 V, ID = 5.2 A VGS = 2.5 V, ID = 4.5 A VGS = 1.8 V, ID = 2.0 A Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf IF = 1.1 A, di/dt = 100 A/s VDD = 4.0 V, RL = 4 ID ^ 1.0 10A A, VGEN = 4 4.5 5V V, RG = 6 0V 5V VDS = 4 4.0 V, VGS = 4 4.5 V, ID = 5.2 A 17 2.8 2.6 15 45 110 65 30 26 25 70 165 100 60 ns nC gfs VSD VDS = 5.0 V, ID = 5.2 A IS = 1.1 A, VGS = 0 V 0.45 20 0.030 0.040 0.052 18 0.8 "100 1.0 5.0 0.035 0.047 0.062 1.2 S V A V nA A Symbol Test Condition Min Typ Max Unit

SourceDrain Reverse Recovery Time trr 2. Surface Mounted on 1 x 1 FR4 Board. 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing.

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115

NTHS5445T1
TYPICAL ELECTRICAL CHARACTERISTICS
20 VGS = 5 thru 2.5 V 16 ID,Drain Current (A) ID,Drain Current (A) 2V 16 20 TC = 55C 25C 125C

12

12

8 1.5 V 4 1V 0 0.5 1.0 1.5 2.0 2.5 VDS, DraintoSource Voltage (V) 3.0

0.5 1.0 1.5 2.0 VGS, GatetoSource Voltage (V)

2.5

Figure 1. Output Characteristics

Figure 2. Transfer Characteristics

0.10 r DS(on),OnResistance ( )

3000 2500 C, Capacitance (pF) 2000 1500 1000 500 0 0 4 8 12 ID, Drain Current (A) 16 20 0 2 4 6 VDS, DraintoSource Voltage (V) 8 Coss

0.08

VGS = 1.8 V

Ciss

0.06 VGS = 2.5 V 0.04 VGS = 4.5 V

0.02

Crss

Figure 3. OnResistance vs. Drain Current

Figure 4. Capacitance

5 VGS,GatetoSource Voltage (V) VDS = 4 V ID = 5.2 A r DS(on),OnResistance ( ) (Normalized)

1.6 VGS = 4.5 V ID = 5.2 A

1.4

1.2

1.0

0.8

8 12 Qg, Total Gate Charge (nC)

16

20

0.6 50

25

0 25 50 75 100 TJ, Junction Temperature (C)

125

150

Figure 5. Gate Charge

Figure 6. OnResistance vs. Junction Temperature

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116

NTHS5445T1
TYPICAL ELECTRICAL CHARACTERISTICS
20 rDS(on), OnResistance ( ) TJ = 150C I S, Source Current (A) 10 0.10

0.08 ID = 5.2 A

0.06

0.04

TJ = 25C

0.02

0 0 0.2 0.4 0.6 0.8 1.0 VDS, DraintoSource Voltage (V) 1.2

1 2 3 4 VGS, GatetoSource Voltage (V)

Figure 7. SourceDrain Diode Forward Voltage

Figure 8. OnResistance vs. GatetoSource Voltage

0.4 0.3 V GS (th), Varience (V) ID = 250 A Power (W) 0.2

50

40

30

0.1

20

0.0 10

0.1 0.2 50

25

25 50 75 100 TJ, Temperature (C)

125

150

0 103

102

10 1 1 Time (sec)

10

100

600

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

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117

NTHS5445T1
TYPICAL ELECTRICAL CHARACTERISTICS
2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 1 Square Wave Pulse Duration (sec) PDM t1 t2 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80C/W 3. TJM TA = PDMZthJA(t) 4. Surface Mounted 10 100 600

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5

0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 104 103 102 10 1 Square Wave Pulse Duration (sec) 1 10

Figure 12. Normalized Thermal Transient Impedance, JunctiontoFoot

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118

NTHS5445T1
80 mm 18 mm 25 mm 68 mm 80 mm

28 mm 26 mm 26 mm

28 mm

Figure 13.

Figure 14.

BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 13. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 14 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further.

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119

NTMD3P03R2 Product Preview Power MOSFET -3.05 Amps, -30 Volts


Dual PChannel SO8
Features

High Efficiency Components in a Dual SO8 Package High Density Power MOSFET with Low RDS(on) Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for the SO8 Package is Provided

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3.05 AMPERES 30 VOLTS 0.085 W @ VGS = 10 V


PChannel D

Applications

DCDC Converters Low Voltage Motor Control Power Management in Portable and BatteryPowered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 4.5 Vdc, Peak IL = 7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 30 20 171 0.73 2.34 1.87 8.0 100 1.25 3.05 2.44 12 62.5 2.0 3.86 3.1 15 55 to +150 140 Unit V V C/W W A A A C/W W A A A C/W W A A A C mJ G

MARKING DIAGRAM
SO8 CASE 751 STYLE 11 1 ED3P03 L Y WW = Device Code = Assembly Location = Year = Work Week

ED3P03 LYWW

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View

TL

260

ORDERING INFORMATION
Device NTMD3P03R2 Package SO8 Shipping 2500/Tape & Reel

1. Minimum FR4 or G10 PCB, t = Steady State. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

120

January, 2001 Rev. 0

Publication Order Number: NTMD3P03R2/D

NTMD3P03R2
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 5.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 25C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 10 Vdc, ID = 3.05 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 3.05 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. and 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 6.) Diode Forward OnVoltage Reverse Recovery Time (IS = 3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. (IS = 3.05 Adc, VGS = 0 V) (IS = 3.05 Adc, VGS = 0 V, TJ = 125C) VSD trr ta tb QRR 0.96 0.78 34 18 16 0.03 1.25 C Vdc ns (VDS = 24 Vdc, VGS = 10 Vdc, ID = 3.05 3 05 Adc) Ad ) (VDD = 24 Vdc, ID = 1.5 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) (VDD = 24 Vdc, ID = 3.05 Adc, VGS = 10 10 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 12 16 45 45 16 42 32 35 16 2.0 4.5 22 30 80 80 25 nC ns ns (VDS = 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 520 170 70 750 325 135 pF VGS(th) 1.0 RDS(on) gFS 0.063 0.090 5.0 0.085 0.125 Mhos 1.7 3.6 2.5 Vdc V(BR)DSS 30 IDSS IGSS IGSS 100 100 nAdc 1.0 20 2.0 nAdc 30 Vdc mV/C Adc Symbol Min Typ Max Unit

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NTMD3P03R2
TYPICAL ELECTRICAL CHARACTERISTICS
6 ID, DRAIN CURRENT (AMPS) 5 4 TJ = 25C 3 2 1 0 6 ID, DRAIN CURRENT (AMPS) VGS = 4.4 V VGS = 4 V VGS = 4.6 V VGS = 4.8 V VGS = 3.6 V VGS = 2.8 V VGS = 3.2 V VGS = 5 V VGS = 2.6 V VGS = 3 V VDS > = 10 V 5 4 TJ = 100C 3 2 1 0 TJ = 25C TJ = 55C

VGS = 10 V VGS = 8 V VGS = 6 V

0.25

0.5

0.75

1.25

1.5

1.75

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3 4 5 6 7 8 ID = 3.05 A TJ = 25C

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 5 6 7 ID = 1.5 A TJ = 25C

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 0.25 TJ = 25C 0.2 VGS = 4.5 V 1.6

Figure 4. OnResistance vs. GatetoSource Voltage

1.4

ID = 3.05 A VGS = 10 V

1.2

0.15 VGS = 10 V 0.1

0.8

0.05 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS)

0.6 50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance vs. Drain Current and Gate Voltage

Figure 6. On Resistance Variation with Temperature

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NTMD3P03R2

10000 VGS = 0 V IDSS, LEAKAGE (nA) TJ = 150C 1000 C, CAPACITANCE (pF) 1200 1000 800 600 400 200

VDS = 0 V

VGS = 0 V

Ciss

TJ = 125C 100

Crss

Ciss

Coss TJ = 25C Crss 0 5 10 15 20 25 30

10 6

10

14

18

22

26

30

0 10

VGS

VDS

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 7. DraintoSource Leakage Current vs. Voltage


12 10 VDS t, TIME (ns) 8 VGS 6 4 2 0 ID = 3.05 A TJ = 25C 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) Q1 Q2 15 10 5 0 16 1 20 100 QT 30 1000 25

Figure 8. Capacitance Variation

VDS = 24 V ID = 3.05 A VGS = 10 V td(off) tf 10 td(on) tr

10 RG, GATE RESISTANCE ()

100

Figure 9. GatetoSource and DraintoSource Voltage vs. Total Charge


1000 IS, SOURCE CURRENT (AMPS) VDS = 24 V ID = 1.5 A VGS = 4.5 V t, TIME (ns) 3 2.5 2 1.5 1 0.5

Figure 10. Resistive Switching Time Variation vs. Gate Resistance


VGS = 0 V TJ = 25C

100

tr tf

td(off) td(on)

10

10 RG, GATE RESISTANCE ()

100

0 0.2

0.4

0.6

0.8

1.2

VSD, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Resistive Switching Time Variation vs. Gate Resistance

Figure 12. Diode Forward Voltage vs. Current

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NTMD3P03R2

100 ID, DRAIN CURRENT (AMPS)

10

VGS = 12 V SINGLE PULSE TC = 25C

1.0 ms

10 ms 1.0 dc IS

di/dt

ta 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 1.0 10 100

trr tb TIME

tp IS

0.25 IS

0.01

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 13. Maximum Rated Forward Biased Safe Operating Area

Figure 14. Diode Reverse Recovery Waveform

1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE D = 0.5

0.2 0.1 0.1 0.05 0.02 0.01 Single Pulse 1E02 1E01 1E+00 t, TIME (s) 1E+01 1E+02 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8

24.4

0.0014 F

0.0073 F

0.022 F

0.105 F

0.484 F

3.68 F Ambient 1E+03

0.01 1E03

Figure 15. FET Thermal Response

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124

NTMD3P03R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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NTMD3P03R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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126

NTMD6N02R2 Product Preview Power MOSFET 6.0 Amps, 20 Volts


NChannel Enhancement Mode Dual SO8 Package
Features http://onsemi.com

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual SO8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified SO8 Mounting Information Provided

6.0 AMPERES 20 VOLTS 35 mW @ VGS = 4.5 V


NChannel D

Applications

DCDC Converters Low Voltage Motor Control Power Management in Portable and BatteryPowered Products, i.e.:
Computers, Printers, Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 MW) GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) 1. 2. 3. 4. Symbol VDSS VDGR VGS RJA PD ID ID IDM RJA PD ID ID IDM Value 20 20 "12 62.5 2.0 6.5 5.5 20 102 1.22 5.07 4.07 16 172 0.73 3.92 3.14 12 Unit V V V 8 G

1 C/W W A A A C/W W A A A C/W W A A A SO8 CASE 751 STYLE 11

MARKING DIAGRAM & PIN ASSIGNMENT


Source 1 Gate 1 Source 2 Gate 2 1 2 3 4 (Top View) E6N02 L Y WW = Device Code = Assembly Location = Year = Work Week E6N02 LYWW 8 7 6 5 Drain 1 Drain 1 Drain 2 Drain 2

RJA PD ID ID IDM Mounted onto a 2 square FR4 Board (1 sq. 2 oz. Cu sided), t < 10 seconds. Mounted onto a 2 square FR4 Board (1 sq. 2 oz. Cu sided), t = steady state. Minimum FR4 or G10 PCB, t = steady state. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

0.06 thick single 0.06 thick single

ORDERING INFORMATION
Device NTMD6N02R2 Package SO8 Shipping 2500/Tape & Reel

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2000

127

November, 2000 Rev. 0

Publication Order Number: NTMD6N02R2/D

NTMD6N02R2
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (continued)
Rating Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 20 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol TJ, Tstg EAS TL Value 55 to +150 360 260 Unit C mJ C

ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 6.0 Adc) (VGS = 4.5 Vdc, ID = 4.0 Adc) (VGS = 2.7 Vdc, ID = 2.0 Adc) (VGS = 2.5 Vdc, ID = 3.0 Adc) Forward Transconductance (VDS = 12 Vdc, ID = 3.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. and 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 6.0 6 0 Ad Adc) ) (VDD = 16 Vdc, ID = 4.0 Adc, 5 Vdc VGS = 4 4.5 Vdc, RG = 6.0 ) (VDD = 16 Vdc, ID = 6.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 12 50 45 80 11 35 45 60 12 1.5 4.0 20 90 75 130 18 65 75 110 20 nC ns ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 785 260 75 1100 450 180 pF VGS(th) 0.6 RDS(on) gFS 0.028 0.028 0.033 0.035 10 0.035 0.043 0.048 0.049 Mhos 0.9 3.0 1.2 Vdc mV/C V(BR)DSS 20 IDSS IGSS IGSS 1.0 10 100 100 nAdc nAdc 19.2 Vdc mV/C Adc Symbol Min Typ Max Unit

5. Handling precautions to protect against electrostatic discharge is mandatory 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature.

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NTMD6N02R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (continued) (Note 8.)
Characteristic BODYDRAIN DIODE RATINGS (Note 9.) Diode Forward OnVoltage (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 6.0 6 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 8. Handling precautions to protect against electrostatic discharge is mandatory. 9. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. VSD 0.83 0.88 0.75 30 15 15 0.02 1.1 1.2 C Vdc Symbol Min Typ Max Unit

Reverse Recovery Time

trr ta tb QRR

ns

12 I D, DRAIN CURRENT (AMPS) 10 8

10 V

2.5 V 4.5 V 3.2 V

2.0 V ID, DRAIN CURRENT (AMPS) TJ = 25C 1.8 V

12 VDS 10 V 10 8 6 4 2 0 100C 25C TJ = 55C 0.5 1 1.5 2 VGS, GATETOSOURCE VOLTAGE (VOLTS) 2.5

6 4 2 0 VGS = 1.5 V

0.25 0.5 0.75 1 1.25 1.5 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1.75

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 2 4 6 8 VGS, GATETOSOURCE VOLTAGE (VOLTS) 10 ID = 6.0 A TJ = 25C

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.05 TJ = 25C 0.04 VGS = 2.5 V 0.03 4.5 V

0.02

0.01

9 5 7 ID, DRAIN CURRENT (AMPS)

11

13

Figure 3. OnResistance versus GateToSource Voltage

Figure 4. On-Resistance versus Drain Current and Gate Voltage

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129

NTMD6N02R2
RDS(on) , DRAINTOSOURCE RESISTANCE (NORMALIZED) 1.6 ID = 6.0 A VGS = 4.5 V 1000 VGS = 0 V TJ = 125C 100C 10

1.2

I DSS , LEAKAGE (nA)

1.4

100

25C

0.8 0.6 50

0.1 0.01 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 4 8 12 16 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 20

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

VDS = 0 V Ciss

VGS = 0 V

TJ = 25C

QT 4 VDS 3 Q1 Q2 ID = 6 A VDS = 16 V VGS = 4.5 V TJ = 25C VGS 12 16

C, CAPACITANCE (pF)

2000

1500

Crss

1000

Ciss Coss 5 10 15 20

500 Crss 0 10 5 0 VGS VDS

1 0 0 4 8 12 16 Qg, TOTAL GATE CHARGE (nC)

4 0

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

1000 VDS = 16 V ID = 6.0 A VGS = 4.5 V t, TIME (ns)

100 tf tr td(off)

10 1

td(on) 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance

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130

V DS, DRAINTOSOURCE VOLTAGE (VOLTS)

2500

VGS , GATETOSOURCE VOLTAGE (VOLTS)

20

NTMD6N02R2
DRAINTOSOURCE DIODE CHARACTERISTICS
5 I S, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C 100 I D , DRAIN CURRENT (AMPS) VGS = 12 V SINGLE PULSE TC = 25C 10 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 1 ms

1 0

0.1 0 0.2 0.4 0.6 0.8 1.0 1.2 VSD, SOURCETODRAIN VOLTAGE (VOLTS)

dc 100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Figure 11. Maximum Rated Forward Biased Safe Operating Area

di/dt IS ta trr tb TIME tp IS 0.25 IS

Figure 12. Diode Reverse Recovery Waveform

TYPICAL ELECTRICAL CHARACTERISTICS


1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 t2 DUTY CYCLE, D = t1/t2 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

SINGLE PULSE 0.001 1.0E05 1.0E04

Figure 13. Thermal Response

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131

NTMD6N02R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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132

NTMD6N02R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 14. Typical Solder Heating Profile

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NTMD6P02R2
Preferred Device

Power MOSFET 6 Amps, 20 Volts


PChannel SO8, Dual
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual SO8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified SO8 Mounting Information Provided

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6 AMPERES 20 VOLTS RDS(on) = 33 mW


PChannel D Unit V V C/W W A A W A A C/W W A A W A A C/W W A A W A A 8 1 E6P02 L Y WW = Device Code = Location Code = Year = Work Week S G

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Symbol VDSS VGS RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM Value 20 "12 62.5 2.0 7.8 5.7 0.5 3.89 40 98 1.28 6.2 4.6 0.3 3.01 35 166 0.75 4.8 3.5 0.2 2.48 30

MARKING DIAGRAM

SO8, Dual CASE 751 STYLE 11

E6P02 LYWW

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

1. Mounted onto a 2 square FR4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t = 10 seconds. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), t = steady state. 3. Minimum FR4 or G10 PCB, t = steady state. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

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ORDERING INFORMATION
Device NTMD6P02R2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

134

November, 2000 Rev. 1

Publication Order Number: NTMD6P02R2/D

NTMD6P02R2
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (continued)
Rating Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 5.0 Apk, L = 40 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol TJ, Tstg EAS TL Value 55 to +150 500 260 Unit C mJ C

ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 6.2 Adc) (VGS = 2.5 Vdc, ID = 5.0 Adc) (VGS = 2.5 Vdc, ID = 3.1 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 6.2 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. and 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 6.2 6 2 Ad Adc) ) (VDD = 16 Vdc, ID = 6.2 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) (VDD = 10 Vdc, ID = 1.0 Adc, 10 Vdc, Vdc VGS = 10 RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 15 20 85 50 17 65 50 80 20 4.0 8.0 25 50 125 110 35 nC ns ns Vd VGS = 0 Vdc, Vd (VDS = 16 Vdc, f = 1.0 MHz) Ciss Coss Crss 1380 515 250 1700 775 450 pF VGS(th) 0.6 RDS(on) gFS 0.027 0.038 0.038 15 0.033 0.050 Mhos 0.88 2.6 1.20 Vdc mV/C V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 1.0 5.0 nAdc 11.6 Vdc mV/C Adc Symbol Min Typ Max Unit

5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature.

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NTMD6P02R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (continued) (Note 8.)
Characteristic BODYDRAIN DIODE RATINGS (Note 9..) Diode Forward OnVoltage Diode Forward OnVoltage Reverse Recovery Time (IS = 1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 8. Handling precautions to protect against electrostatic discharge is mandatory. 9. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 6.2 Adc, VGS = 0 Vdc) (IS = 6.2 Adc, VGS = 0 Vdc, TJ = 125C) VSD VSD trr ta tr QRR 0.80 0.65 0.95 0.80 50 20 30 0.04 1.2 80 C Vdc Vdc ns Symbol Min Typ Max Unit

12 ID, DRAIN CURRENT (AMPS) 10 8.0

10 V

ID, DRAIN CURRENT (AMPS)

4.5 V 3.8 V

2.1 V TJ = 25C

10 VDS 10 V 8.0

3.1 V 6.0 4.0 2.0 0 1.5 V VGS = 1.3 V 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 2.5 V 1.8 V

6.0 25C 100C 2.0 0

4.0

TJ = 55C

1.0 1.5 2.0 2.5 VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics

0.05 ID = 6.2 A TJ = 25C

0.05 TJ = 25C 0.04 VGS = 2.5 V 2.7 V 0.03 4.5 V

0.04

0.03

0.02

0.01 0

0.02

2.0 4.0 6.0 8.0 VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

0.01

2.0

8.0 10 4.0 6.0 ID, DRAIN CURRENT (AMPS)

12

14

Figure 3. OnResistance versus GateToSource Voltage

Figure 4. On-Resistance versus Drain Current and Gate Voltage

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NTMD6P02R2
RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

1.6 ID = 6.2 A VGS = 4.5 V

1000

VGS = 0 V

TJ = 125C 100C

I DSS , LEAKAGE (nA)

1.4

100

1.2

10

1 25C 0.1 0.01

0.8 0.6 50

25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

8 12 16 20 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature


VGS , GATETOSOURCE VOLTAGE (VOLTS) 5000 4500 C, CAPACITANCE (pF) 4000 3500 3000 2500 Crss 2000 1500 1000 500 0 10 5.0 0 VGS VDS 5.0 10 15 20 Crss Ciss Coss Ciss VDS = 0 V VGS = 0 V TJ = 25C 5

Figure 6. DrainToSource Leakage Current versus Voltage


20 QT 4 VDS 3 Q1 Q2 VGS 12 16 V DS, DRAINTOSOURCE VOLTAGE (VOLTS)

2 ID = 6.2 A VDS = 16 V VGS = 4.5 V TJ = 25C 0 5.0 10 15 20 25

1 0

4 0

Qg, TOTAL GATE CHARGE (nC)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation


1000 VDD = 16 V ID = 1.0 A VGS = 10 V t, TIME (ns)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge


1000 VDD = 16 V ID = 6.2 A VGS = 4.5 V

td(off) t, TIME (ns) tf

100 tr

100

tf tr td(off)

td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100 10 1

td(on) 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Resistive Switching Time Variation versus Gate Resistance

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137

NTMD6P02R2
DRAINTOSOURCE DIODE CHARACTERISTICS
5 IS, SOURCE CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) VGS = 0 V TJ = 25C 100

VGS = 2.5 V SINGLE PULSE TC = 25C

1.0 ms

10 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10

1 0

0.1 0 0.2 0.4 0.6 0.8 1.0 1.2 VSD, SOURCETODRAIN VOLTAGE (VOLTS)

dc 100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current

Figure 12. Maximum Rated Forward Biased Safe Operating Area

di/dt IS ta trr tb TIME tp IS 0.25 IS

Figure 13. Diode Reverse Recovery Waveform

TYPICAL ELECTRICAL CHARACTERISTICS


10 Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 Chip


0.0175

0.1

Normalized to ja at 10s.
0.0710 0.2706 0.5776 0.7086

0.01 SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F

Ambient

Figure 14. Thermal Response

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138

NTMD6P02R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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NTMD6P02R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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140

NTMD7C02 Power MOSFET 9.5 Amps, 20 Volts (N-Ch) 4 Amps, 20 Volts (P-Ch)
Complementary SO8
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Drain Current Continuous (Note 1.) Operating and Storage Temperature Range Thermal Resistance (Note 2.) JunctiontoAmbient Symbol VDSS VGS ID TJ, Tstg N 20 20 7.0 P 20 12 4.5 Unit Vdc Vdc A C C/W 50

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9.5 AMPERES, 20 VOLTS RDS(on) = 24 mW (NChannel) 4 AMPERES, 20 VOLTS RDS(on) = 108 mW (PChannel)
NChannel D PChannel D

55 to +150

RJA 50 1. Mounted on 1 square FR4 board. 2. Mounted on 1 square FR4 board, t 10 seconds.

G S

G S

MARKING DIAGRAM

8 1

SO8 CASE 751 STYLE 20

NTMDC02 YWW

NTMDC02 Y WW

= Device Code = Year = Work Week

PIN ASSIGNMENT
Source (N) Gate (N) Source (P) Gate (P) 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

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ORDERING INFORMATION
Device NTMD7C02R2 Package SO8 Shipping 2500 Units/Rail

Semiconductor Components Industries, LLC, 2001

141

January, 2001 Rev. 0

Publication Order Number: NTMD7C02/D

NTMD7C02
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) (VGS = 12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) (VDS = VGS, ID = 250 Adc) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 7.0 Adc) (VGS = 4.5 Vdc, ID = 4.5 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vd Vdc, ID = 4.5 Adc, VGS = 4.5 Vdc) td(on) (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) tr td(off) tf QT Qgs Qgd SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 3.) Reverse Recovery Time (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 25_C) VSD trr ta (IF = 1.7 Adc, VGS = 0 Vdc, di/dt = 100 As) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width = 300 s, Duty Cycle= 2%. tb Qrr (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 730 840 104 24 18 13.5 85 11 0.082 0.018 760 870 160 36 28 22 140 20 0.12 0.028 C Vdc ns (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 22 12 38 22 38 36 31 24 16 7.0 4.5 0.6 7.0 1.7 30 20 50 30 50 50 45 35 20 9.0 6.0 1.0 9.0 2.5 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss (N) (P) (N) (P) (N) (P) 1470 500 660 190 189 58 1750 570 770 220 260 80 pF VGS(th) (N) (P) RDS(on) (N) (P) (P) 19 63 94 24 74 108 1.0 0.6 mOhms Vdc IDSS (N) (P) IGSS (N) (P) 100 100 1.0 1.0 nAdc Adc Symbol Polarity Min Typ Max Unit

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142

NTMS10P02R2 Product Preview Power MOSFET -10 Amps, -20 Volts


PChannel EnhancementMode Single SO8 Package
Features http://onsemi.com

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature SO8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified SO8 Mounting Information Provided

10 AMPERES 20 VOLTS 14 mW @ VGS = 4.5 V


PChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 3.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 5.0 Apk, L = 40 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM TJ, Tstg EAS Value 20 "12 50 2.5 10 8.0 0.6 5.5 50 80 1.6 8.8 6.4 0.4 4.5 44 55 to +150 500 Unit Vdc Vdc C/W W A A W A A C/W W A A W A A C mJ S G

8 1 SO8 CASE 751 STYLE 12

MARKING DIAGRAM & PIN ASSIGNMENT


Source Source Source Gate 1 2 3 4 Top View E10P02 L Y WW = Device Code = Assembly Location = Year = Work Week E10P02 LYWW 8 7 6 5 Drain Drain Drain Drain

TL

260

1. Mounted onto a 2 square FR4 Board (1 sq. Cu 0.06 thick single sided), t = 10 seconds. 2. Mounted onto a 2 square FR4 Board (1 sq. Cu 0.06 thick single sided), t = steady state. 3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

ORDERING INFORMATION
Device NTMS10P02R2 Package SO8 Shipping 2500/Tape & Reel

Semiconductor Components Industries, LLC, 2000

143

December, 2000 Rev. 2

Publication Order Number: NTMS10P02R2/D

NTMS10P02R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 10 Adc) (VGS = 2.5 Vdc, ID = 8.8 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 5.) Diode Forward OnVoltage Diode Forward OnVoltage Reverse Recovery Time (IS = 2.1 2 1 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. (IS = 2.1 Adc, VGS = 0 Vdc) (IS = 2.1 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) VSD VSD trr ta tb QRR 0.72 0.60 0.90 0.75 65 25 40 0.075 1.2 100 C Vdc Vdc ns (VDS = 10 Vdc, VGS = 4.5 Vdc, ID = 10 Ad Adc) ) (VDD = 10 Vdc, ID = 10 Adc, 4 5 Vdc, Vdc VGS = 4.5 RG = 6.0 ) (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 25 40 110 110 25 100 100 125 48 6.5 17 35 65 190 190 70 nC ns ns (VDS = 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 3100 1100 475 3640 1670 1010 pF VGS(th) 0.6 RDS(on) gFS 0.012 0.017 30 0.014 0.020 Mhos 0.88 2.8 1.20 Vdc mV/C V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 1.0 5.0 nAdc 12.1 Vdc mV/C Adc Symbol Min Typ Max Unit

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NTMS10P02R2
20 2.3 V 2.1 V TJ = 25C 1.9 V -I D , DRAIN CURRENT (AMPS) 10 VDS 10 V 8.0

-I D , DRAIN CURRENT (AMPS)

15

10 V 3.1 V

6.0 25C 100C TJ = 55C

10

4.0

5.0

VGS = 1.7 V

2.0 0

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.5 1.0 1.5 2.0 2.5 VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.100 ID = 10 A TJ = 25C 0.075

0.020

TJ = 25C

VGS = 2.5 V

0.016

0.050

VGS = 4.5 V 0.012

0.025

2.0 4.0 6.0 8.0 VGS, GATETOSOURCE VOLTAGE (VOLTS)

10

0.008

6.0

10 14 ID, DRAIN CURRENT (AMPS)

18

R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus GateToSource Voltage


1.6 ID = 10 A VGS = 4.5 V -I DSS , LEAKAGE (nA) 1000 10,000

Figure 4. On-Resistance versus Drain Current and Gate Voltage

VGS = 0 V

1.4

TJ = 125C

1.2

1.0

TJ = 100C 100

0.8 0.6 50 10

25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

2.0

6.0 10 14 18 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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NTMS10P02R2
10,000 VGS = 0 V C, CAPACITANCE (pF) 8000 Ciss VDS = 0 V TJ = 25C

6000 Crss 4000 Ciss Coss

2000 Crss 0 10 5.0 0 5.0 VGS VDS 10

15

20

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation


VGS , GATETOSOURCE VOLTAGE (VOLTS) VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 5.0 QT 4.0 VGS 8.0 10

VDS

3.0 Q1 2.0 ID = 10 A TJ = 25C Q2

6.0

4.0

1.0 0 0

Q3

2.0 0

10

20

30

40

50

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

1000 VDD = 10 V ID = 1.0 A VGS = 4.5 V t, TIME (ns) td(off) tf t, TIME (ns)

1000 VDD = 10 V ID = 10 A VGS = 4.5 V td(off) tr tf 100 td(on)

tr 100 td(on)

10 1.0 10 RG, GATE RESISTANCE (OHMS) 100

10 1.0 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Resistive Switching Time Variation versus Gate Resistance

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NTMS10P02R2
DRAINTOSOURCE DIODE CHARACTERISTICS
100 IS, SOURCE CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) 2.0 1.6 1.2 0.8 0.4 0 VGS = 0 V TJ = 25C 100 ms 10 1.0 ms

1.0

VGS = 2.5 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10

10 ms

0.1 0.50 0.55 0.60 0.65 0.70 VSD, SOURCETODRAIN VOLTAGE (VOLTS)

dc 100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current

Figure 12. Maximum Rated Forward Biased Safe Operating Area

di/dt IS ta trr tb TIME tp IS 0.25 IS

Figure 13. Diode Reverse Recovery Waveform

TYPICAL ELECTRICAL CHARACTERISTICS


10 Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE

1.0

D = 0.5 0.2 0.1 0.05 0.02 0.01 Chip


0.0163

0.1

Normalized to ja at 10s.
0.0652 0.1988 0.6411 0.9502

0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F

SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 14. Thermal Response

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147

NTMS10P02R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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148

NTMS10P02R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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149

NTMS3P03R2 Product Preview Power MOSFET -3.05 Amps, -30 Volts


PChannel SO8
Features

High Efficiency Components in a Single SO8 Package High Density Power MOSFET with Low RDS(on) Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for the SO8 Package is Provided

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3.05 AMPERES 30 VOLTS 0.085 W @ VGS = 10 V


PChannel D

Applications

DCDC Converters Low Voltage Motor Control Power Management in Portable and BatteryPowered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 4.5 Vdc, Peak IL = 7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 30 20 171 0.73 2.34 1.87 8.0 100 1.25 3.05 2.44 12 62.5 2.0 3.86 3.1 15 55 to +150 140 Unit V V C/W W A A A C/W W A A A C/W W A A A C mJ G

MARKING DIAGRAM
SO8 CASE 751 STYLE 13 1 E3P03 L Y WW = Device Code = Assembly Location = Year = Work Week

E3P03 LYWW

PIN ASSIGNMENT
N.C. Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
TL 260 C Device NTMS3P03R2 Package SO8 Shipping 2500/Tape & Reel

1. Minimum FR4 or G10 PCB, t = Steady State. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

150

January, 2001 Rev. 0

Publication Order Number: NTMS3P03R2/D

NTMS3P03R2
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 5.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 10 Vdc, ID = 3.05 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 3.05 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 6.) Diode Forward OnVoltage Reverse Recovery Time (IS = 3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. (IS = 3.05 Adc, VGS = 0 V) (IS = 3.05 Adc, VGS = 0 V, TJ = 125C) VSD trr ta tb QRR 0.96 0.78 34 18 16 0.03 1.25 C Vdc ns (VDS = 24 Vdc, VGS = 10 Vdc, ID = 3.05 3 05 Adc) Ad ) (VDD = 24 Vdc, ID = 1.5 Adc, 4 5 Vdc, Vdc VGS = 4.5 RG = 6.0 ) (VDD = 24 Vdc, ID = 3.05 Adc, VGS = 10 10 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 12 16 45 45 16 42 32 35 16 2.0 4.5 22 30 80 80 25 nC ns ns (VDS = 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 520 170 70 750 325 135 pF VGS(th) 1.0 RDS(on) gFS 0.063 0.090 5.0 0.085 0.115 Mhos 1.7 3.6 2.5 Vdc V(BR)DSS 30 IDSS IGSS IGSS 100 100 nAdc 1.0 10 nAdc 30 Vdc mV/C Adc Symbol Min Typ Max Unit

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151

NTMS3P03R2
TYPICAL ELECTRICAL CHARACTERISTICS
6 ID, DRAIN CURRENT (AMPS) 5 4 TJ = 25C 3 2 1 0 6 ID, DRAIN CURRENT (AMPS) VGS = 4.4 V VGS = 4 V VGS = 4.6 V VGS = 4.8 V VGS = 3.6 V VGS = 2.8 V VGS = 3.2 V VGS = 5 V VGS = 2.6 V VGS = 3 V VDS > = 10 V 5 4 TJ = 100C 3 2 1 0 TJ = 25C TJ = 55C

VGS = 10 V VGS = 8 V VGS = 6 V

0.25

0.5

0.75

1.25

1.5

1.75

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3 4 5 6 7 8 ID = 3.05 A TJ = 25C

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 5 6 7 ID = 1.5 A TJ = 25C

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 0.25 TJ = 25C 0.2 VGS = 4.5 V 1.6

Figure 4. OnResistance vs. GatetoSource Voltage

1.4

ID = 3.05 A VGS = 10 V

1.2

0.15 VGS = 10 V 0.1

0.8

0.05 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS)

0.6 50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance vs. Drain Current and Gate Voltage

Figure 6. On Resistance Variation with Temperature

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152

NTMS3P03R2

10000 VGS = 0 V IDSS, LEAKAGE (nA) TJ = 150C 1000 C, CAPACITANCE (pF) 1200 1000 800 600 400 Coss 200 TJ = 25C 10 6 10 14 18 22 26 30 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 0 10
VGS VDS = 0 V VGS = 0 V

Ciss

TJ = 125C 100

Crss

Ciss

Crss 0 5 10 15 20 25 30

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 7. DraintoSource Leakage Current vs. Voltage


12 10 VDS VGS 6 4 2 0 ID = 3.05 A TJ = 25C 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) Q1 Q2 15 10 5 0 16 1 t, TIME (ns) 8 20 100 QT 30 1000 25

Figure 8. Capacitance Variation

VDS = 24 V ID = 3.05 A VGS = 10 V td(off) tf 10 td(on) tr

10 RG, GATE RESISTANCE ()

100

Figure 9. GatetoSource and DraintoSource Voltage vs. Total Charge


1000 IS, SOURCE CURRENT (AMPS) VDS = 24 V ID = 1.5 A VGS = 4.5 V t, TIME (ns) 3 2.5 2 1.5 1 0.5

Figure 10. Resistive Switching Time Variation vs. Gate Resistance


VGS = 0 V TJ = 25C

100

tr tf

td(off) td(on)

10

10 RG, GATE RESISTANCE ()

100

0 0.2

0.4

0.6

0.8

1.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 11. Resistive Switching Time Variation vs. Gate Resistance

Figure 12. Diode Forward Voltage vs. Current

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153

NTMS3P03R2

100 ID, DRAIN CURRENT (AMPS)

10

VGS = 12 V SINGLE PULSE TA = 25C

1.0 ms

10 ms 1.0 dc IS

di/dt

ta 0.1 RDS(on) THERMAL LIMIT PACKAGE LIMIT 1.0 10 100

trr tb TIME

tp IS

0.25 IS

0.01 0.1

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 13. Maximum Rated Forward Biased Safe Operating Area

Figure 14. Diode Reverse Recovery Waveform

1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE D = 0.5

0.2 0.1 0.1 0.05 0.02 0.01 Single Pulse 1E02 1E01 1E+00 t, TIME (s) 1E+01 1E+02 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8

24.4

0.0014 F

0.0073 F

0.022 F

0.105 F

0.484 F

3.68 F Ambient 1E+03

0.01 1E03

Figure 15. FET Thermal Response

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154

NTMS3P03R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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155

NTMS3P03R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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156

NTMS4N01R2 Power MOSFET 4.2 Amps, 20 Volts


NChannel EnhancementMode Single SO8 Package
Features

High Density Power MOSFET with Ultra Low RDS(on) Providing


Higher Efficiency Miniature SO8 Surface Mount Package Saving Board Space; Mounting Information for the SO8 Package is Provided IDSS Specified at Elevated Temperature DraintoSource Avalanche Energy Specified Diode Exhibits High Speed, Soft Recovery

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4.2 AMPERES 20 VOLTS 0.045 W @ VGS = 4.5 V


Single NChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 mW) GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 7.5 Apk, L = 6 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS RJA PD ID ID IDM RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 20 20 10 50 2.5 5.9 4.7 25 100 1.25 4.2 3.3 20 162 0.77 3.3 2.6 15 55 to +150 169 Unit V V V C/W W A A A C/W W A A A C/W W A A A C mJ G

8 1 SO8 CASE 751 STYLE 13

MARKING DIAGRAM & PIN ASSIGNMENT


N.C. Source Source Gate 1 2 3 4 Top View E4N01 L Y WW = Device Code = Assembly Location = Year = Work Week E4N01 LYWW 8 7 6 5 Drain Drain Drain Drain

TL

260

1. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Minimum FR4 or G10 PCB, t = Steady State. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

ORDERING INFORMATION
Device NTMS4N01R2 Package SO8 Shipping 2500/Tape & Reel

Semiconductor Components Industries, LLC, 2001

157

February, 2001 Rev. 2

Publication Order Number: NTMS4N01R2/D

NTMS4N01R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) GateBody Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = 10 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 4.2 Adc) (VGS = 2.7 Vdc, ID = 2.1 Adc) (VGS = 2.5 Vdc, ID = 2.0 Adc) Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 6.) Diode Forward OnVoltage Reverse Recovery Time (IS = 4.2 4 2 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. (IS = 4.2 Adc, VGS = 0 Vdc) (IS = 4.2 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.85 0.70 20 12 8.0 0.01 1.1 C Vdc ns (VDS = 12 Vdc, VGS = 4.5 Vdc, ID = 4.2 4 2 Ad Adc) ) (VDD = 12 Vdc, ID = 4.2 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 2.3 ) td(on) tr td(off) tf Qtot Qgs Qgd 13 35 45 50 11 2.0 3.0 25 65 75 90 16 nC ns (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 870 260 60 1200 400 100 pF VGS(th) 0.6 RDS(on) gFS 0.030 0.035 0.037 10 0.04 0.05 Mhos 0.95 3.0 1.2 Vdc mV/C V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 0.2 1.0 10 nAdc 20 Vdc mV/C Adc Symbol Min Typ Max Unit

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158

NTMS4N01R2
7 ID, DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 0 1.5 V VGS = 1.3 V 0.25 0.5 0.75 1 1.25 1.5 1.75 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 2 8V 2.1 V 4.5 V 3.1 V 2.7 V 2.5 V 2.3 V 1.9 V ID, DRAIN CURRENT (AMPS) 8

VDS 10 V

TJ = 25C

1.7 V

4 100C 2 25C

TJ = 55C 2.5

0.5

1 1.5 2 VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTO SOURCERESISTANCE (W) RDS(on), DRAINTO SOURCERESISTANCE (W)

Figure 2. Transfer Characteristics

0.08 0.07 0.06 0.05 0.04 0.03 0.02 0 2 4 6 VGS, GATETOSOURCE VOLTAGE (VOLTS) 8 ID = 4.2 A TJ = 25C

0.05

TJ = 25C

0.04

VGS = 2.5 V VGS = 2.7 V VGS = 4.5 V

0.03

0.02

0.01

8 4 6 ID, DRAIN CURRENT (AMPS)

10

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus GateToSource Voltage


1.6 ID = 4.2 A VGS = 4.5 V 10,000

Figure 4. On-Resistance versus Drain Current and Gate Voltage

VGS = 0 V IDSS, LEAKAGE (nA)

1.4

1.2

TJ = 150C 1000

0.8 0.6 50 100

TJ = 125C

25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

4 8 14 16 18 6 10 12 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

20

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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159

NTMS4N01R2
2500 Ciss C, CAPACITANCE (pF) 2000 VDS = 0 V VGS = 0 V TJ = 25C

1500

Crss Ciss

1000

500 Coss 0 8 6 4 Crss 0 2 2 VGS VDS 4 6 8 10 12

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation


VGS , GATETOSOURCE VOLTAGE (VOLTS) 5 QT 4 VDS Q1 2 ID = 4.2 A TJ = 25C Q2 8 VGS 16 20 V DS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

1 0 0 2 4 6 8

4 0

10

12

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

1000 VDD = 10 V ID = 4.2 A VGS = 4.5 V t, TIME (ns) td(off) 100 tf tr td(on) t, TIME (ns)

1000 VDD = 10 V ID = 2.1 A VGS = 4.5 V tf 100 td(off) tr td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100 1 10 RG, GATE RESISTANCE (OHMS) 100

10

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Resistive Switching Time Variation versus Gate Resistance

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160

NTMS4N01R2
DRAINTOSOURCE DIODE CHARACTERISTICS
4 IS, SOURCE CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) VGS = 0 V TJ = 25C 3 100 VGS = 20 V SINGLE PULSE TC = 25C 100 ms 1.0 ms 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max. 0.1 1 10 100

10

dc

0.01 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCETODRAIN VOLTAGE (VOLTS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current

Figure 12. Maximum Rated Forward Biased Safe Operating Area

di/dt IS ta trr tb TIME tp IS 0.25 IS

Figure 13. Diode Reverse Recovery Waveform

TYPICAL ELECTRICAL CHARACTERISTICS


10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

Normalized to ja at 10s.
Chip
0.0022 0.0210 0.2587 0.7023 0.6863

0.01
0.0020 F 0.0207 F 0.3517 F 3.1413 F 108.44 F

SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 14. Thermal Response

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161

NTMS4N01R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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162

NTMS4N01R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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163

NTMS4P01R2 Product Preview Power MOSFET -4.5 Amps, -12 Volts


PChannel EnhancementMode Single SO8 Package
Features http://onsemi.com

High Density Power MOSFET with Ultra Low RDS(on)

Providing Higher Efficiency Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature DraintoSource Avalanche Energy Specified Mounting Information for the SO8 Package is Provided

4.5 AMPERES 12 VOLTS 0.045 W @ VGS = 4.5 V


Single PChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MAXIMUM RATINGS
Please See the Table on the Following Page S G

8 1 SO8 CASE 751 STYLE 13

MARKING DIAGRAM & PIN ASSIGNMENT


N.C. Source Source Gate 1 2 3 4 Top View E4P01 L Y WW = Device Code = Assembly Location = Year = Work Week E4P01 LYWW 8 7 6 5 Drain Drain Drain Drain

ORDERING INFORMATION
Device NTMS4P01R2
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package SO8

Shipping 2500/Tape & Reel

Semiconductor Components Industries, LLC, 2001

164

February, 2001 Rev. 0

Publication Order Number: NTMS4P01R2/D

NTMS4P01R2
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 mW) GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Symbol VDSS VDGR VGS RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM TJ, Tstg Value 12 12 10 50 2.5 6.04 4.82 1.2 4.18 20 85 1.47 4.50 3.65 0.7 3.20 15 159 0.79 3.40 2.72 0.38 2.32 12 55 to +150 320 260 Unit V V V C/W W A A W A A C/W W A A W A A C/W W A A W A A C mJ C

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C EAS (VDD = 12 Vdc, VGS = 5.0 Vdc, Peak IL = 8.0 Apk, L = 10 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 1. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Minimum FR4 or G10 PCB, t = Steady State. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

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165

NTMS4P01R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 10 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 4.5 Adc) (VGS = 2.7 Vdc, ID = 2.25 Adc) (VGS = 2.5 Vdc, ID = 2.25 Adc) Forward Transconductance (VDS = 2.5 Vdc, ID = 2.25 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 6.) Diode Forward OnVoltage Reverse Recovery Time (IS = 4.5 4 5 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. (IS = 4.5 Adc, VGS = 0 V) (IS = 4.5 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.9 0.7 38 20 18 0.03 1.25 C Vdc ns (VDS = 9.6 Vdc, VGS = 4.5 Vdc, ID = 4.5 4 5 Ad Adc) ) (VDD = 12 Vdc, ID = 4.5 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) td(on) tr td(off) tf Qtot Qgs Qgd 20 60 65 75 20 4.0 7.0 35 100 100 125 35 nC ns (VDS = 9.6 9 6 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 1435 635 210 1850 1000 400 pF VGS(th) 0.65 RDS(on) gFS 0.030 0.040 0.045 10 0.045 0.055 Mhos 0.9 2.9 1.15 Vdc mV/C V(BR)DSS 12 IDSS IGSS IGSS 100 100 nAdc 1.0 10 nAdc 15 Vdc mV/C Adc Symbol Min Typ Max Unit

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166

NTMS4P01R2
8 8 V ID, DRAIN CURRENT (AMPS) 7 6 5 4 3 1.7 V 2 1 0 VGS = 1.3 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 2 2.3 V 2.1 V 4.5 V 3.7 V 3.1 V 2.7 V TJ = 25C VDS 10 V

1.9 V

ID, DRAIN CURRENT (AMPS)

2.5 V

4 100C 2 25C TJ = 55C 0 0.5 2.5 1 1.5 2 VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics

0.12 ID = 4.5 A TJ = 25C 0.09

0.05 TJ = 25C 0.04 VGS = 2.5 V VGS = 2.7 V 0.03 VGS = 4.5 V 0.02

0.06

0.03

0 0 2 4 6 VGS, GATETOSOURCE VOLTAGE (VOLTS) 8

0.01

4 6 ID, DRAIN CURRENT (AMPS)

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus GateToSource Voltage


1.6 ID = 4.5 A VGS = 4.5 V 10,000

Figure 4. On-Resistance versus Drain Current and Gate Voltage

VGS = 0 V IDSS, LEAKAGE (nA) 1.4 TJ = 150C

1.2

1000 TJ = 125C

0.8 0.6 50

25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

100

4 8 6 10 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

12

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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167

NTMS4P01R2
VGS , GATETOSOURCE VOLTAGE (VOLTS) VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V Ciss C, CAPACITANCE (pF) 3000 Crss 2000 Ciss 1000 Crss 0 10 8 6 4 2 2 0 VGS VDS 4 6 8 10 12 Coss TJ = 25C 5 QT 4 VDS 3 Q1 Q2 VGS 6 8 10

4000

2 ID = 4.5 A TJ = 25C

1 0 0 4 8 12 16

2 0

20

24

Qg, TOTAL GATE CHARGE (nC)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge


4

Figure 7. Capacitance Variation


1000 VDD = 12 V ID = 4.5 A VGS = 4.5 V t, TIME (ns) IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C 3

td(off) tf tr

100

td(on)

10 1 10 RG, GATE RESISTANCE (OHMS) 100

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Diode Forward Voltage versus Current

DRAINTOSOURCE DIODE CHARACTERISTICS


100 ID , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C

10

1.0 ms 10 ms di/dt

1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max. 0.1 1 10 100 dc

IS ta trr tb TIME tp IS 0.25 IS

0.01

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Diode Reverse Recovery Waveform

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168

NTMS4P01R2
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 Chip


0.0163

0.1

Normalized to ja at 10s.
0.0652 0.1988 0.6411 0.9502

0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F

SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 13. Thermal Response

INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270

inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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169

NTMS4P01R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 14. Typical Solder Heating Profile

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170

NTMS5P02R2 Product Preview Power MOSFET -5.4 Amps, -20 Volts


PChannel EnhancementMode Single SO8 Package
Features http://onsemi.com

High Density Power MOSFET with Ultra Low RDS(on)

Providing Higher Efficiency Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed with Soft Recovery IDSS Specified at Elevated Temperature DraintoSource Avalanche Energy Specified Mounting Information for the SO8 Package is Provided

5.4 AMPERES 20 VOLTS 0.033 W @ VGS = 4.5 V


Single PChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MAXIMUM RATINGS
Please See the Table on the Following Page S G

8 1 SO8 CASE 751 STYLE 13

MARKING DIAGRAM & PIN ASSIGNMENT


N.C. Source Source Gate 1 2 3 4 Top View E5P02 L Y WW = Device Code = Assembly Location = Year = Work Week E5P02 LYWW 8 7 6 5 Drain Drain Drain Drain

ORDERING INFORMATION
Device NTMS5P02R2
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package SO8

Shipping 2500/Tape & Reel

Semiconductor Components Industries, LLC, 2001

171

February, 2001 Rev. 0

Publication Order Number: NTMS5P02R2/D

NTMS5P02R2
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 mW) GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ 25C Continuous Drain Current @ 70C Maximum Operating Power Dissipation Maximum Operating Drain Current Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Symbol VDSS VDGR VGS RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM TJ, Tstg Value 20 20 10 50 2.5 7.05 5.62 1.2 4.85 28 85 1.47 5.40 4.30 0.7 3.72 20 159 0.79 3.95 3.15 0.38 2.75 12 55 to +150 360 260 Unit V V V C/W W A A W A A C/W W A A W A A C/W W A A W A A C mJ C

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C EAS (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 8.5 Apk, L = 10 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 1. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t = steady state. 3. Minimum FR4 or G10 PCB, t = Steady State. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

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172

NTMS5P02R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 5.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) GateBody Leakage Current (VGS = 10 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 5.4 Adc) (VGS = 2.5 Vdc, ID = 2.7 Adc) Forward Transconductance (VDS = 9.0 Vdc, ID = 5.4 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 6. & 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 6.) Diode Forward OnVoltage Reverse Recovery Time (IS = 5.4 5 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Handling precautions to protect against electrostatic discharge is mandatory. 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. (IS = 5.4 Adc, VGS = 0 V) (IS = 5.4 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.95 0.72 40 20 20 0.03 1.25 75 C Vdc ns (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 5.4 5 4 Ad Adc) ) (VDD = 16 Vdc, ID = 5.4 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) (VDD = 16 Vdc, ID = 1.0 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 18 25 70 55 22 70 65 90 20 4.0 7.0 35 50 125 100 35 nC ns ns (VDS = 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 1375 510 200 1900 900 380 pF VGS(th) 0.65 RDS(on) gFS 0.026 0.037 15 0.033 0.048 Mhos 0.9 2.9 1.25 Vdc mV/C V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 0.2 1.0 10 nAdc 15 Vdc mV/C Adc Symbol Min Typ Max Unit

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173

NTMS5P02R2
12 ID, DRAIN CURRENT (AMPS) 10 8 6 4 1.7 V 2 0 VGS = 1.3 V 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 2 2.7 V 2.5 V 8 V 2.3 V 4.5 V 3.7 V 3.1 V 12 ID, DRAIN CURRENT (AMPS) TJ = 25C 2.1 V VDS 10 V 10 8 6 4 2 0

1.9 V

100C 25C TJ = 55C

2.5 1.5 2 VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics

0.08 ID = 5.4 A TJ = 25C 0.06

0.05 TJ = 25C 0.04 VGS = 2.7 V 0.03 VGS = 4.5 V 0.02 VGS = 2.5 V

0.04

0.02

0 0 8 2 4 6 VGS, GATETOSOURCE VOLTAGE (VOLTS) 10

0.01

8 10 6 ID, DRAIN CURRENT (AMPS)

12

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus GateToSource Voltage


1.6 ID = 5.4 A VGS = 4.5 V 10,000

Figure 4. On-Resistance versus Drain Current and Gate Voltage

VGS = 0 V IDSS, LEAKAGE (nA) 1.4 TJ = 150C

1.2

1000 TJ = 125C

0.8 0.6 50

25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

100

4 8 14 16 18 20 6 10 12 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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174

NTMS5P02R2
VGS , GATETOSOURCE VOLTAGE (VOLTS) VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V Ciss C, CAPACITANCE (pF) 3000 Crss 2000 Ciss 1000 Coss 0 10 5 Crss 0 VGS VDS GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS) 5 10 15 20 TJ = 25C 5 QT 4 VDS Q1 Q2 VGS 16 20

4000

12

2 ID = 5.4 A TJ = 25C

1 0 0 4 8 12 16

4 0

20

24

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 7. Capacitance Variation


1000 IS, SOURCE CURRENT (AMPS) VDD = 16 V ID = 5.4 A VGS = 4.5 V t, TIME (ns) 5 4 3 2 1 0 VGS = 0 V TJ = 25C

td(off) tf tr

100

td(on)

10 1 10 RG, GATE RESISTANCE (OHMS) 100

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Diode Forward Voltage versus Current

DRAINTOSOURCE DIODE CHARACTERISTICS


100 ID , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 di/dt 10 ms 1 ta RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 IS trr tb TIME dc 100 tp IS 0.25 IS 1 ms

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Diode Reverse Recovery Waveform

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175

NTMS5P02R2
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 Chip


0.0163

0.1

Normalized to ja at 10s.
0.0652 0.1988 0.6411 0.9502

0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F

SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 13. Thermal Response

INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270

inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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NTMS5P02R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 14. Typical Solder Heating Profile

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NTMSD2P102LR2 Product Preview FETKY


Power MOSFET and Schottky Diode Dual SO8 Package
Features

High Efficiency Components in a Single SO8 Package High Density Power MOSFET with Low RDS(on), Logic Level Gate Drive Independent PinOuts for MOSFET and Schottky Die Less Component Placement for Board Space Savings SO8 Surface Mount Package,
Mounting Information for SO8 Package Provided
Applications

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Schottky Diode with Low VF

Allowing for Flexibility in Application Use

MOSFET 2.3 AMPERES 20 VOLTS 90 mW @ VGS = 4.5 V SCHOTTKY DIODE 2.0 AMPERES 20 VOLTS 580 mV @ IF = 2.0 A

Power Management in Portable and BatteryPowered Products, i.e.:


Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 100C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 5.0 Apk, L = 28 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 20 "10 175 0.71 2.3 1.45 9.0 105 1.19 2.97 1.88 12 62.5 2.0 3.85 2.43 15 55 to +150 350 Unit V V C/W W A A A C/W W A A A C/W W A A A C mJ

A 8 1 SO8 CASE 751 STYLE 18 A S G

1 2 3 4

8 7 6 5

C C D D

TOP VIEW

MARKING DIAGRAM & PIN ASSIGNMENTS


Anode Anode Source Gate 1 2 3 4 (Top View) E2P102 L Y WW = Device Code = Assembly Location = Year = Work Week E2P102 LYWW 8 7 6 5 Cathode Cathode Drain Drain

TL

260

1. Minimum FR4 or G10 PCB, Steady State. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

ORDERING INFORMATION
Device NTMSD2P102LR2 Package SO8 Shipping 2500/Tape & Reel

Semiconductor Components Industries, LLC, 2000

178

December, 2000 Rev. 1

Publication Order Number: NTMSD2P102LR2/D

NTMSD2P102LR2
SCHOTTKY MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive Reverse Voltage DC Blocking Voltage Average Forward Current (Note 5.) (Rated VR, TA = 100C) Peak Repetitive Forward Current (Note 5.) (Rated VR, Square Wave, 20 kHz, TA = 105C) NonRepetitive Peak Surge Current (Note 5.) (Surge Applied at Rated Load Conditions, HalfWave, Single Phase, 60 Hz) Symbol VRRM VR IO IFRM IFSM Value 20 1.0 2.0 20 Unit V A A A

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 6.)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 25C) GateBody Leakage Current (VGS = 10 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +10 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 2.4 Adc) (VGS = 2.7 Vdc, ID = 1.2 Adc) (VGS = 2.5 Vdc, ID = 1.2 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 1.2 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 550 200 100 750 300 175 pF VGS(th) 0.5 RDS(on) gFS 4.2 0.070 0.100 0.110 0.090 0.130 0.150 Mhos 0.90 2.5 1.5 Vdc mV/C V(BR)DSS 20 IDSS IDSS IGSS IGSS 100 100 nAdc 2.0 nAdc 1.0 25 Adc 12.7 Vdc mV/C Adc Symbol Min Typ Max Unit

5. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. 6. Handling precautions to protect against electrostatic discharge is mandatory.

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NTMSD2P102LR2
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (continued) (Note 7.)
Characteristic SWITCHING CHARACTERISTICS (Notes 8. & 9.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 8.) Diode Forward OnVoltage Reverse Recovery Time (IS = 2.4 2 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge (IS = 2.4 Adc, VGS = 0 Vdc) (IS = 2.4 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.88 0.75 37 16 21 0.025 1.0 C Vdc ns (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 2.4 2 4 Ad Adc) ) (VDD = 10 Vdc, ID = 1.2 Adc, VGS = 2.7 2 7 Vdc, Vdc RG = 6.0 ) (VDD = 10 Vdc, ID = 2.4 Adc, 4 5 Vdc, Vdc VGS = 4.5 RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 10 35 33 29 15 40 35 35 10 1.5 5.0 20 65 60 55 18 nC ns ns Symbol Min Typ Max Unit

SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 8.)
g Maximum Instantaneous Forward Voltage IF = 1.0 1 0 Ad Adc IF = 2.0 Adc Maximum Instantaneous Reverse Current Vd VR = 20 Vdc Maximum Voltage Rate of Change VR = 20 Vdc 7. Handling precautions to protect against electrostatic discharge is mandatory. 8. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 9. Switching characteristics are independent of operating junction temperature. dV/dt IR VF TJ = 25C 0.47 0.58 TJ = 25C 0.05 10,000 TJ = 125C 0.39 0.53 TJ = 125C 10 V/ms mA Volts

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180

NTMSD2P102LR2
4 VGS = 2.1 V ID, DRAIN CURRENT (AMPS) 3 VGS = 10 V VGS = 4.5 V VGS = 2.5 V ID, DRAIN CURRENT (AMPS) TJ = 25C 5 VDS > = 10 V 4

VGS = 1.9 V

3 TJ = 25C

2 VGS = 1.7 V 1 VGS = 1.5 V 0 0 2 4 6 8 10 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1 0 1

TJ = 100C 1.5

TJ = 55C 2 2.5 3

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics.


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics.

0.2

TJ = 25C

0.12

TJ = 25C

0.15

0.1 VGS = 2.7 V 0.08 VGS = 4.5 V 0.06

0.1

0.05

0 2 4 6 8 VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.04 1 1.5 2 2.5 3 3.5 4 4.5 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GatetoSource Voltage.

Figure 4. OnResistance vs. Drain Current and Gate Voltage.

1.6 RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) ID = 2.4 A VGS = 4.5 V

1000 VGS = 0 V IDSS, LEAKAGE (nA) 100 TJ = 100C 10 TJ = 25C 1 TJ = 125C

1.4

1.2

0.8

0.1

0.6 50

0.01 25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 0 4 8 12 16 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 20

Figure 5. OnResistance Variation with Temperature.

Figure 6. DraintoSource Leakage Current vs. Voltage.

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181

NTMSD2P102LR2
1500 VDS = 0 V C, CAPACITANCE (pF) 1200 Ciss VGS = 0 V TJ = 25C 5 QT 4 20 18 16 14 3 Q1 2 ID = 2.4 A TJ = 25C Q2 VGS 12 10 8 6 1 0 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) VDS 4 2 0 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS)

900 Crss 600 Ciss

300

Coss Crss 10 5 0 VGS VDS 5 10 15 20

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

Figure 7. Capacitance Variation


1000 VDD = 10 V ID = 1.2 A VGS = 2.7 V t, TIME (ns) t, TIME (ns) 100

td (off) tr tf

100 tr td (off) td (on) 10 1.0 10 RG, GATE RESISTANCE (OHMS) 100 tf

10

td (on)

VDD = 10 V ID = 2.4 A VGS = 4.5 V 1.0 1.0 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance


2 IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C

Figure 10. Resistive Switching Time Variation versus Gate Resistance

1.6

di/dt IS

1.2

ta

trr tb TIME

0.8 tp 0.4 0 0.4 IS 0.25 IS

0.5

0.6

0.7

0.8

0.9

Figure 12. Diode Reverse Recovery Waveform

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current

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182

NTMSD2P102LR2
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE

D = 0.5

0.2 Normalized to Rja at Steady State (1 inch pad) 0.0125 0.0563 0.110 0.273 0.113 0.436

0.1

0.1

0.05 0.02 0.01 0.021 F 0.137 F 1.15 F 2.93 F 152 F 261 F

Single Pulse 0.01 1E03

1E02

1E01

1E+00 t, TIME (s)

1E+03

1E+02

1E+03

Figure 13. FET Thermal Response

TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS


10 IF, INSTANTANEOUS FORWARD CURRENT (AMPS) IF, INSTANTANEOUS FORWARD CURRENT (AMPS) 10 TJ = 125C

TJ = 125C 1.0 85C 25C

1.0

85C 25C

40C 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

0.1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

Figure 14. Typical Forward Voltage

Figure 15. Maximum Forward Voltage

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NTMSD2P102LR2
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
IR, MAXIMUM REVERSE CURRENT (AMPS) 1E2 IR , REVERSE CURRENT (AMPS) TJ = 125C 85C 1E1 TJ = 125C

1E3

1E2

1E4

1E3

1E5 25C

1E4 25C 1E5 1E6 0 5.0 10 15 20 VR, REVERSE VOLTAGE (VOLTS)

1E6 1E7 0 5.0 10 15 20 VR, REVERSE VOLTAGE (VOLTS)

Figure 16. Typical Reverse Current

Figure 17. Maximum Reverse Current

1000 TYPICAL CAPACITANCE AT 0 V = 170 pF C, CAPACITANCE (pF)

IO, AVERAGE FORWARD CURRENT (AMPS)

1.6 dc 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 TA, AMBIENT TEMPERATURE (C) Ipk/Io = 10 Ipk/Io = 20 SQUARE WAVE Ipk/Io = p Ipk/Io = 5.0 FREQ = 20 kHz

100

10 0 5.0 10 15 20 VR, REVERSE VOLTAGE (VOLTS)

Figure 18. Typical Capacitance

Figure 19. Current Derating

PFO, AVERAGE POWER DISSIPATION (WATTS)

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 IO, AVERAGE FORWARD CURRENT (AMPS) SQUARE WAVE dc

Ipk/Io = p Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20

Figure 20. Forward Power Dissipation

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184

NTMSD2P102LR2
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03 NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.0031 W CHIP JUNCTION 0.0014 F 0.0154 W 0.0082 F 0.1521 W 0.4575 W 0.3719 W 0.1052 F 2.7041 F 158.64 F AMBIENT

Figure 21. Schottky Thermal Response

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185

NTMSD2P102LR2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0
inches mm

0.024 0.6

0.050 1.270

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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186

NTMSD2P102LR2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 22 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 22. Typical Solder Heating Profile

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187

NTMSD3P102R2 Product Preview FETKY


PChannel EnhancementMode Power MOSFET and Schottky Diode Dual SO8 Package
Features http://onsemi.com

High Efficiency Components in a Single SO8 Package High Density Power MOSFET with Low RDS(on), Independent PinOuts for MOSFET and Schottky Die Less Component Placement for Board Space Savings SO8 Surface Mount Package,
Mounting Information for SO8 Package Provided
Applications

Schottky Diode with Low VF

Allowing for Flexibility in Application Use

MOSFET 3.05 AMPERES 20 VOLTS 0.085 W @ VGS = 10 V SCHOTTKY DIODE 1.0 AMPERES 20 VOLTS 470 mV @ IF = 1.0 A
A 8 1 A S G 1 2 3 4 5 8 7 6 C C D D

DCDC Converters Low Voltage Motor Control Power Management in Portable and BatteryPowered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. 2. 3. 4. Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 20 "20 171 0.73 2.34 1.87 8.0 100 1.25 3.05 2.44 12 62.5 2.0 3.86 3.10 15 55 to +150 140 Unit V V C/W W A A A C/W W A A A C/W W A A A C mJ

SO8 CASE 751 STYLE 18

TOP VIEW

MARKING DIAGRAM & PIN ASSIGNMENTS


Anode Anode Source Gate 1 2 3 4 (Top View) E3P102 L Y WW = Device Code = Assembly Location = Year = Work Week E3P102 LYWW 8 7 6 5 Cathode Cathode Drain Drain

ORDERING INFORMATION
Device TL 260 C NTMSD3P102R2 Package SO8 Shipping 2500/Tape & Reel

Minimum FR4 or G10 PCB, Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

188

January, 2001 Rev. 0

Publication Order Number: NTMSD3P102R2/D

NTMSD3P102R2
SCHOTTKY MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive Reverse Voltage DC Blocking Voltage Thermal Resistance JunctiontoAmbient (Note 5.) Thermal Resistance JunctiontoAmbient (Note 6.) Thermal Resistance JunctiontoAmbient (Note 7.) Average Forward Current (Note 7.) (Rated VR, TA = 100C) Peak Repetitive Forward Current (Note 7.) (Rated VR, Square Wave, 20 kHz, TA = 105C) NonRepetitive Peak Surge Current (Note 7.) (Surge Applied at Rated Load Conditions, HalfWave, Single Phase, 60 Hz) Symbol VRRM VR RJA RJA RJA IO IFRM IFSM Value 20 204 122 83 1.0 2.0 20 Unit V C/W C/W C/W A A A

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 8.)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 10 Vdc, ID = 3.05 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 3.05 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 5. 6. 7. 8. (VDS = 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 518 190 70 750 350 135 pF VGS(th) 1.0 RDS(on) gFS 5.0 0.063 0.090 0.085 0.125 Mhos 1.7 3.6 2.5 Vdc V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 1.0 25 nAdc 30 Vdc mV/C Adc Symbol Min Typ Max Unit

Minimum FR4 or G10 PCB, Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Handling precautions to protect against electrostatic discharge is mandatory.

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NTMSD3P102R2
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 9.)
Characteristic SWITCHING CHARACTERISTICS (Notes 10. & 11.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 10.) Diode Forward OnVoltage Reverse Recovery Time (IS = 3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge (IS = 3.05 Adc, VGS = 0 Vdc) (IS = 3.05 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.96 0.78 34 18 16 0.03 1.25 C Vdc ns (VDS = 20 Vdc, VGS = 10 Vdc, ID = 3.05 3 05 Adc) Ad ) (VDD = 20 Vdc, ID = 1.5 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) (VDD = 20 Vdc, ID = 3.05 Adc, 10 Vdc, Vdc VGS = 10 RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 12 16 45 45 16 42 32 35 16 2.0 4.5 22 30 80 80 25 nC ns ns Symbol Min Typ Max Unit

SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 10.)
g Maximum Instantaneous Forward Voltage IF = 1.0 1 0 Ad Adc IF = 2.0 Adc Maximum Instantaneous Reverse Current Vd VR = 20 Vdc Maximum Voltage Rate of Change VR = 20 Vdc 9. Handling precautions to protect against electrostatic discharge is mandatory. 10. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 11. Switching characteristics are independent of operating junction temperature. dV/dt IR VF TJ = 25C 0.47 0.58 TJ = 25C 0.05 10,000 TJ = 125C 0.39 0.53 TJ = 125C 10 V/ms mA Volts

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TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
6 ID, DRAIN CURRENT (AMPS) 5 4 TJ = 25C 3 2 1 0 6 ID, DRAIN CURRENT (AMPS) VGS = 4.4 V VGS = 4 V VGS = 4.6 V VGS = 4.8 V VGS = 3.6 V VGS = 2.8 V VGS = 3.2 V VGS = 5 V VGS = 2.6 V VGS = 3 V VDS > = 10 V 5 4 TJ = 100C 3 2 1 0 TJ = 25C TJ = 55C

VGS = 10 V VGS = 8 V VGS = 6 V

0.25

0.5

0.75

1.25

1.5

1.75

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3 4 5 6 7 8 ID = 3.05 A TJ = 25C

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 5 6 7 ID = 1.5 A TJ = 25C

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 0.25 TJ = 25C 0.2 VGS = 4.5 V 1.6

Figure 4. OnResistance vs. GatetoSource Voltage

1.4

ID = 3.05 A VGS = 10 V

1.2

0.15 VGS = 10 V 0.1

0.8

0.05 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS)

0.6 50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance vs. Drain Current and Gate Voltage

Figure 6. On Resistance Variation with Temperature

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10000 VGS = 0 V C, CAPACITANCE (pF) IDSS, LEAKAGE (nA) 1200 1000 800 600 400 200

VDS = 0 V

VGS = 0 V

Ciss

1000

TJ = 150C

Crss

Ciss Coss Crss

100

TJ = 125C

TJ = 25C 10 2 4 6 8 10 12 14 16 18 20 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 0 10


VGS

VDS

10

15

20

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 7. DraintoSource Leakage Current vs. Voltage


12 10 VDS t, TIME (ns) 8 VGS 6 4 2 0 ID = 3.05 A TJ = 25C 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) Q1 Q2 12 8 4 0 16 1 16 100 QT 24 1000 20

Figure 8. Capacitance Variation

VDS = 20 V ID = 3.05 A VGS = 10 V td(off) tf 10 td(on) tr

10 RG, GATE RESISTANCE ()

100

Figure 9. GatetoSource and DraintoSource Voltage vs. Total Charge


1000 IS, SOURCE CURRENT (AMPS) VDS = 20 V ID = 1.5 A VGS = 4.5 V t, TIME (ns) 3 2.5 2 1.5 1 0.5

Figure 10. Resistive Switching Time Variation vs. Gate Resistance


VGS = 0 V TJ = 25C

100

tr tf

td(off) td(on)

10

10 RG, GATE RESISTANCE ()

100

0 0.2

0.4

0.6

0.8

1.2

VSD, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Resistive Switching Time Variation vs. Gate Resistance

Figure 12. Diode Forward Voltage vs. Current

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di/dt IS ta trr tb TIME tp IS 0.25 IS

Figure 13. Diode Reverse Recovery Waveform

1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE D = 0.5

0.2 0.1 0.1 0.05 0.02 0.01 Single Pulse 1E02 1E01 1E+00 t, TIME (s) 1E+01 1E+02 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8

24.4

0.0014 F

0.0073 F

0.022 F

0.105 F

0.484 F

3.68 F Ambient 1E+03

0.01 1E03

Figure 14. FET Thermal Response

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NTMSD3P102R2
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
10 IF, INSTANTANEOUS FORWARD CURRENT (AMPS) IF, INSTANTANEOUS FORWARD CURRENT (AMPS) 10 TJ = 125C

TJ = 125C 1.0 85C 25C

1.0

85C 25C

40C 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

0.1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

Figure 15. Typical Forward Voltage


IR, MAXIMUM REVERSE CURRENT (AMPS) 1E2 IR , REVERSE CURRENT (AMPS) TJ = 125C 85C 1E1

Figure 16. Maximum Forward Voltage

1E3

1E2

TJ = 125C

1E4

1E3

1E5 25C

1E4 25C 1E5 1E6 0 5.0 10 15 20 VR, REVERSE VOLTAGE (VOLTS)

1E6 1E7 0 5.0 10 15 20 VR, REVERSE VOLTAGE (VOLTS)

Figure 17. Typical Reverse Current

Figure 18. Maximum Reverse Current

1000 TYPICAL CAPACITANCE AT 0 V = 170 pF C, CAPACITANCE (pF)

IO, AVERAGE FORWARD CURRENT (AMPS)

1.6 dc 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 TA, AMBIENT TEMPERATURE (C) Ipk/Io = 10 Ipk/Io = 20 SQUARE WAVE Ipk/Io = p Ipk/Io = 5.0 FREQ = 20 kHz

100

10 0 5.0 10 15 20 VR, REVERSE VOLTAGE (VOLTS)

Figure 19. Typical Capacitance

Figure 20. Current Derating

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TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
PFO, AVERAGE POWER DISSIPATION (WATTS) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 IO, AVERAGE FORWARD CURRENT (AMPS) SQUARE WAVE dc

Ipk/Io = p Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20

Figure 21. Forward Power Dissipation

1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03 NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.0031 W CHIP JUNCTION 0.0014 F 0.0154 W 0.0082 F 0.1521 W 0.4575 W 0.3719 W 0.1052 F 2.7041 F 158.64 F AMBIENT

Figure 22. Schottky Thermal Response

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NTMSD3P102R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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NTMSD3P102R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 23 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 23. Typical Solder Heating Profile

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NTMSD3P303R2 Product Preview FETKY


PChannel EnhancementMode Power MOSFET and Schottky Diode Dual SO8 Package
Features http://onsemi.com

High Efficiency Components in a Single SO8 Package High Density Power MOSFET with Low RDS(on), Independent PinOuts for MOSFET and Schottky Die Less Component Placement for Board Space Savings SO8 Surface Mount Package,
Mounting Information for SO8 Package Provided
Applications

Schottky Diode with Low VF

Allowing for Flexibility in Application Use

MOSFET 3.05 AMPERES 30 VOLTS 0.085 W @ VGS = 10 V SCHOTTKY DIODE 3.0 AMPERES 30 VOLTS 420 mV @ IF = 3.0 A
A 8 1 A S G 1 2 3 4 5 8 7 6 C C D D

DCDC Converters Low Voltage Motor Control Power Management in Portable and BatteryPowered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 4.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 4.5 Vdc, Peak IL = 7.5 Apk, L = 5 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. 2. 3. 4. Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 30 "20 171 0.73 2.34 1.87 8.0 100 1.25 3.05 2.44 12 62.5 2.0 3.86 3.10 15 55 to +150 140 Unit V V C/W W A A A C/W W A A A C/W W A A A C mJ

SO8 CASE 751 STYLE 18

(TOP VIEW)

MARKING DIAGRAM & PIN ASSIGNMENTS


Anode Anode Source Gate 1 2 3 4 (Top View) E3P303 L Y WW = Device Code = Assembly Location = Year = Work Week E3P303 LYWW 8 7 6 5 Cathode Cathode Drain Drain

ORDERING INFORMATION
Device TL 260 C NTMSD3P303R2 Package SO8 Shipping 2500/Tape & Reel

Minimum FR4 or G10 PCB, Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

198

January, 2001 Rev. 0

Publication Order Number: NTMSD3P303R2/D

NTMSD3P303R2
SCHOTTKY MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive Reverse Voltage DC Blocking Voltage Thermal Resistance JunctiontoAmbient (Note 5.) Thermal Resistance JunctiontoAmbient (Note 6.) Thermal Resistance JunctiontoAmbient (Note 7.) Average Forward Current (Note 7.) (Rated VR, TA = 100C) Peak Repetitive Forward Current (Note 7.) (Rated VR, Square Wave, 20 kHz, TA = 105C) NonRepetitive Peak Surge Current (Note 7.) (Surge Applied at Rated Load Conditions, HalfWave, Single Phase, 60 Hz) Symbol VRRM VR RJA RJA RJA IO IFRM IFSM Value 30 197 97 62.5 3.0 6.0 30 Unit V C/W C/W C/W A A A

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 8.)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 10 Vdc, ID = 3.05 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 3.05 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 5. 6. 7. 8. (VDS = 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss 520 170 70 750 325 135 pF VGS(th) 1.0 RDS(on) gFS 5.0 0.063 0.090 0.085 0.125 Mhos 1.7 3.6 2.5 Vdc V(BR)DSS 30 IDSS IGSS IGSS 100 100 nAdc 1.0 25 nAdc 30 Vdc mV/C Adc Symbol Min Typ Max Unit

Crss Minimum FR4 or G10 PCB, Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), t 10 seconds. Handling precautions to protect against electrostatic discharge is mandatory.

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NTMSD3P303R2
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 9.)
Characteristic SWITCHING CHARACTERISTICS (Notes 10. & 11.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 10.) Diode Forward OnVoltage Reverse Recovery Time (IS = 3.05 3 05 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge (IS = 3.05 Adc, VGS = 0 Vdc) (IS = 3.05 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.96 0.78 34 18 16 0.03 1.25 C Vdc ns (VDS = 24 Vdc, VGS = 10 Vdc, ID = 3.05 3 05 Adc) Ad ) (VDD = 24 Vdc, ID = 1.5 Adc, VGS = 4.5 4 5 Vdc, Vdc RG = 6.0 ) (VDD = 24 Vdc, ID = 3.05 Adc, 10 Vdc, Vdc VGS = 10 RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 12 16 45 45 16 42 32 35 16 2.0 4.5 22 30 80 80 25 nC ns ns Symbol Min Typ Max Unit

SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 10.)
Maximum Instantaneous Forward Voltage IF = 100 mAdc IF = 3.0 Adc IF = 6.0 Adc Maximum Instantaneous Reverse Current VR = 30 Vdc Vd IR VF TJ = 25C 0.28 0.42 0.50 TJ = 25C 250 25 Maximum Voltage Rate of Change VR = 30 Vdc 9. Handling precautions to protect against electrostatic discharge is mandatory. 10. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 11. Switching characteristics are independent of operating junction temperature. dV/dt 10,000 TJ = 125C 0.13 0.33 0.45 TJ = 125C mA mA V/ms Volts

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NTMSD3P303R2
TYPICAL MOSFET ELECTRICAL CHARACTERISTICS
6 ID, DRAIN CURRENT (AMPS) 5 4 TJ = 25C 3 2 1 0 6 ID, DRAIN CURRENT (AMPS) VGS = 4.4 V VGS = 4 V VGS = 4.6 V VGS = 4.8 V VGS = 3.6 V VGS = 2.8 V VGS = 3.2 V VGS = 5 V VGS = 2.6 V VGS = 3 V VDS > = 10 V 5 4 TJ = 100C 3 2 1 0 TJ = 25C TJ = 55C

VGS = 10 V VGS = 8 V VGS = 6 V

0.25

0.5

0.75

1.25

1.5

1.75

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3 4 5 6 7 8 ID = 3.05 A TJ = 25C

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 5 6 7 ID = 1.5 A TJ = 25C

VGS, GATETOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 0.25 TJ = 25C 0.2 VGS = 4.5 V 1.6

Figure 4. OnResistance vs. GatetoSource Voltage

1.4

ID = 3.05 A VGS = 10 V

1.2

0.15 VGS = 10 V 0.1

0.8

0.05 1 2 3 4 5 6 ID, DRAIN CURRENT (AMPS)

0.6 50

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance vs. Drain Current and Gate Voltage

Figure 6. On Resistance Variation with Temperature

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10000 VGS = 0 V IDSS, LEAKAGE (nA) TJ = 150C 1000 C, CAPACITANCE (pF) 1200 1000 800 600 400 200

VDS = 0 V

VGS = 0 V

Ciss

TJ = 125C 100

Crss

Ciss

Coss TJ = 25C Crss 0 5 10 15 20 25 30

10 6

10

14

18

22

26

30

0 10

VGS

VDS

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 7. DraintoSource Leakage Current vs. Voltage


12 10 VDS VGS 6 4 2 0 ID = 3.05 A TJ = 25C 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) Q1 Q2 15 10 5 0 16 1 t, TIME (ns) 8 20 100 QT 30 1000 25

Figure 8. Capacitance Variation

VDS = 24 V ID = 3.05 A VGS = 10 V td(off) tf 10 td(on) tr

10 RG, GATE RESISTANCE ()

100

Figure 9. GatetoSource and DraintoSource Voltage vs. Total Charge


1000 IS, SOURCE CURRENT (AMPS) VDS = 24 V ID = 1.5 A VGS = 4.5 V t, TIME (ns) 3 2.5 2 1.5 1 0.5

Figure 10. Resistive Switching Time Variation vs. Gate Resistance


VGS = 0 V TJ = 25C

100

tr tf

td(off) td(on)

10

10 RG, GATE RESISTANCE ()

100

0 0.2

0.4

0.6

0.8

1.2

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 11. Resistive Switching Time Variation vs. Gate Resistance

Figure 12. Diode Forward Voltage vs. Current

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100 ID, DRAIN CURRENT (AMPS)

10

VGS = 12 V SINGLE PULSE TA = 25C

1.0 ms

10 ms 1.0 dc IS

di/dt

ta 0.1 RDS(on) THERMAL LIMIT PACKAGE LIMIT 1 1.0 10 100

trr tb TIME

tp IS

0.25 IS

0.01

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 13. Maximum Rated Forward Biased Safe Operating Area

Figure 14. Diode Reverse Recovery Waveform

1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE D = 0.5

0.2 0.1 0.1 0.05 0.02 0.01 Single Pulse 1E02 1E01 1E+00 t, TIME (s) 1E+01 1E+02 Normalized to RJA at Steady State (1 pad) Chip Junction 2.32 18.5 50.9 37.1 56.8

24.4

0.0014 F

0.0073 F

0.022 F

0.105 F

0.484 F

3.68 F Ambient 1E+03

0.01 1E03

Figure 15. FET Thermal Response

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NTMSD3P303R2
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
IF, INSTANTANEOUS FORWARD CURRENT (AMPS) IF, INSTANTANEOUS FORWARD CURRENT (AMPS) 10 85C 25C 10 85C TJ = 125C 25C

1.0

TJ = 125C

-40C

1.0

0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

Figure 16. Typical Forward Voltage


0.1 IR, REVERSE CURRENT (AMPS) 0.01 0.001 TJ = 125C 85C 0.1

Figure 17. Maximum Forward Voltage

IR, MAXIMUM REVERSE CURRENT (AMPS)

TJ = 125C 0.01 0.001 0.0001 25C

0.0001 25C

0.00001 0.000001

0.00001

5.0

10

15

20

25

30

0.000001

5.0

10

15

20

25

30

VR, REVERSE VOLTAGE (VOLTS)

VR, REVERSE VOLTAGE (VOLTS)

Figure 18. Typical Reverse Current


1000 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0

Figure 19. Maximum Reverse Current

IO , AVERAGE FORWARD CURRENT (AMPS)

dc SQUARE WAVE Ipk/Io = p Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20

FREQ = 20 kHz

C, CAPACITANCE (pF)

100

10

5.0

10

15

20

25

30

20

40

60

80

100

120

140

160

VR, REVERSE VOLTAGE (VOLTS)

TA, AMBIENT TEMPERATURE (C)

Figure 20. Typical Capacitance

Figure 21. Current Derating

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NTMSD3P303R2
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
PFO , AVERAGE POWER DISSIPATION (WATTS) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 1.0 2.0 3.0 4.0 5.0 Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20 Ipk/Io = p SQUARE WAVE dc

IO, AVERAGE FORWARD CURRENT (AMPS)

Figure 22. Forward Power Dissipation

1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2

0.1

0.1 0.05 0.02 0.01 NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.1010 W CHIP JUNCTION 39.422 mF SINGLE PULSE 1.2674 W 27.987 W 30.936 W 36.930 W 0.2292 F 2.267 F AMBIENT 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

0.01

493.26 mF 0.0131 F

0.001

1.0E-05

1.0E-04

1.0E-03

Figure 23. Schottky Thermal Response

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205

NTMSD3P303R2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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206

NTMSD3P303R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 24 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 24. Typical Solder Heating Profile

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207

NTP27N06 Advance Information Power MOSFET 27 Amps, 60 Volts


NChannel TO220
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits

27 AMPERES 60 VOLTS RDS(on) = 46 m


NChannel D

G S

Typical Applications

MARKING DIAGRAM & PIN ASSIGNMENT


4 Unit Vdc Vdc Vdc VGS VGS ID ID IDM PD TJ, Tstg EAS 109 20 30 1 27 15 80 88.2 0.59 55 to 175 Adc Apk W W/C C mJ NTP27N06 LL Y WW 2 3 TO220AB CASE 221A STYLE 5 60 60 4 Drain Symbol VDSS VDGR Value

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vdc, L = 0.3 mH, IL(pk) = 27 A, VDS = 60 Vdc) Thermal Resistance JunctiontoCase Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds

NTP27N06 LLYWW 3 Source 2 Drain

1 Gate

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device Package TO220AB Shipping 50 Units/Rail

RJC TL

1.7 260

C/W C

NTP27N06

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Semiconductor Components Industries, LLC, 2001

208

March, 2001 Rev. 1

Publication Order Number: NTP27N06/D

NTP27N06
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 1.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (Note 1.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 1.) (VGS = 10 Vdc, ID = 13.5 Adc) Static DraintoSource OnResistance (Note 1.) (VGS = 10 Vdc, ID = 27 Adc) (VGS = 10 Vdc, ID = 13.5 Adc, TJ = 150C) Forward Transconductance (Note 1.) (VDS = 7.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 27 Adc, Ad VGS = 10 Vdc) (Note 1.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 27 Adc, VGS = 0 Vdc) (Note 1.) (IS = 27 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (IS = 27 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 1.) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. trr ta tb QRR VSD 1.05 0.93 42 26 16 0.07 1.25 c ns Vdc (VDD = 30 Vdc, ID = 27 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (Note 1.) td(on) tr td(off) tf QT Q1 Q2 13.6 62.7 26.6 70.4 21.2 5.6 7.3 30 125 60 140 30 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 725 213 58 1015 300 120 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.05 2.12 13.2 1.5 mhos 37.5 46 Vdc 2.8 6.9 4.0 Vdc mV/C mW V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 70 79.4 Vdc mV/C Adc Symbol Min Typ Max Unit

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209

NTP45N06, NTB45N06 Power MOSFET 45 Amps, 60 Volts

NChannel TO220 and D2PAK


Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits

45 AMPERES 60 VOLTS RDS(on) = 26 m


NChannel D

Typical Applications

G 4 S 1 TO220AB CASE 221A STYLE 5 2 3 2 3 D2PAK CASE 418B STYLE 2 4

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vdc, RG = 25 , IL(pk) = 40 A, L = 0.3 mH, VDS = 60 Vdc) Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "20 "30 45 30 150 125 0.83 3.2 2.4 55 to +175 240 Adc Apk W W/C W W C mJ Unit Vdc Vdc Vdc 1

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain

NTP45N06 LLYWW 1 Gate 2 Drain 3 Source 1 Gate

NTB45N06 LLYWW

TJ, Tstg EAS

2 Drain

3 Source

1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).

NTx45N06 LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device NTP45N06 NTB45N06 NTB45N06T4 Package TO220AB D2PAK D2PAK Shipping 50 Units/Rail 50 Units/Rail 800/Tape & Reel

Semiconductor Components Industries, LLC, 2001

210

March, 2001 Rev. 0

Publication Order Number: NTP45N06/D

NTP45N06, NTB45N06
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 3.) JunctiontoAmbient (Note 4.) Symbol RJC RJA RJA TL Value 1.2 46.8 63.2 260 Unit C/W

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 5.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 5.) Gate Threshold Voltage (Note 5.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 5.) (VGS = 10 Vdc, ID = 22.5 Adc) Static DraintoSource OnVoltage (Note 5.) (VGS = 10 Vdc, ID = 45 Adc) (VGS = 10 Vdc, ID = 22.5 Adc, TJ = 150C) Forward Transconductance (Note 5.) (VDS = 8.0 Vdc, ID = 12 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge Ad (VDS = 48 Vd Vdc, ID = 45 Adc, VGS = 10 Vdc) (Note 5.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 45 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 5.) Reverse Recovery Stored Charge 3. 4. 5. 6. (IS = 45 Adc, VGS = 0 Vdc) (Note 5.) (IS = 45 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb 1.08 0.93 53.1 36 16.9 1.2 C Vdc ns (VDD = 30 Vdc, ID = 45 Adc, VGS = 10 Vdc, RG = 9.1 ) (Note 5.) td(on) tr td(off) tf QT Q1 Q2 10 101 33 106 33 6.4 15 25 200 70 220 46 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1224 345 76 1725 485 160 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 0.93 0.93 16.6 1.4 mhos 21 26 Vdc 2.8 7.2 4.0 Vdc mV/C mOhm V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 70 57 Vdc mV/C Adc Symbol Min Typ Max Unit

QRR 0.087 When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Switching characteristics are independent of operating junction temperatures.

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211

NTP45N06, NTB45N06
90 ID, DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 0 4 5 1 2 3 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 6 VGS = 4.5 V VGS = 7.5 V VGS = 5.5 V VGS = 5 V VGS = 9 V VGS = 6.5 V VGS = 8 V VGS = 6 V VGS = 10 V 90 VGS = 7 V ID, DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 3 TJ = 25C TJ = 100C TJ = 55C 3.5 4 4.5 5 5.5 6 6.5 7 7.5 VGS, GATETOSOURCE VOLTAGE (VOLTS) 8 VDS > = 10 V

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.05 VGS = 10 V

0.032 0.03 0.028 0.026 0.024 0.022 0.02 0.018 0 10 20 30 40 VGS = 15 V 50 60 70 80 90 VGS = 10 V

0.042 TJ = 100C TJ = 25C TJ = 55C

0.034

0.026

0.018

0.01

10

20

30

40

50

60

70

80

90

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 50 25 10 0 25 50 75 100 125 150 175 0 ID = 22.5 A VGS = 10 V 10000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V IDSS, LEAKAGE (nA) TJ = 150C

1000 TJ = 125C 100 TJ = 100C

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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212

NTP45N06, NTB45N06
VGS, GATETOSOURCE VOLTAGE (VOLTS)

3600 3200 C, CAPACITANCE (pF) 2800 2400 2000 1600 1200 800 400 0 10

VDS = 0 V Ciss Crss

VGS = 0 V

TJ = 25C

12 10 8 6 4 2 0 0 ID = 45 TJ = 25C 4 8 12 16 20 24 28 32 36 Q1 Q2 QT VGS

Ciss

Coss Crss 5 VGS 0 VDS 5 10 15 20 25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation


1000 IS, SOURCE CURRENT (AMPS) VDS = 30 V ID = 45 A VGS = 10 V t, TIME (ns) 100 tf tr td(off) td(on) 50

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge


VGS = 0 V TJ = 25C 40

30

20

10

10

10 RG, GATE RESISTANCE ()

100

0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 1.04 VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance


1000 ID, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C dc 10 10 ms 1 ms 1 RDS(on) Limit Thermal Limit Package Limit 100 s EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 280

Figure 10. Diode Forward Voltage vs. Current

ID = 45 A 240 200 160 120 80 40 0 25 50 75 100 125 150 175

100

0.1 0.10

10

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature

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213

NTP45N06, NTB45N06
1 r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RJC at Steady State

0.1

0.01 0.00001

0.0001

0.001

0.01 t, TIME (s)

0.1

10

Figure 13. Thermal Response

10 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board

0.1

0.01

0.001 0.00001

0.0001

0.001

0.01

0.1 t, TIME (s)

10

100

1000

Figure 14. Thermal Response

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214

NTP45N06L, NTB45N06L Power MOSFET 45 Amps, 60 Volts, Logic Level


NChannel TO220 and D2PAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features http://onsemi.com

Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Power Supplies Converters Power Motor Controls Bridge Circuits

45 AMPERES 60 VOLTS RDS(on) = 28 m


NChannel D

Typical Applications

G 4 S 1 TO220AB CASE 221A STYLE 5 2 3 2 3 D2PAK CASE 418B STYLE 2 4

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tpv10 s) Total Power Dissipation @ TA = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 0.3 mH IL(pk) = 40 A, VDS = 60 Vdc, RG = 25 ) Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "15 "20 45 30 150 125 0.83 3.2 2.4 55 to +175 240 Adc Apk W W/C W W C mJ Unit Vdc Vdc Vdc 1

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain

NTP45N06L LLYWW 1 Gate 2 Drain 3 Source 1 Gate

NTB45N06L LLYWW

TJ, Tstg EAS

2 Drain

3 Source

1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2).

NTx45N06L LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device NTP45N06L NTB45N06L NTB45N06LT4 Package TO220AB D2PAK D2PAK Shipping 50 Units/Rail 50 Units/Rail 800/Tape & Reel

Semiconductor Components Industries, LLC, 2001

215

March, 2001 Rev. 0

Publication Order Number: NTP45N06L/D

NTP45N06L, NTB45N06L
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Thermal Resistance JunctiontoCase JunctiontoAmbient (Note 3.) JunctiontoAmbient (Note 4.) Symbol RJC RJA RJA TL Value 1.2 46.8 63.2 260 Unit C/W

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Note 4.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 5.) Gate Threshold Voltage (Note 5.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 5.) (VGS = 5.0 Vdc, ID = 22.5 Adc) Static DraintoSource OnVoltage (Note 5.) (VGS = 5.0 Vdc, ID = 45 Adc) (VGS = 5.0 Vdc, ID = 22.5 Adc, TJ = 150C) Forward Transconductance (Note 5.) (VDS = 8.0 Vdc, ID = 12 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vd Vdc, ID = 45 Adc, Ad VGS = 5.0 Vdc) (Note 5.) SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 45 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) (Note 5.) Reverse Recovery Stored Charge 3. 4. 5. 6. (IS = 45 Adc, VGS = 0 Vdc) (Note 5.) (IS = 45 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR 1.01 0.92 56 30 26 0.09 1.15 C Vdc ns (VDD = 30 Vdc, ID = 45 Adc, VGS = 5.0 Vdc, RG = 9.1 ) (Note 5.) td(on) tr td(off) tf QT Q1 Q2 13 341 36 158 23 4.6 14.1 30 680 75 320 32 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1212 352 90 1700 480 180 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 1.03 0.93 22.8 1.51 mhos 23 28 Vdc 1.8 4.7 2.0 Vdc mV/C mOhm V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 67 67.2 Vdc mV/C Adc Symbol Min Typ Max Unit

When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Switching characteristics are independent of operating junction temperatures.

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216

NTP45N06L, NTB45N06L

80 ID, DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 1 VGS = 8 V VGS = 9 V 2 VGS = 10 V

VGS = 5.5 V VGS = 5 V VGS = 6 V VGS = 7 V VGS = 4.5 V ID, DRAIN CURRENT (AMPS)

80 70 60 50 40 30 20 10 0 1.8 TJ = 100C TJ = 55C 2.6 3.4 4.2 5 5.8 TJ = 25C VDS > = 10 V

VGS = 4 V

VGS = 3.5 V

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE () RDS(on), DRAINTOSOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.046 VGS = 5 V 0.042 0.038 0.034 0.03 0.026 0.022 0.018 0.014 0 10 20 30 40 50 60 70 80 TJ = 55C TJ = 25C TJ = 100C

0.046 0.042 0.038 0.034 0.03 0.026 0.022 0.018 0 10 20 30 40 50 60 70 80 ID, DRAIN CURRENT (AMPS) VGS = 10 V VGS = 5 V

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GatetoSource Voltage


RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 50 25 10 0 25 50 75 100 125 150 175 10000 ID = 22.5 A VGS = 5 V IDSS, LEAKAGE (nA) 1000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V TJ = 150C

TJ = 125C

100 TJ = 100C

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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217

NTP45N06L, NTB45N06L
VGS, GATETOSOURCE VOLTAGE (VOLTS)

4000 3600 C, CAPACITANCE (pF) 3200 2800 2400 2000 1600 1200 800 400 0 10

VDS = 0 V Ciss Crss

VGS = 0 V

TJ = 25C

6 5 Q1 4 3 2 1 0 0 ID = 45 A TJ = 25C 4 8 12 16 20 24 QT Q2 VGS

Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation


1000 48 IS, SOURCE CURRENT (AMPS) tr tf 100 td(off) 40 32 24 16 8 0 0.6

Figure 8. GatetoSource and DraintoSource Voltage vs. Total Charge


VGS = 0 V TJ = 25C

VDS = 30 V ID = 45 A VGS = 5 V

t, TIME (ns)

td(on) 10 1 10 RG, GATE RESISTANCE () 100

0.64 0.68 0.72 0.76 0.8

0.84 0.88 0.92 0.96 1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance


1000 ID, DRAIN CURRENT (AMPS) VGS = 15 V SINGLE PULSE TC = 25C EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 280 240 200 160 120 80 40 0 25

Figure 10. Diode Forward Voltage vs. Current

ID = 45 A

100

dc 10 10 ms 1 ms 1 RDS(on) Limit Thermal Limit Package Limit 100 s

0.1 0.10

10

100

50

75

100

125

150

175

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature

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218

NTP45N06L, NTB45N06L
1 r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RJC at Steady State

0.1

0.01 0.00001

0.0001

0.001

0.01 t, TIME (s)

0.1

10

Figure 13. Thermal Response

10 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Normalized to RJA at Steady State, 1 square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board

0.1

0.01

0.001 0.00001

0.0001

0.001

0.01

0.1 t, TIME (s)

10

100

1000

Figure 14. Thermal Response

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219

NTP75N03-06, NTB75N03-06 Power MOSFET 75 Amps, 30 Volts

NChannel TO220 and D2PAK


This 10 VGS gate drive vertical Power MOSFET is a general purpose part that provides the best of design available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The draintosource diode has a ideal fast but soft recovery.
Features http://onsemi.com

UltraLow RDS(on), Single Base, Advanced Technology SPICE Parameters Available Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperatures High Avalanche Energy Specified ESD JEDAC Rated HBM Class 1, MM Class B, CDM Class 0 Power Supplies Inductive Loads PWM Motor Controls Replaces MTP1306 and MTB1306 in Many Applications

75 AMPERES 30 VOLTS RDS(on) = 6.5 m


NChannel D

Typical Applications

G S 4 1 TO220AB CASE 221A STYLE 5 2 3 2 3 D2PAK CASE 418B STYLE 2

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain E75 N0306 YWW 1 Gate 3 Source

E75 N0306 YWW 1 Gate 2 Drain 3 Source

2 Drain

N0306 Y WW

= Device Code = Year = Work Week

ORDERING INFORMATION
Device NTP75N0306 NTB75N0306 NTB75N0306T4 Package TO220 D2PAK D2PAK Shipping 50 Units/Rail 50 Units/Rail 800 Tape & Reel

Semiconductor Components Industries, LLC, 2000

220

December, 2000 Rev. 0

Publication Order Number: NTP75N0306/D

NTP75N0306, NTB75N0306
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ TA = 25_C Continuous @ TA = 100_C Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 38 Vdc, VGS = 10 Vdc, L = 1 mH, IL(pk) = 55 A, VDS = 40 Vdc) Thermal Resistance JunctiontoCase JunctiontoAmbient JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. When surface mounted to an FR4 board using the minimum recommended pad size. Symbol VDSS VDGB VGS VGS ID ID IDM PD Value 30 30 20 24 75 59 225 150 1.0 2.5 55 to 150 1500 Unit Vdc Vdc Vdc Vdc Adc Apk W W/_C W _C mJ

TJ and Tstg EAS

RJC RJA RJA TL

1.0 62.5 50 260

_C/W

_C

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221

NTP75N0306, NTB75N0306
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ. Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Negative) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 57 Vdc mVC Adc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 2.) (VGS = 10 Vdc, ID = 37.5 Adc) Static DraintoSource On Resistance (Note 2.) (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 37.5 Adc, TJ = 125C) Forward Transconductance (Notes 2. & 4.) (VDS = 3 Vdc, ID = 20 Adc) VGS(th) 1.0 RDS(on) VDS(on) gFS 0.53 0.35 58 0.68 0.50 Mhos 5.3 6.5 Vdc 1.6 6 2.0 Vdc mVC m

DYNAMIC CHARACTERISTICS (Note 4.)


Input Capacitance Output Capacitance Transfer Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 4398 1160 317 5635 1894 430 pF

SWITCHING CHARACTERISTICS (Notes 3. & 4.)


TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VGS = 5.0 Vdc, ID = 75 Adc, Ad VDS = 24 Vdc) (Note 2.) (VGS = 5 5.0 0 Vd Vdc, VDD = 20 Vdc, ID = 75 Adc, RG = 4.7 ) (Note 2.) td(on) tr td(off) tf QT Q1 Q2 31 510 99 203 52 6.6 28 48 986 120 300 122 28 66 nC ns

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) (Note 2.) (IS = 75 Ad Adc, VGS = 0 Vd Vdc dlS/dt = 100 A/s) (Note 2.) VSD 1.19 1.09 37 20 17 0.023 1.25 C Vdc

Reverse Recovery Time (N t 4 (Note 4.) ) Reverse Recovery Stored Ch Charge (Note (N t 4.) 4)

trr ta tb QRR

ns

2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. 3. Switching characteristics are independent of operating junction temperatures. 4. From characterization test data.

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222

NTP75N0306, NTB75N0306
150 VGS = 3.5 V ID, DRAIN CURRENT (AMPS) 135 120 105 90 75 60 45 30 15 0 0.5 1 1.5 TJ = 25C TJ = 100C 2 2.5 TJ = 55C 3 3.5 4 VDS 10 V

120 ID, DRAIN CURRENT (AMPS)

VGS = 4 V VGS = 4.5 V VGS = 5 V VGS = 6 V VGS = 8 V VGS = 10 V

90

60

VGS = 3 V

30 TJ = 25C 0 0 0.2 0.4 0.6 0.8 1 VGS = 2.5 V

1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTO SOURCE RESISTANCE () RDS(on), DRAINTO SOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.0085 0.008 0.0075 0.007 0.0065 0.006 0.0055 0.005 0.0045 0.004 10 20 30 40 50 60 70 80 90 100 120 ID, DRAIN CURRENT (AMPS) TJ = 55C VGS = 5 V TJ = 100C

0.009 TJ = 25C 0.008

TJ = 25C

0.007

VGS = 5 V VGS = 10 V

0.006

0.005

0.004 0 20 40 60 80 100 120 ID, DRAIN CURRENT (AMPS)

RDS(on), DRAINTO SOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance vs. Drain Current and Temperature


1.6 VGS = 10 V ID = 37.5 A 1.4 IDSS, LEAKAGE (nA) 100 1000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V TJ = 125C

1.2

TJ = 100C 10

0.8

0.6 50

1 25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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223

NTP75N0306, NTB75N0306
1200 VGS VDS 1000 C, CAPACITANCE (pF) 800 600 400 Coss 200 Crss 0 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 22 25 GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V TJ = 25C VGS, GATETOSOURCE VOLTAGE (VOLTS) 12 10 8 VGS 6 4 2 0 Q1 Q2 15 10 ID = 75 A TJ = 25C 0 4 8 5 QT 30 25 20

Ciss

0 12 16 20 24 28 32 36 40 44 48 52 Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation

Figure 8. GatetoSource Voltage vs. Total Charge

1000 tr IS, SOURCE CURRENT (AMPS)

tf 100 td(off) td(on) TJ = 25C ID = 75 A 1 2.2 4.7 6.2 9.1 VDD = 15 V VGS = 5 V 10 20

10

75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0.0

VGS = 0 V TJ = 25C

t, TIME (ns)

0.2

0.4

0.6

0.8

1.0

RG, GATE RESISTANCE ()

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance


EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 1600 1400 1200 1000 800 600 400 200 0 25 50 75 100

Figure 10. Diode Forward Voltage vs. Current

ID = 75 A

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Avalanche Energy vs. Starting Junction Temperature

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224

NTP75N03L09, NTB75N03L09 Power MOSFET 75 Amps, 30 Volts

NChannel TO220 and D2PAK


This Logic Level Vertical Power MOSFET is a general purpose part that provides the best of design available today in a low cost power package. Avalanche energy issues make this part an ideal design in. The draintosource diode has a ideal fast but soft recovery.
Features http://onsemi.com

UltraLow RDS(on), Single Base, Advanced Technology SPICE Parameters Available Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperatures High Avalanche Energy Specified ESD JEDAC Rated HBM Class 1, MM Class B, CDM Class 0 Power Supplies Inductive Loads PWM Motor Controls Replaces MTP75N03HDL and MTB75N03HDL in Many Applications

75 AMPERES 30 VOLTS RDS(on) = 9 m


NChannel D

Typical Applications

G S 4 4 1 TO220AB CASE 221A STYLE 5 2 3 2 3 D2PAK CASE 418B STYLE 2

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain 4 Drain E75 N03L09 YWW 1 Gate 3 Source

E75 N03L09 YWW 1 Gate 2 Drain 3 Source

2 Drain

N03L09 Y WW

= Device Code = Year = Work Week

ORDERING INFORMATION
Device NTP75N03L09 NTB75N03L09 NTB75N03L09T4 Package TO220 D2PAK D2PAK Shipping 50 Units/Rail 50 Units/Rail 800 Tape & Reel

Semiconductor Components Industries, LLC, 2000

225

December, 2000 Rev. 0

Publication Order Number: NTP75N03L09/D

NTP75N03L09, NTB75N03L09
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 10 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ TA = 25_C Continuous @ TA = 100_C Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 38 Vdc, VGS = 10 Vdc, L = 1 mH, IL(pk) = 55 A, VDS = 40 Vdc) Thermal Resistance JunctiontoCase JunctiontoAmbient JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds 1. When surface mounted to an FR4 board using the minimum recommended pad size. Symbol VDSS VDGB VGS VGS ID ID IDM PD Value 30 30 20 24 75 59 225 150 1.0 2.5 55 to 150 1500 Unit Vdc Vdc Vdc Vdc Adc Apk W W/_C W _C mJ

TJ and Tstg EAS

RJC RJA RJA TL

1.0 62.5 50 260

_C/W

_C

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226

NTP75N03L09, NTB75N03L09
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ. Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (Note 2.) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Negative) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 34 57 Vdc mVC Adc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (Note 2.) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 2.) (VGS = 5.0 Vdc, ID = 37.5 Adc) Static DraintoSource On Resistance (Note 2.) (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 37.5 Adc, TJ = 125C) Forward Transconductance (Notes 2. & 4.) (VDS = 3 Vdc, ID = 20 Adc) VGS(th) 1.0 RDS(on) VDS(on) gFS 0.52 0.35 58 0.68 0.50 m 7.5 9 Vdc 1.6 6 2.0 Vdc mVC m

DYNAMIC CHARACTERISTICS (Note 4.)


Input Capacitance Output Capacitance Transfer Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 4398 1160 317 5635 1894 430 pF

SWITCHING CHARACTERISTICS (Notes 3. & 4.)


TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VGS = 5.0 Vdc, ID = 75 Adc, Ad VDS = 24 Vdc) (Note 2.) (VGS = 5 5.0 0 Vd Vdc, VDD = 20 Vdc, ID = 75 Adc, RG = 4.7 ) (Note 2.) td(on) tr td(off) tf QT Q1 Q2 31 510 99 203 52 6.6 28 48 986 120 300 122 28 66 nC ns

SOURCEDRAIN DIODE CHARACTERISTICS


Forward OnVoltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) (Note 2.) (IS = 75 Ad Adc, VGS = 0 Vd Vdc dlS/dt = 100 A/s) (Note 2.) VSD 1.19 1.09 37 20 17 0.023 1.25 C Vdc

Reverse Recovery Time (N t 4 (Note 4.) ) Reverse Recovery Stored Ch Charge (Note (N t 4.) 4)

trr ta tb QRR

ns

2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. 3. Switching characteristics are independent of operating junction temperatures. 4. From characterization test data.

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227

NTP75N03L09, NTB75N03L09
150 VGS = 3.5 V ID, DRAIN CURRENT (AMPS) 135 120 105 90 75 60 45 30 15 0 0.5 1 1.5 TJ = 25C TJ = 100C 2 2.5 TJ = 55C 3 3.5 4 VDS 10 V

120 ID, DRAIN CURRENT (AMPS)

VGS = 4 V VGS = 4.5 V VGS = 5 V VGS = 6 V VGS = 8 V VGS = 10 V

90

60

VGS = 3 V

30 TJ = 25C 0 0 0.2 0.4 0.6 0.8 1 VGS = 2.5 V

1.2 1.4 1.6 1.8 2 2.2 2.4 2.6

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTO SOURCE RESISTANCE () RDS(on), DRAINTO SOURCE RESISTANCE ()

Figure 2. Transfer Characteristics

0.0085 0.008 0.0075 0.007 0.0065 0.006 0.0055 0.005 0.0045 0.004 10 20 30 40 50 60 70 80 90 100 120 ID, DRAIN CURRENT (AMPS) TJ = 55C VGS = 5 V TJ = 100C

0.009 TJ = 25C 0.008

TJ = 25C

0.007

VGS = 5 V VGS = 10 V

0.006

0.005

0.004 0 20 40 60 80 100 120 ID, DRAIN CURRENT (AMPS)

RDS(on), DRAINTO SOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance vs. Drain Current and Temperature


1.6 VGS = 10 V ID = 37.5 A 1.4 IDSS, LEAKAGE (nA) 100 1000

Figure 4. OnResistance vs. Drain Current and Gate Voltage

VGS = 0 V TJ = 125C

1.2

TJ = 100C 10

0.8

0.6 50

1 25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation Temperature

Figure 6. DraintoSource Leakage Current vs. Voltage

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228

NTP75N03L09, NTB75N03L09
1200 VGS VDS 1000 C, CAPACITANCE (pF) 800 600 400 Coss 200 Crss 0 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 22 25 GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V TJ = 25C VGS, GATETOSOURCE VOLTAGE (VOLTS) 12 10 8 VGS 6 4 2 0 Q1 Q2 15 10 ID = 75 A TJ = 25C 0 4 8 5 QT 30 25 20

Ciss

0 12 16 20 24 28 32 36 40 44 48 52 Qg, TOTAL GATE CHARGE (nC)

Figure 7. Capacitance Variation

Figure 8. GatetoSource Voltage vs. Total Charge

1000 tr IS, SOURCE CURRENT (AMPS)

tf 100 td(off) td(on) TJ = 25C ID = 75 A 1 2.2 4.7 6.2 9.1 VDD = 15 V VGS = 5 V 10 20

10

75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0.0

VGS = 0 V TJ = 25C

t, TIME (ns)

0.2

0.4

0.6

0.8

1.0

RG, GATE RESISTANCE ()

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance


EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 1600 1400 1200 1000 800 600 400 200 0 25 50 75 100

Figure 10. Diode Forward Voltage vs. Current

ID = 75 A

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Avalanche Energy vs. Starting Junction Temperature

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229

NTQD6866 Product Preview Power MOSFET 5.8 Amps, 20 Volts


NChannel TSSOP8
Features

New Low Profile TSSOP8 Package Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperatures Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones Lithium Ion Battery Applications Note Book PC

http://onsemi.com

5.8 AMPERES 20 VOLTS RDS(on) = 30 m


NChannel D NChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:

G1 S1

G2 S2

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous Drain Current Continuous @ 70C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5 Vdc, IL = 10 Apk, L = 10 mH, RG = 25 ) Thermal Resistance JunctiontoAmbient (Note 1.) Single Channel Steady State Both Channels JunctiontoAmbient (Note 2.) Both Channels Thermal Resistance JunctiontoLead Single Channel Both Channels Steady State 1. Surface Mounted to Min Pad. 2. Surface Mounted to 1 x 1 FR4 Board. Symbol VDSS VGS ID ID IDM PD TJ, Tstg EAS Value 20 "12 5.8 TBD 20 1.6 55 to +150 580 Unit Vdc Vdc Adc 8

TSSOP8 CASE 948S PLASTIC 1

W C mJ S1 G1 S2 G2

MARKING DIAGRAM & PIN ASSIGNMENT


1 2 3 4 DEVICE MARKING TBD Top View 8 7 6 5 D D D D

RqJA 180 176 100 RqJL

C/W

C/W 27 24

ORDERING INFORMATION
Device NTQD6866 NTQD6866R2 Package TSSOP8 TSSOP8 Shipping 100 Units/Rail 3000/Tape & Reel

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

230

January, 2001 Rev. 1

Publication Order Number: NTQD6866/D

NTQD6866
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Collector Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 85C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 7.0 Adc) (VGS = 4.0 Vdc, ID = 7.0 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 7.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vdc, VGS = 4.5 Vdc, ID = 5.8 5 8 Ad Adc) ) (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RL = 10, RG = 6.0 ) td(on) tr td(off) tf QT Q1 Q2 8.6 14 57 54 11 2.4 2.4 TBD TBD TBD TBD 15 nC ns (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 930 370 105 TBD TBD TBD pF VGS(th) 0.6 RDS(on) gFS TBD TBD 0.026 0.031 17 TBD 0.030 0.040 Mhos 0.9 TBD 1.2 Vdc mV/C V(BR)DSS 20 IDSS IGSS(f) IGSS(r) 1.0 25 100 100 nAdc TBD Vdc mV/C Adc Symbol Min Typ Max Unit

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 3.) Reverse Recovery Time (IS = 1.5 1 5 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%. 4. Switching characteristics are independent of operating junction temperature. (IS = 1.8 Adc, VGS = 0 Vdc) (IS = 1.8 Adc, VGS = 0 Vdc, TJ = 85C) VSD trr ta tb QRR 0.7 TBD 30 14.5 15.5 0.01 1.0 C Vdc ns

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231

NTQS6463 Product Preview Power MOSFET 6.2 Amps, 20 Volts


PChannel TSSOP8
Features

New Low Profile TSSOP8 Package Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperatures Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones Lithium Ion Battery Applications Note Book PC

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6.2 AMPERES 20 VOLTS RDS(on) = 20 m


PChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:

G S Unit Vdc 8 Adc TSSOP8 CASE 948S PLASTIC 1 Apk Adc W 463 Y WW X = Device Code = Year = Work Week = MOSFET 463 YWW X

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current TJ = 150C (Note 1.) TA = 25C TA = 70C Pulsed Drain Current (10 s Pulse Width) Continuous Source Current (Diode Conduction) (Note 1.) Maximum Power Dissipation (Note 1.) TA = 25C TA = 70C Operating Junction and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ= 25C (VDD = 50 V, IL = 16.3 Apk, L = 10 mH) Symbol VDS VGS ID 10 secs Steady State 20 "12

MARKING DIAGRAM

"7.4 "5.9 IDM IS PD 1.5 1.0 TJ, Tstg EAS "30 1.35

"6.2 "4.9

0.95

PIN ASSIGNMENT
1.05 0.67 C J D S S G 1 2 3 4 Top View 8 7 6 5 D S S D

55 to +150 1.38

1. Surface mounted to 1 x 1 FR4 board.

ORDERING INFORMATION
Device NTQS6463 NTQS6463R2 Package TSSOP8 TSSOP8 Shipping 100 Units/Rail 3000/Tape & Reel

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

232

January, 2001 Rev. 0

Publication Order Number: NTQS6463/D

NTQS6463
THERMAL RESISTANCE RATINGS
Rating Maximum JunctiontoAmbient (Note 2.) t 10 sec Steady State Maximum JunctiontoFoot Steady State Symbol RJA Typical 65 100 43 Max 83 120 C/W 52 Unit C/W

RJF

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic STATIC Gate Threshold Voltage (VDS = VGS, ID = 250 A) GateBody Leakage (VGS = 0 Vdc, VGS = 8 Vdc) Zero Gate Threshold Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 70_C) OnState Drain Current (Note 3.) (VDS = 5.0 Vdc, VGS = 4.5 Vdc) DrainSource OnState Resistance (Note 3.) (VGS = 4.5 Vdc, ID = 7.4 Adc) (VGS = 2.5 Vdc, ID = 6.3 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 7.4 Adc) (Note 3.) Diode Forward Voltage (IS = 1.3 Adc, VGS = 0 Vdc) (Note 3.) DYNAMIC (Note 4.) Total Gate Charge GateSource Charge GateDrain Charge TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time SourceDrain Reverse Recovery Time (VDS = 10 Vdc, VGS = 5.0 Vdc, ID = 7.4 7 4 Ad Adc) ) (VDD = 10 Vdc, Vdc RL = 15 , ID 1 .0 Adc, 1.0 VGEN = 4.5 Vdc, RG = 6 6.0 0 ) (IF = 1.3 Adc, di/dt = 100 A/s) Qg Qgs Qgd td(on) tr td(off) tf trr 28 4.0 9.0 19 20 95 65 45 50 50 50 120 100 80 ns ns nC VGS(th) 0.45 IGSS IDSS ID(on) 20 RDS(on) gFS VSD 0.018 0.025 21 0.71 0.020 0.027 1.1 S Vdc 1.0 10 0.9 100 nAdc dc Adc Vdc Symbol Min Typ Max Unit

2. Surface mounted to 1 x 1 FR4 board. 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Guaranteed by design, not subject to production testing.

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233

NTTD1P02R2 Product Preview Power MOSFET -1.45 Amps, -20 Volts


PChannel Enhancement Mode Dual Micro8 Package
Features http://onsemi.com

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Dual Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided

1.45 AMPERES 20 VOLTS 160 mW @ VGS = 4.5


Dual PChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 3.5 Apk, L = 5.6 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 20 "8.0 250 0.50 1.45 1.15 10 125 1.0 2.04 1.64 16 55 to +150 35 Unit V V C/W W A A A C/W W A A A C mJ G

8 1 Micro8 CASE 846A STYLE 2

MARKING DIAGRAM & PIN ASSIGNMENT


Source 1 Gate 1 Source 2 Gate 2 1 8 2 YWW 7 3 6 BC 4 5 (Top View) Drain 1 Drain 1 Drain 2 Drain 2

TL

260

1. Minimum FR4 or G10 PCB, Steady State. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Y = Year WW = Work Week BC = Device Code

ORDERING INFORMATION
Device NTTD1P02R2 Package Micro8 Shipping 4000/Tape & Reel

Semiconductor Components Industries, LLC, 2000

234

November, 2000 Rev. 0

Publication Order Number: NTTD1P02R2/D

NTTD1P02R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 8 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 1.45 Adc) (VGS = 2.7 Vdc, ID = 0.7 Adc) (VGS = 2.5 Vdc, ID = 0.7 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 0.7 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 5.) Diode Forward OnVoltage (IS = 1.45 Adc, VGS = 0 Vdc) (IS = 1.45 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 1.45 1 45 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. VSD 0.91 0.72 25 13 12 0.015 1.1 C Vdc (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 1.45 1 45 Adc) Ad ) (VDD = 1 16 6 Vdc, ID = 0 0.7 .7 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (VDD = 1 16 6 Vdc, ID = 1 1.45 .45 Adc, VGS = 4.5 Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 10 25 30 25 10 20 30 20 5.0 1.5 2.0 10 nC ns ns (VDS = 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 265 100 60 pF VGS(th) 0.7 RDS(on) gFS 0.130 0.175 0.190 2.5 0.160 0.250 Mhos 0.95 2.3 1.4 Vdc V(BR)DSS 20 IDSS IGSS IGSS 100 100 nAdc 1.0 10 nAdc 12 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

trr ta tb QRR

ns

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NTTD1P02R2
3 2.7 V 2.9 V 3.1 V 3.3 V 3.7 V 4.5 V 2 8 V 1.9 V 1 1.7 V VGS = 1.5 V 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 3 2.5 V TJ = 25C ID, DRAIN CURRENT (AMPS) 2.3 V VDS 10 V

ID, DRAIN CURRENT (AMPS)

2.1 V

TJ = 55C 1 TJ = 100C TJ = 25C

0 0 0.5 1 1.5 2 2.5 3 3.5 VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics

0.4

0.3 TJ = 25C VGS = 2.5 V 0.2 VGS = 2.7 V 0.1 VGS = 4.5 V

0.3

ID = 1.45 A TJ = 25C

0.2

0.1

0 0 2 4 6 8 10 12 VGS, GATETOSOURCE VOLTAGE (VOLTS)

0 0 0.5 1 1.5 2 2.5 3 3.5 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage

Figure 4. OnResistance versus Drain Current and Gate Voltage

1.6 RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) ID = 1.45 A VGS = 4.5 V

100 VGS = 0 V IDSS, LEAKAGE (nA) TJ = 125C

1.4

1.2

10

TJ = 100C

0.8

0.6 50

1 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 4 8 12 16 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 20

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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NTTD1P02R2
800 Ciss C, CAPACITANCE (pF) 600 Crss 400 Ciss 200 Coss 0 10 5 0 VGS VDS 5 10 15 Crss 20 VDS = 0 V VGS = 0 V TJ = 25C 5 QT 4 VGS Q1 2 ID = 1.45 A TJ = 25C Q2 20 18 16 14 12 10 8 6 1 0 0 1 2 3 4 5 6 Qg, TOTAL GATE CHARGE (nC) VDS 4 2 0 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 1 VGS, GATETOSOURCE VOLTAGE (VOLTS)

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

Figure 7. Capacitance Variation


100 IS, SOURCE CURRENT (AMPS) VDD = 16 V ID = 1.45 A VGS = 4.5 V t, TIME (ns) 1.6 VGS = 0 V TJ = 25C

1.2

10

tr td (off) tf td (on)

0.8

0.4

1 1 10 RG, GATE RESISTANCE (OHMS) 100

0 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation versus Gate Resistance


100 ID , DRAIN CURRENT (AMPS)

Figure 10. Diode Forward Voltage versus Current

VGS = 8 V SINGLE PULSE TC = 25C 100 ms 1 ms IS

di/dt

10

1 10 ms tp 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10

ta

trr tb TIME 0.25 IS IS

dc 100

0.01

Figure 12. Diode Reverse Recovery Waveform

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

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NTTD1P02R2
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (C/W)

100

D = 0.5 0.2 0.1 0.05 0.02 0.01

10

P(pk)

1 SINGLE PULSE 0.1 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s)

t2 DUTY CYCLE, D = t1/t2 1.0E+00

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

Figure 13. Thermal Response

INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65 inches mm

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238

NTTD1P02R2
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows
STEP 1 PREHEAT ZONE 1 RAMP 200C STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 4 HEATING ZONES 3 & 6 SOAK STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 14. Typical Solder Heating Profile

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NTTD1P02R2
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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240

NTTD2P02R2 Power MOSFET -2.4 Amps, -20 Volts


Dual PChannel Micro8
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided

http://onsemi.com

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 5.0 Apk, L = 28 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 20 "8.0 160 0.78 2.4 1.92 20 88 1.42 3.25 2.6 30 55 to +150 350 Unit V V C/W W A A A C/W W A A A C mJ 8

2.4 AMPERES 20 VOLTS RDS(on) = 90 mW


PChannel D

G S

MARKING DIAGRAM

1 Micro8 CASE 846A STYLE 2

YWW BE

Y WW BE TL 260 C Source 1 Gate 1 Source 2 Gate 2

= Year = Work Week = Device Code

PIN ASSIGNMENT
1 2 3 4 8 7 6 5 Drain 1 Drain 1 Drain 2 Drain 2

1. Minimum FR4 or G10 PCB, Steady State. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Pulse Test: Pulse Width  300 ms, Duty Cycle  2%.

Top View

ORDERING INFORMATION
Device NTTD2P02R2 Package Micro8 Shipping 4000/Tape & Reel

Semiconductor Components Industries, LLC, 2000

241

December, 2000 Rev. 0

Publication Order Number: NTTD2P02R2/D

NTTD2P02R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 16 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 16 Vdc, TJ = 125C) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 25C) GateBody Leakage Current (VGS = 8 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 2.4 Adc) (VGS = 2.7 Vdc, ID = 1.2 Adc) (VGS = 2.5 Vdc, ID = 1.2 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 1.2 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 5.) Diode Forward OnVoltage Reverse Recovery Time (IS = 2.4 2 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. (IS = 2.4 Adc, VGS = 0 Vdc) (IS = 2.4 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.88 0.75 37 16 21 0.025 1.0 C Vdc ns (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 2.4 2 4 Ad Adc) ) (VDD = 1 10 0 Vdc, ID = 1 1.2 .2 Adc, VGS = 2.7 Vdc, RG = 6.0 ) (VDD = 1 10 0 Vdc, ID = 2 2.4 .4 Adc, VGS = 4.5 Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 10 31 33 29 15 40 35 35 10 1.5 5.0 18 nC ns ns (VDS = 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 550 200 100 pF VGS(th) 0.5 RDS(on) gFS 2.0 0.070 0.100 0.110 4.2 0.090 0.130 Mhos 0.90 2.5 1.4 Vdc mV/C V(BR)DSS 20 IDSS IDSS IGSS IGSS 100 100 nAdc 5.0 nAdc 1.0 25 Adc 12.7 Vdc mV/C Adc Symbol Min Typ Max Unit

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NTTD2P02R2
4 VGS = 2.1 V ID, DRAIN CURRENT (AMPS) 3 VGS = 10 V VGS = 4.5 V VGS = 2.5 V ID, DRAIN CURRENT (AMPS) TJ = 25C 5 VDS > = 10 V 4

VGS = 1.9 V

3 TJ = 25C

2 VGS = 1.7 V 1 VGS = 1.5 V 0 0 2 4 6 8 10 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1 0 1

TJ = 100C 1.5

TJ = 55C 2 2.5 3

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics.


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics.

0.2

TJ = 25C

0.12

TJ = 25C

0.15

0.1 VGS = 2.7 V 0.08 VGS = 4.5 V 0.06

0.1

0.05

0 2 4 6 8 VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.04 1 1.5 2 2.5 3 3.5 4 4.5 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GatetoSource Voltage.


RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 4. OnResistance vs. Drain Current and Gate Voltage.

1.6 ID = 2.4 A VGS = 4.5 V

1000 VGS = 0 V IDSS, LEAKAGE (nA) 100 TJ = 100C 10 TJ = 25C 1 TJ = 125C

1.4

1.2

0.8

0.1

0.6 50

0.01 25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 0 4 8 12 16 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 20

Figure 5. OnResistance Variation with Temperature.

Figure 6. DraintoSource Leakage Current vs. Voltage.

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NTTD2P02R2
1500 VDS = 0 V C, CAPACITANCE (pF) 1200 Ciss VGS = 0 V TJ = 25C 5 QT 4 20 18 16 14 3 Q1 2 ID = 2.4 A TJ = 25C Q2 VGS 12 10 8 6 1 0 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) VDS 4 2 0 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS)

900 Crss 600 Ciss

300

Coss Crss 10 5 0 VGS VDS 5 10 15 20

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

Figure 7. Capacitance Variation


1000 VDD = 10 V ID = 1.2 A VGS = 2.7 V t, TIME (ns) t, TIME (ns) 100

td (off) tr tf

100 tr td (off) td (on) 10 1.0 10 RG, GATE RESISTANCE (OHMS) 100 tf

10

td (on)

VDD = 10 V ID = 2.4 A VGS = 4.5 V 1.0 1.0 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance


2 IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C

Figure 10. Resistive Switching Time Variation versus Gate Resistance

1.6

di/dt IS

1.2

ta

trr tb TIME

0.8 tp 0.4 0 0.4 IS 0.25 IS

0.5

0.6

0.7

0.8

0.9

Figure 12. Diode Reverse Recovery Waveform

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current http://onsemi.com


244

NTTD2P02R2
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE

D = 0.5

0.2 Normalized to Rja at Steady State (1 inch pad) 0.0125 0.0563 0.110 0.273 0.113 0.436

0.1

0.1

0.05 0.02 0.01 0.021 F 0.137 F 1.15 F 2.93 F 152 F 261 F

Single Pulse 0.01 1E03

1E02

1E01

1E+00 t, TIME (s)

1E+03

1E+02

1E+03

Figure 13. FET Thermal Response.

INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65 inches mm

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245

NTTD2P02R2
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 14. Typical Solder Heating Profile

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NTTD2P02R2
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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247

NTTS2P02R2 Power MOSFET -2.4 Amps, -20 Volts


Single PChannel Micro8t
Features

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided

http://onsemi.com

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 3.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 4.5 Vdc, Peak IL = 5.0 Apk, L = 28 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol VDSS VGS RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg EAS Value 20 8.0 160 0.78 2.4 1.92 20 88 1.42 3.25 2.6 30 55 to +150 350 Unit V V C/W W A A A C/W W A A A C mJ 8

2.4 AMPERES 20 VOLTS RDS(on) = 90 mW


Single PChannel D

G S

MARKING DIAGRAM

1 Micro8 CASE 846A STYLE 1

YWW AD

Y WW AD TL 260 C Source Source Source Gate

= Year = Work Week = Device Code

PIN ASSIGNMENT
1 2 3 4 8 7 6 5 Drain Drain Drain Drain

1. Minimum FR4 or G10 PCB, Steady State. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.

Top View

ORDERING INFORMATION
Device NTTS2P02R2 Package Micro8 Shipping 4000/Tape & Reel

Semiconductor Components Industries, LLC, 2000

248

December, 2000 Rev. 4

Publication Order Number: NTTS2P02R2/D

NTTS2P02R2
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 16 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 16 Vdc, TJ = 125C) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc, TJ = 25C) GateBody Leakage Current (VGS = 8 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +8 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 4.5 Vdc, ID = 2.4 Adc) (VGS = 2.7 Vdc, ID = 1.2 Adc) (VGS = 2.5 Vdc, ID = 1.2 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 1.2 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 5. & 6.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 5.) Diode Forward OnVoltage Reverse Recovery Time (IS = 2.4 2 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 4. Handling precautions to protect against electrostatic discharge is mandatory. 5. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 6. Switching characteristics are independent of operating junction temperature. (IS = 2.4 Adc, VGS = 0 Vdc) (IS = 2.4 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.88 0.75 37 16 21 0.025 1.0 C Vdc ns (VDS = 16 Vdc, VGS = 4.5 Vdc, ID = 2.4 2 4 Ad Adc) ) (VDD = 1 10 0 Vdc, ID = 1 1.2 .2 Adc, VGS = 2.7 Vdc, RG = 6.0 ) (VDD = 1 10 0 Vdc, ID = 2 2.4 .4 Adc, VGS = 4.5 Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 10 31 33 29 15 40 35 35 10 1.5 5.0 18 nC ns ns (VDS = 16 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 550 200 100 pF VGS(th) 0.5 RDS(on) gFS 2.0 0.070 0.100 0.110 4.2 0.090 0.130 Mhos 0.90 2.5 1.4 Vdc mV/C V(BR)DSS 20 IDSS IDSS IGSS IGSS 100 100 nAdc 5.0 nAdc 1.0 25 Adc 12.7 Vdc mV/C Adc Symbol Min Typ Max Unit

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NTTS2P02R2
4 VGS = 2.1 V ID, DRAIN CURRENT (AMPS) 3 VGS = 10 V VGS = 4.5 V VGS = 2.5 V ID, DRAIN CURRENT (AMPS) TJ = 25C 5 VDS > = 10 V 4

VGS = 1.9 V

3 TJ = 25C

2 VGS = 1.7 V 1 VGS = 1.5 V 0 0 2 4 6 8 10 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

1 0 1

TJ = 100C 1.5

TJ = 55C 2 2.5 3

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics.


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics.

0.2

TJ = 25C

0.12

TJ = 25C

0.15

0.1 VGS = 2.7 V 0.08 VGS = 4.5 V 0.06

0.1

0.05

0 2 4 6 8 VGS, GATETOSOURCE VOLTAGE (VOLTS)

0.04 1 1.5 2 2.5 3 3.5 4 4.5 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance vs. GatetoSource Voltage.


RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

Figure 4. OnResistance vs. Drain Current and Gate Voltage.

1.6 ID = 2.4 A VGS = 4.5 V

1000 VGS = 0 V IDSS, LEAKAGE (nA) 100 TJ = 100C 10 TJ = 25C 1 TJ = 125C

1.4

1.2

0.8

0.1

0.6 50

0.01 25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 0 4 8 12 16 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 20

Figure 5. OnResistance Variation with Temperature.

Figure 6. DraintoSource Leakage Current vs. Voltage.

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NTTS2P02R2
1500 VDS = 0 V C, CAPACITANCE (pF) 1200 Ciss VGS = 0 V TJ = 25C 5 QT 4 20 18 16 14 3 Q1 2 ID = 2.4 A TJ = 25C Q2 VGS 12 10 8 6 1 0 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) VDS 4 2 0 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS)

900 Crss 600 Ciss

300

Coss Crss 10 5 0 VGS VDS 5 10 15 20

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

Figure 7. Capacitance Variation


1000 VDD = 10 V ID = 1.2 A VGS = 2.7 V t, TIME (ns) t, TIME (ns) 100

td (off) tr tf

100 tr td (off) td (on) 10 1.0 10 RG, GATE RESISTANCE (OHMS) 100 tf

10

td (on)

VDD = 10 V ID = 2.4 A VGS = 4.5 V 1.0 1.0 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance


2 IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C

Figure 10. Resistive Switching Time Variation versus Gate Resistance

1.6

di/dt IS

1.2

ta

trr tb TIME

0.8 tp 0.4 0 0.4 IS 0.25 IS

0.5

0.6

0.7

0.8

0.9

Figure 12. Diode Reverse Recovery Waveform

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 11. Diode Forward Voltage versus Current http://onsemi.com


251

NTTS2P02R2
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE

D = 0.5

0.2 Normalized to Rja at Steady State (1 inch pad) 0.0125 0.0563 0.110 0.273 0.113 0.436

0.1

0.1

0.05 0.02 0.01 0.021 F 0.137 F 1.15 F 2.93 F 152 F 261 F

Single Pulse 0.01 1E03

1E02

1E01

1E+00 t, TIME (s)

1E+03

1E+02

1E+03

Figure 13. FET Thermal Response.

INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65 inches mm

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252

NTTS2P02R2
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 14. Typical Solder Heating Profile

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NTTS2P02R2
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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254

NTTS2P03R2 Product Preview Power MOSFET -2.48 Amps, -30 Volts


PChannel Enhancement Mode Single Micro8t Package
Features http://onsemi.com

Ultra Low RDS(on) Higher Efficiency Extending Battery Life Miniature Micro8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Micro8 Mounting Information Provided

2.48 AMPERES 30 VOLTS 85 mW @ VGS = 10 V


Single PChannel D

Applications

Power Management in Portable and BatteryPowered Products, i.e.:


Cellular and Cordless Telephones and PCMCIA Cards
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Thermal Resistance JunctiontoAmbient (Note 1.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Thermal Resistance JunctiontoAmbient (Note 2.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Thermal Resistance JunctiontoAmbient (Note 3.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 5.) Thermal Resistance JunctiontoAmbient (Note 4.) Total Power Dissipation @ TA = 25C Continuous Drain Current @ TA = 25C Continuous Drain Current @ TA = 70C Pulsed Drain Current (Note 5.) Operating and Storage Temperature Range Symbol VDSS VGS RJA PD ID ID RJA PD ID ID RJA PD ID ID IDM RJA PD ID ID IDM TJ, Tstg Value 30 "20 160 0.78 2.48 1.98 70 1.78 3.75 3.0 210 0.60 2.10 1.67 17 100 1.25 3.02 2.42 24 55 to +150 Unit V V C/W W A A C/W W A A C/W W A A A C/W W A A A C G

8 1 Micro8 CASE 846A STYLE 1

MARKING DIAGRAM & PIN ASSIGNMENT


Source Source Source Gate 1 2 YWW 3 AE 4 8 7 6 5 Drain Drain Drain Drain

(Top View) Y = Year WW = Work Week AE = Device Code

1. Minimum FR4 or G10 PCB, Time 10 Seconds. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Time 10 Seconds. 3. Minimum FR4 or G10 PCB, Steady State. 4. Mounted onto a 2 square FR4 Board (1 sq. 2 oz Cu 0.06 thick single sided), Steady State. 5. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

ORDERING INFORMATION
Device NTTS2P03R2 Package Micro8 Shipping 4000/Tape & Reel

Semiconductor Components Industries, LLC, 2001

255

February, 2001 Rev. 0

Publication Order Number: NTTS2P03R2/D

NTTS2P03R2
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (continued)
Rating Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 65 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes for 10 seconds Symbol EAS TL Symbol Min Typ Value 292.5 260 Unit mJ C

ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 6.)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 30 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) GateBody Leakage Current (VGS = +20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnState Resistance (VGS = 10 Vdc, ID = 2.48 Adc) (VGS = 4.5 Vdc, ID = 1.24 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 1.24 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 7. & 8.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge BODYDRAIN DIODE RATINGS (Note 7.) Diode Forward OnVoltage (IS = 2.48 Adc, VGS = 0 Vdc) (IS = 2.48 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 1.45 1 45 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 6. Handling precautions to protect against electrostatic discharge is mandatory. 7. Indicates Pulse Test: Pulse Width = 300 sec max, Duty Cycle = 2%. 8. Switching characteristics are independent of operating junction temperature. VSD 0.92 0.72 38 20 18 0.04 1.3 C Vdc (VDS = 24 Vdc, VGS = 4.5 Vdc, 2 48 Adc) Ad ) ID = 2.48 (VDD = 2 24 4 Vdc, ID = 1 1.24 .24 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (VDD = 2 24 4 Vdc, ID = 2 2.48 .48 Adc, VGS = 10 Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf Qtot Qgs Qgd 10 20 40 35 16 40 30 30 15 3.2 4.0 22 nC ns ns (VDS = 24 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Ciss Coss Crss 500 160 65 pF VGS(th) RDS(on) gFS 0.063 0.100 3.1 0.085 0.135 Mhos 1.0 1.7 3.6 3.0 Vdc V(BR)DSS IDSS IGSS IGSS 1.0 25 100 100 nAdc nAdc 30 30 Vdc mV/C Adc Max Unit

Reverse Recovery Time

trr ta tb QRR

ns

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NTTS2P03R2
3 ID, DRAIN CURRENT (AMPS) 10 V 5 3.5 V ID, DRAIN CURRENT (AMPS) 3.3 V 3.7 V 3.9 V 2 4.1 V 4.5 V 4.9 V 6 V TJ = 25C 3.1 V VDS 10 V 4

3 TJ = 25C 2 TJ = 100C TJ = 55C 0 1 2 3 4 5

2.9 V

2.7 V 2.5 V VGS = 2.3 V

0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on), DRAINTOSOURCE RESISTANCE (W) RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 2. Transfer Characteristics

0.3 0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8 10 VGS, GATETOSOURCE VOLTAGE (VOLTS) ID = 2.48 A TJ = 25C

0.15

TJ = 25C

0.1

VGS = 4.5 V

VGS = 10 V 0.05

0 0.5 1.5 2.5 3.5 4.5 5.5 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)

1.6 ID = 2.48 A VGS = 10 V

10,000 VGS = 0 V IDSS, LEAKAGE (nA)

1.4

1000

TJ = 150C

1.2

100 TJ = 100C 10

0.8

0.6 50

1 25 0 25 75 50 100 125 TJ, JUNCTION TEMPERATURE (C) 150 5 10 15 20 25 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 30

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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NTTS2P03R2
6 5 QT 4 Q1 3 2 1 VDS 0 0 2 4 6 8 10 12 14 16 Qg, TOTAL GATE CHARGE (nC) ID = 2.48 A TJ = 25C Q2 VGS 20 15 10 5 0 30 25 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 1 VGS, GATETOSOURCE VOLTAGE (VOLTS)

1200 C, CAPACITANCE (pF) 1000 800

VDS = 0 V Ciss

VGS = 0 V TJ = 25C

Crss 600 400 200 0 10 Coss Crss 5 0 VGS VDS GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS) 5 10 15 20 25 30 Ciss

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

Figure 7. Capacitance Variation


100 IS, SOURCE CURRENT (AMPS) 3 2.5 2 1.5 1 0.5 0 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCETODRAIN VOLTAGE (VOLTS) VGS = 0 V TJ = 25C

td (off) t, TIME (ns) tf 10 tr td (on)

VDD = 24 V ID = 2.48 A VGS = 10 V 1 1 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Diode Forward Voltage versus Current

100 ID , DRAIN CURRENT (AMPS) VGS = 30 V SINGLE PULSE TC = 25C 1 ms 10 ms 1 tp 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 dc IS 0.25 IS di/dt IS ta trr tb TIME

10

0.01

100

Figure 12. Diode Reverse Recovery Waveform

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com
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NTTS2P03R2
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (C/W)

100

D = 0.5 0.2 0.1 0.05 0.02 0.01

10

P(pk)

1 SINGLE PULSE 0.1 1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 t, TIME (s)

t2 DUTY CYCLE, D = t1/t2 1.0E+00

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

Figure 13. Thermal Response

INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65 inches mm

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259

NTTS2P03R2
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 14. Typical Solder Heating Profile

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260

NTTS2P03R2
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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261

NTUD01N02 Product Preview Power MOSFET 100 mAmps, 20 Volts


Dual NChannel SC88

2.5 V Gate Drive with Low OnResistance Low Threshold Voltage: Vth = 0.5 to 1.5 V, Ideal for Portable High Speed Enhancement Mode Small Package Easily Designed Drive Circuits
http://onsemi.com

100 mAMPS 20 VOLTS RDS(on) = 10 W


NChannel D

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Total Power Dissipation @ TA = 25C Channel Temperature Operating and Storage Temperature Range Symbol VDS VGSS ID PD Tch Tstg Value 20 10 100 150 150 55 to 150 mW C C 4 Unit Vdc Vdc mAdc G

MARKING DIAGRAM
5

2 3

SC88/SOT363 CASE 419B STYLE 1

N02 D

N02 D

= Device Code = Date Code

PIN ASSIGNMENT
Source1 Gate1 Drain2 2 3 1 6 5 4 Drain1 Gate2 Source2

Top View

ORDERING INFORMATION
Device NTUD01N02 Package SC88 Shipping 3000 Tape & Reel

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2001

262

January, 2001 Rev. 0

Publication Order Number: NTUD01N02/D

NTUD01N02
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 100 A) Drain Cutoff Current (VDS = 20 Vdc, VGS = 0 Vdc) GateBody Leakage Current (VGS = 10 Vdc, VDS = 0) ON CHARACTERISTICS Gate Threshold Voltage (VDS = 3.0 Vdc, ID = 0.1 mAdc) DraintoSource OnResistance (VGS = 2.5 Vdc, ID = 10 mAdc) Forward Transfer Admittance (VDS = 3.0 Vdc, ID = 10 mAdc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time TurnOff Delay Time (VDD = 3.0 Vdc, ID = 10 mAdc, VGS = 0 to 2.5 Vdc) ton toff 0.14 0.14 s (VDS = 3.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) (VDS = 3.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) (VDS = 3.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss 5.5 25 1.6 pF Vth 0.5 RDS(on) YFS 20 5.0 10 mS 1.5 Vdc V(BR)DSS IDSS IGSS 1.0 1.0 Adc 20 Vdc Adc Symbol Min Typ Max Unit

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263

2N7000
Preferred Device

Small Signal MOSFET 200 mAmps, 60 Volts


NChannel TO92
MAXIMUM RATINGS
Rating Drain Source Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Nonrepetitive (tp 50 s) Drain Current Continuous Pulsed Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg Value 60 60 20 40 200 500 350 2.8 55 to +150 mW mW/C C G S Unit Vdc Vdc Vdc Vpk mAdc

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200 mAMPS 60 VOLTS RDS(on) = 5


NChannel D

THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds Symbol RJA TL Max 357 300 Unit C/W C TO92 CASE 29 Style 22 12

MARKING DIAGRAM & PIN ASSIGNMENT


2N7000 YWW

1 Source 2 Gate Y WW

3 Drain

= Year = Work Week

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 266 of this data sheet. Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

264

November, 2000 Rev. 5

Publication Order Number: 2N7000/D

2N7000
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 10 Adc) Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0) (VDS = 48 Vdc, VGS = 0, TJ = 125C) GateBody Leakage Current, Forward (VGSF = 15 Vdc, VDS = 0) V(BR)DSS IDSS IGSSF 1.0 1.0 10 60 Vdc

Adc mAdc nAdc

ON CHARACTERISTICS (Note 1.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc) (VGS = 4.5 Vdc, ID = 75 mAdc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 0.5 Adc) (VGS = 4.5 Vdc, ID = 75 mAdc) OnState Drain Current (VGS = 4.5 Vdc, VDS = 10 Vdc) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) VGS(th) rDS(on) VDS(on) Id(on) gfs 75 100 2.5 0.45 mAdc mhos 5.0 6.0 Vdc 0.8 3.0 Vdc Ohm

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 V, ( , VGS = 0, , f=1 1.0 0 MH MHz) ) Ciss Coss Crss 60 25 5.0 pF

SWITCHING CHARACTERISTICS (Note 1.)


TurnOn Delay Time TurnOff Delay Time (VDD = 15 V, ID = 500 mA, RG = 25 W, RL = 30 W, Vgen = 10 V) ton toff 10 10 ns

1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.

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265

2N7000
2.0 1.8 I D, DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN SOURCE VOLTAGE (VOLTS) TA = 25C I D, DRAIN CURRENT (AMPS) VGS = 10 V 9V 8V 7V 6V 5V 4V 3V 9.0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, GATE SOURCE VOLTAGE (VOLTS) 9.0 10 0.8 0.6 0.4 0.2 1.0 VDS = 10 V -55C 125C 25C

Figure 1. Ohmic Region

Figure 2. Transfer Characteristics

r DS(on) , STATIC DRAIN-SOURCE ON-RESISTANCE (NORMALIZED)

2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VGS = 10 V ID = 200 mA

VGS(th) , THRESHOLD VOLTAGE (NORMALIZED)

2.4

1.2 1.05 1.1 1.10 1.0 0.95 0.9 0.85 0.8 0.75 0.7 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VDS = VGS ID = 1.0 mA

Figure 3. Temperature versus Static DrainSource OnResistance

Figure 4. Temperature versus Gate Threshold Voltage

ORDERING INFORMATION
Device
2N7000 2N7000RLRA 2N7000RLRM 2N7000RLRP 2N7000ZL1

Package
TO92 TO92 TO92 TO92 TO92

Shipping
1000 Unit/Box 2000 Tape & Reel 2000 Ammo Pack 2000 Ammo Pack 2000 Ammo Pack

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266

2N7002LT1
Preferred Device

Small Signal MOSFET 115 mAmps, 60 Volts


NChannel SOT23
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) Drain Current Continuous TC = 25C (Note 1.) Continuous TC = 100C (Note 1.) Pulsed (Note 2.) GateSource Voltage Continuous Nonrepetitive (tp 50 s) Symbol VDSS VDGR ID ID IDM Value 60 60 115 75 800 Unit Vdc Vdc mAdc

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115 mAMPS 60 VOLTS RDS(on) = 7.5 W


NChannel 3

VGS VGSM

20 40

Vdc Vpk 1

THERMAL CHARACTERISTICS
Characteristic Total Device Dissipation FR5 Board (Note 3.) TA = 25C Derate above 25C Thermal Resistance, Junction to Ambient Total Device Dissipation Alumina Substrate,(Note 4.) TA = 25C Derate above 25C Thermal Resistance, Junction to Ambient Junction and Storage Temperature Symbol PD Max 225 1.8 556 300 2.4 RJA TJ, Tstg 417 55 to +150 C/W C Unit mW mW/C C/W mW mW/C

2
3

RJA PD

1 2

SOT23 CASE 318 STYLE 21

1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 3. FR5 = 1.0 x 0.75 x 0.062 in. 4. Alumina = 0.4 x 0.3 x 0.025 in 99.5% alumina.

MARKING DIAGRAM & PIN ASSIGNMENT


Drain
3

702 W
1 2

Gate 702 W

Source = Device Code = Work Week

ORDERING INFORMATION
Device 2N7002LT1 2N7002LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

267

December, 2000 Rev. 4

Publication Order Number: 2N7002LT1/D

2N7002LT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 10 Adc) Zero Gate Voltage Drain Current (VGS = 0, VDS = 60 Vdc) GateBody Leakage Current, Forward (VGS = 20 Vdc) GateBody Leakage Current, Reverse (VGS = 20 Vdc) TJ = 25C TJ = 125C V(BR)DSS IDSS IGSSF IGSSR 60 1.0 500 100 100 Vdc Adc nAdc nAdc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) OnState Drain Current (VDS 2.0 VDS(on), VGS = 10 Vdc) Static DrainSource OnState Voltage (VGS = 10 Vdc, ID = 500 mAdc) (VGS = 5.0 Vdc, ID = 50 mAdc) Static DrainSource OnState Resistance (VGS = 10 V, ID = 500 mAdc) TC = 25C TC = 125C (VGS = 5.0 Vdc, ID = 50 mAdc) TC = 25C TC = 125C Forward Transconductance (VDS 2.0 VDS(on), ID = 200 mAdc) VGS(th) ID(on) VDS(on) rDS(on) gFS 80 7.5 13.5 7.5 13.5 mmhos 3.75 0.375 Ohms 1.0 500 2.5 Vdc mA Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Ciss Coss Crss 50 25 5.0 pF pF pF

SWITCHING CHARACTERISTICS (Note 2.)


TurnOn Delay Time TurnOff Delay Time (VDD = 25 Vdc, ID ^ 500 mAdc, RG = 25 , RL = 50 , Vgen = 10 V) td(on) td(off) 20 40 ns ns

BODYDRAIN DIODE RATINGS


Diode Forward OnVoltage (IS = 11.5 mAdc, VGS = 0 V) Source Current Continuous (Body Diode) Source Current Pulsed 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. VSD IS ISM 1.5 115 800 Vdc mAdc mAdc

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268

2N7002LT1
TYPICAL ELECTRICAL CHARACTERISTICS
2.0 1.8 I D, DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN SOURCE VOLTAGE (VOLTS) TA = 25C I D, DRAIN CURRENT (AMPS) VGS = 10 V 9V 8V 7V 6V 5V 4V 3V 9.0 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, GATE SOURCE VOLTAGE (VOLTS) 9.0 10 0.8 0.6 0.4 0.2 1.0 VDS = 10 V -55C 125C 25C

Figure 1. Ohmic Region

Figure 2. Transfer Characteristics

r DS(on) , STATIC DRAIN-SOURCE ON-RESISTANCE (NORMALIZED)

2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VGS = 10 V ID = 200 mA

VGS(th) , THRESHOLD VOLTAGE (NORMALIZED)

2.4

1.2 1.05 1.1 1.10 1.0 0.95 0.9 0.85 0.8 0.75 0.7 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VDS = VGS ID = 1.0 mA

Figure 3. Temperature versus Static DrainSource OnResistance

Figure 4. Temperature versus Gate Threshold Voltage

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269

2N7002LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150C 25C 556C/W = 225 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 556C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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270

BS107, BS107A
Preferred Device

Small Signal MOSFET 250 mAmps, 200 Volts


NChannel TO92
MAXIMUM RATINGS
Rating DrainSource Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 s) Drain Current Continuous (Note 1.) Pulsed (Note 2.) Total Device Dissipation @ TA = 25C Derate above 25C Operating and Storage Junction Temperature Range Symbol VDS VGS VGSM ID IDM PD TJ, Tstg Value 200 20 30 250 500 350 55 to 150 mW C Unit Vdc Vdc Vpk mAdc NChannel D

http://onsemi.com

250 mAMPS 200 VOLTS RDS(on) = 14 (BS107) RDS(on) = 6.4 (BS107A)

G S

1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%.

TO92 CASE 29 Style 30 12

MARKING DIAGRAM & PIN ASSIGNMENT


BS107 YWW

1 Drain 2 Gate Y WW

3 Source

= Year = Work Week

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 274 of this data sheet. Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

271

November, 2000 Rev. 2

Publication Order Number: BS107/D

BS107, BS107A
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
ZeroGateVoltage Drain Current (VDS = 130 Vdc, VGS = 0) DrainSource Breakdown Voltage (VGS = 0, ID = 100 Adc) Gate Reverse Current (VGS = 15 Vdc, VDS = 0) IDSS V(BR)DSX IGSS VGS(Th) rDS(on) 4.5 4.8 28 14 6.0 6.4 200 0.01 30 10 nAdc Vdc nAdc

ON CHARACTERISTICS (Note 3.)


Gate Threshold Voltage (ID = 1.0 mAdc, VDS = VGS) Static DrainSource On Resistance BS107 (VGS = 2.6 Vdc, ID = 20 mAdc) (VGS = 10 Vdc, ID = 200 mAdc) BS107A (VGS = 10 Vdc) (ID = 100 mAdc) (ID = 250 mAdc) 1.0 3.0 Vdc Ohms

SMALLSIGNAL CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Forward Transconductance (VDS = 25 Vdc, ID = 250 mAdc) Ciss Crss Coss gfs 200 60 6.0 30 400 pF pF pF mmhos

SWITCHING CHARACTERISTICS
TurnOn Time TurnOff Time 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. ton toff 6.0 12 15 15 ns ns

RESISTIVE SWITCHING
+25 V 23 PULSE GENERATOR 50 Vin 40 pF 1M 20 dB 50 ATTENUATOR TO SAMPLING SCOPE 50 INPUT Vout ton 90% toff 90% 10% 90% 50% 10% PULSE WIDTH 50%

50

OUTPUT Vout INVERTED 10 V INPUT Vin

Figure 1. Switching Test Circuit

Figure 2. Switching Waveforms

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272

BS107, BS107A
10 VDS , DRAIN-SOURCE VOLTAGE (VOLTS) 5.0 2.0 1.0 0.5 0.2 0.1 -55 -35 85 105 -15 +5.0 25 65 45 TJ, JUNCTION TEMPERATURE (C) 125 145 100 mA 200 180 160 C, CAPACITANCE (pF) VGS = 10 V 250 mA 140 120 100 80 60 40 20 0 0 Crss Coss 40 10 20 30 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 50 Ciss VGS = 0 V

Figure 3. On Voltage versus Temperature

Figure 4. Capacitance Variation

0.8 ID(on) , DRAIN CURRENT (AMPS) VGS = 10 V I D(on) , DRAIN CURRENT (AMPS) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1.0 5.0 6.0 7.0 8.0 2.0 3.0 4.0 VGS, GATE-SOURCE VOLTAGE (VOLTS) 9.0 10

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.0

10 V

5.0 V

4.0 V

3.0 V 10 4.0 6.0 8.0 12 14 16 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 18 20

Figure 5. Transfer Characteristic


0.7 ID(on), DRAIN CURRENT (AMPS) 0.6 0.5 0.4 0.3 0.2 0.1 1.0 2.0 3.0

Figure 6. Output Characteristic

10 V 5.0 V

4.0 V

3.0 V 4.0 5.0

VDS, DRAIN-SOURCE VOLTAGE (VOLTS)

Figure 7. Saturation Characteristic

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273

BS107, BS107A
ORDERING INFORMATION
Device
BS107 BS107RLRA BS107RL1 BS107A BS107ARLRM BS107ARLRP BS107ARL1

Package
TO92 TO92 TO92 TO92 TO92 TO92 TO92

Shipping
1000 Unit/Box 2000 Tape & Reel 2000 Tape & Reel 1000 Units/Box 2000 Ammo Pack 2000 Ammo Pack 2000 Tape & Reel

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274

BS108
Preferred Device

Small Signal MOSFET 250 mAmps, 200 Volts, Logic Level


NChannel TO92
http://onsemi.com

This MOSFET is designed for high voltage, high speed switching applications such as line drivers, relay drivers, CMOS logic, microprocessor or TTL to high voltage interface and high voltage display drivers. Low Drive Requirement, VGS = 3.0 V max Inherent Current Sharing Capability Permits Easy Paralleling of many Devices
MAXIMUM RATINGS
Rating DrainSource Voltage GateSource Voltage Drain Current Continuous (Note 1.) Pulsed (Note 2.) Total Power Dissipation @ TA = 25C Derate above TA = 25C Operating and Storage Temperature Range Symbol VDSS VGS ID IDM PD 350 6.4 TJ, Tstg 55 to +150 mW mW/C C 12 Value 200 20 250 500 Unit Vdc Vdc mAdc

250 mAMPS 200 VOLTS RDS(on) = 8


NChannel D

G S

TO92 CASE 29 Style 30

1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%.

MARKING DIAGRAM & PIN ASSIGNMENT


BS108 YWW

1 Drain 2 Gate

3 Source

BS108 = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device BS108 BS108ZL1 Package TO92 TO92 Shipping 1000 Units/Box 2000 Ammo Pack

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

275

November, 2000 Rev. 1

Publication Order Number: BS108/D

BS108
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0, ID = 10 A) Zero Gate Voltage Drain Current (VDSS = 130 Vdc, VGS = 0) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (ID = 1.0 mA, VDS = VGS) Static DraintoSource OnResistance (VGS = 2.0 Vdc, ID = 50 mA) (VGS = 2.8 Vdc, ID = 100 mA) Drain Cutoff Current (VGS = 0.2 V, VDS = 70 V) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) SWITCHING CHARACTERISTICS TurnOn Time (See Figure 1) TurnOff Time (See Figure 1) 3. Pulse Test: Pulse Width 300 s, Duty Cycle = 2.0%. td(on) td(off) 15 15 ns ns Ciss Coss Crss 10 30 pF 150 pF pF VGS(th) 0.5 rDS(on) IDSX 25 10 8.0 mA 1.5 Ohms Vdc V(BR)DS 200 IDSS IGSSF 10 30 nAdc Vdc nAdc Symbol Min Typ Max Unit

RESISTIVE SWITCHING
+25 V 23 PULSE GENERATOR 50 Vin 40 pF 1.0 M 20 dB 50 ATTENUATOR TO SAMPLING SCOPE 50 INPUT Vout OUTPUT V INVERTED out 90% 10 V INPUT Vin 50% 10% PULSE WIDTH 50% ton 90% toff 90% 10%

50

Figure 1. Switching Test Circuit

Figure 2. Switching Waveforms

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276

BS170
Preferred Device

Small Signal MOSFET 500 mAmps, 60 Volts


NChannel TO92
MAXIMUM RATINGS
Rating DrainSource Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 s) Drain Current (Note 1.) Total Device Dissipation @ TA = 25C Operating and Storage Junction Temperature Range Symbol VDS VGS VGSM ID PD TJ, Tstg Value 60 20 40 0.5 350 55 to +150 Unit Vdc Vdc Vpk Adc mW C G S

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500 mAMPS 60 VOLTS RDS(on) = 5


NChannel D

1. The Power Dissipation of the package may result in a lower continuous drain current.

TO92 CASE 29 Style 30 12

MARKING DIAGRAM & PIN ASSIGNMENT


BS170 YWW

1 Drain 2 Gate Y WW

3 Source

= Year = Work Week

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 278 of this data sheet. Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

277

November, 2000 Rev. 2

Publication Order Number: BS170/D

BS170
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
Gate Reverse Current (VGS = 15 Vdc, VDS = 0) DrainSource Breakdown Voltage (VGS = 0, ID = 100 Adc) IGSS V(BR)DSS 60 0.01 90 10 nAdc Vdc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DrainSource On Resistance (VGS = 10 Vdc, ID = 200 mAdc) Drain Cutoff Current (VDS = 25 Vdc, VGS = 0 Vdc) Forward Transconductance (VDS = 10 Vdc, ID = 250 mAdc) VGS(Th) rDS(on) ID(off) gfs 0.8 2.0 1.8 200 3.0 5.0 0.5 Vdc A mmhos

SMALLSIGNAL CHARACTERISTICS
Input Capacitance (VDS = 10 Vdc, VGS = 0, f = 1.0 MHz) Ciss 60 pF

SWITCHING CHARACTERISTICS
TurnOn Time (ID = 0.2 Adc) See Figure 1 TurnOff Time (ID = 0.2 Adc) See Figure 1 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. ton toff 4.0 4.0 10 10 ns ns

ORDERING INFORMATION
Device
BS170 BS170RLRA BS170RLRM BS170RLRP BS170RL1 BS170ZL1

Package
TO92 TO92 TO92 TO92 TO92 TO92

Shipping
1000 Unit/Box 2000 Tape & Reel 2000 Ammo Pack 2000 Ammo Pack 2000 Tape & Reel 2000 Ammo Pack

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278

BS170
RESISTIVE SWITCHING
+25 V Vin PULSE GENERATOR 50 50 40 pF 1.0 M ton TO SAMPLING SCOPE 50 INPUT Vout OUTPUT V INVERTED out 10% INPUT (Vin Amplitude 10 Volts) Vin PULSE WIDTH 90% 10% 90% 50% toff

125 20 dB 50 ATTENUATOR

Figure 1. Switching Test Circuit

Figure 2. Switching Waveforms

2.0 VGS(th), THRESHOLD VOLTAGE 1.6 1.2 0.8 0.4 0 50 I D(on) , DRAIN CURRENT (AMPS) VDS = VGS ID = 1.0 mA

2.0 VGS = 10 V 1.6 1.2 0.8 0.4 9.0 V 8.0 V 7.0 V 6.0 V 5.0 V 4.0 V 0 1.0 2.0 3.0 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 4.0

100 0 50 TJ, JUNCTION TEMPERATURE (C)

150

Figure 3. VGS(th) Normalized versus Temperature

Figure 4. OnRegion Characteristics

2.0 I D(on) , DRAIN CURRENT (AMPS) 1.6 1.2 0.8 0.4

VGS = 10 V 9.0 V 8.0 V 7.0 V 6.0 V 5.0 V 4.0 V 0 20 10 30 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 40 C, CAPACITANCE (pF)

100 80 60 40 Ciss 20 Coss Crss 0 10 20 30 40 50 60 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS = 0 V

Figure 5. Output Characteristics

Figure 6. Capacitance versus DrainToSource Voltage

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279

BSS123LT1
Preferred Device

Power MOSFET 170 mAmps, 100 Volts


NChannel SOT23
MAXIMUM RATINGS
Rating DrainSource Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 s) Drain Current Continuous (Note 1.) Pulsed (Note 2.) Symbol VDSS VGS VGSM ID IDM Value 100 20 40 0.17 0.68 Unit Vdc Vdc Vpk Adc

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170 mAMPS 100 VOLTS RDS(on) = 6 W


NChannel 3

THERMAL CHARACTERISTICS
Characteristic Total Device Dissipation FR5 Board (Note 3.) TA = 25C Derate above 25C Thermal Resistance, Junction to Ambient Junction and Storage Temperature Symbol PD Max 225 1.8 RqJA 556 Unit mW mW/C C/W 2 1

TJ, Tstg 55 to +150 C 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Width v 300 ms, Duty Cycle v 2.0%. 3. FR5 = 1.0  0.75  0.062 in.

MARKING DIAGRAM
3

1 2

SOT23 CASE 318 STYLE 21

SA W

SA W

= Device Code = Work Week

PIN ASSIGNMENT
Drain
3

Gate

Source

ORDERING INFORMATION
Device BSS123LT1 BSS123LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

280

February, 2001 Rev. 3

Publication Order Number: BSS123LT1/D

BSS123LT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 250 Adc) Zero Gate Voltage Drain Current (VGS = 0, VDS = 100 Vdc) TJ = 25C TJ = 125C GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) V(BR)DSS IDSS IGSS 15 60 50 nAdc 100 Vdc Adc

ON CHARACTERISTICS (Note 4.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 100 mAdc) Forward Transconductance (VDS = 25 Vdc, ID = 100 mAdc) VGS(th) rDS(on) gfs 0.8 80 5.0 2.8 6.0 Vdc mmhos

DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Ciss Coss Crss 20 9.0 4.0 pF pF pF

SWITCHING CHARACTERISTICS(4)
TurnOn Delay Time TurnOff Delay Time (VCC = 30 Vdc, IC = 0.28 Adc, VGS = 10 Vdc, RGS = 50 ) td(on) td(off) 20 40 ns ns

REVERSE DIODE
Diode Forward OnVoltage (ID = 0.34 Adc, VGS = 0 Vdc) 4. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%. VSD 1.3 V

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281

BSS123LT1
TYPICAL ELECTRICAL CHARACTERISTICS

2.0 1.8 I D, DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAN SOURCE VOLTAGE (VOLTS) TA = 25C I D, DRAIN CURRENT (AMPS) VGS = 10 V 9V 8V 7V 6V 5V 4V 3V 9.0 10

1.0 VDS = 10 V 0.8 0.6 0.4 0.2 -55C 125C 25C

1.0

2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, GATE SOURCE VOLTAGE (VOLTS)

9.0

10

Figure 1. Ohmic Region

Figure 2. Transfer Characteristics

r DS(on) , STATIC DRAIN-SOURCE ON-RESISTANCE (NORMALIZED)

2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VGS = 10 V ID = 200 mA

VGS(th) , THRESHOLD VOLTAGE (NORMALIZED)

2.4

1.2 1.05 1.1 1.10 1.0 0.95 0.9 0.85 0.8 0.75 0.7 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VDS = VGS ID = 1.0 mA

Figure 3. Temperature versus Static DrainSource OnResistance

Figure 4. Temperature versus Gate Threshold Voltage

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282

BSS123LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 The power dissipation of the SOT23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150C 25C 556C/W = 225 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 556C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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283

BSS138LT1
Preferred Device

Power MOSFET 200 mAmps, 50 Volts


NChannel SOT23
Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low Threshold Voltage (VGS(th): 0.5V...1.5V) makes it ideal for low voltage applications Miniature SOT23 Surface Mount Package saves board space
MAXIMUM RATINGS (TA = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 50 20 200 800 225 55 to 150 556 260 mW C C/W C
3

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200 mAMPS 50 VOLTS RDS(on) = 3.5 W


NChannel 3

Unit Vdc Vdc mA 1

MARKING DIAGRAM

1 2

SOT23 CASE 318 STYLE 21

J1 W

J1 W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device BSS138LT1 BSS138LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

284

November, 2000 Rev. 2

Publication Order Number: BSS138LT1/D

BSS138LT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc) GateSource Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) GateSource Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DraintoSource OnResistance (VGS = 2.75 Vdc, ID < 200 mAdc, TA = 40C to +85C) (VGS = 5.0 Vdc, ID = 200 mAdc) Forward Transconductance (VDS = 25 Vdc, ID = 200 mAdc, f = 1.0 kHz) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1 MHz) (VDS = 25 Vdc, VGS = 0, f = 1 MHz) (VDG = 25 Vdc, VGS = 0, f = 1 MHz) Ciss Coss Crss 40 12 3.5 50 25 5.0 pF VGS(th) rDS(on) gfs 100 5.6 10 3.5 mmhos 0.5 1.5 Vdc Ohms V(BR)DSS IDSS IGSS 0.1 0.5 0.1 Adc 50 Vdc Adc Symbol Min Typ Max Unit

SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time TurnOff Delay Time (VDD = 30 Vdc Vdc, ID = 0.2 0 2 Adc,) Adc ) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. td(on) td(off) 20 20 ns

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285

BSS138LT1
TYPICAL ELECTRICAL CHARACTERISTICS
0.8 I D , DRAIN CURRENT (AMPS) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 0.9 0.8 I D , DRAIN CURRENT (AMPS) VGS = 3.25 V VGS = 3.0 V VGS = 2.75 V VGS = 2.5 V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

TJ = 25C

VGS = 3.5 V

VDS = 10 V -55C

25C

150C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 -55 -5 45 95 145 0.75 -55 -30 VGS = 4.5 V ID = 0.5 A VGS = 10 V ID = 0.8 A 1.25

Figure 2. Transfer Characteristics

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

ID = 1.0 mA Vgs(th) , VARIANCE (VOLTS) 1.125

0.875

-5

20

45

70

95

120

145

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. OnResistance Variation with Temperature


VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 8 6 4 ID = 200 mA 2 0 VDS = 40 V TJ = 25C

Figure 4. Threshold Voltage Variation with Temperature

500

1000

1500

2000

2500

3000

QT, TOTAL GATE CHARGE (pC)

Figure 5. Gate Charge

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286

BSS138LT1
TYPICAL ELECTRICAL CHARACTERISTICS
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 10 9 8 7 6 5 4 3 2 1 0 0.05 0.1 0.15 0.2 0.25 -55C 25C 8 7 6 5 4 3 2 1 0 0.05 0.1 0.15 0.2 25C -55C 0.25

VGS = 2.5 V 150C

VGS = 2.75 V 150C

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 6. OnResistance versus Drain Current


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -55C 25C 4.5 4 3.5 3 2.5 2 1.5 1

Figure 7. OnResistance versus Drain Current

VGS = 4.5 V 150C

VGS = 10 V

150C

25C

-55C 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 8. OnResistance versus Drain Current

Figure 9. OnResistance versus Drain Current

1 I D , DIODE CURRENT (AMPS)

120 100

0.1

TJ = 150C

25C

-55C

80 60

0.01

40 20

Ciss Coss Crss 0 5 10 15 20 25

0.001

0.2

0.4

0.6

0.8

1.0

1.2

VSD, DIODE FORWARD VOLTAGE (VOLTS)

Figure 10. Body Diode Forward Voltage

Figure 11. Capacitance

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287

BSS138LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150C 25C 556C/W = 225 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 556C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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288

BSS84LT1
Preferred Device

Power MOSFET 130 mAmps, 50 Volts


PChannel SOT23
These miniature surface mount MOSFETs reduce power loss conserve energy, making this device ideal for use in small power management circuitry. Typical applications are dcdc converters, load switching, power management in portable and batterypowered products such as computers, printers, cellular and cordless telephones. Energy Efficient Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 50 20 130 520 225 55 to 150 556 260 mW C C/W C
3

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130 mAMPS 50 VOLTS RDS(on) = 10 W


PChannel 3

Unit Vdc Vdc mA 1

MARKING DIAGRAM

1 2

SOT23 CASE 318 STYLE 21

PD W

PD W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device BSS84LT1 Package SOT23 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

289

November, 2000 Rev. 2

Publication Order Number: BSS84LT1/D

BSS84LT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) GateSource Threaded Voltage (VDS = VGS, ID = 1.0 mAdc) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 100 mAdc) Transfer Admittance (VDS = 25 Vdc, ID = 100 mAdc, f = 1.0 kHz) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 2.5 0.130 0.520 V A (VDD = 1 15 5 Vdc, ID = 2 2.5 .5 Adc, RL = 50 ) td(on) tr td(off) tf QT 2.5 1.0 16 8.0 6000 pC ns (VDS = 5.0 Vdc) (VDS = 5.0 Vdc) (VDG = 5.0 Vdc) Ciss Coss Crss 30 10 5.0 pF VGS(th) rDS(on) |yfs| 0.8 50 5.0 2.0 10 Vdc Ohms mS V(BR)DSS IDSS IGSS 0.1 15 60 60 Adc 50 Vdc Adc Symbol Min Typ Max Unit

TYPICAL ELECTRICAL CHARACTERISTICS


0.6 I D , DRAIN CURRENT (AMPS) 0.5 0.4 0.3 0.2 0.1 0 1 1.5 2 2.5 3 3.5 4 VDS = 10 V -55C 25C 150C 0.5 0.45 I D , DRAIN CURRENT (AMPS) 0.4 0.3 0.2 0.1 0 0.35 3.0 V 2.75 V 2.5 V 2.25 V 0 1 2 3 4 5 6 7 8 9 10 TJ = 25C VGS = 3.5 V 3.25 V

0.25 0.15

0.05

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Transfer Characteristics http://onsemi.com


290

Figure 2. OnRegion Characteristics

BSS84LT1
TYPICAL ELECTRICAL CHARACTERISTICS

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

9 8 7 6 5 4 3 2 0

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

VGS = 4.5 V 150C

7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 0 0.1 0.2 0.3 0.4 VGS = 10 V

150C

25C

25C

-55C

-55C 0.5 0.6

0.1

0.2

0.3

0.4

0.5

0.6

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


2 1.8 1.6 1.4 1.2 1 0.8 0.6 -55 -5 45 95 145 VGS = 10 V ID = 0.52 A

Figure 4. OnResistance versus Drain Current

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

8 7 6 5 4 3 2 1 0 0

VDS = 40 V TJ = 25C

VGS = 4.5 V ID = 0.13 A

ID = 0.5 A

500

1000

1500

2000

TJ, JUNCTION TEMPERATURE (C)

QT, TOTAL GATE CHARGE (pC)

Figure 5. OnResistance Variation with Temperature

Figure 6. Gate Charge

1 I D , DIODE CURRENT (AMPS)

0.1

TJ = 150C

25C

-55C

0.01

0.001

0.5

1.0

1.5

2.0

2.5

3.0

VSD, DIODE FORWARD VOLTAGE (VOLTS)

Figure 7. Body Diode Forward Voltage

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291

BSS84LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150C 25C 556C/W = 225 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 556C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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292

MGP15N35CL, MGB15N35CL
Preferred Device

Ignition IGBT 15 Amps, 350 Volts

NChannel TO220 and D2PAK


This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and OverVoltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. Ideal for CoilOnPlug, IGBTOnCoil, or Distributorless Ignition System Applications High Pulsed Current Capability up to 50 A GateEmitter ESD Protection Temperature Compensated GateCollector Voltage Clamp Limits Stress Applied to Load Integrated ESD Diode Protection Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices Low Saturation Voltage Optional Gate Resistor (RG)
MAXIMUM RATINGS (55C TJ 175C unless otherwise noted)
Rating CollectorEmitter Voltage CollectorGate Voltage GateEmitter Voltage Collector CurrentContinuous @ TC = 25C Pulsed ESD (Human Body Model) R = 1500 , C = 100 pF ESD (Machine Model) R = 0 , C = 200 pF Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Symbol VCES VCER VGE IC ESD 8.0 ESD PD TJ, Tstg 800 150 1.0 55 to 175 V Watts W/C C G15N35CL YWW 1 Gate 2 Collector Unit mJ 3 Emitter G15N35CL YWW Value 380 380 22 15 50 Unit VDC VDC VDC ADC AAC kV 1 2 3 TO220AB CASE 221A STYLE 9

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15 AMPERES 350 VOLTS (Clamped) VCE(on) @ 10 A = 1.8 V Max


NChannel C

G RGE 4

RG

E 4 1 2 3 D2PAK CASE 418B STYLE 4

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Collector

4 Collector

1 Gate

3 Emitter 2 Collector

UNCLAMPED COLLECTORTOEMITTER AVALANCHE CHARACTERISTICS (55C TJ 175C)


Characteristic Single Pulse CollectortoEmitter Avalanche Energy VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L = 2.0 mH, Starting TJ = 25C VCC = 50 V, VGE = 5.0 V, Pk IL = 14.2 A, L = 2.0 mH, Starting TJ = 150C Reverse Avalanche Energy VCC = 100 V, VGE = 20 V, L = 3.0 mH, Pk IL = 25.8 A, Starting TJ = 25C Symbol EAS 300 Value

G15N35CL = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device 200 EAS(R) 1000
Preferred devices are recommended choices for future use and best overall value.

Package TO220 D2PAK

Shipping 50 Units/Rail 800 Tape & Reel

MGP15N35CL mJ MGB15N35CLT4

Semiconductor Components Industries, LLC, 2001

293

March, 2001 Rev. 4

Publication Order Number: MGP15N35CL/D

MGP15N35CL, MGB15N35CL
THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient TO220 D2PAK (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds Symbol RJC RJA RJA TL Value 1.0 62.5 50 275 C Unit C/W

ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit

OFF CHARACTERISTICS
CollectorE Emitter mitter Clamp Clam Voltage BVCES IC = 2.0 mA IC = 10 mA Zero Gate Voltage g Collector Current ICES VCE = 300 V, V VGE = 0 V Reverse CollectorEmitter Leakage g Current IECS VCE = 24 V TJ = 4 40 0C to 150C TJ = 40C to 150C TJ = 25C TJ = 150C TJ = 40C TJ = 25C TJ = 150C TJ = 40C Reverse CollectorEmitter Clamp Voltage g BVCES(R) IC = 75 mA A TJ = 25C TJ = 150C TJ = 40C GateEmitter Clamp Voltage GateEmitter Leakage Current Gate Resistor (Optional) Gate Emitter Resistor BVGES IGES RG RGE IG = 5.0 mA VGE = 10 V TJ = 40C to 150C TJ = 40C to 150C TJ = 40C to 150C TJ = 40C to 150C 320 330 25 25 25 17 384 10 350 360 1.5 10 0.7 0.35 8.0 0.05 33 36 30 20 600 70 16 380 380 20 40* 1.5 1.0 15* 0.5 50 50 50 22 1000 26 VDC ADC k VDC mA ADC VDC

ON CHARACTERISTICS (Note 2.)


g Gate Threshold Voltage VGE(th) IC = 1.0 1 0 mA, A VGE = VCE Threshold Temperature Coefficient (Negative) TJ = 25C TJ = 150C TJ = 40C 1.4 0.75 1.6 1.7 1.1 1.9 4.4 2.0 1.4 2.1* mV/C VDC

1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range.

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MGP15N35CL, MGB15N35CL
ELECTRICAL CHARACTERISTICS (continued)
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit

ON CHARACTERISTICS (continued) (Note 3.)


g CollectortoEmitter OnVoltage VCE(on) IC = 6.0 6 0 A, A VGE = 4.0 V TJ = 25C TJ = 150C TJ = 40C TJ = 25C IC = 10 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 15 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 20 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 25 A, A VGE = 4.0 V CollectortoEmitter OnVoltage Forward Transconductance VCE(on) gfs IC = 10 A, VGE = 4.5 V VCE = 5.0 V, IC = 6.0 A TJ = 150C TJ = 40C TJ = 150C TJ = 40C to 150C 1.0 0.9 1.1 1.3 1.2 1.3 1.6 1.7 1.6 1.9 2.1 1.85 2.1 2.5 2.0 8.0 1.3 1.2 1.4 1.6 1.5 1.6 1.95 2.0 1.9 2.2 2.4 2.15 2.5 2.9 2.4 1.5 15 1.6 1.5 1.7* 1.9 1.8 1.9* 2.25 2.3* 2.2 2.5 2.7* 2.45 2.9 3.3* 2.8 1.8 25 VDC Mhos VDC

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance CISS COSS CRSS TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C VCC = 25 V V, VGE = 0 V f = 1.0 MHz TJ = 40C to 150C 1000 100 5.0 1300 130 8.0 pF

SWITCHING CHARACTERISTICS (Note 3.)


y Time (Inductive) ( ) TurnOff Delay td(off) VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, L = 300 H VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, L = 300 H VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 46 , VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 46 , VCC = 10 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 1 1.5 5 VCC = 10 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 1 1.5 5 4.0 4.5 7.0 10 4.0 4.5 13 16 1.0 1.0 4.5 5.0 10 10 10 15* 10 10 20 20 1.5 1.5 6.0 6.0 Sec Sec Sec

Fall Time ( (Inductive) )

tf

TurnOff Delay y Time ( (Resistive) )

td(off)

Fall Time ( (Resistive) )

tf

TurnOn Delay y Time

td(on)

Rise Time

tr

3. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range.

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295

MGP15N35CL, MGB15N35CL
TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)
60 IC, COLLECTOR CURRENT (AMPS) VGE = 10.0 V 50 VGE = 5.0 V 40 30 20 VGE = 3.0 V 10 VGE = 2.5 V 0 0 1 2 3 4 5 6 7 8 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TJ = 25C VGE = 4.0 V IC, COLLECTOR CURRENT (AMPS) VGE = 4.5 V 60 VGE = 10.0 V 50 VGE = 5.0 V 40 VGE = 4.0 V 30 20 10 0 0 1 2 3 4 5 6 7 8 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TJ = 150C VGE = 3.5 V VGE = 3.0 V VGE = 2.5 V VGE = 4.5 V

VGE = 3.5 V

Figure 1. Output Characteristics


VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

Figure 2. Output Characteristics

30 IC, COLLECTOR CURRENT (AMPS) 25 20 15 TJ = 150C 10 TJ = 25C 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VGE, GATE TO EMITTER VOLTAGE (VOLTS) TJ = 40C VCE = 10 V

4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 50 25 IC = 15 A IC = 10 A 0 25 50 75 100 125 150 IC = 5 A VGE = 5.0 V IC = 20 A IC = 25 A

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation Voltage vs. Junction Temperature


2.5 THRESHOLD VOLTAGE (VOLTS) Mean + 4 2.0

10000 Ciss

Mean

IC = 1 mA

C, CAPACITANCE (pF)

1000

100

Coss

1.5 Mean 4 1.0

10

Crss

0.5 0.0 50

1 0 20 40 60 80 100 120 140 160 180 200 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

25

25

50

75

100

125

150

TEMPERATURE (C)

Figure 5. Capacitance Variation http://onsemi.com


296

Figure 6. Threshold Voltage vs. Temperature

MGP15N35CL, MGB15N35CL
30 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 25 20 T = 25C 15 10 5 0 0 2 4 6 8 10 INDUCTOR (mH) VCC = 50 V VGE = 5.0 V RG = 1000 30 25 20 15 L = 3.0 mH 10 L = 6.0 mH 5 0 50 L = 2.0 mH VCC = 50 V VGE = 5.0 V RG = 1000

T = 150C

25

25

50

75

100

125

150

175

TEMPERATURE (C)

Figure 7. Minimum Open Secondary Latch Current vs. Inductor

Figure 8. Minimum Open Secondary Latch Current vs. Temperature

30 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 25 20 15 10 5 0 0 2 4 6 8 10 INDUCTOR (mH) T = 150C T = 25C VCC = 50 V VGE = 5.0 V RG = 1000

30 25 20 L = 3.0 mH 15 L = 6.0 mH 10 5 0 50 L = 2.0 mH VCC = 50 V VGE = 5.0 V RG = 1000

25

25

50

75

100

125

150

175

TEMPERATURE (C)

Figure 9. Typical Open Secondary Latch Current vs. Inductor


12 10 SWITCHING TIME (S) 8 6 4 2 0 50 VCC = 300 V VGE = 5.0 V RG = 1000 IC = 10 A L = 300 H 14 12 tf SWITCHING TIME (S) 10 8 6 4 2 0 25 0 25 50 75 100 125 150 0

Figure 10. Typical Open Secondary Latch Current vs. Temperature

tf VCC = 300 V VGE = 5.0 V RG = 1000 TJ = 150C L = 300 H

td(off)

td(off)

10

12

14

16

TC, CASE TEMPERATURE (C)

IC, COLLECTOR CURRENT (AMPS)

Figure 11. Switching Speed vs. Case Temperature

Figure 12. Switching Speed vs. Collector Current

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MGP15N35CL, MGB15N35CL
14 12 SWITCHING TIME (S) 10 8 6 4 2 0 250 td(off) VCC = 300 V VGE = 5.0 V TJ = 25C IC = 10 A L = 300 H tf 14 12 SWITCHING TIME (S) 10 8 6 4 2 0 250 VCC = 300 V VGE = 5.0 V TJ = 150C IC = 10 A L = 300 H tf

td(off)

500

750

1000

500

750

1000

RG, EXTERNAL GATE RESISTANCE ()

RG, EXTERNAL GATE RESISTANCE ()

Figure 13. Switching Speed vs. External Gate Resistance

Figure 14. Switching Speed vs. External Gate Resistance

10

R(t), TRANSIENT THERMAL RESISTANCE (C/Watt)

Duty Cycle = 0.5

0.2 0.1 0.05

0.02 0.1 0.01 Single Pulse P(pk) t1 t2 DUTY CYCLE, D = t1/t2 0.01 0.00001 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT T1 TJ(pk) TA = P(pk) RJA(t) RJC R(t) for t 0.2 s

0.0001

0.001

0.01

0.1 t,TIME (S)

10

100

1000

Figure 15. Transient Thermal Resistance (Nonnormalized JunctiontoAmbient mounted on fixture in Figure 16)

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298

MGP15N35CL, MGB15N35CL

1.5 4 4

0.125 4

Figure 16. Test Fixture for Transient Thermal Curve (48 square inches of 1/8, thick aluminum)
100 COLLECTOR CURRENT (AMPS) DC 10 100 s 1 ms 1 100 ms 0.1 10 ms COLLECTOR CURRENT (AMPS) 100 DC 10 100 s 1 1 ms 10 ms 0.1 100 ms

0.01 1

10

100

1000

0.01 1

10

100

1000

COLLECTOREMITTER VOLTAGE (VOLTS)

COLLECTOREMITTER VOLTAGE (VOLTS)

Figure 17. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C)

Figure 18. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C)

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299

MGP15N35CL, MGB15N35CL
100 COLLECTOR CURRENT (AMPS) DC 10 t1 = 1 ms, D = 0.05 t1 = 2 ms, D = 0.10 t1 = 3 ms, D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 COLLECTOR CURRENT (AMPS) 100 DC 10 t1 = 1 ms, D = 0.05 t1 = 2 ms, D = 0.10 t1 = 3 ms, D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 10 100 1000

0.01 1

COLLECTOREMITTER VOLTAGE (VOLTS)

COLLECTOREMITTER VOLTAGE (VOLTS)

Figure 19. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C)

Figure 20. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C)

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300

MGP15N40CL, MGB15N40CL
Preferred Device

Ignition IGBT 15 Amps, 410 Volts

NChannel TO220 and D2PAK


This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and OverVoltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. Ideal for CoilOnPlug, IGBTOnCoil, or Distributorless Ignition System Applications High Pulsed Current Capability up to 50 A GateEmitter ESD Protection Temperature Compensated GateCollector Voltage Clamp Limits Stress Applied to Load Integrated ESD Diode Protection Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices Low Saturation Voltage Optional Gate Resistor (RG)
MAXIMUM RATINGS (55C TJ 175C unless otherwise noted)
Rating CollectorEmitter Voltage CollectorGate Voltage GateEmitter Voltage Collector CurrentContinuous @ TC = 25C Pulsed ESD (Human Body Model) R = 1500 , C = 100 pF ESD (Machine Model) R = 0 , C = 200 pF Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Symbol VCES VCER VGE IC ESD 8.0 ESD PD TJ, Tstg 800 150 1.0 55 to 175 V Watts W/C C 1 Gate 2 Collector 3 Emitter G15N40CL YWW 1 Gate 3 Emitter 2 Collector G15N40CL YWW Value 380 380 22 15 50 Unit VDC VDC VDC ADC AAC kV 1 2 3 TO220AB CASE 221A STYLE 9

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15 AMPERES 410 VOLTS (Clamped) VCE(on) @ 10 A = 1.8 V Max


NChannel C

G RGE 4

RG

E 4 1 2 3 D2PAK CASE 418B STYLE 4

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Collector

4 Collector

UNCLAMPED COLLECTORTOEMITTER AVALANCHE CHARACTERISTICS (55C TJ 175C)


Characteristic Single Pulse CollectortoEmitter Avalanche Energy VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L = 2.0 mH, Starting TJ = 25C VCC = 50 V, VGE = 5.0 V, Pk IL = 14.2 A, L = 2.0 mH, Starting TJ = 150C Reverse Avalanche Energy VCC = 100 V, VGE = 20 V, L = 3.0 mH, Pk IL = 25.8 A, Starting TJ = 25C Symbol EAS 300 Value Unit mJ

G15N40CL = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device 200 EAS(R) 1000
Preferred devices are recommended choices for future use and best overall value.

Package TO220 D2PAK

Shipping 50 Units/Rail 800 Tape & Reel

MGP15N40CL mJ MGB15N40CLT4

Semiconductor Components Industries, LLC, 2001

301

March, 2001 Rev. 5

Publication Order Number: MGP15N40CL/D

MGP15N40CL, MGB15N40CL
THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient TO220 D2PAK (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds Symbol RJC RJA RJA TL Value 1.0 62.5 50 275 C Unit C/W

ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit

OFF CHARACTERISTICS
CollectorE Emitter mitter Clamp Clam Voltage BVCES IC = 2.0 mA IC = 10 mA Zero Gate Voltage g Collector Current ICES VCE = 300 V, V VGE = 0 V Reverse CollectorEmitter Leakage g Current IECS VCE = 24 V TJ = 4 40 0C to 150C TJ = 40C to 150C TJ = 25C TJ = 150C TJ = 40C TJ = 25C TJ = 150C TJ = 40C Reverse CollectorEmitter Clamp Voltage g BVCES(R) IC = 75 mA A TJ = 25C TJ = 150C TJ = 40C GateEmitter Clamp Voltage GateEmitter Leakage Current Gate Resistor (Optional) Gate Emitter Resistor BVGES IGES RG RGE IG = 5.0 mA VGE = 10 V TJ = 40C to 150C TJ = 40C to 150C TJ = 40C to 150C TJ = 40C to 150C 320 330 25 25 25 17 384 10 350 360 1.5 10 0.7 0.35 8.0 0.05 33 36 30 20 600 70 16 380 380 20 40* 1.5 1.0 15* 0.5 50 50 50 22 1000 26 VDC ADC k VDC mA ADC VDC

ON CHARACTERISTICS (Note 2.)


g Gate Threshold Voltage VGE(th) IC = 1.0 1 0 mA, A VGE = VCE Threshold Temperature Coefficient (Negative) TJ = 25C TJ = 150C TJ = 40C 1.4 0.75 1.6 1.7 1.1 1.9 4.4 2.0 1.4 2.1* mV/C VDC

1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range.

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MGP15N40CL, MGB15N40CL
ELECTRICAL CHARACTERISTICS (continued)
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit

ON CHARACTERISTICS (continued) (Note 3.)


g CollectortoEmitter OnVoltage VCE(on) IC = 6.0 6 0 A, A VGE = 4.0 V TJ = 25C TJ = 150C TJ = 40C TJ = 25C IC = 10 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 15 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 20 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 25 A, A VGE = 4.0 V CollectortoEmitter OnVoltage Forward Transconductance VCE(on) gfs IC = 10 A, VGE = 4.5 V VCE = 5.0 V, IC = 6.0 A TJ = 150C TJ = 40C TJ = 150C TJ = 40C to 150C 1.0 0.9 1.1 1.3 1.2 1.3 1.6 1.7 1.6 1.9 2.1 1.85 2.1 2.5 2.0 8.0 1.3 1.2 1.4 1.6 1.5 1.6 1.95 2.0 1.9 2.2 2.4 2.15 2.5 2.9 2.4 1.5 15 1.6 1.5 1.7* 1.9 1.8 1.9* 2.25 2.3* 2.2 2.5 2.7* 2.45 2.9 3.3* 2.8 1.8 25 VDC Mhos VDC

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance CISS COSS CRSS TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C VCC = 25 V V, VGE = 0 V f = 1.0 MHz TJ = 40C to 150C 1000 100 5.0 1300 130 8.0 pF

SWITCHING CHARACTERISTICS (Note 3.)


y Time (Inductive) ( ) TurnOff Delay td(off) VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, L = 300 H VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, L = 300 H VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 46 , VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 46 , VCC = 10 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 1 1.5 5 VCC = 10 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 1 1.5 5 4.0 4.5 7.0 10 4.0 4.5 13 16 1.0 1.0 4.5 5.0 10 10 10 15* 10 10 20 20 1.5 1.5 6.0 6.0 Sec Sec Sec

Fall Time ( (Inductive) )

tf

TurnOff Delay y Time ( (Resistive) )

td(off)

Fall Time ( (Resistive) )

tf

TurnOn Delay y Time

td(on)

Rise Time

tr

3. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range.

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303

MGP15N40CL, MGB15N40CL
TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)
60 IC, COLLECTOR CURRENT (AMPS) VGE = 10.0 V 50 VGE = 5.0 V 40 30 20 VGE = 3.0 V 10 VGE = 2.5 V 0 0 1 2 3 4 5 6 7 8 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TJ = 25C VGE = 4.0 V IC, COLLECTOR CURRENT (AMPS) VGE = 4.5 V 60 VGE = 10.0 V 50 VGE = 5.0 V 40 VGE = 4.0 V 30 20 10 0 0 1 2 3 4 5 6 7 8 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) TJ = 150C VGE = 3.5 V VGE = 3.0 V VGE = 2.5 V VGE = 4.5 V

VGE = 3.5 V

Figure 1. Output Characteristics


VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

Figure 2. Output Characteristics

30 IC, COLLECTOR CURRENT (AMPS) 25 20 15 TJ = 150C 10 TJ = 25C 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VGE, GATE TO EMITTER VOLTAGE (VOLTS) TJ = 40C VCE = 10 V

4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 50 25 IC = 15 A IC = 10 A 0 25 50 75 100 125 150 IC = 5 A VGE = 5.0 V IC = 20 A IC = 25 A

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation Voltage vs. Junction Temperature


2.5 THRESHOLD VOLTAGE (VOLTS) Mean + 4 2.0

10000 Ciss

Mean

IC = 1 mA

C, CAPACITANCE (pF)

1000

100

Coss

1.5 Mean 4 1.0

10

Crss

0.5 0.0 50

1 0 20 40 60 80 100 120 140 160 180 200 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

25

25

50

75

100

125

150

TEMPERATURE (C)

Figure 5. Capacitance Variation http://onsemi.com


304

Figure 6. Threshold Voltage vs. Temperature

MGP15N40CL, MGB15N40CL
30 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 25 20 T = 25C 15 10 5 0 0 2 4 6 8 10 INDUCTOR (mH) VCC = 50 V VGE = 5.0 V RG = 1000 30 25 20 15 L = 3.0 mH 10 L = 6.0 mH 5 0 50 L = 2.0 mH VCC = 50 V VGE = 5.0 V RG = 1000

T = 150C

25

25

50

75

100

125

150

175

TEMPERATURE (C)

Figure 7. Minimum Open Secondary Latch Current vs. Inductor

Figure 8. Minimum Open Secondary Latch Current vs. Temperature

30 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 25 20 15 10 5 0 0 2 4 6 8 10 INDUCTOR (mH) T = 150C T = 25C VCC = 50 V VGE = 5.0 V RG = 1000

30 25 20 L = 3.0 mH 15 L = 6.0 mH 10 5 0 50 L = 2.0 mH VCC = 50 V VGE = 5.0 V RG = 1000

25

25

50

75

100

125

150

175

TEMPERATURE (C)

Figure 9. Typical Open Secondary Latch Current vs. Inductor


12 10 SWITCHING TIME (S) 8 6 4 2 0 50 VCC = 300 V VGE = 5.0 V RG = 1000 IC = 10 A L = 300 H 14 12 tf SWITCHING TIME (S) 10 8 6 4 2 0 25 0 25 50 75 100 125 150 0

Figure 10. Typical Open Secondary Latch Current vs. Temperature

tf VCC = 300 V VGE = 5.0 V RG = 1000 TJ = 150C L = 300 H

td(off)

td(off)

10

12

14

16

TC, CASE TEMPERATURE (C)

IC, COLLECTOR CURRENT (AMPS)

Figure 11. Switching Speed vs. Case Temperature

Figure 12. Switching Speed vs. Collector Current

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305

MGP15N40CL, MGB15N40CL
14 12 SWITCHING TIME (S) 10 8 6 4 2 0 250 td(off) VCC = 300 V VGE = 5.0 V TJ = 25C IC = 10 A L = 300 H tf 14 12 SWITCHING TIME (S) 10 8 6 4 2 0 250 VCC = 300 V VGE = 5.0 V TJ = 150C IC = 10 A L = 300 H tf

td(off)

500

750

1000

500

750

1000

RG, EXTERNAL GATE RESISTANCE ()

RG, EXTERNAL GATE RESISTANCE ()

Figure 13. Switching Speed vs. External Gate Resistance

Figure 14. Switching Speed vs. External Gate Resistance

10

R(t), TRANSIENT THERMAL RESISTANCE (C/Watt)

Duty Cycle = 0.5

0.2 0.1 0.05

0.02 0.1 0.01 Single Pulse P(pk) t1 t2 DUTY CYCLE, D = t1/t2 0.01 0.00001 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT T1 TJ(pk) TA = P(pk) RJA(t) RJC R(t) for t 0.2 s

0.0001

0.001

0.01

0.1 t,TIME (S)

10

100

1000

Figure 15. Transient Thermal Resistance (Nonnormalized JunctiontoAmbient mounted on fixture in Figure 16)

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306

MGP15N40CL, MGB15N40CL

1.5 4 4

0.125 4

Figure 16. Test Fixture for Transient Thermal Curve (48 square inches of 1/8, thick aluminum)
100 COLLECTOR CURRENT (AMPS) DC 10 100 s 1 ms 1 100 ms 0.1 10 ms COLLECTOR CURRENT (AMPS) 100 DC 10 100 s 1 1 ms 10 ms 0.1 100 ms

0.01 1

10

100

1000

0.01 1

10

100

1000

COLLECTOREMITTER VOLTAGE (VOLTS)

COLLECTOREMITTER VOLTAGE (VOLTS)

Figure 17. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C)

Figure 18. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C)

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307

MGP15N40CL, MGB15N40CL
100 COLLECTOR CURRENT (AMPS) DC 10 t1 = 1 ms, D = 0.05 t1 = 2 ms, D = 0.10 t1 = 3 ms, D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 COLLECTOR CURRENT (AMPS) 100 DC 10 t1 = 1 ms, D = 0.05 t1 = 2 ms, D = 0.10 t1 = 3 ms, D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 10 100 1000

0.01 1

COLLECTOREMITTER VOLTAGE (VOLTS)

COLLECTOREMITTER VOLTAGE (VOLTS)

Figure 19. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C)

Figure 20. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C)

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308

MGP19N35CL, MGB19N35CL
Preferred Device

Ignition IGBT 19 Amps, 350 Volts

NChannel TO220 and D2PAK


This Logic Level Insulated Gate Bipolar Transistor (IGBT) features monolithic circuitry integrating ESD and OverVoltage clamped protection for use in inductive coil drivers applications. Primary uses include Ignition, Direct Fuel Injection, or wherever high voltage and high current switching is required. Ideal for IGBTOnCoil or Distributorless Ignition System Applications High Pulsed Current Capability up to 50 A GateEmitter ESD Protection Temperature Compensated GateCollector Voltage Clamp Limits Stress Applied to Load Integrated ESD Diode Protection Low Threshold Voltage to Interface Power Loads to Logic or Microprocessor Devices Low Saturation Voltage Optional Gate Resistor (RG)
MAXIMUM RATINGS (55C TJ 175C unless otherwise noted)
Rating CollectorEmitter Voltage CollectorGate Voltage GateEmitter Voltage Collector Current Continuous @ TC = 25C Pulsed ESD (Human Body Model) R = 1500 , C = 100 pF ESD (Machine Model) R = 0 , C = 200 pF Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Symbol VCES VCER VGE IC ESD 8.0 ESD PD TJ, Tstg 800 165 1.1 55 to 175 V Watts W/C C 1 Gate 2 Collector 3 Emitter G19N35CL YWW 1 Gate 3 Emitter 2 Collector G19N35CL YWW Value 380 380 22 19 50 Unit VDC VDC VDC ADC AAC kV 1 2 3 TO220AB CASE 221A STYLE 9

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19 AMPERES 350 VOLTS (Clamped) VCE(on) @ 10 A = 1.8 V Max


NChannel C

G RGE 4 E 4 1 2 3 D2PAK CASE 418B STYLE 4

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Collector

4 Collector

UNCLAMPED COLLECTORTOEMITTER AVALANCHE CHARACTERISTICS (55C TJ 175C)


Characteristic Single Pulse CollectortoEmitter Avalanche Energy VCC = 50 V, VGE = 5.0 V, Pk IL = 22.4 A, L = 2.0 mH, Starting TJ = 25C VCC = 50 V, VGE = 5.0 V, Pk IL = 17.4 A, L = 2.0 mH, Starting TJ = 150C Reverse Avalanche Energy VCC = 100 V, VGE = 20 V, L = 3.0 mH, Pk IL = 25.8 A, Starting TJ = 25_C Symbol EAS 500 300 Value Unit mJ

G19N35CL = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device MGP19N35CL Package TO220 D2PAK Shipping 50 Units/Rail 800 Tape & Reel

EAS(R) 1000

mJ

MGB19N35CLT4

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

309

March, 2001 Rev. 3

Publication Order Number: MGP19N35CL/D

MGP19N35CL, MGB19N35CL
THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient TO220 D2PAK (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds Symbol RJC RJA RJA TL Value 0.9 62.5 50 275 C Unit C/W

ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit

OFF CHARACTERISTICS
CollectorEmitter Clamp Voltage BVCES IC = 2.0 mA IC = 10 mA Zero Gate Voltage g Collector Current ICES VCE = 300 V, V VGE = 0 V Reverse CollectorEmitter Leakage g Current IECS VCE = 24 V TJ = 40C to 150C TJ = 40C to 150C TJ = 25C TJ = 150C TJ = 40C TJ = 25C TJ = 150C TJ = 40C Reverse CollectorEmitter Clamp Voltage g BVCES(R) IC = 75 mA A TJ = 25C TJ = 150C TJ = 40C GateEmitter Clamp Voltage GateEmitter Leakage Current Gate Resistor (Optional) Gate Emitter Resistor BVGES IGES RG RGE IG = 5.0 mA VGE = 10 V TJ = 40C to 150C TJ = 40C to 150C TJ = 40C to 150C TJ = 40C to 150C 320 330 25 25 25 17 384 10 350 360 1.5 15 0.7 0.35 10 0.05 33 36 30 20 500 70 20 380 380 20 40* 1.5 1.0 20* 0.5 50 50 50 22 1000 26 VDC ADC k VDC mA ADC VDC

ON CHARACTERISTICS (Note 2.)


g Gate Threshold Voltage VGE(th) IC = 1.0 1 0 mA, A VGE = VCE Threshold Temperature Coefficient (Negative) TJ = 25C TJ = 150C TJ = 40C 1.4 0.75 1.6 1.7 1.1 1.9 4.4 2.0 1.4 2.1* mV/C VDC

1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range.

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310

MGP19N35CL, MGB19N35CL
ELECTRICAL CHARACTERISTICS (continued)
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit

ON CHARACTERISTICS (continued) (Note 3.)


g CollectortoEmitter OnVoltage VCE(on) IC = 6.0 6 0 A, A VGE = 4.0 V TJ = 25C TJ = 150C TJ = 40C TJ = 25C IC = 10 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 15 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 20 A, A VGE = 4.0 V TJ = 150C TJ = 40C TJ = 25C IC = 25 A, A VGE = 4.0 V CollectortoEmitter OnVoltage Forward Transconductance VCE(on) gfs IC = 10 A, VGE = 4.5 V VCE = 5.0 V, IC = 6.0 A TJ = 150C TJ = 40C TJ = 150C TJ = 40C to 150C 1.0 0.8 1.15 1.2 1.0 1.3 1.5 1.35 1.5 1.7 1.6 1.7 2.0 2.0 2.0 8.0 1.25 1.05 1.4 1.5 1.3 1.6 1.75 1.65 1.8 2.0 1.9 2.0 2.25 2.3 2.2 1.3 15 1.6 1.4 1.75* 1.8 1.6 1.9* 2.1 1.95 2.1* 2.3 2.2 2.3* 2.6 2.7* 2.6 1.8 25 VDC Mhos VDC

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance CISS COSS CRSS TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C TJ = 25C TJ = 150C VCC = 25 V V, VGE = 0 V f = 1.0 MHz TJ = 40C to 150C 1500 130 6.0 1800 160 8.0 pF

SWITCHING CHARACTERISTICS (Note 3.)


y Time (Inductive) ( ) TurnOff Delay td(off) VCC = 300 V, , IC = 10 A RG = 1 1.0 0 k, L = 300 H VCC = 300 V, , IC = 10 A RG = 1 1.0 0 k, L = 300 H VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 46 VCC = 300 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 46 VCC = 10 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 1 1.5 5 VCC = 10 V, , IC = 6.5 A RG = 1 1.0 0 k, RL = 1 1.5 5 5.0 6.0 6.0 11 6.0 7.0 12 18 1.5 1.5 4.0 5.0 10 10 10 15* 10 10 20 22* 2.0 2.0 6.0 6.0 Sec Sec Sec

Fall Time ( (Inductive) )

tf

TurnOff Delay y Time ( (Resistive) )

td(off)

Fall Time ( (Resistive) )

tf

TurnOn Delay y Time

td(on)

Rise Time

tr

3. Pulse Test: Pulse Width v 300 S, Duty Cycle v 2%. *Maximum Value of Characteristic across Temperature Range.

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311

MGP19N35CL, MGB19N35CL
TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)
60 IC, COLLECTOR CURRENT (AMPS) VGE = 10.0 V 50 VGE = 5.0 V 40 TJ = 25C 30 20 10 0 0 1 2 3 4 5 6 7 8 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VGE = 3.0 V VGE = 2.5 V VGE = 4.5 V VGE = 3.5 V VGE = 4.0 V IC, COLLECTOR CURRENT (AMPS) 60 VGE = 10.0 V 50 VGE = 5.0 V 40 TJ = 150C 30 20 10 0 0 1 2 3 4 5 6 7 8 VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VGE = 3.0 V VGE = 2.5 V VGE = 3.5 V VGE = 4.0 V VGE = 4.5 V

Figure 1. Output Characteristics


VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

Figure 2. Output Characteristics

60 IC, COLLECTOR CURRENT (AMPS) 55 50 45 40 35 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VGE, GATE TO EMITTER VOLTAGE (VOLTS) TJ = 25C TJ = 150C TJ = 40C VCE = 10 V

3.0 VGE = 5.0 V 2.5 2.0 1.5 1.0 0.5 0.0 50 IC = 20 A IC = 25 A

IC = 15 A IC = 10 A

IC = 5 A

25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics

Figure 4. CollectortoEmitter Saturation Voltage vs. Junction Temperature


2.5 THRESHOLD VOLTAGE (VOLTS)

10000 Ciss C, CAPACITANCE (pF) 1000 Coss 100 Crss

Mean + 4 2.0 Mean

IC = 1 mA

1.5

Mean 4

10

1.0

0.5 0.0 50

20

40

60

80

100 120

140 160 180

25

25

50

75

100

125

150

VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

TEMPERATURE (C)

Figure 5. Capacitance Variation http://onsemi.com


312

Figure 6. Threshold Voltage vs. Temperature

MGP19N35CL, MGB19N35CL
14 12 SWITCHING TIME (S) 10 8 6 4 2 0 50 td(off) VCC = 300 V VGE = 5.0 V RG = 1000 IC = 10 A L = 300 H 14 12 SWITCHING TIME (S) 10 8 6 4 2 0 25 0 25 50 75 100 125 150 0 2 4 6 8 10 TC, CASE TEMPERATURE (C) td(off) VCC = 300 V VGE = 5.0 V RG = 1000 TJ = 150C L = 300 H 12 14 16 tf

tf

IC, COLLECTOR CURRENT (AMPS)

Figure 7. Switching Speed vs. Case Temperature

Figure 8. Switching Speed vs. Collector Current

30 IL, LATCH CURRENT (AMPS) IL, LATCH CURRENT (AMPS) 25 T = 25C 20 15 T = 150C 10 5 0 0 2 4 6 8 10 INDUCTOR (mH) VCC = 50 V VGE = 5.0 V RG = 1000

30 25 L = 2.0 mH 20 15 10 5 0 50 VCC = 50 V VGE = 5.0 V RG = 1000 25 0 25 50 75 100 125 150 175 L = 3.0 mH L = 6.0 mH

TEMPERATURE (C)

Figure 9. Minimum Open Secondary Latch Current vs. Inductor


30 IL, LATCH CURRENT (AMPS) 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 INDUCTOR (mH) T = 150C T = 25C IL, LATCH CURRENT (AMPS) VCC = 50 V VGE = 5.0 V RG = 1000 30

Figure 10. Minimum Open Secondary Latch Current vs. Temperature

L = 2.0 mH 25 L = 3.0 mH 20 15 10 5 0 50 VCC = 50 V VGE = 5.0 V RG = 1000 25 0 25 50 75 100 125 150 175 L = 6.0 mH

TEMPERATURE (C)

Figure 11. Typical Open Secondary Latch vs. Inductor

Figure 12. Typical Open Secondary Latch vs. Temperature

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313

MGP19N35CL, MGB19N35CL
10

R(t), TRANSIENT THERMAL RESISTANCE (C/Watt)

Duty Cycle = 0.5

0.2 0.1 0.05

0.02 0.1 0.01 P(pk) t1 Single Pulse t2 DUTY CYCLE, D = t1/t2 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT T1 TJ(pk) TA = P(pk) RJA(t) RJC R(t) for t 0.2 s

0.01 0.00001

0.0001

0.001

0.01

0.1 t,TIME (S)

10

100

1000

Figure 13. Transient Thermal Resistance (Nonnormalized JunctiontoAmbient mounted on fixture in Figure 14)

1.5 4 4

0.125 4

Figure 14. Test Fixture for Transient Thermal Curve (48 square inches of 1/8, thick aluminum)

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314

MGP19N35CL, MGB19N35CL
100 COLLECTOR CURRENT (AMPS) DC 10 1 ms 1 100 ms 0.1 10 ms COLLECTOR CURRENT (AMPS) 100 s 100 DC 10 100 s

1 ms 10 ms

0.1

100 ms

0.01 1

10

100

1000

0.01 1

10

100

1000

COLLECTOREMITTER VOLTAGE (VOLTS)

COLLECTOREMITTER VOLTAGE (VOLTS)

Figure 15. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C)
100 COLLECTOR CURRENT (AMPS) COLLECTOR CURRENT (AMPS) DC 10 t1 = 3 ms D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 0.01 1 10 100 1000 t1 = 1 ms D = 0.05 t1 = 2 ms D = 0.10 100

Figure 16. Single Pulse Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C)

DC 10 t1 = 3 ms D = 0.30 1 P(pk) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 10

t1 = 1 ms D = 0.05 t1 = 2 ms D = 0.10

0.01 1

100

1000

COLLECTOREMITTER VOLTAGE (VOLTS)

COLLECTOREMITTER VOLTAGE (VOLTS)

Figure 17. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 255C)

Figure 18. Pulse Train Safe Operating Area (Mounted on an Infinite Heatsink at TC = 1255C)

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315

MGSF1N02ELT1
Preferred Device

Power MOSFET 750 mAmps, 20 Volts


NChannel SOT23
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dcdc converters and power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 20 8.0 750 2000 400 55 to 150 300 260 mW C C/W C
1 2 3

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750 mAMPS 20 VOLTS RDS(on) = 85 mW


NChannel 3

Unit Vdc Vdc mA 1

MARKING DIAGRAM

SOT23 CASE 318 STYLE 21

NE W

NE W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device MGSF1N02ELT1 MGSF1N02ELT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

316

November, 2000 Rev. 1

Publication Order Number: MGSF1N02ELT1/D

MGSF1N02ELT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateSource Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) GateSource Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 1.0 A) (VGS = 2.5 Vdc, ID = 0.75 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge (VDS = 16 Vdc, ID = 1.2 Adc, VGS = 4.0 Vdc) (VDD = 5 Vdc, ID = 1.0 Adc, RL = 5 , RG = 6 ) td(on) tr td(off) tf QT 6.0 26 117 105 6500 pC ns (VDS = 5.0 Vdc, VGS = 0 V, f = 1.0 Mhz) (VDS = 5.0 Vdc, VGS = 0 V, f = 1.0 Mhz) (VDG = 5.0 Vdc, VGS = 0 V, f = 1.0 Mhz) Ciss Coss Crss 160 130 60 pF VGS(th) rDS(on) 0.085 0.115 0.5 1.0 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 0.1 Adc 20 Vdc Adc Symbol Min Typ Max Unit

SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) (VGS = 0 Vdc, IS = 0.6 Adc) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 0.6 0.75 1.2 V A

TYPICAL ELECTRICAL CHARACTERISTICS


2.5 2 1.5 1 0.5 0 TJ = 150C 25C -55C 2 1.8 ID, DRAIN CURRENT (AMPS) ID , DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0.5 0.8 1.1 1.4 1.7 2.0 0 0 0.5 1 1.5 2 2.5 VGS = 1.25 V 2.5 V 2.25 V 2.0 V 1.5 V 1.75 V

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Transfer Characteristics http://onsemi.com


317

Figure 2. OnRegion Characteristics

MGSF1N02ELT1
TYPICAL ELECTRICAL CHARACTERISTICS
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 25C -55C VGS = 2.5 V TJ = 150C 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 25C -55C

VGS = 4.5 V

TJ = 150C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 -50

Figure 4. OnResistance versus Drain Current

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 4.5 V ID = 1.2 A VGS = 2.5 V ID = 1.0 A

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

5 4 3 2

VDS = 16 V TJ = 25C

ID = 1.2 A 1 0

-25

25

50

75

100

125

150

2000

4000

6000

8000

10000

TJ, JUNCTION TEMPERATURE (C)

QT, TOTAL GATE CHARGE (pC)

Figure 5. OnResistance Variation Over Temperature


1 ID, DIODE CURRENT (AMPS) 500 450 C, CAPACITANCE (pF) TJ = 150C 0.1 25C -55C 400 350 300 250 200 150 100 50 0.001 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0 1 2

Figure 6. Gate Charge

f = 1 MHz TJ = 25C

0.01

Ciss Coss Crss 3 4 5 6 7 8 9 10

VSD, DIODE FORWARD VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Body Diode Forward Voltage

Figure 8. Capacitance Variation

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318

MGSF1N02ELT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 416 milliwatts.
PD = 150C 25C 300C/W = 416 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 300C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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319

MGSF1N02LT1
Preferred Device

Power MOSFET 750 mAmps, 20 Volts


NChannel SOT23
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dcdc converters and power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 20 20 750 2000 400 55 to 150 300 260 Unit Vdc Vdc 1 mA mW C C/W C
1 2 3

http://onsemi.com

750 mAMPS 20 VOLTS RDS(on) = 90 mW


NChannel 3

MARKING DIAGRAM

SOT23 CASE 318 STYLE 21

N2 W

N2 W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device MGSF1N02LT1 MGSF1N02LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

320

November, 2000 Rev. 3

Publication Order Number: MGSF1N02LT1/D

MGSF1N02LT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.2 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 6) SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 0.8 0.6 0.75 V A (VDD = 15 Vdc, ID = 1.0 Adc, RL = 50 ) td(on) tr td(off) tf QT 2.5 1.0 16 8.0 6000 pC ns (VDS = 5.0 Vdc) (VDS = 5.0 Vdc) (VDG = 5.0 Vdc) Ciss Coss Crss 125 120 45 pF VGS(th) rDS(on) 0.075 0.115 0.090 0.130 1.0 1.7 2.4 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 20 Vdc Adc Symbol Min Typ Max Unit

TYPICAL ELECTRICAL CHARACTERISTICS


2.5 I D , DRAIN CURRENT (AMPS) 2 1.5 1 -55C TJ = 150C 3 I D , DRAIN CURRENT (AMPS) 2.5 2 VGS = 3.0 V 1.5 1 0.5 3 3.5 0 2.75 V 2.5 V 2.25 V 0 1 2 3 4 5 6 7 8 9 10 4V 3.5 V 3.25 V

VDS = 10 V

0.5 0

25C 1 1.5 2 2.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Transfer Characteristics

Figure 2. OnRegion Characteristics

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321

MGSF1N02LT1
TYPICAL ELECTRICAL CHARACTERISTICS

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VGS = 4.5 V

150C

0.14 0.13 0.12 0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 25C -55C VGS = 10 V 150C

25C -55C

0.9

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

Figure 4. OnResistance versus Drain Current

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 -55 -5 45 95 145 VGS = 4.5 V ID = 1 A VGS = 10 V ID = 2 A

10 8 6 4 2 0

VDS = 16 V TJ = 25C

ID = 2.0 A

1000

2000

3000

4000

5000

6000

TJ, JUNCTION TEMPERATURE (C)

QT, TOTAL GATE CHARGE (pC)

Figure 5. OnResistance Variation with Temperature

Figure 6. Gate Charge

1 I D , DIODE CURRENT (AMPS)

1000 VGS = 0 V f = 1 MHz TJ = 25C Ciss Coss Crss

0.1

C, CAPACITANCE (pF)

TJ = 150C

25C

-55C

100

0.01

0.001

0.2

0.4

0.6

0.8

10

10

15

20

VSD, DIODE FORWARD VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Body Diode Forward Voltage

Figure 8. Capacitance

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322

MGSF1N02LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 416 milliwatts.
PD = 150C 25C 300C/W = 416 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 300C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

http://onsemi.com
323

MGSF1N03LT1
Preferred Device

Power MOSFET 750 mAmps, 30 Volts


NChannel SOT23
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dcdc converters and power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 30 20 750 2000 400 55 to 150 300 260 mW C C/W C
1 2 3

http://onsemi.com

750 mAMPS 30 VOLTS RDS(on) = 100 mW


NChannel 3

Unit Vdc Vdc mA 1

MARKING DIAGRAM

SOT23 CASE 318 STYLE 21

N3 W

N3 W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device MGSF1N03LT1 MGSF1N03LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

324

November, 2000 Rev. 5

Publication Order Number: MGSF1N03LT1/D

MGSF1N03LT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.2 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 6) SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 0.8 0.6 0.75 V A (VDD = 15 Vdc, ID = 1.0 Adc, RL = 50 ) td(on) tr td(off) tf QT 2.5 1.0 16 8.0 6000 pC ns (VDS = 5.0 Vdc) (VDS = 5.0 Vdc) (VDG = 5.0 Vdc) Ciss Coss Crss 140 100 40 pF VGS(th) rDS(on) 0.08 0.125 0.10 0.145 1.0 1.7 2.4 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 30 Vdc Adc Symbol Min Typ Max Unit

TYPICAL ELECTRICAL CHARACTERISTICS


2.5 I D , DRAIN CURRENT (AMPS) 2 1.5 1 -55C TJ = 150C 25C 1 1.5 2 2.5 3 3.5 0 0 2 4 6 8 2.5 I D , DRAIN CURRENT (AMPS) 2 1.5 1 0.5

VDS = 10 V

VGS = 3.75 V

3.5 V

3.25 V

3.0 V 2.75 V 2.5 V 10

0.5 0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Transfer Characteristics

Figure 2. OnRegion Characteristics

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325

MGSF1N03LT1
TYPICAL ELECTRICAL CHARACTERISTICS

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.24

150C VGS = 4.5 V 25C -55C

0.16 0.14 0.12 0.1 0.08 0.06 0.04 VGS = 10 V 150C

0.19

0.14

25C

0.09

-55C

0.04

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -55 -25 0 25 50 75 100 125 150 VGS = 10 V ID = 2 A VGS = 4.5 V ID = 1 A

Figure 4. OnResistance versus Drain Current

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10 8 6 4 2 0

VDS = 24 V TJ = 25C

ID = 2.0 A

1000

2000

3000

4000

5000

6000

TJ, JUNCTION TEMPERATURE (C)

QT, TOTAL GATE CHARGE (pC)

Figure 5. OnResistance Variation with Temperature

Figure 6. Gate Charge

1 I D , DIODE CURRENT (AMPS)

350 300 VGS = 0 V f = 1 MHz TJ = 25C

0.1

C, CAPACITANCE (pF)

TJ = 150C

25C

-55C

250 200 150 100 50

0.01

Ciss Coss Crss 0 4 8 12 16 20

0.001

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, DIODE FORWARD VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Body Diode Forward Voltage

Figure 8. Capacitance

http://onsemi.com
326

MGSF1N03LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 416 milliwatts.
PD = 150C 25C 300C/W = 416 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 300C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

http://onsemi.com
327

MGSF1P02ELT1
Preferred Device

Power MOSFET 750 mAmps, 20 Volts


PChannel SOT23
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dcdc converters and power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 20 8.0 750 2000 400 55 to 150 300 260 mW C C/W C
1 2 3

http://onsemi.com

750 mAMPS 20 VOLTS RDS(on) = 260 mW


PChannel 3

Unit Vdc Vdc mA 1

MARKING DIAGRAM

SOT23 CASE 318 STYLE 21

PE W

PE W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device MGSF1P02ELT1 MGSF1P02ELT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

328

November, 2000 Rev. 2

Publication Order Number: MGSF1P02ELT1/D

MGSF1P02ELT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 0.75 Adc) (VGS = 2.5 Vdc, ID = 0.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge (VDS = 16 Vdc, ID = 1.5 Adc, VGS = 4.0 Vdc) (VDD = 5 Vdc, ID = 1.0 Adc, RL = 5 , RG = 6 ) td(on) tr td(off) tf QT 9.5 32 200 200 5500 pC ns (VDS = 5.0 Vdc) (VDS = 5.0 Vdc) (VDG = 5.0 Vdc) Ciss Coss Crss 140 130 50 pF VGS(th) rDS(on) 0.22 0.40 0.26 0.50 0.7 1.0 1.25 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 20 Vdc Adc Symbol Min Typ Max Unit

SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) (VGS = 0 Vdc, IS = 0.6 Adc) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 0.6 0.75 1.0 V A

TYPICAL ELECTRICAL CHARACTERISTICS


1.6 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 1.2 1.4 1.6 1.8 TJ = 150C 25C -55C 2 2.2 2.4 2.6 0 0 1 2 3 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1.5 1.25 1 2.0 V

VGS = 2.5 V

2.25 V

0.75 0.5

0.25

1.75 V 1.5 V 1.25 V 9 10

Figure 1. Transfer Characteristics

Figure 2. OnRegion Characteristics

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329

MGSF1P02ELT1
TYPICAL ELECTRICAL CHARACTERISTICS
0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -55C 25C 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -55C 25C

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

VGS = 2.5 V

150C

VGS = 4.5 V 150C

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 125 150 VGS = 4.5 V ID = .75 A

Figure 4. OnResistance versus Drain Current

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS = 16 V TJ = 25C ID = 1.5 A

VGS = 2.5 V ID = .5 A

TJ, JUNCTION TEMPERATURE (C)

QT, TOTAL GATE CHARGE (nC)

Figure 5. OnResistance Variation with Temperature

Figure 6. Gate Charge

1 I D , DIODE CURRENT (AMPS)

400 350 Coss VGS = 0 V f = 1 MHz TJ = 25C

0.1

C, CAPACITANCE (pF)

TJ = 150C

25C

-55C

300 250 200 150 100 50

Ciss Crss

0.01

0.001

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, DIODE FORWARD VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Body Diode Forward Voltage

Figure 8. Capacitance Variation

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330

MGSF1P02ELT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 416 milliwatts.
PD = 150C 25C 300C/W = 416 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 300C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

http://onsemi.com
331

MGSF1P02LT1
Preferred Device

Power MOSFET 750 mAmps, 20 Volts


PChannel SOT23
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dcdc converters and power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 20 20 750 2000 400 55 to 150 300 260 mW C C/W C
1 2 3

http://onsemi.com

750 mAMPS 20 VOLTS RDS(on) = 350 mW


PChannel 3

Unit Vdc Vdc mA 1

MARKING DIAGRAM

SOT23 CASE 318 STYLE 21

PC W

PC W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device MGSF1P02LT1 MGSF1P02LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

332

November, 2000 Rev. 3

Publication Order Number: MGSF1P02LT1/D

MGSF1P02LT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 Adc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 0.75 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 6) SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 1.5 0.6 0.75 V A (VDD = 15 Vdc, ID = 1.0 Adc, RL = 50 ) td(on) tr td(off) tf QT 2.5 1.0 16 8.0 6000 pC ns (VDS = 5.0 Vdc) (VDS = 5.0 Vdc) (VDG = 5.0 Vdc) Ciss Coss Crss 130 120 60 pF VGS(th) rDS(on) 0.235 0.375 0.350 0.500 1.0 1.7 2.4 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 20 Vdc Adc Symbol Min Typ Max Unit

TYPICAL ELECTRICAL CHARACTERISTICS


1.5 I D , DRAIN CURRENT (AMPS) 1.25 1 0.75 0.5 0.25 0 1 1.5 2 2.5 -55C TJ = 150C 25C 1.5 I D , DRAIN CURRENT (AMPS) 1.25 1 3.0 V

VDS = 10 V

VGS = 3.5 V

3.25 V

0.75 0.5 2.75 V 2.5 V 2.25 V 0 1 2 3 4 5 6 7 8 9 10

0.25 3.5 0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Transfer Characteristics

Figure 2. OnRegion Characteristics

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333

MGSF1P02LT1
TYPICAL ELECTRICAL CHARACTERISTICS
0.55 150C VGS = 4.5 V 0.4 0.38 0.36 0.34 0.32 0.3 0.28 0.26 0.24 0.22 0.2 0 0.2 0.4 0.6 0.8 1 1.2 25C -55C VGS = 10 V 150C

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.5

0.45 25C 0.4 -55C 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

1.4

1.6

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


1.25 1.2 VGS = 10 V ID = 1.5 A

Figure 4. OnResistance versus Drain Current

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10 8 6 4 2 0

1.15 1.1

VDS = 16 V TJ = 25C

1.05 1

VGS = 4.5 V ID = .75 A

0.95 0.9

ID = 1.5 A

0.85 0.8 -55 -5 45 95 145

1000

2000

3000

4000

5000

6000

TJ, JUNCTION TEMPERATURE (C)

QT, TOTAL GATE CHARGE (pC)

Figure 5. OnResistance Variation with Temperature

Figure 6. Gate Charge

1 I D , DIODE CURRENT (AMPS)

1000 VGS = 0 V f = 1 MHz TJ = 25C Ciss 100 Coss Crss

0.1

0.01

C, CAPACITANCE (pF)

TJ = 150C

25C

-55C

0.001

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

10

10

VSD, DIODE FORWARD VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Body Diode Forward Voltage

Figure 8. Capacitance

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334

MGSF1P02LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 416 milliwatts.
PD = 150C 25C 300C/W = 416 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 300C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 416 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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335

MGSF2P02HD Product Preview Power MOSFET 2 Amps, 20 Volts


PChannel TSOP6
This device represents a series of Power MOSFETs which are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. These devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Miniature TSOP6 Surface Mount Package Saves Board Space Low Profile for Thin Applications such as PCMCIA Cards Very Low RDS(on) Provides Higher Efficiency and Expands Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Diode is Characterized for Use in Bridge Circuits Diode Exhibits High Speed, with Soft Recovery IDSS Specified at Elevated Temperatures Avalanche Energy Specified Package Mounting Information Provided
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2 AMPERES 20 VOLTS RDS(on) = 175 mW


PChannel 1 2 5 6

MARKING DIAGRAM
3 2

TSOP6 CASE 318G STYLE 1

3V W

3V W

= Device Code = Work Week

PIN ASSIGNMENT
Drain Drain Source
6 5 4

Drain Drain Gate

ORDERING INFORMATION
Device MGSF2P02HDT1 MGSF2P02HDT3
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package TSOP6 TSOP6

Shipping 3000 Tape & Reel 10,000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

336

November, 2000 Rev. 1

Publication Order Number: MGSF2P02HD/D

MGSF2P02HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Drain Current Continuous Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Total Power Dissipation @ TC = 85C Thermal Resistance Junction to Ambient (Note 1.) Drain Current Continuous Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Total Power Dissipation @ TC = 85C Thermal Resistance Junction to Ambient (Note 2.) Operating and Storage Temperature Range Single Pulse Drain Source Avalanche Energy VDD = 20 V, VGS = 4.5 Vpk, IL = 3.6 Apk, L = 25 mH, RG = 25 W Symbol VDSS VDGR VGS ID IDM PD PD RqJA ID IDM PD PD RqJA TJ, Tstg EAS 160 C Value 20 20 9 1.3 10 400 210 312 2.9 15 2.0 1.0 62.5 55 to 150 Unit V V V A mW mW C/W A W W C/W C mJ

THERMAL CHARACTERISTICS
Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 seconds TL 1. Minimum FR4 or G10 PCB, Operating to Steady State. 2. Mounted onto a 2 square FR4 Board (1 sq. 2 oz. Cu 0.06 thick single sided), Operating time 5 seconds. 260

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337

MGSF2P02HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GatetoSource Leakage Current (VGS = 9.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) DraintoSource OnVoltage (VGS = 4.5 Vdc, ID = 1.3 Adc) (VGS = 2.7 Vdc, ID = 0.8 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 0.6 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 1.2 Adc, VGS = 4.5 Vdc) (VDD = 10 Vdc, ID = 0.6 Adc, VGS = 2 2.7 7 Vdc Vdc, RG = 6.0 ) (VDS = 10 Vdc, ID = 1.2 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 1.2 Adc, VGS = 0 Vdc) Reverse Recovery Time (IS = 1.2 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) trr ta tb QRR NOTE: Pulse Test: Pulse Width 300 s, Duty Cycle 2%. VSD 0.89 0.72 86 27 59 0.115 1.1 C nsec Vdc 15 27 60 72 20 94 49 76 5.3 0.7 2.6 1.9 7.5 nC nsec (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 225 150 60 pF VGS(th) 0.7 RDS(on) gFS 1.3 2.0 145 220 175 280 mhos 0.95 2.2 1.4 Vdc mV/C mW V(BR)DSS 20 IDSS IGSS 1.0 10 nAdc 100 A Vdc Symbol Min Typ Max Unit

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338

MGSF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
4.0 4.0 2.9 V ID , DRAIN CURRENT (AMPS) TJ = 25C

VGS = 8.0 V 4.5 V 3.7 V 3.3 V

3.1 V

VDS 10 V

ID , DRAIN CURRENT (AMPS)

3.0

2.7 V 2.5 V 2.3 V 2.1 V 1.9 V 1.7 V

3.0

2.0

2.0

1.0

1.0

100C

25C TJ = -55C

0.4 0.8 1.2 1.6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

2.0

1.0

2.0

3.0

4.0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.4 0.6 0.5 0.4 0.3 0.2 0.1 0

Figure 2. Transfer Characteristics

TJ = 25C

0.3

ID = 1.3 A TJ = 25C

0.2

VGS = 2.7 V

0.1

4.5 V

2.0

4.0

6.0

8.0

10

1.0

2.0 ID, DRAIN CURRENT (AMPS)

3.0

4.0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance versus Drain Current

Figure 4. OnResistance versus Drain Current and Gate Voltage


100

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.0 VGS = 4.5 V ID = 0.8 A IDSS , LEAKAGE (nA) 1.5

TJ = 125C 10 100C

1.0

1.0 25C 0.1 VGS = 0 V 0 4.0 8.0 12 16 20 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.5

-50

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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339

MGSF2P02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
800 Ciss C, CAPACITANCE (pF) 600 VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

400 Ciss Coss Crss 0 -10 VGS 0 VDS 10 20

200

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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340

MGSF2P02HD
VGS, GATETOSOURCE VOLTAGE (VOLTS) 5.0 QT 4.0 3.0 Q1 2.0 1.0 Q3 0 0 1.0 2.0 3.0 4.0 5.0 0 6.0 ID = 1.2 A TJ = 25C Q2 VDS VGS 16 12 VDS , DRAINTOSOURCE VOLTAGE (VOLTS) 20 1000 VDD = 10 V ID = 1.2 A VGS = 4.5 V TJ = 25C

t, TIME (ns)

100

8.0 4.0

tf td(off) tr

10

td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2.0 IS, SOURCE CURRENT (AMPS) 1.6 1.2 0.8 VGS = 0 V TJ = 25C I S , SOURCE CURRENT

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

di/dt = 300 A/s

Standard Cell Density trr High Cell Density trr tb ta

0.4 0

0.4

0.5

0.6

0.7

0.8

0.9

1.0 t, TIME

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Figure 11. Reverse Recovery Time (trr)

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341

MGSF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1.0 0.5 TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.0001 0.001 0.01 0.1 t, TIME (s) P(pk) t1 t2 DUTY CYCLE, D = t1/t2 1.0 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 RJC(t) = r(t) RJC TJ(pk) - TC = P(pk) RJC(t) 10 100

Figure 12. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 13. Diode Reverse Recovery Waveform

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342

MGSF2P02HD INFORMATION FOR USING THE TSOP6 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.094 2.4

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm

TSOP6 POWER DISSIPATION The power dissipation of the TSOP6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP6 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 400 milliwatts.
PD = 150C 25C 312C/W = 400 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 312C/W for the TSOP6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 400 milliwatts. There are other alternatives to achieving higher power dissipation from the TSOP6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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343

MGSF3442VT1
Preferred Device

Power MOSFET 4 Amps, 20 Volts


NChannel TSOP6
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature TSOP6 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Mounted on FR4 t  5 sec Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 20 8.0 4.0 20 2.0 55 to 150 62.5 260 W C C/W C
3 2 1

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4 AMPERES 20 VOLTS RDS(on) = 70 m


NChannel 1 2 5 6

Unit Vdc Vdc A 3

MARKING DIAGRAM

TSOP6 CASE 318G STYLE 1

442 W

442 W

= Device Code = Work Week

PIN ASSIGNMENT
Drain Drain Source
6 5 4

Drain Drain Gate

ORDERING INFORMATION
Device MGSF3442VT1 Package TSOP6 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

344

November, 2000 Rev. 1

Publication Order Number: MGSF3442VT1/D

MGSF3442VT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 4.0 A) (VGS = 2.5 Vdc, ID = 3.4 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 1.0 5.0 1.2 A A V (VDD = 10 Vdc, ID = 1.0 A, VGEN = 10 V, RL = 10 ) td(on) tr td(off) tf QT 8.0 24 36 10 20 40 60 20 nC ns (VDS = 5.0 V) (VDS = 5.0 V) (VDG = 5.0 V) Ciss Coss Crss 90 50 10 pF VGS(th) 0.6 rDS(on) 0.058 0.072 0.070 0.095 Ohms Vdc V(BR)DSS 20 IDSS IGSS 1.0 5.0 100 nAdc Adc Vdc Symbol Min Typ Max Unit

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345

MGSF3442VT1
TYPICAL ELECTRICAL CHARACTERISTICS
20 16 ID, DRAIN CURRENT (A) 12 8.0 4.0 1.5 V 0 0 1.0 2.0 3.0 4.0 5.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 2.0 V 20 2.5 V ID , DRAIN CURRENT (A) 16 12 8.0 4.0 TC = -55C 125C 25C

VGS = 4.5 V 4.0 V 3.5 V

3.0 V

VDS, DRAIN-TO-SOURCE VOLTAGE (V)

VGS, GATE-TO-SOURCE VOLTAGE (V)

Figure 1. Output Characteristics


0.14 R DS(on) , ON-RESISTANCE ( W ) 0.12 0.10 0.08 0.06 0.04 0.02 0 0 4.0 8.0 12 16 20 VGS = 4.5 V VGS = 2.5 V C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0

Figure 2. Transfer Characteristics

Ciss Coss Crss 0 4.0 8.0 12 16 20

ID, DRAIN CURRENT (A)

VDS, DRAIN-TO-SOURCE VOLTAGE (V)

Figure 3. OnResistance versus Drain Current


R DS(on) , ON-RESISTANCE ( W ) (NORMALIZED) 5.0 VGS , GATE-TO-SOURCE VOLTAGE (V) 4.0 3.0 2.0 1.0 0 VDS = 10 V ID = 4.0 A 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50

Figure 4. Capacitance

VGS = 4.5 V ID = 4.0 A

2.0

4.0

6.0

8.0

-25

25

50

75

100

125

150

Qg, TOTAL GATE CHARGE (nC)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. Gate Charge

Figure 6. OnResistance versus Junction Temperature

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346

MGSF3442VT1
TYPICAL ELECTRICAL CHARACTERISTICS
20 TJ = 150C IS , SOURCE CURRENT (A) 10 R DS(on) , ON-RESISTANCE ( W ) TJ = 25C 0.20 ID = 4.0 A 0.16 0.12 0.08 0.04 0

1.0

0.25

0.50

0.75

1.00

1.25

1.50

2.0

4.0

6.0

8.0

VSD, SOURCE-TO-DRAIN VOLTAGE (V)

VGS, GATE-TO-SOURCE VOLTAGE (V)

Figure 7. SourceDrain Diode Forward Voltage

Figure 8. OnResistance versus GatetoSource Voltage


20 16 POWER (W)

0.2 0.1 V GS(th) , VARIANCE (V) 0 -0.1 -0.2 -0.3 -0.4 -50

ID = 250 mA

12 8.0 4.0 0

-25

25

50

75

100

125

150

0.01

0.1

1.0 TIME (sec)

10

TJ, TEMPERATURE (C)

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

2.0 NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 1.0 DUTY CYCLE = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.0001 SINGLE PULSE 0.001 0.01 0.1 t1 NOTES: PDM 1. DUTY CYCLE, D = t1/t2 2. PER UNIT BASE = 2. RthJA = 62.5C/W 3. TJM - TA = PDMZthJA(t) 4. SURFACE MOUNTED 1.0 10 30

t2

SQUARE WAVE PULSE DURATION (sec)

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

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347

MGSF3442VT1 INFORMATION FOR USING THE TSOP6 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.094 2.4

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm

TSOP6 POWER DISSIPATION The power dissipation of the TSOP6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP6 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 watts.
PD = 150C 25C 62.5C/W = 2.0 watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the TSOP6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 watts. There are other alternatives to achieving higher power dissipation from the TSOP6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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348

MGSF3454VT1
Preferred Device

Power MOSFET 4 Amps, 30 Volts


NChannel TSOP6
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature TSOP6 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C Mounted on FR4 t 5 sec Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg RJA TL Value 30 20 4.2 20 2.0 55 to 150 62.5 260 W C C/W C
3 2 1

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4 AMPERES 30 VOLTS RDS(on) = 65 m


NChannel 1 2 5 6

Unit Vdc Vdc A 3

MARKING DIAGRAM

TSOP6 CASE 318G STYLE 1

3P W

3P W

= Device Code = Work Week

PIN ASSIGNMENT
Drain Drain Source
6 5 4

Drain Drain Gate

ORDERING INFORMATION
Device MGSF3454VT1 Package TSOP6 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

349

November, 2000 Rev. 1

Publication Order Number: MGSF3454VT1/D

MGSF3454VT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 70C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 4.2 A) (VGS = 4.5 Vdc, ID = 3.4 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 1.0 5.0 1.2 A A V (VDD = 10 Vdc, ID = 1.0 A, VGEN = 10 V, RL = 10 ) td(on) tr td(off) tf QT 10 15 20 10 20 30 35 20 15 nC ns (VDS = 5.0 V) (VDS = 5.0 V) (VDG = 5.0 V) Ciss Coss Crss 90 50 10 pF VGS(th) 1.0 rDS(on) 0.05 0.07 0.065 0.095 Ohms Vdc V(BR)DSS 30 IDSS IGSS 1.0 25 100 nAdc Adc Vdc Symbol Min Typ Max Unit

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350

MGSF3454VT1
TYPICAL ELECTRICAL CHARACTERISTICS
20 VGS = 10, 9, 8, 7, 6V I D , DRAIN CURRENT (A) 16 12 8 4 3V 0 0 1 2 3 4 0 0 1 2 3 4 5 6 4V 20 16 12 8 4

5V I D , DRAIN CURRENT (A)

TJ = -55C 25C 125C

VDS, DRAIN-TO-SOURCE VOLTAGE (V)

VGS, GATE-TO-SOURCE VOLTAGE (V)

Figure 1. Output Characteristics


0.20 R DS(on) , ON-RESISTANCE (OHMS) 0.16 0.12 0.08 0.04 0 VGS = 4.5 V VGS = 10 V C, CAPACITANCE (pF) 560 480 400 320 240 160 80 0 4 8 12 ID, DRAIN CURRENT (A) 16 20 0 0

Figure 2. Transfer Characteristics

Ciss

Coss

Crss 6 12 18 24 30

VDS - DRAIN-TO-SOURCE VOLTAGE (V)

Figure 3. OnResistance vs. Drain Current

Figure 4. Capacitance

10 VGS, GATE-TO-SOURCE VOLTAGE (V) 8 6 4 2 0 RDS(on) , ON-RESISTANCE (OHMS) (NORMALIZED) VDS = 15 V ID = 4.2 A

1.75 VGS = 10 V ID = 4.2 A 1.50

1.25

1.00

1.5

3.0

4.5

6.0

7.5

9.0

0.75 -50

-25

Qg, TOTAL GATE CHARGE (nC)

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. Gate Charge

Figure 6. OnResistance vs. Junction Temperature

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351

MGSF3454VT1
TYPICAL ELECTRICAL CHARACTERISTICS
40 RDS(on) , ON-RESISTANCE (OHMS) I S , SOURCE CURRENT (A) 0.20 0.16 0.12 0.08 0.04 0 ID = 4.2 A

10

TJ = 150C TJ = 25C

0.25

0.50

0.75

1.00

1.25

1.5

1.75

VSD, SOURCE-TO-DRAIN VOLTAGE (V)

2 4 6 8 VGS - GATE-TO-SOURCE VOLTAGE (V)

10

Figure 7. SourceDrain Diode Forward Voltage


0.4 0.2 V GS(th) , VARIANCE (V) 0.0 -0.2 -0.4 -0.6 -0.8 -50 -25 0 25 50 75 100 125 150

Figure 8. OnResistance vs. GatetoSource Voltage

30 24 POWER (W) ID = 250 A 18 12 6 0 0.01

TJ, TEMPERATURE (C)

0.10

1.00 TIME (sec)

10.00

Figure 9. Threshold Voltage

Figure 10. Single Pulse Power

2 NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 1.0E-04 SINGLE PULSE 1.0E-03 1.0E-02 t2 DUTY CYCLE, D = t1/t2 1.0E-01 Square Wave Pulse Duration (sec) t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 11. Normalized Thermal Transient Impedance, JunctiontoAmbient

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352

MGSF3454VT1 INFORMATION FOR USING THE TSOP6 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.094 2.4

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0 inches mm

TSOP6 POWER DISSIPATION The power dissipation of the TSOP6 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the TSOP6 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 watts.
PD = 150C 25C 62.5C/W = 2.0 watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the TSOP6 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 watts. There are other alternatives to achieving higher power dissipation from the TSOP6 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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353

MLD1N06CL
Preferred Device

SMARTDISCRETESt MOSFET 1 Amp, 62 Volts, Logic Level


NChannel DPAK
The MLD1N06CL is designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontrol unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high inrush current or a shorted load condition could occur. This Logic Level Power MOSFET features current limiting for short circuit protection, integrated GateSource clamping for ESD protection and integral GateDrain clamping for overvoltage protection and Sensefet technology for low onresistance. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition. The internal GateSource and GateDrain clamps allow the device to be applied without use of external transient suppression components. The GateSource clamp protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The GateDrain clamp protects the MOSFET drain from the avalanche stress that occurs with inductive loads. Their unique design provides voltage clamping that is essentially independent of operating temperature.
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous Single Pulse Total Power Dissipation Operating and Storage Temperature Range Electrostatic Discharge Voltage (Human Model) Symbol VDSS VDGR Value Clamped Clamped Unit Vdc Vdc 1 2 3 VGS ID IDM PD TJ, Tstg ESD 10 Selflimited 1.8 40 50 to 150 2.0 Vdc Adc Apk Watts C kV L1N06C Y WW T 4 CASE 369A DPAK STYLE 2 = Device Code = Year = Work Week = MOSFET

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1 AMPERE 62 VOLTS (Clamped) RDS(on) = 750 m


NChannel D

R1

R2 S

MARKING DIAGRAM
YWW L1N 06C

PIN ASSIGNMENT
4 Drain

THERMAL CHARACTERISTICS
Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 sec. C/W RJC RJA RJA TL 3.12 100 71.4 260 C 1 Gate 2 Drain 3 Source

ORDERING INFORMATION
Device MLD1N06CLT4 Package DPAK Shipping 2500 Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

354

November, 2000 Rev. 1

Publication Order Number: MLD1N06CL/D

MLD1N06CL
UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS
Rating Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C Symbol EAS Value 80 Unit mJ

ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (Internally Clamped) (ID = 20 mAdc, VGS = 0 Vdc) (ID = 20 mAdc, VGS = 0 Vdc, TJ = 150C) Zero Gate Voltage Drain Current (VDS = 45 Vdc, VGS = 0 Vdc) (VDS = 45 Vdc, VGS = 0 Vdc, TJ = 150C) GateSource Leakage Current (VG = 5.0 Vdc, VDS = 0 Vdc) (VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150C) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (ID = 250 Adc, VDS = VGS) (ID = 250 Adc, VDS = VGS, TJ = 150C) Static DraintoSource OnResistance (ID = 1.0 Adc, VGS = 4.0 Vdc) (ID = 1.0 Adc, VGS = 5.0 Vdc) (ID = 1.0 Adc, VGS = 4.0 Vdc, TJ = 150C) (ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150C) Static SourcetoDrain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc) Static Drain Current Limit (VGS = 5.0 Vdc, VDS = 10 Vdc) (VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150C) Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) RESISTIVE SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 4.5 nH nH (VDD = 25 Vdc, ID = 1.0 Adc, VGS(on) = 5.0 Vdc, RGS = 50 Ohms) td(on) tr td(off) tf 1.2 4.0 4.0 3.0 2.0 6.0 6.0 5.0 ns VGS(th) 1.0 0.6 RDS(on) VSD ID(lim) 2.0 1.1 gFS 1.0 2.3 1.3 1.4 2.75 1.8 mhos 0.63 0.59 1.1 1.0 1.1 0.75 0.75 1.9 1.8 1.5 Vdc Adc 1.5 2.0 1.6 Ohms Vdc V(BR)DSS 59 59 IDSS IGSS 0.5 1.0 5.0 20 0.6 6.0 5.0 20 Adc 62 62 65 65 Adc Vdc Symbol Min Typ Max Unit

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355

MLD1N06CL
4 TJ = 25C ID , DRAIN CURRENT (AMPS) VDS 7.5 V

-50C

ID , DRAIN CURRENT (AMPS)

10 V 6V

8V 4V

3 25C 2 TJ = 150C

VGS = 3 V

1 0

2 4 6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

2 4 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics THE SMARTDISCRETES CONCEPT

Figure 2. Transfer Function SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE

From a standard power MOSFET process, several active and passive elements can be obtained that provide onchip protection to the basic power device. Such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The SMARTDISCRETES device functions can now provide an economical alternative to smart power ICs for power applications requiring low onresistance, high voltage and high current. These devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high inrush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE

The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. Without some form of current limiting, a shorted load can raise a devices junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLD1N06CL can withstand a shorted load powered by an automotive battery (10 to 14 Volts) for almost a second if its initial operating temperature is under 100C. For longer periods of operation in the currentlimited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided.

The onchip circuitry of the MLD1N06CL offers an integrated means of protecting the MOSFET component from high inrush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistors base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the voltage across the gatetosource of the power MOSFET and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3 Amps at 25C to about 1.3 Amps at 150C. Since the MLD1N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C. The metal current sense resistor R2 adds about 0.4 ohms to the power MOSFETs onresistance, but the effect of temperature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The onresistance variation with temperature for gate voltages of 4 and 5 Volts is shown in Figure 5. Backtoback polysilicon diodes between gate and source provide ESD protection to greater than 2 kV, HBM. This onchip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients.

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356

MLD1N06CL
4 R DS(on), ON-RESISTANCE (OHMS) ID(lim) , DRAIN CURRENT (AMPS) VGS=5V VDS=7.5V 3 4 ID = 1 A

2 25C 1 TJ=-50C

150C

0 -50

0 0 50 100 TJ, JUNCTION TEMPERATURE (C) 150

2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

Figure 3. ID(lim) Variation With Temperature

Figure 4. RDS(on) Variation With GateToSource Voltage

1.25 RDS(on), ON-RESISTANCE (OHMS)

ID = 1 A

1 VGS = 4 V 0.75 VGS=5 V 0.5

0.25 -50

0 50 100 TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation With Temperature

BV(DSS) , DRAIN-SOURCE SUSTAINING VOLTAGE (VOLTS)

WAS , SINGLE PULSE AVALANCHE ENERGY (mJ)

100 80 60 40 20 0

64

63

62

61

25

50

75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

60 -50

0 50 100 TJ, JUNCTION TEMPERATURE (C)

150

Figure 6. Single Pulse Avalanche Energy versus Junction Temperature

Figure 7. DrainSource Sustaining Voltage Variation With Temperature

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357

MLD1N06CL
FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal Resistance General Data and Its Use provides detailed instructions.
MAXIMUM DC VOLTAGE CONSIDERATIONS

(1.8 A at 150C) and not the RDS(on). The maximum voltage can be calculated by the following equation:
Vsupply = (150 TA) ID(lim) (RJC + RCA)

where the value of RCA is determined by the heatsink that is being used in the application.
DUTY CYCLE OPERATION

When operating in the duty cycle mode, the maximum drain voltage can be increased. The maximum operating temperature is related to the duty cycle (DC) by the following equation:
TC = (VDS x ID x DC x RCA) + TA

The maximum draintosource voltage that can be continuously applied across the MLD1N06CL when it is in current limit is a function of the power that must be dissipated. This power is determined by the maximum current limit at maximum rated operating temperature
10 ID , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C

The maximum value of VDS applied when operating in a duty cycle mode can be approximated by:
VDS = 150 TC ID(lim) x DC x RJC

10 s 1.0 100 s 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

0.1 0.1

dc 100

1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Forward Bias Safe Operating Area (MLD1N06CL)

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

0.01 1.0E-05

1.0E+00

1.0E+01

Figure 9. Thermal Response (MLD1N06CL)

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358

MLD1N06CL
VDD RL Vin z = 50 50 INPUT, Vin Vout DUT td(on) ton tr 90% td(off) toff tf 90%

PULSE GENERATOR Rgen 50

OUTPUT, Vout INVERTED

10% 90% 50% 10% PULSE WIDTH 50%

Figure 10. Switching Test Circuit ACTIVE CLAMPING

Figure 11. Switching Waveforms

SMARTDISCRETES technology can provide onchip realization of the popular gatetosource and gatetodrain Zener diode clamp elements. Until recently, such features have been implemented only with discrete components which consume board space and add system cost. The SMARTDISCRETES technology approach economically melds these features and the power chip with only a slight increase in chip area. In practice, backtoback diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. Each backtoback diode element provides a temperature compensated voltage element of about 7.2 volts. As the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. To achieve high gatetodrain clamp voltages, several voltage elements are strung together; the MLD1N06CL uses 8 such elements. Customarily, two voltage elements are used to provide a 14.4 volt gatetosource voltage clamp. For the

MLD1N06CL, the integrated gatetosource voltage elements provide greater than 2.0 kV electrostatic voltage protection. The avalanche voltage of the gatetodrain voltage clamp is set less than that of the power MOSFET device. As soon as the draintosource voltage exceeds this avalanche voltage, the resulting gatetodrain Zener current builds a gate voltage across the gatetosource impedance, turning on the power device which then conducts the current. Since virtually all of the current is carried by the power device, the gatetodrain voltage clamp element may be small in size. This technique of establishing a temperature compensated draintosource sustaining voltage (Figure 7) effectively removes the possibility of draintosource avalanche in the power device. The gatetodrain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. An improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gatetodrain clamped conduction mode rather than in the more stressful gatetosource avalanche mode.

TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS The MLD1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.
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MLP1N06CL
Preferred Device

SMARTDISCRETESt MOSFET 1 Amp, 62 Volts, Logic Level


NChannel TO220
These SMARTDISCRETES devices feature current limiting for short circuit protection, an integral gatetosource clamp for ESD protection and gatetodrain clamp for overvoltage protection. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition. The internal gatetosource and gatetodrain clamps allow the devices to be applied without use of external transient suppression components. The gatetosource clamp protects the MOSFET input from electrostatic gate voltage stresses up to 2.0 kV. The gatetodrain clamp protects the MOSFET drain from drain avalanche stresses that occur with inductive loads. This unique design provides voltage clamping that is essentially independent of operating temperature. Temperature Compensated GatetoDrain Clamp Limits Voltage Stress Applied to the Device and Protects the Load From Overvoltage Integrated ESD Diode Protection Controlled Switching Minimizes RFI Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous Drain Current Single Pulse Total Power Dissipation Electrostatic Discharge Voltage (Human Body Model) Operating and Storage Junction Temperature Range Symbol VDSS VDGR VGS ID IDM PD ESD TJ, Tstg Value Clamped Clamped 10 Selflimited 1.8 40 2.0 50 to 150 Unit Vdc Vdc Vdc Adc Watts kV C L1N06CL LL Y WW 1 2 TO220AB CASE 221A STYLE 5 4

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1 AMPERE 62 VOLTS (Clamped) RDS(on) = 750 m


NChannel D

R1

R2

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

L1N06CL LLYWW 3 Source 2 Drain

1 Gate

THERMAL CHARACTERISTICS
Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case RJC RJA TL 3.12 62.5 260 C/W

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MLP1N06CL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

360

November, 2000 Rev. 2

Publication Order Number: MLP1N06CL/D

MLP1N06CL
UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS
Rating Single Pulse DraintoSource Avalanche Energy (Starting TJ = 25C, ID = 2.0 A, L = 40 mH) (Figure 6) Symbol EAS Value 80 Unit mJ

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


Characteristic OFF CHARACTERISTICS DraintoSource Sustaining Voltage (Internally Clamped) (ID = 20 mA, VGS = 0) (ID = 20 mA, VGS = 0, TJ = 150C) Zero Gate Voltage Drain Current (VDS = 45 V, VGS = 0) (VDS = 45 V, VGS = 0, TJ = 150C) GateBody Leakage Current (VG = 5.0 V, VDS = 0) (VG = 5.0 V, VDS = 0, TJ = 150C) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (ID = 250 A, VDS = VGS) (ID = 250 A, VDS = VGS, TJ = 150C) Static DraintoSource OnResistance (ID = 1.0 A, VGS = 4.0 V) (ID = 1.0 A, VGS = 5.0 V) (ID = 1.0 A, VGS = 4.0 V, TJ = 150C) (ID = 1.0 A, VGS = 5.0 V, TJ = 150C) Forward Transconductance (ID = 1.0 A, VDS = 10 V) Static SourcetoDrain Diode Voltage (IS = 1.0 A, VGS = 0) Static Drain Current Limit (VGS = 5.0 V, VDS = 10 V) (VGS = 5.0 V, VDS = 10 V, TJ = 150C) RESISTIVE SWITCHING CHARACTERISTICS (Note 1.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time 1. Indicates Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. (VDD = 25 V, ID = 1.0 A, VGS = 5.0 V, RG = 50 Ohms) td(on) tr td(off) tf 1.2 4.0 4.0 3.0 2.0 6.0 6.0 5.0 s VGS(th) 1.0 0.6 RDS(on) gFS VSD ID(lim) 2.0 1.1 2.3 1.3 2.75 1.8 1.0 0.63 0.59 1.1 1.0 1.4 1.1 0.75 0.75 1.9 1.8 1.5 mhos Vdc A 1.5 2.0 1.6 Ohms Vdc V(BR)DSS 59 59 IDSS IGSS 0.5 1.0 5.0 20 0.6 6.0 5.0 20 Adc 62 62 65 65 Adc Vdc Symbol Min Typ Max Unit

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MLP1N06CL
4 TJ = 25C ID , DRAIN CURRENT (AMPS) VDS 7.5 V

-50C

ID , DRAIN CURRENT (AMPS)

10 V 6V

8V 4V

3 25C 2 TJ = 150C

VGS = 3 V

1 0

2 4 6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

2 4 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics THE SMARTDISCRETES CONCEPT

Figure 2. Transfer Function SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE

From a standard power MOSFET process, several active and passive elements can be obtained that provide onchip protection to the basic power device. Such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The SMARTDISCRETES device functions can now provide an economical alternative to smart power ICs for power applications requiring low onresistance, high voltage and high current. These devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high inrush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE

The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. Without some form of current limiting, a shorted load can raise a devices junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLP1N06CL can withstand a shorted load powered by an automotive battery (10 to 14 Volts) for almost a second if its initial operating temperature is under 100C. For longer periods of operation in the currentlimited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided.

The onchip circuitry of the MLP1N06CL offers an integrated means of protecting the MOSFET component from high inrush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistor s base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the voltage across the gatetosource of the power MOSFET and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3 Amps at 25C to about 1.3 Amps at 150C. Since the MLP1N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C. The metal current sense resistor R2 adds about 0.4 ohms to the power MOSFETs onresistance, but the effect of temperature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The onresistance variation with temperature for gate voltages of 4 and 5 Volts is shown in Figure 5. Backtoback polysilicon diodes between gate and source provide ESD protection to greater than 2 kV, HBM. This onchip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients.

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MLP1N06CL
4 R DS(on), ON-RESISTANCE (OHMS) ID(lim) , DRAIN CURRENT (AMPS) VGS=5V VDS=7.5V 3 4 ID = 1 A

2 25C 1 TJ=-50C

150C

0 -50

0 0 50 100 TJ, JUNCTION TEMPERATURE (C) 150

2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

Figure 3. ID(lim) Variation With Temperature

Figure 4. RDS(on) Variation With GateToSource Voltage

1.25 RDS(on), ON-RESISTANCE (OHMS)

ID = 1 A

1 VGS = 4 V 0.75 VGS=5 V 0.5

0.25 -50

0 50 100 TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance Variation With Temperature

BV(DSS) , DRAIN-SOURCE SUSTAINING VOLTAGE (VOLTS)

WAS , SINGLE PULSE AVALANCHE ENERGY (mJ)

100 80 60 40 20 0

64

63

62

61

25

50

75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

60 -50

0 50 100 TJ, JUNCTION TEMPERATURE (C)

150

Figure 6. Single Pulse Avalanche Energy versus Junction Temperature

Figure 7. DrainSource Sustaining Voltage Variation With Temperature

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363

MLP1N06CL
FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal Resistance General Data and Its Use provides detailed instructions.
MAXIMUM DC VOLTAGE CONSIDERATIONS

(1.8 A at 150C) and not the RDS(on). The maximum voltage can be calculated by the following equation:
Vsupply = (150 TA) ID(lim) (RJC + RCA)

where the value of RCA is determined by the heatsink that is being used in the application.
DUTY CYCLE OPERATION

When operating in the duty cycle mode, the maximum drain voltage can be increased. The maximum operating temperature is related to the duty cycle (DC) by the following equation:
TC = (VDS x ID x DC x RCA) + TA

The maximum draintosource voltage that can be continuously applied across the MLP1N06CL when it is in current limit is a function of the power that must be dissipated. This power is determined by the maximum current limit at maximum rated operating temperature
10 6 I D , DRAIN CURRENT (AMPS) 3 2 1 0.6 0.3 0.2 0.1 1 ID(lim)-MAX ID(lim)-MIN

The maximum value of VDS applied when operating in a duty cycle mode can be approximated by:
VDS = 150 TC ID(lim) x DC x RJC

1.5 ms 5ms dc

1ms

VGS=5V SINGLE PULSE TC = 25C 2 3

DEVICE/POWER LIMITED RDS(on) LIMITED

10

20

30

60

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Forward Bias Safe Operating Area (MLP1N06CL)

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 0.7 0.5 0.3 0.2

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 t, TIME (ms)

0.1 0.07 0.05 0.03 0.02 0.01 0.01

RJC(t) = r(t) RJC RJC(t) = 3.12C/W Max D Curves Apply for Power Pulse Train Shown Read Time at t1 TJ(pk) - TC = P(pk) RJC(t) P(pk) t2 DUTY CYCLE, D =t1/t2 100 200 300 500 1000 t1

Figure 9. Thermal Response (MLP1N06CL)

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364

MLP1N06CL
VDD RL Vin z = 50 50 INPUT, Vin Vout DUT td(on) ton tr 90% td(off) toff tf 90%

PULSE GENERATOR Rgen 50

OUTPUT, Vout INVERTED

10% 90% 50% 10% PULSE WIDTH 50%

Figure 10. Switching Test Circuit ACTIVE CLAMPING

Figure 11. Switching Waveforms

SMARTDISCRETES technology can provide onchip realization of the popular gatetosource and gatetodrain Zener diode clamp elements. Until recently, such features have been implemented only with discrete components which consume board space and add system cost. The SMARTDISCRETES technology approach economically melds these features and the power chip with only a slight increase in chip area. In practice, backtoback diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. Each backtoback diode element provides a temperature compensated voltage element of about 7.2 volts. As the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. To achieve high gatetodrain clamp voltages, several voltage elements are strung together; the MLP1N06CL uses 8 such elements. Customarily, two voltage elements are used to provide a 14.4 volt gatetosource voltage clamp. For the

MLP1N06CL, the integrated gatetosource voltage elements provide greater than 2.0 kV electrostatic voltage protection. The avalanche voltage of the gatetodrain voltage clamp is set less than that of the power MOSFET device. As soon as the draintosource voltage exceeds this avalanche voltage, the resulting gatetodrain Zener current builds a gate voltage across the gatetosource impedance, turning on the power device which then conducts the current. Since virtually all of the current is carried by the power device, the gatetodrain voltage clamp element may be small in size. This technique of establishing a temperature compensated draintosource sustaining voltage (Figure 7) effectively removes the possibility of draintosource avalanche in the power device. The gatetodrain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. An improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gatetodrain clamped conduction mode rather than in the more stressful gatetosource avalanche mode.

TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS The MLP1N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.
VBAT VDD

D MCU G S MLP1N06CL

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365

MLP2N06CL
Preferred Device

SMARTDISCRETESt MOSFET 2 Amps, 62 Volts, Logic Level


NChannel TO220
This logic level power MOSFET features current limiting for short circuit protection, integrated GateSource clamping for ESD protection and integral GateDrain clamping for overvoltage protection and Sensefet technology for low onresistance. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition. The internal GateSource and GateDrain clamps allow the device to be applied without use of external transient suppression components. The GateSource clamp protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The GateDrain clamp protects the MOSFET drain from the avalanche stress that occurs with inductive loads. Their unique design provides voltage clamping that is essentially independent of operating temperature.
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TC = 25C Total Power Dissipation @ TC = 25C Electrostatic Voltage Operating and Storage Temperature Range Symbol VDSS VDGR VGS ID PD ESD TJ, Tstg Value Clamped Clamped 10 Selflimited 40 2.0 50 to 150 Unit Vdc Vdc Vdc Adc Watts kV C TO220AB CASE 221A STYLE 5 1 S R2

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2 AMPERES 62 VOLTS (Clamped) RDS(on) = 400 m


NChannel D

R1

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

THERMAL CHARACTERISTICS
Maximum Junction Temperature Thermal Resistance Junction to Case Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 sec. TJ(max) RJC TL 150 3.12 260 C C/W C 2 1 Gate

L2N06CL LLYWW 3 Source 2 Drain

DRAINTOSOURCE AVALANCHE CHARACTERISTICS


Single Pulse DraintoSource Avalanche Energy (Starting TJ = 25C, ID = 2.0 A, L = 40 mH) EAS 80 mJ

L2N06CL LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MLP2N06CL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

366

November, 2000 Rev. 1

Publication Order Number: MLP2N06CL/D

MLP2N06CL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (ID = 20 mAdc, VGS = 0 Vdc) (ID = 20 mAdc, VGS = 0 Vdc, TJ = 150C) Zero Gate Voltage Drain Current (VDS = 40 Vdc, VGS = 0 Vdc) (VDS = 40 Vdc, VGS = 0 Vdc, TJ = 150C) GateSource Leakage Current (VG = 5.0 Vdc, VDS = 0 Vdc) (VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150C) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (ID = 250 Adc, VDS = VGS) (ID = 250 Adc, VDS = VGS, TJ = 150C) Static Drain Current Limit (VGS = 5.0 Vdc, VDS = 10 Vdc) (VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150C) Static DraintoSource OnResistance (ID = 1.0 Adc, VGS = 5.0 Vdc) (ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150C) Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) Static SourcetoDrain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc) SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time (VDD = 30 Vdc, ID = 1.0 Adc, VGS(on) = 5.0 Vdc, RGS = 25 Ohms) td(on) tr td(off) tf 1.0 3.0 5.0 3.0 1.5 5.0 8.0 5.0 s VGS(th) 1.0 0.6 ID(lim) 3.8 1.6 RDS(on) gFS VSD 1.1 1.5 1.0 0.3 0.53 1.4 0.4 0.7 mhos Vdc 4.4 2.4 5.2 2.9 Ohms 1.5 1 2.0 1.6 Adc Vdc V(BR)DSS 58 58 IDSS IGSS 0.5 1.0 5.0 20 0.6 6.0 5.0 20 Adc 62 62 66 66 Adc Vdc Symbol Min Typ Max Unit

1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature.

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MLP2N06CL
5 4 3 2 1 0 TJ = 25C 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 4.0 I D , DRAIN CURRENT (AMPS) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 6 8 0 0 1 2 3 4 5 6 7 8 VDS 7.5 V -55C 25C TJ = 150C

I D , DRAIN CURRENT (AMPS)

2.5 V 2.0 V 0 2 4 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics THE SMARTDISCRETES CONCEPT

Figure 2. Transfer Function SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE

From a standard power MOSFET process, several active and passive elements can be obtained that provide onchip protection to the basic power device. Such elements require only a small increase in silicon area and/or the addition of one masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The SMARTDISCRETES device functions can now provide an economical alternative to smart power ICs for power applications requiring low onresistance, high voltage and high current. These devices are designed for applications that require a rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector driver, incandescent lamp driver or other applications where a high inrush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE

The amount of time that an unprotected device can withstand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the device, its initial junction temperature, and the supply voltage. Without some form of current limiting, a shorted load can raise a devices junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLP2N06CL can withstand a shorted load powered by an automotive battery (10 to 14 Volts) for almost a second if its initial operating temperature is under 100C. For longer periods of operation in the currentlimited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the amount of heatsinking provided.

The onchip circuitry of the MLP2N06CL offers an integrated means of protecting the MOSFET component from high inrush current or a shorted load. As shown in the schematic diagram, the current limiting feature is provided by an NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistors base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, dropping the gate drive voltage across it, and thus lowering the voltage across the gatetosource of the power MOSFET and limiting the current. The current limit is temperature dependent as shown in Figure 3, and decreases from about 2.3 Amps at 25C to about 1.3 Amps at 150C. Since the MLP2N06CL continues to conduct current and dissipate power during a shorted load condition, it is important to provide sufficient heatsinking to limit the device junction temperature to a maximum of 150C. The metal current sense resistor R2 adds about 0.4 ohms to the power MOSFETs onresistance, but the effect of temperature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The onresistance variation with temperature for gate voltages of 4 and 5 Volts is shown in Figure 5. Backtoback polysilicon diodes between gate and source provide ESD protection to greater than 2 kV, HBM. This onchip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients.

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MLP2N06CL
6 I D(lim) , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 -50 0 50 100 150 RDS(on) , ON-RESISTANCE (OHMS) VGS = 5 V VDS = 10 V 1.0 ID = 1 A 0.8 0.6 0.4 25C 0.2 0 TJ = -50C 0 1 7 8 2 3 4 5 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 9 10 100C

TJ, JUNCTION TEMPERATURE (C)

Figure 3. ID(lim) Variation With Temperature

Figure 4. RDS(on) Variation With GateToSource Voltage

0.6 RDS(on) , ON-RESISTANCE (OHMS) ID = 1 A 0.5 0.4 0.3 0.2 0.1 0 -50 0 50 100 TJ, JUNCTION TEMPERATURE (C) 150 VGS = 4 V VGS = 5 V

Figure 5. OnResistance Variation With Temperature

ID = 2 A 80 60 40 20 0 25

BV(DSS) , DRAIN-TO-SOURCE SUSTAINING VOLTAGE (VOLTS)

100 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

64.0 63.5 63.0 62.5 62.0 61.5 61.0 60.5 60.0 -50 0 50 100 TJ = JUNCTION TEMPERATURE 150 ID = 20 mA

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 6. Maximum Avalanche Energy versus Starting Junction Temperature

Figure 7. DrainSource Sustaining Voltage Variation With Temperature

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369

MLP2N06CL
FORWARD BIASED SAFE OPERATING AREA

The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal Resistance General Data and Its Use provides detailed instructions.
MAXIMUM DC VOLTAGE CONSIDERATIONS

(1.8 A at 150C) and not the RDS(on). The maximum voltage can be calculated by the following equation:
Vsupply = (150 TA) ID(lim) (RJC + RCA)

where the value of RCA is determined by the heatsink that is being used in the application.
DUTY CYCLE OPERATION

When operating in the duty cycle mode, the maximum drain voltage can be increased. The maximum operating temperature is related to the duty cycle (DC) by the following equation:
TC = (VDS x ID x DC x RCA) + TA

The maximum draintosource voltage that can be continuously applied across the MLP2N06CL when it is in current limit is a function of the power that must be dissipated. This power is determined by the maximum current limit at maximum rated operating temperature
10 ID , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C

The maximum value of VDS applied when operating in a duty cycle mode can be approximated by:
VDS = 150 TC ID(lim) x DC x RJC

1.0

dc 10 ms 1 ms

0.1 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

Figure 8. Maximum Rated Forward Bias Safe Operating Area (MLP2N06CL)

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

0.01 1.0E-05

1.0E+00

1.0E+01

Figure 9. Thermal Response (MLP2N06CL)

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MLP2N06CL
VDD RL Vin z = 50 50 INPUT, Vin Vout DUT td(on) ton tr 90% td(off) toff tf 90%

PULSE GENERATOR Rgen 50

OUTPUT, Vout INVERTED

10% 90% 50% 10% PULSE WIDTH 50%

Figure 10. Switching Test Circuit ACTIVE CLAMPING

Figure 11. Switching Waveforms

SMARTDISCRETES technology can provide onchip realization of the popular gatetosource and gatetodrain Zener diode clamp elements. Until recently, such features have been implemented only with discrete components which consume board space and add system cost. The SMARTDISCRETES technology approach economically melds these features and the power chip with only a slight increase in chip area. In practice, backtoback diode elements are formed in a polysilicon region monolithicly integrated with, but electrically isolated from, the main device structure. Each backtoback diode element provides a temperature compensated voltage element of about 7.2 volts. As the polysilicon region is formed on top of silicon dioxide, the diode elements are free from direct interaction with the conduction regions of the power device, thus eliminating parasitic electrical effects while maintaining excellent thermal coupling. To achieve high gatetodrain clamp voltages, several voltage elements are strung together; the MLP2N06CL uses 8 such elements. Customarily, two voltage elements are used to provide a 14.4 volt gatetosource voltage clamp. For the

MLP2N06CL, the integrated gatetosource voltage elements provide greater than 2.0 kV electrostatic voltage protection. The avalanche voltage of the gatetodrain voltage clamp is set less than that of the power MOSFET device. As soon as the draintosource voltage exceeds this avalanche voltage, the resulting gatetodrain Zener current builds a gate voltage across the gatetosource impedance, turning on the power device which then conducts the current. Since virtually all of the current is carried by the power device, the gatetodrain voltage clamp element may be small in size. This technique of establishing a temperature compensated draintosource sustaining voltage (Figure 7) effectively removes the possibility of draintosource avalanche in the power device. The gatetodrain voltage clamp technique is particularly useful for snubbing loads where the inductive energy would otherwise avalanche the power device. An improvement in ruggedness of at least four times has been observed when inductive energy is dissipated in the gatetodrain clamped conduction mode rather than in the more stressful gatetosource avalanche mode.

TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS The MLP2N06CL has been designed to allow direct interface to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a 40 k gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The internal clamps allow the device to be used without any external transistent suppressing components.
VBAT VDD

D MCU G S MLP2N06CL

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371

MMBF0201NLT1
Preferred Device

Power MOSFET 300 mAmps, 20 Volts


NChannel SOT23
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C(1) Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID ID IDM PD TJ, Tstg RJA TL Value 20 20 300 240 750 225 55 to 150 556 260 mW C C/W C
1 2

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300 mAMPS 20 VOLTS RDS(on) = 1 W


NChannel 3

Unit Vdc Vdc mAdc 1

MARKING DIAGRAM
3

SOT23 CASE 318 STYLE 21

N1 W

N1 W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device MMBF0201NLT1 Package SOT23 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

372

November, 2000 Rev. 2

Publication Order Number: MMBF0201NLT1/D

MMBF0201NLT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 300 mAdc) (VGS = 4.5 Vdc, ID = 100 mAdc) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 5) SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 2.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. IS ISM VSD 0.85 0.3 0.75 V A (VDD = 15 Vdc, ID = 300 mAdc, RL = 50 ) td(on) tr td(off) tf QT 2.5 2.5 15 0.8 1400 pC ns (VDS = 5.0 V) (VDS = 5.0 V) (VDG = 5.0 V) Ciss Coss Crss 45 25 5.0 pF VGS(th) rDS(on) gFS 0.75 1.0 450 1.0 1.4 mMhos 1.0 1.7 2.4 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 20 Vdc Adc Symbol Min Typ Max Unit

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373

MMBF0201NLT1
TYPICAL ELECTRICAL CHARACTERISTICS
1.0 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 0.8 0.6 0.4 0.2 0 1.0 0.8 0.6 0.4 0.2 0

VGS = 5 V VGS = 4 V VGS = 10, 9, 8, 7, 6 V

125C 25C -55C

VGS = 3 V 0 0.3 0.6 0.9 1.2 1.4

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Transfer Characteristics


1.5 1.2 0.9 0.6 VGS = 10 V 0.3 0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 2.4 2.0

Figure 2. OnRegion Characteristics

ON-RESISTANCE (OHMS)

VGS = 4.5 V

1.5 1.0 0.5

0.2

0.4 0.6 ID, DRAIN CURRENT (AMPS)

0.8

5 10 15 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

20

Figure 3. OnResistance versus Drain Current

Figure 4. OnResistance versus GatetoSource Voltage


1.10 1.05 1.00 ID = 250 A

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

16 14 VDS = 16 V ID = 300 mA VGS(th) , NORMALIZED 12 10 8 6 4 2 0 0 160 450 2000 3400

0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 -25 0 25 50 75 100 125 150

Qg, TOTAL GATE CHARGE (pC)

TEMPERATURE (C)

Figure 5. Gate Charge

Figure 6. Threshold Voltage Variance Over Temperature

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374

MMBF0201NLT1
TYPICAL ELECTRICAL CHARACTERISTICS
1.8 RDS(on) , NORMALIZED (OHMS) 1.6 1.4 1.2 1.0 0.8 0.6 -50 VGS = 4.5 V @ 100 mA VGS = 10 V @ 300 mA C, CAPACITANCE (pF) 100 80 60 40 20 0 Ciss Coss Crss 0 5 10 15 20 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 7. OnResistance versus Junction Temperature

Figure 8. Capacitance

10

SOURCE CURRENT (AMPS)

1.0

0.1 125C 25C -55C

0.01

0.001

0.3 0.6 0.9 1.2 SOURCE-TO-DRAIN FORWARD VOLTAGE (VOLTS)

1.4

Figure 9. SourcetoDrain Forward Voltage versus Continuous Current (IS)

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375

MMBF0201NLT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150C 25C 556C/W = 225 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 556C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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376

MMBF0202PLT1
Preferred Device

Power MOSFET 300 mAmps, 20 Volts


PChannel SOT23
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SOT23 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID ID IDM PD TJ, Tstg RJA TL Value 20 20 300 240 750 225 55 to 150 625 260 mW C C/W C
1 2 3

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300 mAMPS 20 VOLTS RDS(on) = 1.4 W


PChannel 3

Unit Vdc Vdc mAdc 1

MARKING DIAGRAM

SOT23 CASE 318 STYLE 21

P3 W

1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

P3 W

= Device Code = Work Week

PIN ASSIGNMENT
3

Drain

Gate

Source

ORDERING INFORMATION
Device MMBF0202PLT1 Package SOT23 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

377

November, 2000 Rev. 1

Publication Order Number: MMBF0202PLT1/D

MMBF0202PLT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 200 mAdc) (VGS = 4.5 Vdc, ID = 50 mAdc) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 5) (VDS = 16 V, VGS = 10 V, ID = 200 mA) (VDD = 15 Vdc, RL = 75 , ID = 200 mAdc, mAdc 10 V, RG = 6.0 ) VGEN = 10 td(on) tr td(off) tf QT 2.5 1.0 16 8.0 2700 pC ns (VDS = 5.0 V) (VDS = 5.0 V) (VDG = 5.0 V) Ciss Coss Crss 50 45 20 pF VGS(th) rDS(on) gFS 0.9 2.0 600 1.4 3.5 mMhos 1.0 1.7 2.4 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 20 Vdc Adc Symbol Min Typ Max Unit

SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 3.) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. IS ISM VSD 1.5 0.3 0.75 V A

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378

MMBF0202PLT1
TYPICAL ELECTRICAL CHARACTERISTICS
1.0 TC = -55C I D , DRAIN CURRENT (AMPS) 0.8 125C 0.6 0.4 0.2 0 I D , DRAIN CURRENT (AMPS) 25C 1.0 5V 0.8 0.6 0.4 0.2 0 3V VGS = 10, 9, 8, 7, 6 V 4V

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. Transfer Characteristics


5 4 3 2 1 0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 5 4

Figure 2. OnRegion Characteristics

ON-RESISTANCE (OHMS)

200 mA 3 2 1 0

VGS = 4.5 V VGS = 10 V 0 100 200 300 ID, DRAIN CURRENT (AMPS) 400 500

50 mA

-5 -10 -15 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

-20

Figure 3. OnResistance versus Drain Current

Figure 4. OnResistance versus GatetoSource Voltage


1.20

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

16 14 12 10 8 6 4 2 0 0 230 690 2270 3500 590 ID = 200 mA 2160 VDS = 10 V VDS = 16 V VGS(th) , NORMALIZED

1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 TEMPERATURE (C)

ID = 250 A

100

125

150

Qg, TOTAL GATE CHARGE (pC)

Figure 5. Gate Charge

Figure 6. Threshold Voltage Variance Over Temperature

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379

MMBF0202PLT1
TYPICAL ELECTRICAL CHARACTERISTICS
1.30 1.25 RDS(on) , NORMALIZED (OHMS) 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 VGS = 10 V @ 200 mA C, CAPACITANCE (pF) VGS = 4.5 V @ 50 mA 140 120 100 80 60 40 20 0 0 5 10 Ciss Coss Crss 15 20 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (C)

Figure 7. OnResistance versus Junction Temperature

Figure 8. Capacitance

10

SOURCE CURRENT (AMPS)

1.0 TJ = 150C 0.1 -55C 25C

0.01

0.001

3 4 1 2 SOURCE-TO-DRAIN FORWARD VOLTAGE (VOLTS)

4.5

Figure 9. SourcetoDrain Forward Voltage versus Continuous Current (IS)

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380

MMBF0202PLT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150C 25C 556C/W = 225 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 556C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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381

MMBF1374T1
Preferred Device

Small Signal MOSFET 50 mAmps, 30 Volts


NChannel SC70/SOT323
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SC70/SOT323 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Pulse Drain Current Continuous @ TA = 25C Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purposes, for 10 seconds Symbol VDS VGS ID PD 100 TJ, Tstg TL 55 to 150 260 mW C C 3 SC70/SOT323 CASE 419 STYLE 8 1 2 F1 W = Device Code = Work Week F1 W Value 20 20 50 Unit Vdc Vdc mAdc G S

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50 mAMPS 30 VOLTS RDS(on) = 50 W


NChannel D

MARKING DIAGRAM

1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.

PIN ASSIGNMENT
3 Drain

Gate 1

2 Source Top View

ORDERING INFORMATION
Device MMBF1374T1 Package SC70/ SOT323 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

382

January, 2001 Rev. 0

Publication Order Number: MMBF1374T1/D

MMBF1374T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 10 mAdc) Forward Transconductance (VDS = 10 Vdc, ID = 50 mAdc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. (VDD = 15 Vdc, ID = 50 mAdc, RL = 50 ) td(on) tr td(off) tf 2.5 2.5 15 0.8 ns (VDS = 5.0 V) (VDS = 5.0 V) (VDG = 5.0 V) Ciss Coss Crss 45 25 5.0 pF VGS(th) rDS(on) gFS 2 27 450 2.8 50 Vdc mMhos V(BR)DSS IDSS IGSS 30 1.0 1.0 Vdc Adc Adc Symbol Min Typ Max Unit

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383

MMBF170LT1 Power MOSFET 500 mAmps, 60 Volts


NChannel SOT23
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 ms) Drain Current Continuous Pulsed Symbol VDSS VDGS VGS VGSM ID IDM Value 60 60 20 40 0.5 0.8 Unit Vdc Vdc Vdc Vpk Adc

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500 mAMPS 60 VOLTS RDS(on) = 5 W


NChannel 3

THERMAL CHARACTERISTICS
Characteristic Total Device Dissipation FR5 Board (Note 1.) TA = 25C Derate above 25C Thermal Resistance, Junction to Ambient Junction and Storage Temperature 1. FR5 = 1.0  0.75  0.062 in. Symbol PD 225 1.8 RqJA TJ, Tstg 556 55 to +150 mW mW/C C/W C 2 Max Unit 1

MARKING DIAGRAM
3

1 2

SOT23 CASE 318 STYLE 21

6Z W

6Z W

= Device Code = Work Week

PIN ASSIGNMENT
3 Drain

Gate 1

2 Source

ORDERING INFORMATION
Device MMBF170LT1 MMBF170LT3 Package SOT23 SOT23 Shipping 3000 Tape & Reel 10,000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

384

November, 2000 Rev. 3

Publication Order Number: MMBF170LT1/D

MMBF170LT1
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 100 mA) GateBody Leakage Current, Forward (VGSF = 15 Vdc, VDS = 0) V(BR)DSS IGSS 60 10 Vdc nAdc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 200 mA) OnState Drain Current (VDS = 25 Vdc, VGS = 0) VGS(th) rDS(on) ID(off) 0.8 3.0 5.0 0.5 Vdc W mA

DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 10 Vdc, VGS = 0 V, f = 1.0 MHz) Ciss 60 pF

SWITCHING CHARACTERISTICS (Note 2.)


TurnOn Delay Time TurnOff Delay Time (VDD = 25 Vdc, ID = 500 mA, Rgen = 50 W) Figure 1 td(on) td(off) 10 10 ns

2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%. +25 V

ton td(on) TO SAMPLING SCOPE 50 W INPUT Vout OUTPUT INVERTED Vout INPUT

PULSE GENERATOR 50 W

Vin 40 pF

125 W 20 dB 50 W ATTENUATOR

tr 90% 10%

td(off)

90%

toff tf

50 W

1 MW

Vin

10%

50% PULSE WIDTH

90% 50%

(Vin AMPLITUDE 10 VOLTS)

Figure 1. Switching Test Circuit

Figure 2. Switching Waveform

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385

MMBF170LT1
TYPICAL ELECTRICAL CHARACTERISTICS

2.0 1.8 I D, DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN SOURCE VOLTAGE (VOLTS) TA = 25C I D, DRAIN CURRENT (AMPS) VGS = 10 V 9V 8V 7V 6V 5V 4V 3V 9.0 10

1.0 VDS = 10 V 0.8 0.6 0.4 0.2 -55C 125C 25C

1.0

2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, GATE SOURCE VOLTAGE (VOLTS)

9.0

10

Figure 3. Ohmic Region

Figure 4. Transfer Characteristics

r DS(on) , STATIC DRAIN-SOURCE ON-RESISTANCE (NORMALIZED)

2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VGS = 10 V ID = 200 mA

VGS(th) , THRESHOLD VOLTAGE (NORMALIZED)

2.4

1.2 1.05 1.1 1.10 1.0 0.95 0.9 0.85 0.8 0.75 0.7 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VDS = VGS ID = 1.0 mA

Figure 5. Temperature versus Static DrainSource OnResistance

Figure 6. Temperature versus Gate Threshold Voltage

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386

MMBF170LT1 INFORMATION FOR USING THE SOT23 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.037 0.95

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.037 0.95

0.079 2.0 0.035 0.9 0.031 0.8


inches mm

SOT23 POWER DISSIPATION The power dissipation of the SOT23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT23 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 225 milliwatts.
PD = 150C 25C 556C/W = 225 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 556C/W for the SOT23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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387

MMBF2201NT1
Preferred Device

Power MOSFET 300 mAmps, 20 Volts


NChannel SC70/SOT323
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SC70/SOT323 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, for 10 seconds Symbol VDSS VGS ID ID IDM PD 150 1.2 TJ, Tstg RJA TL 55 to 150 833 260 mW mW/C C C/W C 1 2 N1 W = Device Code = Work Week 3 SC70/SOT323 CASE 419 STYLE 8 N1 W Value 20 20 300 240 750 Unit Vdc Vdc mAdc 2 1

http://onsemi.com

300 mAMPS 20 VOLTS RDS(on) = 1 W


NChannel 3

MARKING DIAGRAM

1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.

PIN ASSIGNMENT
3 Drain

Gate 1

2 Source Top View

ORDERING INFORMATION
Device MMBF2201NT1 Package SC70/ SOT323 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

388

November, 2000 Rev. 3

Publication Order Number: MMBF2201NT1/D

MMBF2201NT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 300 mAdc) (VGS = 4.5 Vdc, ID = 100 mAdc) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 5) SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 3.) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. IS ISM VSD 0.85 0.3 0.75 V A (VDD = 15 Vdc, ID = 300 mAdc, RL = 50 ) td(on) tr td(off) tf QT 2.5 2.5 15 0.8 1400 pC ns (VDS = 5.0 V) (VDS = 5.0 V) (VDG = 5.0 V) Ciss Coss Crss 45 25 5.0 pF VGS(th) rDS(on) gFS 0.75 1.0 450 1.0 1.4 mMhos 1.0 1.7 2.4 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 20 Vdc Adc Symbol Min Typ Max Unit

TYPICAL CHARACTERISTICS
1.0 0.9 RDS , ON RESISTANCE (OHMS) ID , DRAIN CURRENT (AMPS) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 VGS = 3 V VGS = 2.5 V 4 7 8 2 3 5 6 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 9 10 VGS = 3.5 V VGS = 4 V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 160 VGS = 4.5 V ID = 100 mA VGS = 10 V ID = 300 mA

Figure 1. Typical Drain Characteristics http://onsemi.com


389

Figure 2. On Resistance versus Temperature

MMBF2201NT1
TYPICAL CHARACTERISTICS
10 RDS , ON RESISTANCE (OHMS) 8 6 4 2 0 ID = 300 mA RDS , ON RESISTANCE (OHMS) 1.2 1.0 0.8 0.6 0.4 0.2 0 VGS = 4.5 V

VGS = 10 V

6 7 8 3 4 5 GATE-SOURCE VOLTAGE (VOLTS)

10

0.1

0.2

0.5 0.3 0.4 0.6 ID, DRAIN CURRENT (AMPS)

0.7

0.8

Figure 3. On Resistance versus GateSource Voltage

Figure 4. On Resistance versus Drain Current

1.0 I S , SOURCE CURRENT (AMPS)

45 40 C, CAPACITANCE (pF) 35 30 25 20 15 10 5 0 Ciss Coss Crss 0 2 4 8 12 16 6 10 14 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 18 20 VGS = 0 V F = 1 mHz

0.1

0.01

0.001

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE-DRAIN FORWARD VOLTAGE (VOLTS)

1.0

Figure 5. SourceDrain Forward Voltage

Figure 6. Capacitance Variation

1.0 0.9 I D , DRAIN CURRENT (AMPS) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VGS, GATE-SOURCE VOLTAGE (VOLTS) 4.0 4.5 -55 25 150

Figure 7. Transfer Characteristics

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390

MMBF2201NT1 INFORMATION FOR USING THE SC70/SOT323 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.025 0.65

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.025 0.65

0.075 1.9 0.035 0.9 0.028 0.7 inches mm

SC70/SOT323 POWER DISSIPATION The power dissipation of the SC70/SOT323 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SC70 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 150 milliwatts.
PD = 150C 25C 833C/W = 150 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 833C/W for the SC70/SOT323 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. There are other alternatives to achieving higher power dissipation from the SC70/SOT323 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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391

MMBF2202PT1
Preferred Device

Power MOSFET 300 mAmps, 20 Volts


PChannel SC70/SOT323
These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in small power management circuitry. Typical applications are dcdc converters, power management in portable and batterypowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature SC70/SOT323 Surface Mount Package Saves Board Space
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C Operating and Storage Temperature Range Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, for 10 seconds Symbol VDSS VGS ID ID IDM PD 150 1.2 TJ, Tstg RJA TL 55 to 150 833 260 mW mW/C C C/W C 1 2 P3 W = Device Code = Work Week 3 SC70/SOT323 CASE 419 STYLE 8 P3 W Value 20 20 300 240 750 Unit Vdc Vdc mAdc 2 1

http://onsemi.com

300 mAMPS 20 VOLTS RDS(on) = 2.2 W


PChannel 3

MARKING DIAGRAM

1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.

PIN ASSIGNMENT
3 Drain

Gate 1

2 Source Top View

ORDERING INFORMATION
Device MMBF2202PT1 Package SC70/ SOT323 Shipping 3000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

392

November, 2000 Rev. 3

Publication Order Number: MMBF2202PT1/D

MMBF2202PT1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 200 mAdc) (VGS = 4.5 Vdc, ID = 50 mAdc) Forward Transconductance (VDS = 10 Vdc, ID = 200 mAdc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 5) (VDS = 16 V, VGS = 10 V, ID = 200 mA) (VDD = 15 Vdc, RL = 75 , ID = 200 mAdc, mAdc 10 V, RG = 6.0 ) VGEN = 10 td(on) tr td(off) tf QT 2.5 1.0 16 8.0 2700 pC ns (VDS = 5.0 V) (VDS = 5.0 V) (VDG = 5.0 V) Ciss Coss Crss 50 45 20 pF VGS(th) rDS(on) gFS 1.5 2.0 600 2.2 3.5 mMhos 1.0 1.7 2.4 Vdc Ohms V(BR)DSS IDSS IGSS 1.0 10 100 nAdc 20 Vdc Adc Symbol Min Typ Max Unit

SOURCEDRAIN DIODE CHARACTERISTICS Continuous Current Pulsed Current Forward Voltage (Note 3.) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. IS ISM VSD 1.5 0.3 0.75 V A

TYPICAL CHARACTERISTICS
10 rDS(on) , ON RESISTANCE (OHMS) 8 6 4 2 0 ID = 200 mA rDS(on) , ON RESISTANCE (OHMS) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 100 120 140 160 VGS = 10 V ID = 200 mA VGS = 4.5 V ID = 50 mA

10

VGS, GATE-SOURCE VOLTAGE (VOLTS)

TEMPERATURE (C)

Figure 1. On Resistance versus GateSource Voltage http://onsemi.com


393

Figure 2. On Resistance versus Temperature

MMBF2202PT1
TYPICAL CHARACTERISTICS
6 RDS(on) , ON RESISTANCE (OHMS) 5 4 3 2 1 0 VGS = 10 V VGS = 4.5 V 1.0 0.9 I D, DRAIN CURRENT (AMPS) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -55 150 25

ID, DRAIN CURRENT (AMPS)

VGS, GATE-SOURCE VOLTAGE (VOLTS)

Figure 3. On Resistance versus Drain Current

Figure 4. Transfer Characteristics

1 ID(on), DRAIN CURRENT (AMPS) IS , SOURCE CURRENT (AMPS)

0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6

VGS = 5 V

25 0.1 150

VGS = 4.5 V VGS = 4 V VGS = 3.5 V VGS = 3 V 7 8 9 10

0.01

0.001

0.5

1.0

1.5

2.0

2.5

VSD, SOURCE-DRAIN FORWARD VOLTAGE (VOLTS)

VDS, DRAIN-SOURCE VOLTAGE (VOLTS)

Figure 5. SourceDrain Forward Voltage

Figure 6. On Region Characteristics

50 45 40 C, CAPACITANCE (pF) 35 30 25 20 15 10 5 0 0 2 4 6 8 10 12 14 Ciss Coss Crss 16 18 20 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) VGS = 0 V f = 1 MHz

Figure 7. Capacitance Variation

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394

MMBF2202PT1 INFORMATION FOR USING THE SC70/SOT323 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.025 0.65

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.025 0.65

0.075 1.9 0.035 0.9 0.028 0.7 inches mm

SC70/SOT323 POWER DISSIPATION The power dissipation of the SC70/SOT323 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SC70/SOT323 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

one can calculate the power dissipation of the device which in this case is 150 milliwatts.
PD = 150C 25C 833C/W = 150 milliwatts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C,

The 833C/W for the SC70/SOT323 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. There are other alternatives to achieving higher power dissipation from the SC70/SOT323 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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395

MMDF1300 Power MOSFET 3 Amps, 25 Volts


Complementary SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed, with Soft Recovery
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Drain Current Continuous NChannel PChannel Drain Current Pulsed NChannel PChannel Operating and Storage Temperature Range Total Power Dissipation @ TA = 25C Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 25 mH, RG = 25 W) Thermal Resistance JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 sec. Symbol VDSS VGS ID 3.0 2.0 IDM 9.0 6.0 TJ, Tstg PD EAS 65 to +150 1.8 C Watts mJ Apk Value 25 20 Unit Vdc Vdc Adc 8 1 1300 L Y WW = Device Code = Location Code = Year = Work Week SO8, Dual CASE 751 STYLE 11 1300 LYWW

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3 AMPERES 25 VOLTS RDS(on) = 100 mW (NChannel) RDS(on) = 210 mW (PChannel)


NChannel D PChannel D

G S

G S

MARKING DIAGRAM

PIN ASSIGNMENT
113 Source1 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

RJA TL

66.3 260

C/W C

Gate1 Source2 Gate2

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Device MMDF1300R2

Top View

ORDERING INFORMATION
Package SO8 Shipping 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2001

396

March, 2001 Rev. 1

Publication Order Number: MMDF1300/D

MMDF1300
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Notes 2. & 3.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc) DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge td(on) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) tr td(off) tf QT Q1 Q2 Q3 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Negative signs for PChannel device omitted for clarity. 4. Switching characteristics are independent of operating junction temperature. (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 18 14 98 95 16 22 30 40 3.3 7.0 1.2 1.2 2.0 2.5 1.9 3.5 36 28 196 180 32 45 60 80 5.0 10 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss (N) (P) (N) (P) (N) (P) 215 200 111 100 30 40 301 300 158 160 60 75 pF VGS(th) RDS(on) RDS(on) (N) (P) gFS (N) (P) 1.0 1.0 0.13 0.30 0.16 0.375 mhos (N) (P) (N) (P) 1.0 1.0 1.5 2.0 0.09 0.16 2.0 3.0 0.10 0.21 Vdc Ohms Ohms V(BR)DSS IDSS IGSS (N) (P) 30 1.0 1.0 100 Adc nAdc Vdc Symbol Polarity Min Typ Max Unit

(VDS = 16 Vdc, ID = 2 2.0 0 Adc Adc, VGS = 4.5 Vdc)

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397

MMDF1300
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted)
Characteristic SOURCEDRAIN DIODE CHARACTERISTICS (Note 5.) Forward OnVoltage (Note 6.) Reverse Recovery Time (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr (N) (ID = 2.0 Adc, VGS = 0 Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge 5. Negative signs for PChannel device omitted for clarity. 6. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. ta tb QRR (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 1.0 1.3 23 20 18 13 5.0 7.0 0.02 0.02 1.4 1.7 C Vdc ns Symbol Polarity Min Typ Max Unit

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398

MMDF1N05E Power MOSFET 1 Amp, 50 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed Avalanche Energy Specified Mounting Information for SO8 Package Provided IDSS Specified at Elevated Temperature
8

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1 AMPERE 50 VOLTS RDS(on) = 300 mW


NChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous Drain Current Pulsed Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 V, VGS = 10 V, IL = 2 Apk) Operating and Storage Temperature Range Total Power Dissipation @ TA = 25C Thermal Resistance Junction to Ambient (Note 1.) Maximum Temperature for Soldering, Time in Solder Bath Symbol VDS VGS ID IDM EAS Value 50 20 2.0 10 300 Unit Volts Volts Amps mJ

SO8, Dual CASE 751 STYLE 11 1 F1N05 L Y WW = Device Code = Location Code = Year = Work Week

F1N05 LYWW

PIN ASSIGNMENT
Source1 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

TJ, Tstg PD RJA TL

55 to 150 2.0 62.5 260 10

C Watts C/W C Sec

Gate1 Source2 Gate2

Top View

ORDERING INFORMATION
Device MMDF1N05ER2 Package SO8 Shipping 2500 Tape & Reel

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Semiconductor Components Industries, LLC, 2000

399

November, 2000 Rev. 6

Publication Order Number: MMDF1N05E/D

MMDF1N05E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0, ID = 250 A) Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 0.6 Adc) Forward Transconductance (VDS = 15 V, ID = 1.5 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 2.) Reverse Recovery Time (IS = 1.5 A, VGS = 0 V) (dIS/dt = 100 A/s) VSD trr 45 1.6 V ns (VDS = 10 V V, ID = 1.5 15A A, VGS = 10 V) (VDD = 10 V, ID = 1.5 A, RL = 10 , VG = 10 V, RG = 50 ) td(on) tr td(off) tf Qg Qgs Qgd 12.5 1.9 3.0 20 30 40 25 nC ns (VDS = 25 V V, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 330 160 50 pF VGS(th) 1.0 3.0 Vdc Ohms RDS(on) RDS(on) gFS 1.5 0.30 0.50 mhos V(BR)DSS IDSS IGSS 50 250 100 Vdc Adc nAdc Symbol Min Typ Max Unit

2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 3. Switching characteristics are independent of operating junction temperature.

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400

MMDF1N05E
TYPICAL ELECTRICAL CHARACTERISTICS
10 I D , DRAIN CURRENT (AMPS) 8 4.5 V 6 4V 4 2 0 VGS = 3.5 V 10 5V I D , DRAIN CURRENT (AMPS) 8 6 4 2 100C 0 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 10 0 0 1 2 3 -55C 4 5 6 7 8 VDS 10 V

10 V

6V 8V

TJ = 25C

-55C

25C 100C

25C

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25

Figure 2. Transfer Characteristics

0.5 0.4 VGS = 10 V

VGS = 10 V ID = 1.5 A

0.3 0.2 0.1 -55C 0 0 2 4 6 ID, DRAIN CURRENT (AMPS) 8

100C 25C

25 75 0 50 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 3. OnResistance versus Drain Current


V GS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 4. OnResistance Variation with Temperature

0.5 0.4 0.3 0.2 0.1 0 ID = 1.5 A VGS = 0

1.2 1.1 1 0.9 0.8 0.7 -50 VDS = VGS ID = 1 mA

5 6 7 8 TJ, JUNCTION TEMPERATURE

10

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. On Resistance versus GateToSource Voltage

Figure 6. Gate Threshold Voltage Variation with Temperature

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401

MMDF1N05E
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 VDS = 0 VGS = 0 Ciss Coss Crss 20 10 0 20 25 15 5 5 10 15 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS Ciss Crss TJ = 25C 0 VDS VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 0 2 4 6 10 8 12 Qg, TOTAL GATE CHARGE (nC) 14 16 VDS = 25 V ID = 1.2 A

Figure 7. Capacitance Variation

Figure 8. Gate Charge versus GateToSource Voltage


100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

SAFE OPERATING AREA INFORMATION


Forward Biased Safe Operating Area

The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal Resistance General Data and Its Use provides detailed instructions.

10

10 ms 1 dc

100 s

10 s

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 9. Maximum Rated Forward Biased Safe Operating Area

10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 10. Thermal Response

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MMDF1N05E INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. These can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C 62.5C/W = 2.0 Watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF2C01HD
Preferred Device

Power MOSFET 2 Amps, 12 Volts


Complementary SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)
Rating DraintoSource Voltage NChannel PChannel GatetoSource Voltage Drain Current Continuous Pulsed NChannel PChannel NChannel PChannel Symbol VDSS 20 12 VGS ID IDM TJ and Tstg PD RJA TL 8.0 5.2 3.4 48 17 55 to 150 2.0 62.5 260 Vdc A Value Unit Vdc 8 1 D2C01 L Y WW = Device Code = Location Code = Year = Work Week SO8, Dual CASE 751 STYLE 14 D2C01 LYWW

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2 AMPERES 12 VOLTS RDS(on) = 45 mW (NChannel) RDS(on) = 180 mW (PChannel)


NChannel D PChannel D

G S

G S

MARKING DIAGRAM

Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds.

PIN ASSIGNMENT
Watts NSource C/W C NGate PSource PGate 1 2 3 4 8 7 6 5 NDrain NDrain PDrain PDrain

Top View

1. Negative signs for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device MMDF2C01HDR2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

404

November, 2000 Rev. 6

Publication Order Number: MMDF2C01HD/D

MMDF2C01HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 20 Vdc) (VGS = 0 Vdc, VDS = 12 Vdc) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 4.0 Adc) (VGS = 4.5 Vdc, ID = 2.0 Adc) DraintoSource OnResistance (VGS = 2.7 Vdc, ID = 2.0 Adc) (VGS = 2.7 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 2.5 Adc, ID = 2.0 Adc) (VDS = 2.5 Adc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time (VDS = 6.0 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc, RG = 2.3 ) (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (VDD = 6.0 Vdc, ID = 4.0 Adc, VGS = 2.7 Vdc, RG = 2.3 ) (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 2.7 Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 13 21 60 156 20 38 29 68 10 16 42 44 24 68 28 54 26 45 120 315 40 75 58 135 20 35 84 90 48 135 56 110 ns (VDS = 10 Vdc, VGS = 0 Vdc, f = 1.0 MHz) ) Ciss Coss Crss (N) (P) (N) (P) (N) (P) 425 530 270 410 115 177 595 740 378 570 230 250 pF VGS(th) RDS(on) (N) (P) RDS(on) (N) (P) gFS (N) (P) 3.0 3.0 6.0 4.75 0.043 0.2 0.055 0.22 mhos 0.035 0.16 0.045 0.18 Ohm (N) (P) 0.7 0.7 0.8 1.0 1.1 1.1 Vdc Ohm V(BR)DSS IDSS (N) (P) IGSS 100 1.0 1.0 nAdc (N) (P) 20 12 Vdc Adc Symbol Polarity Min Typ Max Unit

3. Negative signs for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature.

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MMDF2C01HD
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted) (Note 6.)
Characteristic SWITCHING CHARACTERISTICS continued (Note 8.) Total Gate Charge GateSource Charge GateDrain Charge (VDS = 10 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc) (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc) QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) Reverse Recovery Time (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta (IF = IS, dIS/dt = 100 A/s) Reverse Recovery Stored Charge tb QRR (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 0.95 1.69 38 48 17 23 22 25 0.028 0.05 1.1 2.0 C Vdc ns (N) (P) (N) (P) (N) (P) (N) (P) 9.2 9.3 1.3 0.8 3.5 4.0 3.0 3.0 13 13 nC Symbol Polarity Min Typ Max Unit

6. Negative signs for PChannel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Switching characteristics are independent of operating junction temperature.

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406

MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
8 I D , DRAIN CURRENT (AMPS) 4.5 V 3.1 V 6 2.7 V 2.3 V 2.5 V VGS = 8 V 2.1 V TJ = 25C I D , DRAIN CURRENT (AMPS) 4 VGS = 8 V 4.5 V 3.1 V 2.7 V 2.1 V

PChannel
2.5 V 2.3 V TJ = 25C

1.9 V 1.7 V

1.9 V 1 1.7 V 1.5 V 0

2 1.5 V 1.3 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 1. OnRegion Characteristics

8 I D , DRAIN CURRENT (AMPS)

VDS 10 V I D , DRAIN CURRENT (AMPS)

VDS 10 V

100C 25C

2 100C 25C TJ = -55C

TJ = -55C

1.2

1.4

1.6

1.8

2.2

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

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MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.07 TJ = 25C ID = 2 A 0.06 0.35 0.30 0.25 0.20 0.15 0.1 TJ = 25C ID = 1 A

PChannel

0.05

0.04

0.03

6 2 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

6 2 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance versus GateToSource Voltage


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.050 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) TJ = 25C VGS = 2.7 V 0.30

Figure 3. OnResistance versus GateToSource Voltage


TJ = 25C

0.045

0.25

0.040 4.5 V

0.20

VGS = 2.7 V 4.5 V

0.035

0.15

0.030

6 4 ID, DRAIN CURRENT (AMPS)

0.10

0.8

1.6 2.4 ID, DRAIN CURRENT (AMPS)

3.2

Figure 4. OnResistance versus Drain Current and Gate Voltage


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2 VGS = 4.5 V ID = 4 A 2

Figure 4. OnResistance versus Drain Current and Gate Voltage

1.5

1.5

VGS = 4.5 V ID = 2 A

0.5

0.5

0 -50

-25

25

50

75

100

125

150

0 -50

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature http://onsemi.com


408

Figure 5. OnResistance Variation with Temperature

MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
100 VGS = 0 V TJ = 125C I DSS , LEAKAGE (nA) I DSS , LEAKAGE (nA) TJ = 125C 100 1000 VGS = 0 V

PChannel

10

100C

2 4 6 8 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

12

10

4 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

12

Figure 6. DrainToSource Leakage Current versus Voltage

Figure 6. DrainToSource Leakage Current versus Voltage

POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

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MMDF2C01HD
NChannel
2000 1600 C, CAPACITANCE (pF) 1200 800 400 0 Crss Coss Crss 8 4 VGS 0 VDS 4 8 12 VDS = 0 V Ciss VGS = 0 V TJ = 25C 2000 1600 C, CAPACITANCE (pF) 1200 800 400 0 Crss Ciss Coss 8 4 VGS 0 VDS 4 8 Crss 12 Ciss VDS = 0 V

PChannel
VGS = 0 V TJ = 25C

Ciss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Figure 7. Capacitance Variation

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

QT VGS

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

5 4 3 Q1 2 1 0 VDS Q2

10 8 6 ID = 4 A TJ = 25C 4 2 0 10

5 QT 4 VDS 3 2 Q1 1 Q3 0 0 2 4 6 8 ID = 2 A TJ = 25C VGS

10 8 6 4 2 0 10

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Q2

Q3 0 2 4 6 8

QT, TOTAL CHARGE (nC)

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

100 VDD = 6 V ID = 4 A VGS = 4.5 V TJ = 25C 10 tr tf

1000 VDD = 6 V ID = 2 A VGS = 4.5 V TJ = 25C t, TIME (ns) 100 td(off) tf tr td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100

t, TIME (ns)

td(off) td(on)

1 0.1

10

100

10

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 9. Resistive Switching Time Variation versus Gate Resistance

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MMDF2C01HD
DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
NChannel
4 VV == 00 VV GS GS TJ TJ == 25 25 C C 2 VGS = 0 V TJ = 25C 1.5

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

PChannel

I S , SOURCE CURRENT (AMPS)

I S , SOURCE CURRENT (AMPS) 0.5 0.6 0.7 1

0.5

0 0.3

0.4

0.8

0.9

0 0.4

0.6

0.8

1.2

1.4

1.6

1.8

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Figure 10. Diode Forward Voltage versus Current

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411

MMDF2C01HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
NChannel
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 1 100 I D , DRAIN CURRENT (AMPS) 10 s 100 s 1 ms VGS = 8 V SINGLE PULSE TC = 25C

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

PChannel
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

10

10

1 ms 10 ms

dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT


Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

dc

0.1

0.1

0.01 0.1

10

100

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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412

MMDF2C01HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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413

MMDF2C01HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF2C01HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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415

MMDF2C02E Advance Information Power MOSFET 2.5 Amps, 25 Volts


Complementary SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, with Soft Recovery Avalanche Energy Specified Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)
Rating DraintoSource Voltage GatetoSource Voltage Drain Current Continuous NChannel PChannel Pulsed NChannel PChannel Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A, L = 6.0 mH, RG = 25 ) NChannel (VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A, L = 10 mH, RG = 25 ) PChannel Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds. Symbol VDSS VGS ID IDM TJ and Tstg PD EAS Value 25 20 3.6 2.5 18 13 55 to 150 2.0 Unit Vdc Vdc Adc F2C02 L Y WW = Device Code = Location Code = Year = Work Week 1 8

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2.5 AMPERES 25 VOLTS RDS(on) = 100 mW (NChannel) RDS(on) = 250 mW (PChannel)


NChannel D PChannel D

G S

G S

MARKING DIAGRAM

SO8, Dual CASE 751 STYLE 14

F2C02 LYWW

C Watts mJ

PIN ASSIGNMENT
NSource NGate PSource PGate 1 2 3 4 8 7 6 5 NDrain NDrain PDrain PDrain

245 245 RJA TL 62.5 260 C/W C

Top View

ORDERING INFORMATION
Device MMDF2C02ER2 Package SO8 Shipping 2500 Tape & Reel

1. Negative signs for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Semiconductor Components Industries, LLC, 2000

416

November, 2000 Rev. 6

Publication Order Number: MMDF2C02E/D

MMDF2C02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.2 Adc) (VGS = 10 Vdc, ID = 2.0 Adc) DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 1.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) OnState Drain Current (VDS = 5.0 Vdc, VGS = 4.5 Vdc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 9.1 ) (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 5.0 Vdc, RG = 25 ) td(on) tr td(off) tf td(on) tr td(off) tf (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 10 20 35 40 19 53 25 41 7.0 13 17 29 27 30 18 28 30 40 70 80 38 106 50 82 21 26 30 58 48 60 30 56 ns (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss (N) (P) (N) (P) (N) (P) 380 340 235 220 55 75 532 475 329 300 110 150 pF VGS(th) RDS(on) (N) (P) RDS(on) (N) (P) ID(on) gFS (N) (P) 1.0 1.0 2.6 2.8 (N) (P) 2.0 2.0 0.200 0.400 Adc mhos 0.100 0.250 Ohm 1.0 2.0 3.0 Ohm Vdc V(BR)DSS IDSS IGSS (N) (P) 25 1.0 1.0 100 Adc nAdc Vdc Symbol Polarity Min Typ Max Unit

3. Negative signs for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature.

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417

MMDF2C02E
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted) (Note 6.)
Characteristic SWITCHING CHARACTERISTICS continued (Note 8.) Total Gate Charge GateSource Charge GateDrain Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) Reverse Recovery Time see Figure 7 (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta (IF = IS, dIS/dt = 100 A/s) tb QRR 6. Negative signs for PChannel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 1.0 1.5 34 32 17 19 17 12 0.025 0.035 1.4 2.0 66 64 C Vdc ns (N) (P) (N) (P) (N) (P) (N) (P) 10.6 10 1.3 1.0 2.9 3.5 2.7 3.0 30 15 nC Symbol Polarity Min Typ Max Unit

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418

MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
7 I D , DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 0 0.25 0.5 0.75 1 1.25 1.5 3.1 V 2.9 V 2.7 V 2.5 V TJ = 25C 1.75 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS = 10 V 4.5 V 4.3 V 4.1 V 3.7 V 3.9 V I D , DRAIN CURRENT (AMPS) 3.5 V 3.3 V 4

PChannel
5V

VGS = 10

7V

4.7 V

4.5 V 4.3 V

TJ = 25C

4.1 V 3.9 V

3.7 V 3.5 V 3.3 V 0 0.4 0.8 1.2 1.6 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


7 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 1.5 2 2.5 TJ = -55C 3 3.5 4 0 2.5 100C 25C VDS 10 V TJ = 25C

Figure 1. OnRegion Characteristics

VDS 10 V

3 100C 25C TJ = -55C

3.5

4.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

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419

MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) ID = 3.5 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 1 A TJ = 25C

PChannel

4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.15 TJ = 25C VGS = 4.5 0.1 10 V 0.6 0.5 0.4 0.3 0.2 0.1

Figure 3. OnResistance versus GatetoSource Voltage


TJ = 25C

VGS = 4.5

0.05

10 V 0 0.5 1 ID, DRAIN CURRENT (AMPS) 1.5 2

ID, DRAIN CURRENT (AMPS)

RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.0

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 4. OnResistance versus Drain Current and Gate Voltage


VGS = 10 V ID = 3.5 A

Figure 4. OnResistance versus Drain Current and Gate Voltage


2.0 VGS = 10 V ID = 2 A

1.5

1.5

1.0

1.0

0.5

0.5

0 -50

-25

25

50

75

100

125

150

0 -50

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

Figure 5. OnResistance Variation with Temperature

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420

MMDF2C02E
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
10000 VGS = 0 V 100 TJ = 125C 100C I DSS , LEAKAGE (nA) TJ = 125C 10

PChannel

VGS = 0 V

I DSS , LEAKAGE (nA)

1000

100 25C 10

100C

10

15

20

25

12

16

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 6. DraintoSource Leakage Current versus Voltage

Figure 6. DraintoSource Leakage Current versus Voltage

POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

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421

MMDF2C02E
DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
di/dt = 300 A/s I S , SOURCE CURRENT

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 7. Reverse Recovery Time (trr)

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422

MMDF2C02E
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
NChannel
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

PChannel
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

10

10 ms 1 dc

100 s

10 s

10

10 ms 1 dc

100 s

10 s

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 8. Maximum Rated Forward Biased Safe Operating Area


280 EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 240 200 160 120 80 40 0 25 50 75 100 125 150 EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) I pk = 9 A 280 240 200 160 120 80 40 0 25

Figure 8. Maximum Rated Forward Biased Safe Operating Area


I pk = 7 A

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 9. Maximum Avalanche Energy versus Starting Junction Temperature

Figure 9. Maximum Avalanche Energy versus Starting Junction Temperature

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423

MMDF2C02E
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 10. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 11. Diode Reverse Recovery Waveform

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424

MMDF2C02E INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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425

MMDF2C02E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 12. Typical Solder Heating Profile

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426

MMDF2C02HD
Preferred Device

Power MOSFET 2 Amps, 20 Volts


Complementary SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery Avalanche Energy Specified Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)
Rating DraintoSource Voltage GatetoSource Voltage DraintoGate Voltage (RGS = 1.0 m) Drain Current Continuous Pulsed NChannel PChannel NChannel PChannel Symbol VDSS VGS VDGR ID IDM TJ, Tstg PD EAS Value 20 20 20 3.8 3.3 19 20 55 to 150 2.0 Unit Vdc Vdc Vdc A 8 1 D2C02 L Y WW = Device Code = Location Code = Year = Work Week

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2 AMPERES 20 VOLTS RDS(on) = 90 mW (NChannel) RDS(on) = 160 mW (PChannel)


NChannel D PChannel D

G S

G S

MARKING DIAGRAM

SO8, Dual CASE 751 STYLE 14

D2C02 LYWW

Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A, L = 10 mH, RG = 25 ) NChannel (VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A, L = 18 mH, RG = 25 ) PChannel Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds.

C Watts mJ

PIN ASSIGNMENT
NSource NGate PSource PGate 1 2 3 4 8 7 6 5 NDrain NDrain PDrain PDrain

405 324 RJA TL 62.5 260 C/W C

Top View

ORDERING INFORMATION
Device MMDF2C02HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Negative signs for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

427

November, 2000 Rev. 6

Publication Order Number: MMDF2C02HD/D

MMDF2C02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 10 Vdc, ID = 2.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 11 19 58 66 17 25 20 37 7.0 11 32 21 27 45 21 36 22 38 116 132 35 50 40 74 21 22 64 42 54 90 42 72 ns (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) ) Ciss Coss Crss (N) (P) (N) (P) (N) (P) 455 420 184 290 45 116 630 588 250 406 90 232 pF VGS(th) RDS(on) (N) (P) RDS(on) (N) (P) gFS (N) (P) 2.0 2.0 3.88 3.0 0.058 0.118 0.090 0.160 mhos 0.074 0.152 0.100 0.180 Ohm 1.0 1.5 2.0 Ohm Vdc V(BR)DSS IDSS IGSS (N) (P) 20 1.0 1.0 100 Adc nAdc Vdc Symbol Polarity Min Typ Max Unit

3. Negative signs for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature.

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MMDF2C02HD
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted) (Note 6.)
Characteristic SWITCHING CHARACTERISTICS continued (Note 8.) Total Gate Charge GateSource Charge GateDrain Charge (VDS = 16 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) Reverse Recovery Time (IS = 3.0 Adc, VAS = 0 Vdc, dIS/dt = 100 A/s) (IS = 2.0 Adc, VAS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta tb QRR (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 0.79 1.5 23 38 18 17 5.0 21 0.025 0.034 1.3 2.1 C Vdc ns (N) (P) (N) (P) (N) (P) (N) (P) 12.5 15 1.3 1.2 2.8 5.0 2.4 4.0 18 20 nC Symbol Polarity Min Typ Max Unit

6. Negative signs for PChannel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Switching characteristics are independent of operating junction temperature.

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MMDF2C02HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
VGS = 10 V 4.5 V 5 3.9 V 4 3 2 1 0 2.9 V 2.7 V 2.5 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0 0.2 0.4 0.6 0.8 1 1.2 6 3.5 V 3.7 V 3.3 V TJ = 25C I D , DRAIN CURRENT (AMPS) 4 VGS = 10 V 4.5 V

PChannel
3.9 V 3.7 V 3.5 V 3.3 V 2 3.1 V 1 2.9 V 2.7 V 2.5 V 1.4 1.6 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C

I D , DRAIN CURRENT (AMPS)

3.1 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 1. OnRegion Characteristics

6 VDS 10 V I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS)

VDS 10 V

4 TJ = 100C 25C -55C

100C TJ = -55C 1.5 2.0 2.5

25C

1.4

1.8

2.2

2.6

3.4

0 1.0

3.0

3.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

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MMDF2C02HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) ID = 1.5 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.6 ID = 1 A TJ = 25C

PChannel

0.4

0.4

0.2

0.2

3 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance versus GateToSource Voltage


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.08 TJ = 25C 0.20 TJ = 25C

Figure 3. OnResistance versus GateToSource Voltage

VGS = 4.5 V

0.16

VGS = 4.5 V

0.07

0.12

10 V

0.06

10 V

0.08

0.05

2 3 4 ID, DRAIN CURRENT (AMPS)

0.04

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current and Gate Voltage


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.6 1.4 1.2 1 0.8 0.6 -50 VGS = 10 V ID = 1.5 A 1.6 1.4 1.2 1.0 0.8 0.6 -50

Figure 4. OnResistance versus Drain Current and Gate Voltage


VGS = 10 V ID = 2 A

-25

25

50

75

100

125

150

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

Figure 5. OnResistance Variation with Temperature

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MMDF2C02HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
1000 VGS = 0 V TJ = 125C 100C 10 25C 100 VGS = 0 V

PChannel

TJ = 125C

I DSS , LEAKAGE (nA)

100

I DSS, LEAKAGE (nA)

10 100C

8 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

20

10

15

20

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage Current versus Voltage

Figure 6. DrainToSource Leakage Current versus Voltage

POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

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MMDF2C02HD
NChannel
1400 1200 C, CAPACITANCE (pF) 1000 800 600 400 200 10 5 VGS 0 VDS 5 Crss 10 15 20 Crss Ciss Coss VDS = 0 V Ciss C, CAPACITANCE (pF) VGS = 0 V TJ = 25C 1200 VDS = 0 V

PChannel
VGS = 0 V TJ = 25C

C 1000 iss 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Coss Crss 15 20

Crss

Ciss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

Figure 7. Capacitance Variation

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

10 8 6 4 2 0 Q3 0 2 4 6 8 10 QT, TOTAL GATE CHARGE (nC) VDS 12 Q1 Q2 VGS

20 16 ID = 3 A TJ = 25C 12 8 4 0 14

10 8 6 4 Q1 2 Q3 0 0 4 8 Q2 VDS

VGS

15 12 9 6 3 0 16

ID = 2 A TJ = 25C

12

QT, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge


100 1000

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

t, TIME (ns)

10

tf td(on)

t, TIME (ns)

VDD = 10 V ID = 3 A VGS = 10 V tr TJ = 25C t d(off)

VDD = 10 V ID = 2 A VGS = 10 V TJ = 25C

100 td(off) tf tr

10 RG, GATE RESISTANCE (OHMS)

100

10

td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com


433

Figure 9. Resistive Switching Time Variation versus Gate Resistance

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

12

QT

24

12

QT

18

v DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

MMDF2C02HD
DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
NChannel
3.0 2.5 I S , SOURCE CURRENT (AMPS) 2.0 VGS = 0 V TJ = 25C 2.0 1.6 1.2 0.8 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

PChannel

1.5 1.0

0.5 0 0.50

I S , SOURCE CURRENT (AMPS)

0.4 0 0.5

0.55

0.60

0.65

0.70

0.75

0.80

0.7

0.9

1.1

1.3

1.5

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Figure 10. Diode Forward Voltage versus Current

di/dt = 300 A/s I S , SOURCE CURRENT

Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr) http://onsemi.com


434

MMDF2C02HD
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
NChannel
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
PChannel
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

10

1 ms 10 ms

100 s

10

100 s 1 ms 10 ms

dc

dc

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Rated Forward Biased Safe Operating Area

450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125

E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

ID = 9 A

350 300 250 200 150 100 50 0 25 50 75 100 125

ID = 6 A

150

150

TJ, STARTING JUNCTION TEMPERATURE (C)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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435

MMDF2C02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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MMDF2C02HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF2C02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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MMDF2C03HD
Preferred Device

Power MOSFET 2 Amps, 30 Volts


Complementary SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO-8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO-8 Package Provided
8

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2 AMPERES 30 VOLTS RDS(on) = 70 mW (N-Channel) RDS(on) = 200 mW (P-Channel)


NChannel D PChannel D

G S

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)


Rating DraintoSource Voltage GatetoSource Voltage Drain Current Continuous Drain Current Pulsed NChannel PChannel NChannel PChannel Symbol VDSS VGS ID IDM TJ, Tstg PD RJA EAS Value 30 20 4.1 3.0 21 15 55 to 150 2.0 62.5 Unit Vdc Vdc A

SO8, Dual CASE 751 STYLE 14 1 D2C03 L Y WW = Device Code = Location Code = Year = Work Week

D2C03 LYWW

Operating and Storage Temperature Range Total Power Dissipation @ TA= 25C (Note 2.) Thermal Resistance Junction to Ambient (Note 2.) Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 ) NChannel (VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 ) PChannel Maximum Lead Temperature for Soldering, 0.0625 from case. Time in Solder Bath is 10 seconds.

C Watts C/W mJ

PIN ASSIGNMENT
NSource NGate PSource PGate 1 2 3 4 8 7 6 5 NDrain NDrain PDrain PDrain

Top View 324

ORDERING INFORMATION
324 TL 260 C Device MMDF2C03HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Negative signs for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

439

November, 2000 Rev. 6

Publication Order Number: MMDF2C03HD/D

MMDF2C03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 10 Vdc, ID = 2.0 Adc) DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 9.1 ) (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 ) (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 4.5 Vdc, RG = 9.1 ) (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 12 16 65 18 16 63 19 194 8.0 9.0 15 10 30 81 23 192 24 32 130 36 32 126 38 390 16 18 30 20 60 162 46 384 ns (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss (N) (P) (N) (P) (N) (P) 450 397 160 189 35 64 630 550 225 250 70 126 pF VGS(th) RDS(on) (N) (P) RDS(on) (N) (P) gFS (N) (P) 2.0 2.0 3.6 3.4 0.065 0.225 0.075 0.300 mhos 0.06 0.17 0.070 0.200 Ohm (N) (P) 1.0 1.0 1.7 1.5 3.0 2.0 Vdc Ohm V(BR)DSS IDSS IGSS (N) (P) 30 1.0 1.0 100 Adc nAdc Vdc Symbol Polarity Min Typ Max Unit

3. Negative signs for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature.

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MMDF2C03HD
ELECTRICAL CHARACTERISTICS continued (TA = 25C unless otherwise noted) (Note 6.)
Characteristic SWITCHING CHARACTERISTICS continued (Note 8.) Total Gate Charge GateSource Charge GateDrain Charge (VDS = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDS = 24 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS (TC = 25C) Forward Voltage (Note 7.) Reverse Recovery Time (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta (IF = IS, dIS/dt = 100 A/s) Reverse Recovery Storage Charge tb QRR (N) (P) (N) (P) (N) (P) (N) (P) (N) (P) 0.82 1.82 24 42 17 16 7.0 26 0.025 0.043 1.2 2.0 C Vdc ns (N) (P) (N) (P) (N) (P) (N) (P) 11.5 14.2 1.5 1.1 3.5 4.5 2.8 3.5 16 19 nC Symbol Polarity Min Typ Max Unit

6. Negative signs for PChannel device omitted for clarity. 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 8. Switching characteristics are independent of operating junction temperature.

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MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
6 I D , DRAIN CURRENT (AMPS) VGS = 10 V 4.5 V 5 4.3 V 4.1 V 4 3 2 2.9 V 1 0 0.2 0.6 2.7 V 2.5 V 0 0.4 0.8 1 1.2 1.4 1.6 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 3.9 V 3.7 V 3.3 V 3.5 V 4 TJ = 25C I D , DRAIN CURRENT (AMPS) 3

PChannel
VGS = 10 V 4.5 V 3.9 V 3.3 V 3.1 V 2.9 V 1 2.7 V 2.5 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 3.7 V 3.5 V TJ = 25C

3.1 V

Figure 1. OnRegion Characteristics


6 VDS 10 V I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 -55C TJ = 100C 3 4

Figure 1. OnRegion Characteristics


VDS 10 V

2 25C

TJ = 100C

25C

-55C 3.5 4 0 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

2.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

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MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 1.5 A TJ = 25C

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

PChannel
0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 5 6 7 8 2 3 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 9 10 ID = 1 A TJ = 25C

4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

Figure 3. OnResistance versus GateToSource Voltage


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.08 TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.30

Figure 3. OnResistance versus GateToSource Voltage


TJ = 25C

0.25 VGS = 4.5 V 10 V 0.15

0.07 VGS = 4.5

0.20

0.06 10 V

0.05

0.5

1.5

2.5

0.10

0.5

ID, DRAIN CURRENT (AMPS) RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.5 3 1.5 2 ID, DRAIN CURRENT (AMPS)

3.5

Figure 4. OnResistance versus Drain Current and Gate Voltage


2.0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) VGS = 10 V ID = 1.5 A 1.6 1.4 1.2 1.0 0.8 0.6 -50

Figure 4. OnResistance versus Drain Current and Gate Voltage


VGS = 10 V ID = 2 A

1.5

1.0

0.5

0 -50

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

Figure 5. OnResistance Variation with Temperature

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MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
100 VGS = 0 V TJ = 125C 1000 VGS = 0 V

PChannel

I DSS , LEAKAGE (nA)

I DSS , LEAKAGE (nA)

10

100C

100

TJ = 125C

100C

10

15

20

25

30

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

5 10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

30

Figure 6. DrainToSource Leakage Current versus Voltage

Figure 6. DrainToSource Leakage Current versus Voltage

POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

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MMDF2C03HD
NChannel
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10 5 VGS 0 VDS 5 10 15 Coss Crss 20 25 30 Crss VDS = 0 V VGS = 0 V Ciss TJ = 25C 1200 VDS = 0 V VGS = 0 V

PChannel
TJ = 25C

C 1000 iss C, CAPACITANCE (pF) 800 600 Crss 400 200 0 10 5 VGS 0 VDS 5 Ciss Coss Crss 10 15 20 25 30

Ciss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Figure 7. Capacitance Variation

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

QT

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

12

24

12 10

QT VGS

24 20

VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDS

VGS

18

8 6 Q1 4 2 Q3 0 0 2

VDS ID = 2 A TJ = 25C

16 12 8 4 0 16

Q1

Q2

12

Q2

Q3

6 ID = 3 A TJ = 25C 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC)

0 12

10

12

14

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge


1000 1000

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

t, TIME (ns)

10

td(off) tr tf td(on)

t, TIME (ns)

100

VDD = 15 V ID = 3 A VGS = 10 V TJ = 25C

100

VDD = 15 V ID = 2 A VGS = 10 V TJ = 25C

tf td(off) tr td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

10 RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 9. Resistive Switching Time Variation versus Gate Resistance

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MMDF2C03HD
DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
NChannel
3.0 2.5 IS, SOURCE CURRENT (AMPS) 2.0 1.5 1.0 TJ = 25C VGS = 0 V 2 1.6 1.2 TJ = 25C VGS = 0 V

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

PChannel

0.5 0 0.5

I S , SOURCE CURRENT (AMPS) 0.55 0.6 0.65 0.7 0.75 0.8 0.85

0.8 0.4 0 0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Figure 10. Diode Forward Voltage versus Current

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MMDF2C03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
NChannel
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

PChannel
100 I D , DRAIN CURRENT (AMPS) 10 s 100 s VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

10

1 ms

10

100 s 1 ms 10 ms

dc

0.1

0.1

0.01 0.1

10

100

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased Safe Operating Area NChannel http://onsemi.com
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Figure 12. Maximum Rated Forward Biased Safe Operating Area PChannel

MMDF2C03HD
350 300 250 200 150 100 50 0 25 50 75 100 125 150 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) ID = 9 A 350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 6 A

TJ, STARTING JUNCTION TEMPERATURE (C)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS


10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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MMDF2C03HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF2C03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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450

MMDF2N02E Power MOSFET 2 Amps, 25 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits IDSS Specified at Elevated Temperatures Avalanche Energy Specified Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 6.0 mH, RG = 25 ) Thermal Resistance, Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds Symbol VDSS VGS ID ID IDM PD TJ, Tstg EAS 245 Value 25 20 3.6 2.5 18 2.0 55 to 150 Unit Vdc Vdc Adc Apk W C mJ F2N02 L Y WW = Device Code = Location Code = Year = Work Week 1 8

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2 AMPERES 25 VOLTS RDS(on) = 100 mW


NChannel D

G S

MARKING DIAGRAM

SO8, Dual CASE 751 STYLE 11

F2N02 LYWW

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

RJA TL

62.5 260

C/W C

Top View

ORDERING INFORMATION
Device MMDF2N02ER2 Package SO8 Shipping 2500 Tape & Reel

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Semiconductor Components Industries, LLC, 2000

451

November, 2000 Rev. 6

Publication Order Number: MMDFN02E/D

MMDF2N02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.2 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) Reverse Recovery Time S Fi See Figure 11 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta tb QRR 1.0 34 17 17 0.03 1.4 66 C Vdc ns 7.0 17 27 18 10 35 19 25 10.6 1.3 2.9 2.7 21 30 48 30 30 70 38 50 30 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 380 235 55 532 329 110 pF VGS(th) 1.0 RDS(on) gFS 1.0 0.083 0.110 2.6 0.100 0.200 Mhos 2.0 3.0 Ohm Vdc V(BR)DSS 25 IDSS IGSS 1.0 10 100 nAdc Adc Vdc Symbol Min Typ Max Unit

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MMDF2N02E
TYPICAL ELECTRICAL CHARACTERISTICS
7 I D , DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 0 0.25 0.5 0.75 1 1.25 1.5 3.1 V 2.9 V 2.7 V 2.5 V TJ = 25C 1.75 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 7 I D , DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 1.5 2 2.5 TJ = -55C 3 3.5 4 100C 25C VDS 10 V TJ = 25C

VGS = 10 V 4.5 V 4.3 V 4.1 V

3.7 V 3.9 V 3.5 V 3.3 V

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 0.15

Figure 2. Transfer Characteristics

ID = 3.5 A TJ = 25C

TJ = 25C VGS = 4.5 0.1 10 V

0.05

4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.0 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 10 V ID = 3.5 A

VGS = 0 V

TJ = 125C 100C

1.0

I DSS , LEAKAGE (nA)

1.5

1000

100 25C 10

0.5

0 -50

-25

25

50

75

100

125

150

10

15

20

25

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MMDF2N02E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve.
VDS = 0 V Ciss VGS = 0 V TJ = 25C VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10 5 0 5 10 15 20 Crss Ciss Coss Crss VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 25

During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
12 QT 9 VDS VGS 12 16

6 Q1 3 Q3 0 0 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) ID = 2.3 A TJ = 25C 10 Q2

0 12

Figure 7. Capacitance Variation

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

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VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

MMDF2N02E
100 VDD = 10 V ID = 2 A VGS = 10 V TJ = 25C 7 td(off) tf tr t, TIME (ns) 10 td(on) 6 IS, SOURCE CURRENT (AMPS) 5 4 3 2 1 0 0.5 0.6 0.7 0.8 0.9 1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1.1 TJ = 25C VGS = 0 V

10 RG, GATE RESISTANCE (OHMS)

100

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Diode Forward Voltage versus Current

di/dt = 300 A/s I S , SOURCE CURRENT

Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MMDF2N02E
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

280 EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 240 200 160 120 80 40 0 25 50 75 100 125

I pk = 9 A

10

10 ms 1 dc

100 s

10 s

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS


10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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MMDF2N02E INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. These can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.

The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF2N02E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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MMDF2N05ZR2
Preferred Device

Power MOSFET 2 Amps, 50 Volts


NChannel SO8, Dual
EZFETst are an advanced series of power MOSFETs which contain monolithic backtoback zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives.
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2 AMPERES 50 VOLTS RDS(on) = 300 mW


NChannel D

Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery


Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
8 Unit Vdc Vdc Vdc Adc Apk Watts C C/W C 1

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 70C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Thermal Resistance Junction to Ambient Maximum Temperature for Soldering Purposes Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg RJA TL Value 50 50 15 2.0 1.7 8.0 2.0 55 to 150 62.5 260

SO8, Dual CASE 751 STYLE 11

F2N05Z LYWW

F2N05Z L Y WW

= Device Code = Location Code = Year = Work Week

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

1. When mounted on G10/FR 4 glass epoxy board using minimum recommended footprint.

Top View

ORDERING INFORMATION
Device MMDF2N05ZR2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

459

November, 2000 Rev. 2

Publication Order Number: MMDF2N05ZR2/D

MMDF2N05ZR2
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 15 Vdc, VGS = 0 Vdc) (VDS = 15 Vdc, VGS = 0 Vdc, TJ = 55C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 5.0 Vdc, ID = 0.6 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge ( (see fi figure 8) (VDS = 25 Vdc, ID = 1.3 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 0.6 Adc, VGS = 10 Vdc Vdc, RG = 25 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 2.0 2 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta tb QRR 0.82 66 23 43 0.08 1.4 C ns Vdc 24 46 130 71 3.3 0.7 1.3 1.4 48 92 260 142 4.6 nC ns (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 104 58 16 pF (Cpk 2.0) (Note 4.) VGS(th) 2.0 (Cpk 2.0) (Note 4.) RDS(on) gFS 2.0 200 350 300 500 mMhos 3.0 5.0 4.0 Vdc mV/C m (Cpk 2.0) (Note 4.) V(BR)DSS 50 IDSS IGSS 0.14 2.0 25 0.5 56 55 Vdc mV/C Adc Symbol Min Typ Max Unit

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MMDF2N05ZR2
TYPICAL ELECTRICAL CHARACTERISTICS
4 4 6.0 V 5.5 V I D , DRAIN CURRENT (AMPS) 3.5 3 VDS 10 V TJ = 25C

I D , DRAIN CURRENT (AMPS)

VGS = 10 V 3.5 TJ = 25C 3

7V

6.5 V

2.5 2 5.0 V

2.5 2 100C 25C TJ = -55C 3 3.5 4 4.5 5 5.5 6 6.5

1.5 1

1.5 1

0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

4.3 V 3.9 V 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.5 0 2.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 1.2 1.0 0.8 0.6 0.4 0.2 0 0.65

Figure 2. Transfer Characteristics

ID = 1.5 A TJ = 25C

TJ = 25C

0.45

VGS = 5.0 V

0.25

10 V

5.5

6.5 7 7.5 8 9 8.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

9.5

10

0.05

0.5

1.5

2.5

3.5

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

2.0

VGS = 10 V ID = 1 A I DSS , LEAKAGE (nA)

VGS = 0 V

TJ = 125C 100C 25C

1.5

10

1.0

0.5

0.1

0 -50

-25

25

50

75

100

125

150

0.01

10

15

20

25

30

35

40

45

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MMDF2N05ZR2
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
250 200 C, CAPACITANCE (pF) 150 100 50 0 10 Crss Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25 30 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MMDF2N05ZR2
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) QT VGS VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 40 1000 VGS = 10 V TJ = 25C

30

6 Q1 3 Q3 0 0 0.5 1 VDS 2.5 3 2 1.5 Qg, TOTAL GATE CHARGE (nC) ID = 1.3 A TJ = 25C 3.5 Q2

20

t, TIME (ns)

100

td(off) tf tr td(on)

10

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2 1.75 I S , SOURCE CURRENT (AMPS) 1.5 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

1.25 1

0.75 0.5

0.25 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MMDF2N05ZR2
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 1 ms 1 dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

10

0.01 0.1

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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464

MMDF2N05ZR2
TYPICAL ELECTRICAL CHARACTERISTICS
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.1 0.2 0.1 0.05 0.02 0.01 0.01

Dual SO-8 Thermal RC Network


Chip
0.0106 0.0431 0.1643 0.3507 0.4302

0.0253 F

0.1406 F

0.5064 F

2.9468 F

177.14 F

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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465

MMDF2N05ZR2 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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466

MMDF2N05ZR2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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467

MMDF2P01HD
Preferred Device

Power MOSFET 2 Amps, 12 Volts


PChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
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2 AMPERES 12 VOLTS RDS(on) = 180 mW


PChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD Value 12 12 8.0 3.4 2.1 17 2.0 Unit Vdc Vdc Vdc Adc Apk Watts C C/W C 1 8

SO8, Dual CASE 751 STYLE 11

D2P01 LYWW

D2P01 L Y WW

= Device Code = Location Code = Year = Work Week

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

55 to 150 RJA TL 62.5 260

1. Negative sign for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Top View

ORDERING INFORMATION
Device MMDF2P01HDR2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

468

November, 2000 Rev. 6

Publication Order Number: MMDF2P01HD/D

MMDF2P01HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc) (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 2.0 Adc) (VGS = 2.7 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 2.5 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc) (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 2 2.7 7 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 4.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Negative sign for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. ta tb QRR 1.69 1.2 48 23 25 0.05 2.0 C ns Vdc 21 156 38 68 16 44 68 54 9.3 0.8 4.0 3.0 45 315 75 135 35 90 135 110 13 nC ns (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 530 410 177 740 570 250 pF VGS(th) 0.7 RDS(on) gFS 3.0 0.16 0.2 4.75 0.180 0.220 mhos 1.0 3.0 1.1 Vdc mV/C Ohm V(BR)DSS 12 IDSS IGSS 1.0 10 100 nAdc 17 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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469

MMDF2P01HD
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 4 I D , DRAIN CURRENT (AMPS)

VGS = 8 V 4.5 V 3.1 V 2.7 V

2.5 V 2.3 V

TJ = 25C

VDS 10 V

2.1 V

2 100C 25C TJ = -55C

1.9 V 1 1.7 V 1.5 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.35 0.30 0.25 0.20 0.15 0.1

TJ = 25C ID = 1 A

0.30

TJ = 25C

0.25

0.20

VGS = 2.7 V 4.5 V

0.15

6 2 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

0.10

0.8

1.6 2.4 ID, DRAIN CURRENT (AMPS)

3.2

Figure 3. OnResistance versus GateToSource Voltage


1000 VGS = 4.5 V ID = 2 A I DSS , LEAKAGE (nA)

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

1.5

TJ = 125C 100

0.5

-50

-25

25

50

75

100

125

150

10

TJ, JUNCTION TEMPERATURE (C)

8 4 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

12

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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470

MMDF2P01HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2000 1600 C, CAPACITANCE (pF) 1200 800 400 0 Crss Ciss Coss 8 4 VGS 0 VDS 4 8 Crss 12 Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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471

MMDF2P01HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 5 QT 4 VDS 3 2 Q1 1 Q3 0 0 2 4 6 8 0 10 ID = 2 A TJ = 25C VGS 6 4 2 8 10 1000 VDD = 6 V ID = 2 A VGS = 4.5 V TJ = 25C 100 td(off) tf tr td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Q2

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

t, TIME (ns)

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2 VGS = 0 V TJ = 25C 1.5

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.5

0 0.4

0.6

0.8

1.2

1.4

1.6

1.8

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


472

MMDF2P01HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 I D , DRAIN CURRENT (AMPS) VGS = 8 V SINGLE PULSE TC = 25C

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

10

1 ms 10 ms

dc

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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473

MMDF2P01HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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474

MMDF2P01HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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475

MMDF2P01HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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476

MMDF2P02E Power MOSFET 2 Amps, 25 Volts


PChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, with Soft Recovery IDSS Specified at Elevated Temperatures Avalanche Energy Specified Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance, Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds Symbol VDSS VGS ID ID IDM PD Value 25 20 2.5 1.7 13 2.0 16 TJ, Tstg EAS 245 55 to 150 Unit Vdc Vdc Adc Apk W 1 L Y WW = Location Code = Year = Work Week 8

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2 AMPERES 25 VOLTS RDS(on) = 250 mW


PChannel D

G S

MARKING DIAGRAM

SO8, Dual CASE 751 STYLE 11

F2P02 LYWW

PIN ASSIGNMENT
mW/C C mJ Source1 Gate1 Source2 Gate2 C/W C 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View RJA TL 62.5 260

ORDERING INFORMATION
Device MMDF2P02ER2 Package SO8 Shipping 2500 Tape & Reel

1. Negative sign for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Semiconductor Components Industries, LLC, 2000

477

November, 2000 Rev. 6

Publication Order Number: MMDF2P02E/D

MMDF2P02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 4.) Reverse Recovery Time S Fi See Figure 11 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Storage Charge 3. Negative sign for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta tb QRR 1.5 32 19 12 0.035 2.0 64 C Vdc ns 20 40 53 41 13 29 30 28 10 1.0 3.5 3.0 40 80 106 82 26 58 60 56 15 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 340 220 75 475 300 150 pF VGS(th) 1.0 RDS(on) gFS 1.0 0.19 0.3 2.8 0.25 0.4 Mhos 2.0 3.8 3.0 Ohm Vdc V(BR)DSS 25 IDSS IGSS 1.0 10 100 nAdc 2.2 Vdc mV/C Adc Symbol Min Typ Max Unit

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478

MMDF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 4 I D , DRAIN CURRENT (AMPS)

VGS = 10 7 V

5V

4.7 V

4.5 V 4.3 V

TJ = 25C

VDS 10 V

3 100C 25C TJ = -55C

4.1 V 3.9 V

3.7 V 3.5 V 3.3 V 0 0.4 0.8 1.2 1.6 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0 2.5

3.5

4.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 1 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 4.5

10 V 0 0.5 1 ID, DRAIN CURRENT (AMPS) 1.5 2

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.0 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 10 V ID = 2 A I DSS , LEAKAGE (nA)

VGS = 0 V

1.5 TJ = 125C 10

1.0

0.5

100C

0 -50

-25

25

50

75

100

125

150

12

16

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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479

MMDF2P02E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve.
VDS = 0 V Ciss VGS = 0 V TJ = 25C VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1000 800 C, CAPACITANCE (pF) 600 400 200 0 10 Crss

During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
12 QT 9 VDS VGS 12 16

Ciss Coss Crss

Q1

Q2

Q3

4 ID = 2 A TJ = 25C 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) 10

5 5 0 10 15 20 25 30 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0 12

Figure 7. Capacitance Variation

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

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VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

MMDF2P02E
100 VDD = 10 V ID = 2 A VGS = 10 V TJ = 25C 2 1.6 1.2 0.8 0.4 0 0.6 TJ = 25C VGS = 0 V

td(off) tr tf td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100

IS, SOURCE CURRENT (AMPS)

t, TIME (ns)

0.8 1 1.2 1.4 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

1.6

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Diode Forward Voltage versus Current

di/dt = 300 A/s I S , SOURCE CURRENT

Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MMDF2P02E
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

280 EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 240 200 160 120 80 40 0 25 50 75 100 125 150 I pk = 7 A

10

10 ms 1 dc

100 s

10 s

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS


10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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482

MMDF2P02E INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. These can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF2P02E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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484

MMDF2P02HD
Preferred Device

Power MOSFET 2 Amps, 20 Volts


PChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 18 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 20 20 20 3.3 2.1 20 2.0 55 to 150 324 Unit Vdc Vdc Vdc Adc Apk Watts Source1 C mJ Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2 8 1 L Y WW = Location Code = Year = Work Week

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2 AMPERES 20 VOLTS RDS(on) = 160 mW


PChannel D

G S

MARKING DIAGRAM

SO8, Dual CASE 751 STYLE 11

D2P02 LYWW

PIN ASSIGNMENT

Top View RJA TL 62.5 260 C/W C

ORDERING INFORMATION
Device MMDF2P02HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Negative sign for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

485

November, 2000 Rev. 6

Publication Order Number: MMDF2P02HD/D

MMDF2P02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDS = 10 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 4.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (VDD = 15 V, IS = 2.0 A, dIS/dt = 100 A/s) ta tb QRR 3. Negative sign for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.max. 5. Switching characteristics are independent of operating junction temperature. 1.5 1.24 38 17 21 0.034 2.1 C ns Vdc 19 66 25 37 11 21 45 36 15 1.2 5.0 4.0 38 132 50 74 22 42 90 72 20 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 420 290 116 588 406 232 pF VGS(th) 1.0 RDS(on) gFS 2.0 0.118 0.152 3.0 0.160 0.180 mhos 1.5 4.0 2.0 Vdc mV/C Ohm V(BR)DSS 20 IDSS IGSS 1.0 10 100 nAdc 25 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MMDF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 4 I D , DRAIN CURRENT (AMPS)

VGS = 10 V 4.5 V

3.9 V

3.7 V 3.5 V 3.3 V

TJ = 25C

VDS 10 V

2 3.1 V 1 2.9 V 2.7 V 2.5 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2

100C TJ = -55C 1.5 2.0 2.5

25C

0 1.0

3.0

3.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.20

Figure 2. Transfer Characteristics

ID = 1 A TJ = 25C

TJ = 25C VGS = 4.5 V

0.16

0.4

0.12

10 V

0.2

0.08

10

0.04

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


1.6 1.4 1.2 1.0 0.8 0.6 -50 1 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 2 A I DSS, LEAKAGE (nA)

VGS = 0 V

TJ = 125C

10 100C

-25

25

50

75

100

125

150

10

15

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MMDF2P02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Coss Crss 15 20 VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

Crss

Ciss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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MMDF2P02HD
VGS, GATETOSOURCE VOLTAGE (VOLTS) 12 10 8 6 4 Q1 2 Q3 0 0 4 8 VDS 12 QT, TOTAL GATE CHARGE (nC) Q2 ID = 2 A TJ = 25C VDS , DRAINTOSOURCE VOLTAGE (VOLTS) QT VGS 18 15 12 9 6 3 0 16 1000 VDD = 10 V ID = 2 A VGS = 10 V TJ = 25C

t, TIME (ns)

100 td(off) tf tr 10 td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2.0 1.6 1.2 0.8 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.4 0 0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MMDF2P02HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

350 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 300 250 200 150 100 50 0 25 50 75 100 125

ID = 6 A

10

100 s 1 ms 10 ms

dc

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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490

MMDF2P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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491

MMDF2P02HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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492

MMDF2P02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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493

MMDF2P03HD
Preferred Device

Power MOSFET 2 Amps, 30 Volts


PChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
8

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2 AMPERES 30 VOLTS RDS(on) = 200 mW


PChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 30 30 20 3.0 1.9 15 2.0 55 to 150 324 Unit Vdc Vdc Vdc Adc Apk Watts C mJ 1 L Y WW

SO8, Dual CASE 751 STYLE 11

D2P03 LYWW

= Location Code = Year = Work Week

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View RJA TL 62.5 260 C/W C

ORDERING INFORMATION
Device MMDF2P03HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Negative sign for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

494

November, 2000 Rev. 7

Publication Order Number: MMDF2P03HD/D

MMDF2P03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 1.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 24 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 3.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD 1.82 1.36 42.3 15.6 26.7 0.044 2.0 C Vdc 16.25 17.5 62.5 194 9.0 10 81 192 14.2 1.1 4.5 3.5 33 35 125 390 18 20 162 384 19 nC ns (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 397 189 64 550 250 126 pF VGS(th) 1.0 RDS(on) gFS 2.0 0.170 0.225 3.4 0.200 0.300 mhos 1.5 4.0 2.0 Vdc mV/C Ohm V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 27 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time S Fi See Figure 15 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Negative sign for PChannel device omitted for clarity. 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperature.

trr ta tb QRR

ns

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495

MMDF2P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 4 I D , DRAIN CURRENT (AMPS)

VGS = 10 V 4.5 V

3.7 V

3.5 V 3.3 V 3.1 V 2.9 V

TJ = 25C

VDS 10 V

3.9 V

2 25C

TJ = 100C

2.7 V 2.5 V

-55C 1.6 1.8 2 0 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

0.2

0.4

0.6

0.8

1.2

1.4

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.6 0.5 0.4 0.3 0.2 0.1 0 0

ID = 1 A TJ = 25C

0.30

TJ = 25C

0.25 VGS = 4.5 V 10 V 0.15

0.20

5 6 7 8 3 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 2

10

0.10

0.5

2.5 3 1.5 2 ID, DRAIN CURRENT (AMPS)

3.5

Figure 3. OnResistance versus GatetoSource Voltage


1.6 1.4 1.2 1.0 0.8 0.6 -50 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 2 A

VGS = 0 V

I DSS , LEAKAGE (nA)

100

TJ = 125C

100C

-25

25

50

75

100

125

150

10

TJ, JUNCTION TEMPERATURE (C)

10 20 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

30

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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496

MMDF2P03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Ciss 1000 C, CAPACITANCE (pF) 800 600 Crss 400 200 0 10 5 VGS 0 VDS 5 Ciss Coss Crss 10 15 20 25 30

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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497

MMDF2P03HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 VGS 8 6 Q1 4 2 Q3 0 0 2 4 6 8 10 12 14 Q2 VDS ID = 2 A TJ = 25C QT 24 20 16 12 8 4 0 16 1000 VDD = 15 V ID = 2 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

tf td(off) tr td(on)

t, TIME (ns)

100

10

10 RG, GATE RESISTANCE (OHMS)

100

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2 1.6 1.2 TJ = 25C VGS = 0 V

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.8

0.4 0 0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


498

MMDF2P03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
350 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 300 250 200 150 100 50 0 25 50 75 100 125 150

ID = 6 A

10

100 s 1 ms 10 ms

dc

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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499

MMDF2P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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500

MMDF2P03HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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501

MMDF2P03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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502

MMDF3N02HD
Preferred Device

Power MOSFET 3 Amps, 20 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
8

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3 AMPERES 20 VOLTS RDS(on) = 90 mW


NChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 20 20 20 3.8 2.6 19 2.0 55 to 150 405 Unit Vdc Vdc Vdc Adc Apk Watts C mJ

SO8, Dual CASE 751 STYLE 11 1 L Y WW = Location Code = Year = Work Week

D3N02 LYWW

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View

RJA TL

62.5 260

C/W C

ORDERING INFORMATION
Device MMDF3N02HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.
Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

503

November, 2000 Rev. 6

Publication Order Number: MMDF3N02HD/D

MMDF3N02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) Reverse Recovery Time S Fi See Figure 15 (IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.79 0.72 23 18 5.0 0.025 1.3 C Vdc ns 11 58 17 20 7.0 32 27 21 12.5 1.3 2.8 2.4 22 116 35 40 21 64 54 42 18 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 455 184 45 630 250 90 pF VGS(th) 1.0 RDS(on) gFS 2.0 0.058 0.074 3.88 0.090 0.100 Mhos 1.5 4.0 2.0 Vdc mV/C Ohms V(BR)DSS 20 IDSS IGSS 1.0 10 100 nAdc 29 Vdc mV/C Adc Symbol Min Typ Max Unit

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504

MMDF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
6 6 VDS 10 V I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

VGS = 10 V 4.5 V 5 3.9 V 4 3 2 1 0

3.5 V 3.7 V 3.3 V

TJ = 25C

3.1 V 2.9 V 2.7 V 2.5 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

4 TJ = 100C 25C -55C

1.4

1.8

2.2

2.6

3.4

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.6

ID = 1.5 A TJ = 25C

0.08

TJ = 25C

VGS = 4.5 V

0.4

0.07

0.2

0.06

10 V

5 6 7 8 3 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 2

10

0.05

2 3 4 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


1.6 1.4 1.2 1 0.8 0.6 -50 1 VGS = 10 V ID = 1.5 A I DSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C 100C

10

25C

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

4 8 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

20

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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505

MMDF3N02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1400 1200 C, CAPACITANCE (pF) 1000 800 600 400 200 10 5 VGS 0 VDS 5 Crss 10 15 20 Crss Ciss Coss VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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MMDF3N02HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 2 4 6 8 10 QT, TOTAL CHARGE (nC) VDS 12 Q1 Q2 VGS QT 24 20 16 ID = 3 A TJ = 25C 12 8 4 0 14 100 VDD = 10 V ID = 3 A VGS = 10 V tr TJ = 25C t d(off) 10 tf td(on) v DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
3 2.5 I S , SOURCE CURRENT (AMPS) 2 1.5 1 0.5 0 0.5 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.55

0.6

0.65

0.7

0.75

0.8

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


507

MMDF3N02HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 9 A

10

1 ms 10 ms

100 s

dc

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MMDF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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509

MMDF3N02HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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510

MMDF3N02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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MMDF3N03HD
Preferred Device

Power MOSFET 3 Amps, 30 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
8

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3 AMPERES 30 VOLTS RDS(on) = 70 mW


NChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 30 30 20 4.1 3.0 40 2.0 55 to 150 324 Unit Vdc Vdc Vdc Adc Apk Watts C mJ 1 L Y WW

SO8, Dual CASE 751 STYLE 11

D3N03 LYWW

= Location Code = Year = Work Week

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View

RJA TL

62.5 260

C/W C

ORDERING INFORMATION
Device MMDF3N03HDR2 Package SO8 Shipping 2500 Tape & Reel

1. When mounted on 2 square FR4 board (1 square 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.
Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

512

November, 2000 Rev. 7

Publication Order Number: MMDF3N03HD/D

MMDF3N03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 3.0 3 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) VSD trr ta tb Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. QRR 0.82 0.7 24 17 7 0.025 1.2 C ns Vdc 12 65 16 19 8 15 30 23 11.5 1.5 3.5 2.8 24 130 32 38 16 30 60 46 16 nC ns ns (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 450 160 35 630 225 70 pF VGS(th) 1.0 RDS(on) gFS 2.0 3.6 0.06 0.065 0.07 0.075 Mhos 1.7 3.0 mV/C Ohms Vdc V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 34.5 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time S Fi See Figure 12

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MMDF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
6 I D , DRAIN CURRENT (AMPS) 6 VDS 10 V I D , DRAIN CURRENT (AMPS) 5 4 100C 3 2 1 0 25C TJ = -55C 2 2.5 3 3.5 4

VGS = 10 V 4.5 V 5 4.3 V 4.1 V 4 3 2

3.9 V 3.7 V

3.5 V

TJ = 25C

3.3 V

3.1 V

2.9 V 1 0 0.2 0.6 2.7 V 2.5 V 0 0.4 0.8 1 1.2 1.4 1.6 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 1.5 A TJ = 25C 0.08

Figure 2. Transfer Characteristics

TJ = 25C

0.07 VGS = 4.5

0.06 10 V

4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

0.05

0.5

1.5

2.5

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

2.0

VGS = 10 V ID = 1.5 A I DSS , LEAKAGE (nA)

VGS = 0 V TJ = 125C

1.5

1.0

10

100C

0.5

0 -50

-25

25

50

75

100

125

150

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MMDF3N03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

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MMDF3N03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 7. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10 Coss Crss Crss VDS = 0 V VGS = 0 V Ciss TJ = 25C

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
12 24

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

QT

VDS

VGS

18

Ciss

Q1

Q2

12

Q3

6 ID = 3 A TJ = 25C 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) 10

5 5 0 10 15 20 25 30 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0 12

Figure 8. Capacitance Variation

Figure 9. GatetoSource and DraintoSource Voltage versus Total Charge

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MMDF3N03HD
1000 VDD = 15 V ID = 3 A VGS = 10 V TJ = 25C 3.0 2.5 IS, SOURCE CURRENT (AMPS) 2.0 1.5 1.0 0.5 0 0.5 TJ = 25C VGS = 0 V

100 t, TIME (ns)

10

td(off) tr tf td(on)

10 RG, GATE RESISTANCE (OHMS)

100

0.6 0.65 0.7 0.75 0.8 0.55 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

0.85

Figure 10. Resistive Switching Time Variation versus Gate Resistance

Figure 11. Diode Forward Voltage versus Current

100 I D , DRAIN CURRENT (AMPS)

10

1 ms 10 ms

10 s 100 s

EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C

350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 9 A

dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT


Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

0.1

0.01 0.1

10

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MMDF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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MMDF3N03HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF3N03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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MMDF3N04HD
Preferred Device

Power MOSFET 3 Amps, 40 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided Avalanche Energy Specified
8 1 L Y WW = Location Code = Year = Work Week

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3 AMPERES 40 VOLTS RDS(on) = 80 mW


NChannel D

G S

MARKING DIAGRAM

SO8, Dual CASE 751 STYLE 14

D3N04H LYWW

PIN ASSIGNMENT
NSource NGate PSource PGate 1 2 3 4 8 7 6 5 NDrain NDrain PDrain PDrain

Top View

ORDERING INFORMATION
Device MMDF3N04HDR2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

521

November, 2000 Rev. 2

Publication Order Number: MMDF3N04HD/D

MMDF3N04HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C (Note 1.) Drain Current Continuous @ TA = 70C (Note 1.) Drain Current Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor (1) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor (2) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 4.0 mH, VDS = 40 Vdc) Symbol VDSS VDGR VGS ID ID IDM PD PD TJ, Tstg EAS Value 40 40 20 3.4 3.0 40 2.0 16 1.39 11.11 55 to 150 162 Unit Vdc Vdc Vdc Adc Apk Watts mW/C Watts mW/C C mJ

THERMAL RESISTANCE
Rating Thermal Resistance Junction to Ambient, PCB Mount (Note 1.) Junction to Ambient, PCB Mount (Note 2.) Symbol RJA RJA Typ. Max. 62.5 90 Unit C/W

1. When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ 10 Seconds) 2. When mounted on minimum recommended FR4 or G10 board (VGS = 10 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature.

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522

MMDF3N04HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 40 Vdc, VGS = 0 Vdc) (VDS = 40 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.4 Adc) (VGS = 4.5 Vdc, ID = 1.7 Adc) (Cpk 2.0) (Notes 4. & 6.) VGS(th) 1.0 (Notes 4. & 6.) RDS(on) (Note 4.) gFS 2.0 55 79 4.5 80 100 Mhos 2.0 4.9 3.0 Vdc mV/C m (Cpk 2.0) (Notes 4. & 6.) V(BR)DSS 40 IDSS IGSS 0.015 0.15 0.013 2.5 10 500 nAdc 4.3 Vdc mV/C Adc Symbol Min Typ Max Unit

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.7 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge

Ciss (VDS = 32 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Coss Crss

450 130 32

900 230 96

pF

td(on) (VDD = 20 Vdc, ID = 3.4 Adc, VGS = 10 Vdc, RG = 6 ) (Note 4.) tr td(off) tf td(on) (VDD = 20 Vdc, ID = 1.7 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 4.) tr td(off) tf QT (VDS = 40 Vdc, ID = 3.4 Adc, VGS = 10 Vdc) (Note 4.) Q1 Q2 Q3

9.0 15 28 19 13 77 17 20 13.9 2.1 3.7 5.4

18 30 56 38 26 144 34 40 28

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 3.4 Adc, VGS = 0 Vdc) (Note 4.) (IS = 3.4 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 3.4 3 4 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Storage Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. 6. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA VSD trr ta tb QRR 0.87 0.8 27 20 7.0 0.03 1.5 C ns Vdc

Reverse Recovery Time

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MMDF3N04HD
TYPICAL ELECTRICAL CHARACTERISTICS
6 I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 2.7 V 6 I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 1.5 100C 25C TJ = -55C

VGS = 10 V

3.9 V 4.5 V 4.3 V 4.1 V

TJ = 25C 3.7 V

VDS 10 V TJ = 25C

3.5 V

3.3 V 3.1 V 2.9 V 1.4 1.6 1.8 2

0.2

0.4

0.6

0.8

1.2

2.5

3.5

4.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 3.4 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.1 0.095 0.09 0.085 0.08 0.075 0.07 0.065 0.06 0.055 0.05 0

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 4.5

10 V

4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 4. OnResistance versus Drain Current and Gate Voltage

2.0

VGS = 10 V ID = 3.4 A I DSS , LEAKAGE (nA)

100

VGS = 0 V TJ = 125C

1.5

10 100C

1.0

0.5

25C

0 -50

-25

25

50

75

100

125

150

0.1

10

15

20

25

30

35

40

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MMDF3N04HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 VDS = 0 V Ciss C, CAPACITANCE (pF) 900 VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

600

Crss

Ciss

300

Coss Crss 5 VGS 0 VDS 5 10 15 20 25 30

0 10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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525

MMDF3N04HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) QT VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 40 1000 VDD = 20 V ID = 3.4 A VGS = 10 V TJ = 25C

9 VDS VGS

30

100 t, TIME (ns)

20

Q1 Q3

Q2

ID = 3.4 A TJ = 25C

10

10

td(off) tf tr td(on)

8 Qg, TOTAL GATE CHARGE (nC)

12

0 16

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
3.5 3.0 IS, SOURCE CURRENT (AMPS) 2.5 2.0 1.5 1.0 TJ = 25C VGS = 0 V

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.5 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 0.9

Figure 10. Diode Forward Voltage versus Current

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MMDF3N04HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 1 dc

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

160 1 ms EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) ID = 9 A 120

10

80

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

40

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MMDF3N04HD
TYPICAL ELECTRICAL CHARACTERISTICS
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.1 0.2 0.1 0.05 0.01 0.02 0.01 Chip Junction
0.0106 0.0431 0.1643 0.3507 0.4302

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02

0.0253 F

0.1406 F

0.5064 F

2.9468 F

177.14 F

Ambient 1.0E+03

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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528

MMDF3N04HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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529

MMDF3N04HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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530

MMDF3N06HD
Preferred Device

Advance Information Power MOSFET 3 Amps, 60 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. Dual MOSFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Source Current Continuous @ TA = 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 60 Vdc, VGS = 5.0 Vdc, VDS = 32 Vdc, IL = 15 Apk, L = 10 mH, RG = 25 ) Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID IDM IS PD TJ, Tstg EAS Value 60 20 3.3 16.5 1.7 2.0 55 to 150 105 Unit Vdc Vdc Adc Apk Adc Watts C mJ L Y WW = Location Code = Year = Work Week 8 1 SO8, Dual CASE 751 STYLE 11 D3N06 LYWW

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3 AMPERES 60 VOLTS RDS(on) = 100 mW


NChannel D D

G S

G S

MARKING DIAGRAM

PIN ASSIGNMENT
Source1 RJA TL 62.5 260 C/W C Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.

Top View

ORDERING INFORMATION
Device MMDF3N06HDR2 Package SO8 Shipping 2500 Tape & Reel

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

531

November, 2000 Rev. 1

Publication Order Number: MMDF3N06HD/D

MMDF3N06HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0 Vdc) (VDS = 48 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.3 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 30 Vdc, ID = 3.3 Adc, VGS = 10 Vdc) (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (VDD = 30 Vdc, ID = 3.3 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 30 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. trr ta tb QRR VSD 0.78 0.65 27.9 23 4.9 0.038 1.2 C ns Vdc 10.6 15.9 23.8 14.7 7.0 4.8 32.4 14.2 14.5 1.8 3.5 3.75 22.1 31.8 47.6 29.4 14 9.6 64.8 28.4 29 nC ns ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 442 97.6 24.4 618 137 34.2 pF VGS(th) 1.0 RDS(on) gFS 7.5 67.5 82.5 100 200 Mhos mW Vdc V(BR)DSS 60 IDSS IGSS 0.001 0.05 12 1.0 25 100 nAdc Adc Vdc Symbol Min Typ Max Unit

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532

MMDF3N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
6.0 I D , DRAIN CURRENT (AMPS) 5.0 6.0 I D , DRAIN CURRENT (AMPS) TJ = 25C 2.9 V 5.0 4.0 3.0 2.0 1.0 0 VDS 10 V

VGS = 10 V 6.0 V

3.3 V 3.5 V 3.7 V 3.9 V

3.1 V

4.5 V 4.3 V 4.0 4.1 V

100C 25C TJ = -55C

3.0 2.0 1.0 0 0.2 0.6

2.7 V 2.5 V 2.3 V 2.1 V 0 0.4 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1.5

1.75

2.0

2.25

2.5

2.75

3.0

3.25

3.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.3 0.25 0.2 0.15 0.1 0.05 0 ID = 3.0 A TJ = 25C 0.09

Figure 2. Transfer Characteristics

TJ = 25C 0.085 0.08 0.075 0.07 10 V 0.065 0.06 VGS = 4.5 V

2.0

3.0

4.0 5.0 6.0 7.0 8.0 9.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 0 0 VGS = 10 V ID = 1.5 A 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 0 V TJ = 125C 100C

I DSS , LEAKAGE (nA)

100

10

1.0

25C

5.0

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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533

MMDF3N06HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

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534

MMDF3N06HD
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta

t, TIME

Figure 7. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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535

MMDF3N06HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Ciss TJ = 25C 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 Q1 Q2 ID = 3.0 A TJ = 25C 14 16 QT VGS VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 -10 Coss 0 10 15 25 -5.0 5.0 20 VGS VDS VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30 Crss Ciss 12 30

20

10

Q3 2.0

VDS 4.0 6.0 8.0 12 10 Qg, TOTAL GATE CHARGE (nC)

Figure 8. Capacitance Variation


1000 2.5 IS, SOURCE CURRENT (AMPS) 2.0 1.5 1.0 0.5 0

Figure 9. GatetoSource and DraintoSource Voltage versus Total Charge

100 t, TIME (ns)

VDD = 30 V ID = 3.0 A VGS = 10 V TJ = 25C

TJ = 25C VGS = 0 V

td(off) 10 tf tr td(on)

1.0

1.0

10 RG, GATE RESISTANCE (OHMS)

100

0.5

0.6 0.65 0.7 0.75 0.55 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

0.8

Figure 10. Resistive Switching Time Variation versus Gate Resistance

Figure 11. Diode Forward Voltage versus Current

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536

MMDF3N06HD
100 VGS = 12 V SINGLE PULSE TA = 25C 120 EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 100 80 60 40 20 0 25 45 65 85 105 125 145 ID = 3.0 A

I D , DRAIN CURRENT (AMPS)

10

1.0 ms 10 ms

1.0

0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10

dc

0.01

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS


1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2

0.1

0.1 0.05 0.02 0.01

0.01

Chip Junction SINGLE PULSE

0.0106

0.0431

0.1643

0.3507

0.4302

0.0253 F

0.1406 F

0.5064 F

2.9468 F

177.14 F

Ambient 1000

0.001

0.00001

0.0001

0.001

0.01

0.1 t, TIME (s)

1.0

10

100

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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537

MMDF3N06HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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538

MMDF3N06HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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539

MMDF3N06VL Product Preview Power MOSFET 3 Amps, 60 Volts


NChannel SO8, Dual
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Onresistance Area Product about Onehalf that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than EFETt Predecessors Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Static Parameters are the Same for both TMOS V and TMOS EFET Miniature SO8 Surface Mount Package Saves Board Space Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage, (RGS = 1 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.3 Apk, L = 10 mH, RG = 25 ) Thermal Resistance, Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 60 60 15 3.3 0.7 10 2.0 55 to 150 54 Unit Vdc Vdc Vdc Adc Apk W C mJ 8 1 L Y WW = Location Code = Year = Work Week SO8, Dual CASE 751 STYLE 11 3N06V LYWW

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3 AMPERES 60 VOLTS RDS(on) = 130 m


NChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT
RJA TL 62.5 260 C/W C Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.

Top View

ORDERING INFORMATION
Device MMDF3N06VLR2 Package SO8 Shipping 2500 Tape & Reel

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2000

540

November, 2000 Rev. 1

Publication Order Number: MMDF3N06VL/D

MMDF3N06VL
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 3.3 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc, ID = 3.3 Adc) (VGS = 5.0 Vdc, ID = 1.65 Adc, TJ = 150C) Forward Transconductance (VDS = 15 Vdc, ID = 1.65 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 3.3 Adc, VGS = 5.0 Vdc) (VDD = 30 Vdc, ID = 3.3 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) Reverse Recovery Time (IS = 3.3 3 3 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. (IS = 3.3 Adc, VGS = 0 Vdc) (IS = 3.3 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr ta tb QRR 0.84 0.67 58 38 20 0.11 1.2 C Vdc ns 10 30 32 28 9.0 1.5 4.3 3.5 20 60 60 60 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 340 110 27 480 150 50 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 1.0 3.0 0.5 0.4 Mhos 0.12 0.13 Vdc 1.5 3.0 2.0 Vdc mV/C Ohm V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 66 Vdc mV/C Adc Symbol Min Typ Max Unit

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541

MMDF4N01HD
Preferred Device

Power MOSFET 4 Amps, 20 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
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4 AMPERES 20 VOLTS RDS(on) = 45 mW


NChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Thermal Resistance Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg RJA TL Value 20 20 12 5.2 4.1 48 2.0 55 to 150 62.5 260 Unit Vdc Vdc Vdc Adc Apk Watts C C/W C 8 1 L Y WW

SO8, Dual CASE 751 STYLE 11

D4N01 LYWW

= Location Code = Year = Work Week

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.

ORDERING INFORMATION
Device MMDF4N01HDR2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

542

November, 2000 Rev. 6

Publication Order Number: MMDF4N01HD/D

MMDF4N01HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc) (VDS = 12 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 4.0 Adc) (VGS = 2.7 Vdc, ID = 2.0 Adc) Forward Transconductance (VDS = 2.5 Vdc, ID = 2.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 10 Vdc, ID = 4.0 Adc, VGS = 4.5 Vdc) (VDD = 6.0 Vdc, ID = 4.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 2.3 ) (VDD = 6.0 Vdc, ID = 4.0 Adc, VGS = 2 2.7 7 Vdc Vdc, RG = 2.3 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 4.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.95 0.78 38 17 22 0.028 1.1 C ns Vdc 13 60 20 29 10 42 24 28 9.2 1.3 3.5 3.0 26 120 40 58 20 84 48 56 13 nC ns (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 425 270 115 595 378 230 pF VGS(th) 0.6 RDS(on) gFS 3.0 0.035 0.043 6.0 0.045 0.055 mhos 0.8 2.8 1.1 Vdc mV/C Ohm V(BR)DSS 20 IDSS IGSS 1.0 10 100 nAdc 2.0 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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543

MMDF4N01HD
TYPICAL ELECTRICAL CHARACTERISTICS
8 I D , DRAIN CURRENT (AMPS) 4.5 V 3.1 V 6 2.7 V 2.3 V 2.5 V 8 I D , DRAIN CURRENT (AMPS)

VGS = 8 V 2.1 V

TJ = 25C

VDS 10 V

1.9 V 1.7 V

100C 25C

2 1.5 V 1.3 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ = -55C

1.2

1.4

1.6

1.8

2.2

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.07 TJ = 25C ID = 2 A 0.06

0.050

TJ = 25C VGS = 2.7 V

0.045

0.05

0.040 4.5 V

0.04

0.035

0.03

6 2 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

0.030

4 6 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


2 VGS = 4.5 V ID = 4 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C

1.5

10

100C

0.5

-50

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

6 8 10 2 4 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

12

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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544

MMDF4N01HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2000 1600 C, CAPACITANCE (pF) 1200 800 400 0 Crss Coss Crss 8 4 VGS 0 VDS 4 8 12 VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

Ciss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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545

MMDF4N01HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 5 4 3 Q1 2 1 0 VDS Q2 ID = 4 A TJ = 25C Q3 0 2 4 6 8 4 2 0 10 VGS 6 QT 10 8 100 VDD = 6 V ID = 4 A VGS = 4.5 V TJ = 25C 10 tr tf VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

td(off) td(on)

1 0.1

10

100

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
4 VV == 00 VV GS GS TJ TJ == 25 25 C C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0 0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


546

MMDF4N01HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 1

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

10

10 s 100 s 1 ms

dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT


Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.

0.1

0.01 0.1

10

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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547

MMDF4N01HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086

0.01

0.0154 F

0.0854 F

0.3074 F

1.7891 F

107.55 F

Ambient 1.0E+03

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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548

MMDF4N01HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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549

MMDF4N01HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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550

MMDF5N02Z Power MOSFET 5 Amps, 20 Volts


NChannel SO8, Dual
EZFETst are an advanced series of Power MOSFETs which contain monolithic backtoback zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Zener Protected Gates Provide Electrostatic Discharge Protection Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 70C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Thermal Resistance Ambient Junction to Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg RJA Value 20 20 12 5.0 4.5 40 2.0 55 to 150 62.5 260 Unit Vdc Vdc Vdc Adc Apk Watts C C/W C 1 5N02Z L Y WW = Device Code = Location Code = Year = Work Week 8 SO8, Dual CASE 751 STYLE 11 5N02Z LYWW

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5 AMPERES 20 VOLTS RDS(on) = 40 m


NChannel D

MARKING DIAGRAM

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Maximum Temperature for Soldering TL 1. When mounted on 1 inch square FR4 or G10 board (VGS = 4.5 V, @ 10 Seconds).

Top View

ORDERING INFORMATION
Device MMDF5N02ZR2 Package SO8 Shipping 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2001

551

January, 2001 Rev. 2

Publication Order Number: MMDF5N02Z/D

MMDF5N02Z
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 12 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 5.0 Adc) (VGS = 2.7 Vdc, ID = 2.5 Adc) (Cpk 2.0) (Note 4.) VGS(th) 0.5 (Cpk 2.0) (Note 4.) RDS(on) gFS 3.0 34 44 5.6 40 50 Mhos 0.78 3.0 1.1 Vdc mV/C m (Cpk 2.0) (Note 4.) V(BR)DSS 20 IDSS IGSS 0.5 15 150 1.5 Adc 15 Vdc mV/C Adc Symbol Min Typ Max Unit

Forward Transconductance (VDS = 9.0 Vdc, ID = 2.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc) (VDD = 6.0 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc, RG = 6 ) (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz)

Ciss Coss Crss

450 330 160

630 460 225

pF

td(on) tr td(off) tf QT Q1 Q2 Q3

29 182 190 225 10.7 1.1 5.4 3.5

37 258 238 274 12

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 5.0 Adc, VGS = 0 Vdc) (IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 5.0 5 0 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA VSD trr ta tb QRR 0.78 0.65 195 72 123 0.5 1.0 C ns Vdc

Reverse Recovery Time

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552

MMDF5N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
10 I D , DRAIN CURRENT (AMPS) 8 6 4 2 0 8 I D , DRAIN CURRENT (AMPS) 7 6 5 4 3 2 1 0 0.4 0.8 1.2 1.6 2 0 0 0.5 1 1.5 100C 25C TJ = -55C 2 2.5

VGS = 12 V 4.5 V 2.7 V 2.3 V

TJ = 25C 2.0 V 1.9 V 1.8 V 1.7 V 1.6 V 1.5 V

VDS 10 V TJ = 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 2 3 4 6 7 5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8 ID = 5 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 1

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 2.7 V 4.5 V

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 10000 VGS = 4.5 V ID = 2.5 A 1000 I DSS , LEAKAGE (nA) 100 10 1 0.1

Figure 4. OnResistance versus Drain Current and Gate Voltage

1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150

VGS = 0 V TJ = 125C 100C

25C

2.5

7.5

10

12.5

15

17.5

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MMDF5N02Z
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1400 1200 C, CAPACITANCE (pF) 1000 800 600 400 200 0 -10 -5 0 5 10 15 Crss Ciss Coss Crss 20 Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MMDF5N02Z
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 5 4 3 2 1 0 0 2 4 6 8 10 ID = 5 A TJ = 25C 12 VDS QT VGS 6 5 4 3 2 1 0 14 1000 VDD = 6 V ID = 5 A VGS = 4.5 V TJ = 25C

t, TIME (ns)

Q3 Q1 Q2

100

tf td(off) tr

td(on)

10

Qg, TOTAL GATE CHARGE (nC)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

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555

MMDF5N02Z
5 4.5 I S , SOURCE CURRENT (AMPS) 4 3 2 1 0 3.5 2.5 1.5 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

di/dt = 300 A/s I S , SOURCE CURRENT

Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain to source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 25 C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the off state and the on state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded, and that the transition time (t r, tf ) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (T J(MAX) T C )/(R JC ). A power MOSFET designated E FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non linearly with an increase of peak current in avalanche and peak junction temperature.

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MMDF5N02Z
100 I D , DRAIN CURRENT (AMPS) VGS = 12 V SINGLE PULSE TC = 25C 10 ms

1 ms

10

dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.1

Figure 12. Maximum Rated Forward Biased Safe Operating Area

TYPICAL ELECTRICAL CHARACTERISTICS


1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02

0.1

0.01

0.01

SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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MMDF5N02Z INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270 inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMDF5N02Z
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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559

MMDF6N03HD
Preferred Device

Power MOSFET 6 Amps, 30 Volts


NChannel SO8, Dual
These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. Dual MOSFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Single Pulse (tp 10 s) Source Current Continuous @ TA = 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W) Thermal Resistance JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 sec. Symbol VDSS VGS ID IDM IS PD TJ, Tstg EAS Value 30 20 6.0 30 1.7 2.0 55 to 150 325 Unit Vdc Vdc Adc Apk Adc Watts C mJ 8 1 D6N03 L Y WW = Device Code = Location Code = Year = Work Week SO8, Dual CASE 751 STYLE 11 D6N03 LYWW

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6 AMPERES 30 VOLTS RDS(on) = 35 mW


NChannel D D

G S

G S

MARKING DIAGRAM

PIN ASSIGNMENT
RJA TL 62.5 260 C/W C Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

1. Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.

Top View

ORDERING INFORMATION
Device MMDF6N03HDR2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

560

November, 2000 Rev. 3

Publication Order Number: MMDF6N03HD/D

MMDF6N03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 3.9 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDD = 15 Vdc Vdc, VGS = 4.5 Vdc, ID = 1.0 Adc, RG = 6 0 ) 6.0 (VDD = 15 Vdc Vdc, VGS = 10 Vdc, ID = 1.0 Adc, RG = 6 0 ) 6.0 td(on) tr td(off) tf td(on) tr td(off) tf QT (VDS = 15 Vdc, ID = 5 5.0 0 Adc Adc, VGS = 10 Vdc) Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 5.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.77 0.65 54.5 14.8 39.7 0.048 1.2 C ns Vdc 8.2 8.48 89.6 61.1 11.8 51.3 47.2 62 15.7 2.0 4.6 3.86 16.4 16.9 179 122 23 102 94.5 104 31.4 nC ns ns (VDS = 24 Vdc, VGS = 0 Vdc, f=1 1.0 0 MH MHz) ) Ciss Coss Crss 430 217 67.5 600 300 135 pF VGS(th) 1.0 RDS(on) gFS 28 42 9.0 35 50 Mhos m Vdc V(BR)DSS 30 IDSS IGSS 1.0 20 100 nAdc Adc Vdc Symbol Min Typ Max Unit

Reverse Recovery Time

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MMDF6N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
12 10 8.0 6.0 4.0 2.0 0 VGS = 2.5 V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 12 10 8.0 6.0 4.0 2.0 0 1.5 2.0 2.5 3.0 VDS 10 V

10 V 6.0 V 4.5 V 4.3 V 4.1 V

3.9 V

3.7 V 3.5 V

TJ = 25C ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

3.3 V 3.1 V 2.9 V 2.7 V 1.8 2.0

100C

25C

TJ = -55C 3.5 4.0 4.5 5.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.30 0.25 0.20 0.15 0.10 0.05 0 2.0 TJ = 25C ID = 6 A R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.050

Figure 2. Transfer Characteristics

TJ = 25C 0.045 0.040 0.035 0.030 0.025 10 V VGS = 4.5 V

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 0.1 0 VGS = 10 V ID = 3 A IDSS , LEAKAGE (nA) 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 0 V TJ = 125C

100

10

100C

1.0

25C

5.0

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MMDF6N03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 -10 -5.0 0 5.0 10 15 20

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Ciss Coss Crss 25 30

VGS

VDS

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MMDF6N03HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 Q3 0 2.0 4.0 6.0 8.0 10 VDS 12 14 Qg, TOTAL GATE CHARGE (nC) 0 16 ID = 5 A TJ = 25C Q1 Q2 QT VGS 30 1000 V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 15 V ID = 6 A VGS = 10 V TJ = 25C

20

100 t, TIME (ns)

td(off) tf tr td(on)

10

10

1.0 1.0

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
5.0 4.5 IS , SOURCE CURRENT (AMPS) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MMDF6N03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 I D , DRAIN CURRENT (AMPS) VGS = 12 V SINGLE PULSE TA = 25C 10 ms 1.0 dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.
350 300 250 200 150 100 50 0 25 45 65 85 105 125 145 ID = 6 A

10

1.0 ms

0.01 0.1

EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MMDF6N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01 0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F AMBIENT

0.1

0.01

CHIP JUNCTION

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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566

MMDF6N03HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD = 150C 25C = 2.0 Watts 62.5C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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567

MMDF6N03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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568

MMDF7N02Z Power MOSFET 7 Amps, 20 Volts


NChannel SO8, Dual
EZFETst are an advanced series of Power MOSFETs which contain monolithic backtoback zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives.
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7 AMPERES 20 VOLTS RDS(on) = 27 m


NChannel D

Zener Protected Gates Provide Electrostatic Discharge Protection Designed to Withstand 200 V Machine Model and 2000 V Human Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life Logic Level Gate Drive Can be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode is Characterized for use in Bridge Circuits Diode Exhibits High Speed, with Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided Body Model

MARKING DIAGRAM

8 1 7N02Z L Y WW

SO8, Dual CASE 751 STYLE 11

7N02Z LYWW

= Device Code = Location Code = Year = Work Week

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View

ORDERING INFORMATION
Device MMDF7N02ZR2 Package SO8 Shipping 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2001

569

January, 2001 Rev. 1

Publication Order Number: MMDF7N02Z/D

MMDF7N02Z
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C (Note 1.) Continuous @ TA = 70C (Note 1.) Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor @ TA = 25C (Note 2.) Operating and Storage Temperature Range Symbol VDSS VDGR VGS ID ID IDM PD PD TJ, Tstg Symbol RqJA Max 20 20 12 7.0 4.6 35 2.0 16 1.39 11.11 55 to 150 Watts mW/C Watts mW/C C Unit Vdc Vdc Vdc Adc

THERMAL RESISTANCE
Parameter JunctiontoAmbient (Note 1.) JunctiontoAmbient (Note 2.) Typ Max 62.5 90 Unit C/W

ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)


Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Cpk 2.0) (Notes 4. & 5.) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 7.0 Adc) (VGS = 2.5 Vdc, ID = 3.5 Adc) 1. 2. 3. 4. 5. (Cpk 2.0) (Notes 4. & 5.) VGS(th) 0.5 RDS(on) 23 30 11 27 35 Mhos 0.7 2.5 1.0 Vdc mV/C m (Cpk 2.0) (Notes 4. & 5.) V(BR)DSS 20 IDSS IGSS 1.0 10 3.0 Adc 15 Vdc mV/C Adc Symbol Min Typ Max Unit

Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) (Note 4.)

gFS 5.0 When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ 10 seconds). When mounted on minimum recommended FR4 or G10 board (VGS = 10 V, @ Steady State). Repetitive rating; pulse width limited by maximum junction temperature. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA

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570

MMDF7N02Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 7.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 12 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc) (Note 6.) (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) (Note 6.) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage Reverse Recovery Time (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 6.) Reverse Recovery Stored Charge 6. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 7. Switching characteristics are independent of operating junction temperatures. (IS = 7.0 Adc, VGS = 0 Vdc) (Note 6.) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.90 0.84 780 190 590 5.7 1.1 C Vdc ns 31 230 725 780 17 1.4 6.7 6.5 62 460 1450 1560 24 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 450 350 110 630 490 155 pF Symbol Min Typ Max Unit

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571

MMDF7N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
ID, DRAIN CURRENT (AMPS) 10 V 4.5 V ID, DRAIN CURRENT (AMPS) 15 12 9.0 6.0 3.0 0 VGS = 1.7 V 2.3 V 2.1 V 15 12 9.0 6.0 3.0 0 25_C TJ = 25_C 1.9 V VDS 10 V

TJ = 100_C -55_C 0 0.5 1.0 1.5 2.0 2.5

0.5

1.0

1.5

2.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS) RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

0.06 0.05 0.04 0.03 0.02 0.01 ID = 7.0 A TJ = 25_C

0.05 TJ = 25_C 0.04 0.03 0.02 0.01 0 VGS = 2.7 V 4.5 V

4.0 6.0 8.0 2.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

2.0

4.0 6.0 8.0 ID, DRAIN CURRENT (AMPS)

10

12

Figure 3. OnResistance versus Drain Current


RDS(on) , DRAINTOSOURCE RESISTANCE (NORMALIZED) 2.0 VGS = 4.5 V ID = 3.5 A

Figure 4. OnResistance versus Drain Current and Gate Voltage

10,000 1000 100 10

VGS = 0 V

TJ = 125_C 100_C

1.0

I DSS , LEAKAGE (nA)

1.5

0.5

25_C 1.0 0.1

-50

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (_C)

4.0 8.0 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

20

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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572

MMDF7N02Z
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
3000 C, CAPACITANCE (pF) 2500 2000 1500 1000 500 0 -10 Crss Ciss Coss Crss -5.0 0 5.0 10 15 20 Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25_C

Coss

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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573

MMDF7N02Z
VGS , GATETOSOURCE VOLTAGE (VOLTS) 5.0 4.0 3.0 2.0 Q1 1.0 0 Q2 QT 15 12 9.0 6.0 TJ = 25_C 3.0 0 20 1000 VDD = 25 V ID = 1.0 A TJ = 25_C t, TIME (ns) 100 td(off) VDS , DRAINTOSOURCE VOLTAGE (VOLTS) tf

VDS

VGS

tr

td(on)

Q3 0 5.0 10

15

10

1.0

10 RG, GATE RESISTANCE (OHMS)

100

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
7.0 IS, SOURCE CURRENT (AMPS) 6.0 5.0 4.0 3.0 2.0 1.0 0 0.4 0.5 0.6 0.7 0.8 TJ = 25_C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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574

MMDF7N02Z
di/dt = 300 A/s I S, SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 ID, DRAIN CURRENT (AMPS) VGS = 4.5 V SINGLE PULSE TC = 25_C

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

100 S 1.0 ms 10 ms

10

1.0

0.1

0.01

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10

dc

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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575

MMDF7N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
1 Rthja(t) , EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

0.1

0.01

0.01

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02

t2 DUTY CYCLE, D = t1/t2 1.0E-01 t, TIME (s) 1.0E+00

t1

Figure 13. Thermal Response

di/dt IS ta trr tb TIME tp IS 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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576

MMDF7N02Z INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270 inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
T (max) * TA PD + J RqJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD + 150C * 25C + 2.0 Watts 62.5CW

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 62.5C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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577

MMDF7N02Z
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows
STEP 1 PREHEAT ZONE 1 RAMP" 200C STEP 2 VENT SOAK" STEP 3 HEATING ZONES 2 & 5 RAMP"

temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 4 HEATING ZONES 3 & 6 SOAK" STEP 5 HEATING ZONES 4 & 7 SPIKE" 170C 160C STEP 6 VENT STEP 7 COOLING 205 TO 219C PEAK AT SOLDER JOINT

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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578

MMDFS2P102 Power MOSFET 2 Amps, 20 Volts


PChannel SO8, FETKYt
The FETKY product family incorporates low RDS(on), true logic level MOSFETs packaged with industry leading, low forward drop, low leakage Schottky Barrier rectifiers to offer high efficiency components in a space saving configuration. Independent pinouts for MOSFET and Schottky die allow the flexibility to use a single component for switching and rectification functions in a wide variety of applications such as Buck Converter, BuckBoost, Synchronous Rectification, Low Voltage Motor Control, and Load Management in Battery Packs, Chargers, Cell Phones and other Portable Products. Power MOSFET with Low VF, Low IR Schottky Rectifier Lower Component Placement and Inventory Costs along with Board Space Savings Logic Level Gate Drive Can be Driven by Logic ICs Mounting Information for SO8 Package Provided IDSS Specified at Elevated Temperature Applications Information Provided
MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
(Note 1.) Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 MW) GatetoSource Voltage Continuous Drain Current (Note 3.) Continuous @ TA = 25C Continuous @ TA = 100C Single Pulse (tp v 10 ms) Total Power Dissipation @ TA = 25C (Note 2.) Single Pulse DraintoSource Avalanche Energy STARTING TJ = 25C VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W Symbol VDSS VDGR VGS ID ID IDM PD EAS Value 20 20 "20 3.3 2.1 20 2.0 324 Unit Vdc Vdc Vdc Adc Apk Watts mJ 8 1 L Y WW = Location Code = Year = Work Week SO8 CASE 751 STYLE 18 2P102 LYWW

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2 AMPERES 20 VOLTS RDS(on) = 160 mW VF = 0.39 Volts


PChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT
Anode Anode Source Gate 1 2 3 4 8 7 6 5 Cathode Cathode Drain Drain

1. Negative sign for Pchannel device omitted for clarity. 2. Pulse Test: Pulse Width 250 s, Duty Cycle 2.0%. 3. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

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ORDERING INFORMATION
Device MMDFS2P102R2 Package SO8 Shipping 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2000

579

November, 2000 Rev. 1

Publication Order Number: MMDFS2P102/D

MMDFS2P102
SCHOTTKY RECTIFIER MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Peak Repetitive Reverse Voltage DC Blocking Voltage Average Forward Current (Note 4.) (Rated VR) TA = 100C Peak Repetitive Forward Current (Note 3.) (Rated VR, Square Wave, 20 kHz) TA = 105C NonRepetitive Peak Surge Current (Surge applied at rated load conditions, halfwave, single phase, 60 Hz) VRRM VR IO Ifrm Ifsm 20 1.0 2.0 20 Volts Amps Amps Amps

THERMAL CHARACTERISTICS SCHOTTKY AND MOSFET


Thermal Resistance JunctiontoAmbient (Note 5.) MOSFET Thermal Resistance JunctiontoAmbient (Note 6.) MOSFET Thermal Resistance JunctiontoAmbient (Note 3.) MOSFET Thermal Resistance JunctiontoAmbient (Note 5.) Schottky Thermal Resistance JunctiontoAmbient (Note 6.) Schottky Thermal Resistance JunctiontoAmbient (Note 4.) Schottky Operating and Storage Temperature Range RqJA RqJA RqJA RqJA RqJA RqJA Tj, Tstg 167 100 62.5 204 122 83 55 to 150 C/W

4. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. 5. Mounted with minimum recommended pad size, PC Board FR4. 6. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), Steady State.

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580

MMDFS2P102
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Note 7.)
Characteristic OFF CHARACTERISTICS DrainSource Voltage (VGS = 0 Vdc, ID = 0.25 mA) Temperature Coefficient (Positive) Zero Gate Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) Gate Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 8.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) Static DrainSource Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 9.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDS = 10 Vdc, ID = 2.0 Adc, 5 Vdc VGS = 4 4.5 Vdc, RG = 6.0 ) td(on) tr td(off) tf QT Q1 Q2 Q3 DRAIN SOURCE DIODE CHARACTERISTICS Forward OnVoltage (Note 8.) Reverse Recovery Time (IS = 2.0 2 0 Adc, Adc VDD = 15 V V, dIS/dt = 100 A/s) Reverse Recovery Stored Charge (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta tb QRR 1.5 38 17 21 0.034 2.1 C ns V 19 66 25 37 15 1.2 5.0 4.0 38 132 50 74 20 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 420 290 116 588 406 232 pF VGS(th) 1.0 RDS(on) gFS 2.0 0.118 0.152 3.0 0.160 0.180 mhos 1.5 4.0 2.0 Vdc mV/C Ohms V(BR)DSS 20 IDSS IGSS 1.0 10 100 nAdc 25 Vdc mV/C Adc Symbol Min Typ Max Unit

SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)


g (Note ( ) Maximum Instantaneous Forward Voltage 8.) IF = 1.0 10A IF = 2.0 A Maximum Instantaneous Reverse Current (Note ( 8.) ) VR = 20 V Maximum Voltage Rate of Change VR = 20 V 7. Negative sign for Pchannel device omitted for clarity. 8. Pulse Test: Pulse Width 300 sec, Duty Cycle 2.0%. 9. Switching characteristics are independent of operating temperature. VF TJ = 25C 0.47 0.58 IR TJ = 25C 0.05 dV/dt 10,000 TJ = 125C 0.39 0.53 TJ = 125C 10 V/ms mA Volts

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MMDFS2P102
TYPICAL FET ELECTRICAL CHARACTERISTICS
4.0 4.0 VDS 10 V ID, DRAIN CURRENT (AMPS) 3.0

10 V

4.5 V

3.8 V

TJ = 25C

ID, DRAIN CURRENT (AMPS)

3.0

2.0

3.1 V

2.0

25C

1.0 VGS = 2.4 V 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

1.0

100C

TJ = -55C

1.0

1.5

2.0

2.5

3.0

3.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 TJ = 25C ID = 1.0 A 0.20

Figure 2. Transfer Characteristics

TJ = 25C 0.16 VGS = 4.5 V

0.12

10 V

0.08

2.0

4.0

6.0

8.0

10

0.04

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.6 1.4 1.2 1.0 0.8 0.6 -50 1.0 VGS = 10 V ID = 2.0 A IDSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 0 V

TJ = 125C

10 100C

-25

25

50

75

100

125

150

5.0

10

15

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MMDFS2P102
TYPICAL FET ELECTRICAL CHARACTERISTICS
1200 1000 C, CAPACITANCE (pF) 800 600 Crss 400 200 0 -10 Ciss 12 10 8.0 6.0 4.0 2.0 0 Q1 Q2 VGS ID = 2.0 A TJ = 25C Q3 0 4.0 8.0 VDS 12 QG, TOTAL GATE CHARGE (nC) QT 18 16 14 12 10 8.0 6.0 4.0 2.0 0 16

TJ = 25C

Ciss Coss Crss -5.0 VGS 0 VDS 5.0 10 15 20

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS = 0

VGS = 0

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge


2.0 IS, SOURCE CURRENT (AMPS) 1.6 1.2 0.8 0.4 0 VGS = 0 V TJ = 25C

Figure 7. Capacitance Variation


1000

t, TIME (ns)

100 td(off) tf tr 10 td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100

0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation versus Gate Resistance


100 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 s max. VGS = 20 V SINGLE PULSE TC = 25C dc 350 300 250 200 150 100 50 0 25

Figure 10. Diode Forward Voltage versus Current

ID = 6.0 A

ID, DRAIN CURRENT (AMPS)

10

10 ms 1.0 ms 100 ms 10 ms

1.0

0.1

0.01

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10

100

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

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MMDFS2P102
TYPICAL FET ELECTRICAL CHARACTERISTICS
1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W 0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F AMBIENT 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

0.01

0.001

CHIP JUNCTION SINGLE PULSE

0.0001

1.0E-05

1.0E-04

Figure 13. FET Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS


10 10 TJ = 125C

IF, INSTANTANEOUS FORWARD CURRENT (AMPS)

TJ = 125C 1.0 85C 25C

IF, INSTANTANEOUS FORWARD CURRENT (AMPS)

1.0

85C 25C

-40C 0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

0.1

0.2

0.4

0.6

0.8

1.0

1.2

1.4

VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

Figure 15. Typical Forward Voltage

Figure 16. Maximum Forward Voltage

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584

MMDFS2P102
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
1E-2 IR, REVERSE CURRENT (AMPS) 1E-3 1E-4 1E-5 25C 1E-6 1E-7 TJ = 125C 85C 1E-1 1E-2 1E-3 1E-4 25C 1E-5 1E-6 TJ = 125C

5.0

10

15

20

IR, MAXIMUM REVERSE CURRENT (AMPS)

5.0

10

15

20

VR, REVERSE VOLTAGE (VOLTS)

VR, REVERSE VOLTAGE (VOLTS)

Figure 17. Typical Reverse Current


1000 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0

Figure 18. Maximum Reverse Current

TYPICAL CAPACITANCE AT 0 V = 170 pF

IO , AVERAGE FORWARD CURRENT (AMPS)

dc SQUARE WAVE Ipk/Io = p Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20

FREQ = 20 kHz

C, CAPACITANCE (pF)

100

10

5.0

10

15

20

20

40

60

80

100

120

140

160

VR, REVERSE VOLTAGE (VOLTS)

TA, AMBIENT TEMPERATURE (C)

Figure 19. Typical Capacitance


0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 Ipk/Io = p Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20 SQUARE WAVE dc

Figure 20. Current Derating

PFO , AVERAGE POWER DISSIPATION (WATTS)

2.0

IO, AVERAGE FORWARD CURRENT (AMPS)

Figure 21. Forward Power Dissipation

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MMDFS2P102
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2

0.1

0.1 0.05 0.02 0.01 NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.0031 W CHIP JUNCTION 0.0014 F SINGLE PULSE 0.0154 W 0.0082 F 0.1521 W 0.4575 W 0.3719 W 0.1052 F 2.7041 F 158.64 F AMBIENT 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

0.01

0.001

1.0E-05

1.0E-04

Figure 22. Schottky Thermal Response

TYPICAL APPLICATIONS STEP DOWN SWITCHING REGULATORS


LO + Vin CO + Vout LOAD

Buck Regulator
LO + Vin CO + Vout LOAD

Synchronous Buck Regulator

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MMDFS2P102
TYPICAL APPLICATIONS STEP UP SWITCHING REGULATORS
L1 + Vin Q1 CO + Vout LOAD

Boost Regulator

+ Vin CO

+ Vout LOAD

BuckBoost Regulator

MULTIPLE BATTERY CHARGERS


Buck Regulator/Charger
Q1 + Vin D1 CO LO Q2 D2 BATT #1

Q3

D3 BATT #2

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587

MMDFS2P102
TYPICAL APPLICATIONS Lilon BATTERY PACK APPLICATIONS
Battery Pack
PACK +

Li-Ion BATTERY CELLS

SMART IC

DISCHARGE

CHARGE

Q1

Q2 PACK -

SCHOTTKY

SCHOTTKY

Applicable in battery packs which require a high current level. During charge cycle Q2 is on and Q1 is off. Schottky can reduce power loss during fast charge. During discharge Q1 is on and Q2 is off. Again, Schottky can reduce power dissipation. Under normal operation, both transistors are on.

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588

MMDFS6N303 Product Preview Power MOSFET 6 Amps, 30 Volts


NChannel SO8, FETKYt
The FETKY product family incorporates low RDS(on), true logic level MOSFETs packaged with industry leading, low forward drop, low leakage Schottky Barrier rectifiers to offer high efficiency components in a space saving configuration. Independent pinouts for MOSFET and Schottky die allow the flexibility to use a single component for switching and rectification functions in a wide variety of applications such as Buck Converter, BuckBoost, Synchronous Rectification, Low Voltage Motor Control, and Load Management in Battery Packs, Chargers, Cell Phones and other Portable Products. Power MOSFET with Low VF Lower Component Placement and Inventory Costs along with Board Space Savings Logic Level Gate Drive Can be Driven by Logic ICs Mounting Information for SO8 Package Provided Applications Information Provided R2 Suffix for Tape and Reel (2500 units/13 reel) Marking: 6N303
MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
(Note 1.) Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 MW) GatetoSource Voltage Continuous Drain Current (Note 2.) Continuous @ TA = 25C Single Pulse (tp v 10 ms) Total Power Dissipation @ TA = 25C (Note 2.) Single Pulse DraintoSource Avalanche Energy Startin TJ = 25C VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 W Symbol VDSS VDGR VGS ID IDM PD EAS Value 30 30 "20 6.0 30 2.0 325 Unit Vdc Vdc Vdc Adc Apk Watts 8 1 6N303 L Y WW = Device Code = Location Code = Year = Work Week SO8 CASE 751 STYLE 18 6N303 LYWW

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6 AMPERES 30 VOLTS RDS(on) = 35 mW VF = 0.42 Volts


NChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT
mJ Anode Anode Source Gate 1 2 3 4 8 7 6 5 Cathode Cathode Drain Drain

1. Pulse Test: Pulse Width 250 s, Duty Cycle 2.0%. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

Top View

ORDERING INFORMATION
Device MMDFS6N303R2
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.

Package SO8

Shipping 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2000

589

November, 2000 Rev. 1

Publication Order Number: MMDFS6N303/D

MMDFS6N303
SCHOTTKY RECTIFIER MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Peak Repetitive Reverse Voltage DC Blocking Voltage Average Forward Current (Note 3.) (Rated VR) TA = 104C Peak Repetitive Forward Current (Note 3.) (Rated VR, Square Wave, 20 kHz) TA = 108C NonRepetitive Peak Surge Current (Surge applied at rated load conditions, halfwave, single phase, 60 Hz) VRRM VR IO 2.0 Ifrm 4.0 Ifsm 30 Amps Amps 30 Volts Amps

THERMAL CHARACTERISTICS SCHOTTKY AND MOSFET


Thermal Resistance JunctiontoAmbient (Note 4.) MOSFET Thermal Resistance JunctiontoAmbient (Note 5.) MOSFET Thermal Resistance JunctiontoAmbient (Note 2.) MOSFET Thermal Resistance JunctiontoAmbient (Note 4.) Schottky Thermal Resistance JunctiontoAmbient (Note 5.) Schottky Thermal Resistance JunctiontoAmbient (Note 3.) Schottky Operating and Storage Temperature Range RqJA RqJA RqJA RqJA RqJA RqJA Tj, Tstg 167 97 62.5 197 97 62.5 55 to 150 C/W

MOSFET ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 6.)
Characteristic OFF CHARACTERISTICS DrainSource Voltage (VGS = 0 Vdc, ID = 0.25 mA) Temperature Coefficient (Positive) Zero Gate Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) Gate Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 6.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) Static DrainSource Resistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 3.9 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 3. 4. 5. 6. (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 430 217 67.5 600 300 135 pF VGS(th) 1.0 RDS(on) gFS 28 42 9.0 35 50 mhos mW Vdc V(BR)DSS 30 IDSS IGSS 1.0 20 100 nAdc Vdc mV/C Adc Symbol Min Typ Max Unit

Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max. Mounted with minimum recommended pad size, PC Board FR4. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), Steady State. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.

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MMDFS6N303
MOSFET ELECTRICAL CHARACTERISTICS continued (TC = 25C unless otherwise noted) (Note 7.)
Characteristic SWITCHING CHARACTERISTICS (Note 8.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (VDD = 15 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf QT Q1 Q2 Q3 DRAIN SOURCE DIODE CHARACTERISTICS Forward OnVoltage (Note 7.) Reverse Recovery Time (VGS = 0 V V, IS = 5.0 50A A, dIS/dt = 100 A/s) Reverse Recovery Stored Charge (IS = 1.7 Adc, VGS = 0 Vdc) VSD trr ta tb QRR 0.77 54.5 14.8 39.7 0.048 1.2 C ns Vdc 8.2 8.5 89.6 61.1 15.7 2.0 4.6 3.9 16.5 17 179 122 31.4 nC ns Symbol Min Typ Max Unit

SCHOTTKY RECTIFIER ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)


g (Note ( ) Maximum Instantaneous Forward Voltage 7.) IF = 100 mAdc Ad IF = 3.0 Adc IF = 6.0 Adc Maximum Instantaneous Reverse Current (Note ( 7.) ) VR = 30 V VF TJ = 25C 0.28 0.42 0.50 IR TJ = 25C 250 Maximum Voltage Rate of Change VR = 30 V 7. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 8. Switching characteristics are independent of operating junction temperature. dV/dt 10,000 TJ = 125C 0.13 0.33 0.45 TJ = 125C 25 mA V/ms mA Volts

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MMDFS6N303
TYPICAL FET ELECTRICAL CHARACTERISTICS
12 10 8.0 6.0 4.0 2.0 0 VGS = 2.9 V 3.5 V 3.3 V 12 10 8.0 6.0 4.0 2.0 0 25C 125C TJ = -55C VDS 10 V

10 V

4.5 V

3.9 V

TJ = 25C ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

1.5

2.5

3.5

4.5

5.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


0.3 TJ = 25C ID = 6.0 A 0.2 R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.05

Figure 2. Transfer Characteristics


TJ = 25C VGS = 4.5 V 0.04

0.1

0.03

10 V

2.0

4.0

6.0

8.0

10

0.02

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus GateToSource Voltage


1.8 VGS = 10 V ID = 6.0 A IDSS , LEAKAGE (nA) 1.4 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage


VGS = 0 V TJ = 125C

1.0

10

100C

0.6

0.2 -50

-25

25

50

75

100

125

150

1.0

5.0

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MMDFS6N303
TYPICAL FET ELECTRICAL CHARACTERISTICS
12 10 8.0 Q1 6.0 4.0 2.0 0 ID = 5.0 A TJ = 25C Q3 0 4.0 8.0 VDS 12 QG, TOTAL GATE CHARGE (nC) 0 16 10 Q2 VGS QT 30

1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 -10

Ciss

TJ = 25C

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS = 0

VGS = 0

20

Crss Ciss Coss Crss -5.0 VGS 0 VDS 5.0 10 15 20 25 30

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge


5.0 IS, SOURCE CURRENT (AMPS) 4.0 3.0 2.0 1.0 0 VGS = 0 V TJ = 25C

Figure 7. Capacitance Variation


1000

td(off) 100 t, TIME (ns) tf tr 10 td(on)

1.0

1.0

10 RG, GATE RESISTANCE (OHMS)

100

0.5

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation versus Gate Resistance


100 Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 s max. 1.0 ms 10 ms VGS = 12 V SINGLE PULSE TC = 25C dc 350 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 300 250 200 150 100 50 0 25

Figure 10. Diode Forward Voltage versus Current

ID = 6.0 A

ID, DRAIN CURRENT (AMPS)

10

1.0

0.1

0.01

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com
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Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

MMDFS6N303
TYPICAL FET ELECTRICAL CHARACTERISTICS
1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 CHIP JUNCTION SINGLE PULSE 0.001 0.00001 0.0001 0.001 0.01 0.1 t, TIME (s) 1.0 10 100 0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F AMBIENT 1000

0.1

Figure 13. FET Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS


10 85C 25C 10 85C TJ = 125C 25C

IF, INSTANTANEOUS FORWARD CURRENT (AMPS)

1.0

TJ = 125C

-40C

IF, INSTANTANEOUS FORWARD CURRENT (AMPS)

1.0

0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

VF, MAXIMUM INSTANTANEOUS FORWARD VOLTAGE (VOLTS)

Figure 15. Typical Forward Voltage

Figure 16. Maximum Forward Voltage

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594

MMDFS6N303
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
0.1 IR, REVERSE CURRENT (AMPS) 0.01 0.001 TJ = 125C 85C 0.1 TJ = 125C 0.01 0.001 0.0001 25C

0.0001 25C

0.00001 0.000001

5.0

10

15

20

25

30

IR, MAXIMUM REVERSE CURRENT (AMPS)

0.00001

0.000001

5.0

10

15

20

25

30

VR, REVERSE VOLTAGE (VOLTS)

VR, REVERSE VOLTAGE (VOLTS)

Figure 17. Typical Reverse Current

Figure 18. Maximum Reverse Current

IO , AVERAGE FORWARD CURRENT (AMPS)

1000

5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 SQUARE WAVE Ipk/Io = p Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20 dc FREQ = 20 kHz

C, CAPACITANCE (pF)

100

10

5.0

10

15

20

25

30

20

40

60

80

100

120

140

160

VR, REVERSE VOLTAGE (VOLTS)

TA, AMBIENT TEMPERATURE (C)

Figure 19. Typical Capacitance

Figure 20. Current Derating

PFO , AVERAGE POWER DISSIPATION (WATTS)

1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 1.0 2.0 3.0 4.0 5.0 Ipk/Io = 5.0 Ipk/Io = 10 Ipk/Io = 20 Ipk/Io = p SQUARE WAVE dc

IO, AVERAGE FORWARD CURRENT (AMPS)

Figure 21. Forward Power Dissipation

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MMDFS6N303
TYPICAL SCHOTTKY ELECTRICAL CHARACTERISTICS
1.0 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2

0.1

0.1 0.05 0.02 0.01 NORMALIZED TO RqJA AT STEADY STATE (1 PAD) 0.1010 W CHIP JUNCTION 39.422 mF SINGLE PULSE 1.2674 W 27.987 W 30.936 W 36.930 W 0.2292 F 2.267 F AMBIENT 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

0.01

493.26 mF 0.0131 F

0.001

1.0E-05

1.0E-04

1.0E-03

Figure 22. Schottky Thermal Response

TYPICAL APPLICATIONS STEP DOWN SWITCHING REGULATORS


LO + Vin CO + Vout LOAD

Buck Regulator
LO + Vin CO + Vout LOAD

Synchronous Buck Regulator

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596

MMDFS6N303
TYPICAL APPLICATIONS STEP UP SWITCHING REGULATORS
L1 + Vin Q1 CO + Vout LOAD

Boost Regulator

+ Vin CO

+ Vout LOAD

BuckBoost Regulator

MULTIPLE BATTERY CHARGERS


Buck Regulator/Charger
Q1 + Vin D1 CO LO Q2 D2 BATT #1

Q3

D3 BATT #2

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597

MMDFS6N303
TYPICAL APPLICATIONS Lilon BATTERY PACK APPLICATIONS
Battery Pack
PACK +

Li-Ion BATTERY CELLS

SMART IC

DISCHARGE

CHARGE

Q1

Q2 PACK -

SCHOTTKY

SCHOTTKY

Applicable in battery packs which require a high current level. During charge cycle Q2 is on and Q1 is off. Schottky can reduce power loss during fast charge. During discharge Q1 is on and Q2 is off. Again, Schottky can reduce power dissipation. Under normal operation, both transistors are on.

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598

MMFT107T1
Preferred Device

Power MOSFET 250 mA, 200 Volts


NChannel SOT223
This Power MOSFET is designed for high speed, low loss power switching applications such as switching regulators, dcdc converters, solenoid and relay drivers. The device is housed in the SOT223 package which is designed for medium power surface mount applications. Silicon Gate for Fast Switching Speeds Low Drive Requirement The SOT223 Package can be soldered using wave or reflow. The formed leads absorb thermal stress during soldering eliminating the possibility of damage to the die.
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage NonRepetitive Drain Current Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C Operating and Storage Temperature Range Symbol VDSS VGS ID PD Value 200 20 250 0.8 6.4 TJ, Tstg 65 to 150 Unit Volts Volts mAdc Watts mW/C C
1 4

http://onsemi.com

250 mA 200 VOLTS RDS(on) = 14 W


NChannel D

G S

MARKING DIAGRAM

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient Maximum Temperature for Soldering Purposes Time in Solder Bath RJA TL 260 10 156 C/W

2 3

TO261AA CASE 318E STYLE 3

FT107 LWW

C Sec

L WW

= Location Code = Work Week

1. Device mounted on FR 4 glass epoxy printed circuit using minimum recommended footprint.

PIN ASSIGNMENT
4 Drain

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT107T1 MMFT107T3 Package SOT223 SOT223 Shipping 1000 Tape & Reel 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

599

November, 2000 Rev. 4

Publication Order Number: MMFT107T1/D

MMFT107T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage (VGS = 0, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 130 V, VGS = 0) GateBody Leakage Current Reverse (VGS = 15 Vdc, VDS = 0) V(BR)DSS IDSS IGSS 200 30 10 Vdc nAdc nAdc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 200 mA) DraintoSource OnVoltage (VGS = 10 V, ID = 200 mA) Forward Transconductance (VDS = 25 V, ID = 250 mA) VGS(th) RDS(on) VDS(on) gfs 1.0 300 3.0 14 2.8 Vdc Ohms Vdc mmhos

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance (VDS = 25 V V, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 60 30 6.0 pF

SOURCE DRAIN DIODE CHARACTERISTICS


Diode Forward Voltage Continuous Source Current, Body Diode Pulsed Source Current, Body Diode (VGS = 0, IS = 250 mA) VF IS ISM 0.8 250 500 V mA

2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.

TYPICAL ELECTRICAL CHARACTERISTICS


2.5 TJ = 25C I D, DRAIN CURRENT (AMPS) 2 1.5 1 0.5 0 3V VGS = 10 V 500 VDS = 10 V I D, DRAIN CURRENT (mA) 400 300 200 100 0

6V 4V

5V

TJ = 125C -55C 0

25C 5

4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

10

1 2 3 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

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600

MMFT107T1
TYPICAL ELECTRICAL CHARACTERISTICS
10 VGS = 10 V 8 6 4 25C 2 -55C 0 0 100 200 300 ID, DRAIN CURRENT (AMPS) 400 500 TJ = 125C RDS(on) , DRAIN-SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN-SOURCE RESISTANCE (OHMS) 10 ID = 1 A VGS = 10 V

0.1 -75

-50

-25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 3. OnResistance versus Drain Current


1

Figure 4. OnResistance Variation with Temperature

250 200 C, CAPACITANCE (pF) 150 100 50 Crss 0 0 5 10 15 20 25 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 30 Coss VGS = 0 V f = 1 MHz TJ = 25C

I D, DRAIN CURRENT (AMPS)

0.1

Ciss

TJ = 125C 0

25C

0.01

0.3 0.6 0.9 1.2 1.5 VSD, SOURCE-DRAIN DIODE FORWARD VOLTAGE (VOLTS)

Figure 5. SourceDrain Diode Forward Voltage


10 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 Qg, TOTAL GATE CHARGE (nC) 4 4.5 5 160 V VDS = 100 V gFS, TRANSCONDUCTANCE (mhos) 9 ID = 200 mA

Figure 6. Capacitance Variation

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

2 VDS = 10 V 1.5

TJ = -55C 25C 125C

0.5

100

200 300 ID, DRAIN CURRENT (AMPS)

400

500

Figure 7. Gate Charge versus GatetoSource Voltage

Figure 8. Transconductance

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601

MMFT107T1 INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 0.8 watts 156C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.8 watts.

The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.8 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the collector pad. By increasing the area of the collector pad, the power dissipation can be increased. Although the power dissipation can almost be doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus collector pad area is shown in Figure 9.

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602

MMFT107T1
160 R JA , Thermal Resistance, Junction to Ambient (C/W) Board Material = 0.0625 G10/FR4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C

140

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C.

80 0.0

Figure 9. Thermal Resistance versus Collector Pad Area for the SOT-223 Package (Typical)

board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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603

MMFT107T1
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 10 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 10. Typical Solder Heating Profile

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604

MMFT2406T1
Preferred Device

Power MOSFET 700 mA, 240 Volts


NChannel SOT223
This Power MOSFET is designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers. The device is housed in the SOT223 package which is designed for medium power surface mount applications. Silicon Gate for Fast Switching Speeds High Voltage 240 Vdc Low Drive Requirement The SOT223 Package can be soldered using wave or reflow. The formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die.
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C Operating and Storage Temperature Range Symbol VDS VGS ID PD Value 240 20 700 1.5 12 TJ, Tstg 65 to 150 Unit Vdc Vdc mAdc Watts mW/C C
1 2 3 4

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700 mA 240 VOLTS RDS(on) = 6.0 W


NChannel D

G S

MARKING DIAGRAM

TO261AA CASE 318E STYLE 3

T2406 LWW

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient (surface mounted) (Note 1.) Lead Temperature for Soldering Purposes, 1/16 from case Time in Solder Bath RJA 83.3 C/W

L WW

= Location Code = Work Week

TL

260 10

PIN ASSIGNMENT
Sec
4 Drain

1. Device mounted on a glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.059 in.; mounting pad for the collector lead min. 0.93 sq. in.

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT2406T1 MMFT2406T3 Package SOT223 SOT223 Shipping 1000 Tape & Reel 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

605

November, 2000 Rev. 2

Publication Order Number: MMFT2406T1/D

MMFT2406T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristics Symbol Min Max Unit

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage (VGS = 0, ID = 100 A) Zero Gate Voltage Drain Current (VDS = 120 V, VGS = 0) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) V(BR)DSS IDSS IGSS 240 10 100 Vdc Adc nAdc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DraintoSource OnResistance (VGS = 2.5 Vdc, ID = 0.1 Adc) (VGS = 10 Vdc, ID = 0.5 Adc) DraintoSource OnVoltage (VGS = 10 V, ID = 0.5 A) Forward Transconductance (VDS = 6.0 V, ID = 0.5 A) VGS(th) RDS(on) VDS(on) gFS 300 10 6.0 3.0 Vdc mmhos 0.8 2.0 Vdc Ohms

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. (VDS = 25 V V, VGS = 0, 0 f = 1.0 MHz) Ciss Coss Crss 125 50 20 pF

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606

MMFT2406T1 INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.5 watts 83.3C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.5 watts.

The 83.3C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.5 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the collector pad. By increasing the area of the collector pad, the power dissipation can be increased. Although the power dissipation can almost be doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus collector pad area is shown in Figure 1.

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607

MMFT2406T1
R JA , Thermal Resistance, Junctionto Ambient (C/W) 160 Board Material = 0.0625 G10/FR4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C

140

80 0.0

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C.

Figure 1. Thermal Resistance versus Collector Pad Area for the SOT-223 Package (Typical)

board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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608

MMFT2406T1
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 2 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 2. Typical Solder Heating Profile

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609

MMFT2955E
Preferred Device

Power MOSFET 1 Amp, 60 Volts


PChannel SOT223
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient device also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. The device is housed in the SOT223 package which is designed for medium power surface mount applications. Silicon Gate for Fast Switching Speeds The SOT223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die
MAXIMUM RATINGS (TA = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous Drain Current Pulsed Total Power Dissipation @ TA = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 V, VGS = 10 V, Peak IL= 1.2 A, L = 0.2 mH, RG = 25 ) Symbol VDS VGS ID IDM PD (Note 1.) TJ, Tstg EAS Value 60 15 1.2 4.8 0.8 6.4 65 to 150 108 Vdc Adc
4

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1 AMPERE 60 VOLTS RDS(on) = 300 mW


PChannel D

G S

Unit

MARKING DIAGRAM

Watts mW/C C mJ

2 3

TO261AA CASE 318E STYLE 3

2955E LWW

2955E L WW

= Device Code = Location Code = Work Week

PIN ASSIGNMENT
4 Drain

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient (surface mounted) Maximum Temperature for Soldering Purposes, Time in Solder Bath RJA 156 260 TL 10 Sec
1

C/W C

1. Power rating when mounted on FR4 glass epoxy printed circuit board using recommended footprint.

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT2955ET1 MMFT2955ET3 Package SOT223 SOT223 Shipping 1000 Tape & Reel 1000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

610

November, 2000 Rev. 5

Publication Order Number: MMFT2955E/D

MMFT2955E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage, (VGS = 0, ID = 250 A) Zero Gate Voltage Drain Current, (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current, (VGS = 15 V, VDS = 0) ON CHARACTERISTICS Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) Static DraintoSource OnResistance, (VGS = 10 V, ID = 0.6 A) DraintoSource OnVoltage, (VGS = 10 V, ID = 1.2 A) Forward Transconductance, (VDS = 15 V, ID = 0.6 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge (VDS = 48 V, ID = 1.2 A, VGS = 10 Vdc) S Figures See Fi 15 and d 16 (VDD = 25 V, ID = 1.6 A VGS = 10 V V, RG = 50 ohms, ohms RGS = 25 ohms) td(on) tr td(off) tf Qg Qgs Qgd 18 29 44 32 18 2.8 7.5 nC ns (VDS = 20 V, VGS = 0, f = 1 MH MHz) ) Ciss Coss Crss 460 210 84 pF VGS(th) RDS(on) VDS(on) gFS 2.0 7.5 4.5 0.3 0.48 Vdc Ohms Vdc mhos V(BR)DSS IDSS IGSS 100 1.0 50 nAdc 60 Vdc Adc Symbol Min Typ Max Unit

SOURCE DRAIN DIODE CHARACTERISTICS (Note 3.) Forward OnVoltage Forward TurnOn Time Reverse Recovery Time IS = 1.2 A, VGS = 0 IS = 1.2 A, VGS = 0, dlS/dt = 400 A/s, s VR = 30 V VSD ton trr 1.0 Vdc

Limited by stray inductance 90 ns

2. Switching characteristics are independent of operating junction temperature. 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

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611

MMFT2955E
TYPICAL ELECTRICAL CHARACTERISTICS
10 8 6 4 5V 2 VGS = 4 V 0 0 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 10 15 V 1.2 1.1 1 0.9 0.8 0.7 -50

20 V

10 V TJ = 25C

VGS(th), GATE THRESHOLD VOLTS (NORMALIZED)

8V 7V

I D, DRAIN CURRENT (AMPS)

VDS = VGS ID = 1 mA

6V

0 50 100 TJ, JUNCTION TEMPERATURE (C)

150

Figure 1. On Region Characteristics

Figure 2. GateThreshold Voltage Variation With Temperature


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 ID, DRAIN CURRENT (AMPS) 8 25C -55C VGS = 10 V 100C

8 VDS = 10 V 6

-55C

25C 100C

I D, DRAIN CURRENT (AMPS)

25C

-55C

100C -55C 0 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 2 10

Figure 3. Transfer Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.5 0.4 0.3 0.2 0.1 0 TJ = 25C ID = 1.2 A 0.5 0.4 0.3 0.2 0.1

Figure 4. OnResistance versus Drain Current

VGS = 10 V ID = 1.2 A

7 10 13 16 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

19

0 -50

0 50 100 TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance versus GatetoSource Voltage

Figure 6. OnResistance versus Junction Temperature

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612

MMFT2955E
FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a ambient temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal ResistanceGeneral Data and Its Use provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, BVDSS. The switching SOA is applicable for both turnon and turnoff of the devices for switching times less than one microsecond.
1.0 r(t), EFFECTIVE THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 P(pk) RJA(t) = r(t) RJA RJA = 156C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t)

10 20ms 1 100 ms

ID , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TA = 25C

500 ms 1s 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 DC

0.01 0.1

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased Safe Operating Area

0.01

t2

DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 1.0E+00 1.0E+01

0.001 1.0E-05

Figure 8. Thermal Response

COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated sourcedrain current versus reapplied drain voltage when the sourcedrain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 9 are present. Full or halfbridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak draintosource voltage that the device must sustain during commutation; IFM is the maximum forward sourcedrain diode current just prior to the onset of commutation. VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in ON Semiconductors test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was attained with dI S /dt of 400 A/ s.
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613

MMFT2955E
15 V 0 VGS IFM 90% IS 10% ton IRM tfrr VDS(pk) VR VDS VdsL MAX. CSOA STRESS AREA dlS/dt trr

0.25 IRM

Vf

Figure 9. Commutating Waveforms


6 IS , SOURCE CURRENT (AMPS) 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 VGS dIS/dt 400 A/s

RGS

DUT

VR + IFM + 20 V VR = 80% OF RATED VDSS VdsL = Vf + Li dlS/dt IS VDS Li

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 10. Commutating Safe Operating Area (CSOA)

Figure 11. Commutating Safe Operating Area Test Circuit

BVDSS

L VDS IL VDD t RG VDD tP t, (TIME) IL(t)

Figure 12. Unclamped Inductive Switching Test Circuit

Figure 13. Unclamped Inductive Switching Waveforms

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614

MMFT2955E
1800 1600 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 15 Ciss Coss Crss 10 5 0 5 10 15 20 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Coss VGS Crss Ciss VDS TJ = 25C f = 1 MHz

Figure 14. Capacitance Variation with Voltage

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10 9 8 7 6 5 4 3 2 1 0 0 3 7.5 13 Qg, TOTAL GATE CHARGE (nC) 20 TJ = 25C VDS = 48 V ID = 1.2 A

Figure 15. Gate Charge versus GateToSource Voltage

+18V 1mA 2N3904 2N3904 47k 100

VDD 10V 100k 0.1F FERRITE BEAD SAME DEVICETYPE AS DUT

47k Vin 15V 100k

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%.

Figure 16. Gate Charge Test Circuit

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615

MMFT2955E INFORMATION FOR USING THE SOT223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT223 POWER DISSIPATION The power dissipation of the SOT223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 800 milliwatts 156C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 800 milliwatts.

The 156C/W for the SOT223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 800 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17.

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616

MMFT2955E
160 R JA , Thermal Resistance, Junction to Ambient (C/W) Board Material = 0.0625 G-10/FR-4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C

140

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.

80 0.0

Figure 17. Thermal Resistance versus Drain Pad Area for the SOT223 Package (Typical)

board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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617

MMFT2955E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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618

MMFT2N02EL
Preferred Device

Power MOSFET 2 Amps, 20 Volts


NChannel SOT223
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This device is also designed with a low threshold voltage so it is fully enhanced with 5 Volts. This new energy efficient device also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, dcdc converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. The device is housed in the SOT223 package which is designed for medium power surface mount applications. Silicon Gate for Fast Switching Speeds Low Drive Requirement to Interface Power Loads to Logic Level ICs, VGS(th) = 2 Volts Max The SOT223 Package can be Soldered Using Wave or Reflow. The Formed Leads Absorb Thermal Stress During Soldering, Eliminating the Possibility of Damage to the Die
MAXIMUM RATINGS (TA = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous Drain Current Pulsed Total Power Dissipation @ TA = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 10 V, VGS = 5 V, Peak IL= 2 A, L = 0.2 mH, RG = 25 ) Symbol VDS VGS ID IDM PD (Note 1.) TJ, Tstg EAS Value 20 15 1.6 6.4 0.8 6.4 65 to 150 66 Vdc
1

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2 AMPERES 20 VOLTS RDS(on) = 150 mW


NChannel D

G S

MARKING DIAGRAM
Unit
4

Adc Watts mW/C C mJ

2 3

TO261AA CASE 318E STYLE 3

2N02L LWW

L WW

= Location Code = Work Week

PIN ASSIGNMENT
4 Drain

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient (surface mounted) Maximum Temperature for Soldering Purposes, Time in Solder Bath RJA 156 260 TL 10 Sec C/W C
1 2 3

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT2N02ELT1 Package SOT223 Shipping 1000 Tape & Reel

1. Power rating when mounted on FR4 glass epoxy printed circuit board using recommended footprint.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

619

November, 2000 Rev. 4

Publication Order Number: MMFT2N02EL/D

MMFT2N02EL
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage, (VGS = 0, ID = 250 A) Zero Gate Voltage Drain Current, (VDS = 20 V, VGS = 0) GateBody Leakage Current, (VGS = 15 V, VDS = 0) ON CHARACTERISTICS Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) Static DraintoSource OnResistance, (VGS = 5 V, ID = 0.8 A) DraintoSource OnVoltage, (VGS = 5 V, ID = 1.6 A) Forward Transconductance, (VDS = 10 V, ID = 0.8 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge (VDS = 16 V, ID = 1.6 A, VGS = 5 Vdc) S Figures See Fi 15 and d 16 (VDD = 15 V, ID = 1.6 A VGS = 5 V V, RG = 50 ohms, ohms RGS = 25 ohms) td(on) tr td(off) tf Qg Qgs Qgd 16 73 77 107 20 1.7 6 nC ns (VDS = 15 V, VGS = 0, f = 1 MH MHz) ) Ciss Coss Crss 580 430 250 pF VGS(th) RDS(on) VDS(on) gFS 1 2.6 2 0.15 0.32 Vdc Ohms Vdc mhos V(BR)DSS IDSS IGSS 20 10 100 Vdc Adc nAdc Symbol Min Typ Max Unit

SOURCE DRAIN DIODE CHARACTERISTICS (Note 2.) Forward OnVoltage Forward TurnOn Time IS = 1.6 A, VGS = 0 VSD ton trr 0.9 Vdc

IS = 1.6 A, VGS = 0, dlS/dt = 400 A/s s, Reverse Recovery Time VR = 16 V 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%

Limited by stray inductance 55 ns

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620

MMFT2N02EL
TYPICAL ELECTRICAL CHARACTERISTICS
10 7 I D, DRAIN CURRENT (AMPS) 8 6 4 2 0 1.2 VGS(TH), GATE THRESHOLD VOLTAGE (NORMALIZED) 4.5 4 3.5 3 1.1 1 0.9 0.8 0.7 -50

10

TJ = 25C

VDS = VGS ID = 1 mA

VGS = 2.5 V 0 2 3 4 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1 5

50 100 TJ, JUNCTION TEMP (C)

150

Figure 1. On Region Characteristics

Figure 2. GateThreshold Voltage Variation With Temperature


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.3 VGS = 5 V

TJ = -55C 25C 100C

VDS = 8 V

I D, DRAIN CURRENT (AMPS)

0.25 0.2 TJ = 100C 25C -55C

0.15 0.1

0.05 0 0 1 2 3 ID, DRAIN CURRENT (AMPS) 4

2 4 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. Transfer Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.5 0.4 0.3 0.2 0.1 0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.5 0.4 0.3 0.2 0.1 0 -50

Figure 4. OnResistance versus Drain Current

TJ = 25C ID = 1.6 A

VGS = 5 V ID = 1.6 A

3 4 5 6 7 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

0 50 100 TJ, JUNCTION TEMPERATURE (C)

150

Figure 5. OnResistance versus GatetoSource Voltage

Figure 6. OnResistance versus Junction Temperature

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621

MMFT2N02EL
FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on an ambient temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal ResistanceGeneral Data and Its Use provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, BVDSS. The switching SOA is applicable for both turnon and turnoff of the devices for switching times less than one microsecond.
r(t), EFFECTIVE THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t1 P(pk) RJA(t) = r(t) RJA RJA = 156C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t)

10

I D, DRAIN CURRENT (AMPS)

VGS = 15 V SINGLE PULSE TA = 25C 100 1s 20ms ms

0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1

DC 500ms

0.01 0.1

10

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased Safe Operating Area

0.01

0.001 1.0E-05

t2 DUTY CYCLE, D = t1/t2 1.0E-01

1.0E+00

1.0E+01

Figure 8. Thermal Response

COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated sourcedrain current versus reapplied drain voltage when the sourcedrain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 9 are present. Full or halfbridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak draintosource voltage that the device must sustain during commutation; IFM is the maximum forward sourcedrain diode current just prior to the onset of commutation. VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in ON Semiconductor s test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dI S /dt of 400 A/ s.

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622

MMFT2N02EL
15 V 0 VGS IFM 90% IS 10% ton IRM tfrr VDS(pk) VR VDS VdsL MAX. CSOA STRESS AREA dlS/dt trr

0.25 IRM

Vf

Figure 9. Commutating Waveforms

10 9 IS , SOURCE CURRENT (AMPS) 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 VGS + dIS/dt 400 A/s VR IFM + 20 V -

RGS

DUT

IS VDS

Li

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VR = 80% OF RATED VDSS VdsL = Vf + Li dlS/dt

Figure 10. Commutating Safe Operating Area (CSOA)

Figure 11. Commutating Safe Operating Area Test Circuit

BVDSS

L VDS IL VDD t RG VDD tP t, (TIME) IL(t)

Figure 12. Unclamped Inductive Switching Test Circuit

Figure 13. Unclamped Inductive Switching Waveforms

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623

MMFT2N02EL
VGS 1800 1600 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 Ciss Coss Crss 15 5 0 5 10 15 20 20 10 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Ciss Crss Coss VDS TJ = 25C f = 1 MHz

Figure 14. Capacitance Variation With Voltage

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10 9 8 7 6 5 4 3 2 1 0 0 10 15 5 Qg, TOTAL GATE CHARGE (nC) 20 TJ = 25C VDS = 16 V ID = 1.6 A

Figure 15. Gate Charge versus GateToSource Voltage

+18V 1mA 2N3904 2N3904 47k 100

VDD 5V SAME DEVICETYPE AS DUT 0.1F FERRITE BEAD

47k Vin 15V 100k

100k

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%.

Figure 16. Gate Charge Test Circuit

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624

MMFT2N02EL INFORMATION FOR USING THE SOT223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.15 3.8 0.079 2.0

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT223 POWER DISSIPATION The power dissipation of the SOT223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 800 milliwatts 156C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 800 milliwatts.

The 156C/W for the SOT223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 800 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17.

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625

MMFT2N02EL
160 R JA , Thermal Resistance, Junction to Ambient (C/W) Board Material = 0.0625 G-10/FR-4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C

140

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.

80 0.0

Figure 17. Thermal Resistance versus Drain Pad Area for the SOT223 Package (Typical)

board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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626

MMFT2N02EL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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627

MMFT3055V Power MOSFET 1 Amp, 60 Volts


NChannel SOT223
These Power MOSFETs are designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total PD @ TA = 25C mounted on 1 sq. Drain pad on FR4 bd material Total PD @ TA = 25C mounted on 0.70 sq. Drain pad on FR4 bd material Total PD @ TA = 25C mounted on min. Drain pad on FR4 bd material Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Ambient on 1 sq. Drain pad on FR4 bd material Junction to Ambient on 0.70 sq. Drain pad on FR4 bd material Junction to Ambient on min. Drain pad on FR4 bd material Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 1.7 1.4 6.0 2.1 1.7 0.94 6.3 TJ, Tstg EAS 58 C/W RJA RJA RJA TL 70 88 159
1 2 3 1

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1 AMPERE 60 VOLTS RDS(on) = 130 mW


NChannel D

Unit Vdc Vdc Vdc Vpk Adc Apk Watts


4

G S

MARKING DIAGRAM

2 3

TO261AA CASE 318E STYLE 3

TBD LWW

mW/C C mJ

55 to 175

L WW

= Location Code = Work Week

PIN ASSIGNMENT
4 Drain

260

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT3055VT1 MMFT3055VT3 Package SOT223 SOT223 Shipping 1000 Tape & Reel 4000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

628

November, 2000 Rev. 2

Publication Order Number: MMFT3055V/D

MMFT3055V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 0.85 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 1.7 Adc) (VGS = 10 Vdc, ID = 0.85 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 1.7 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 1.7 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 1.7 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 1.7 1 7 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 4.5 nH nH ta tb QRR 0.85 0.7 40 34 6.0 0.089 1.6 C ns Vdc 8.0 9.0 32 18 13 2.0 5.0 4.0 20 20 60 40 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 360 110 25 500 150 50 pF (Cpk 2.0) (Note 3.) VGS(th) 2.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 1.0 2.7 0.27 0.25 mhos 0.115 0.13 Vdc 2.8 5.6 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 63 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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629

MMFT3055V
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 8 4V 3.5 V 9 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 4.5 V 4 I D , DRAIN CURRENT (AMPS) 3.5 3 2.5 2 1.5 1 0.5 0 2 2.5 100C 25C TJ = -55C 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5

VGS = 10 V 7V 6V 5.5 V

TJ = 25C 5V

VDS 10 V

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.25 0.2 TJ = 100C 25C -55C 0.15 0.1 0.05 0

0.225

VGS = 10 V

0.170 0.155

TJ = 25C

0.175 0.125 0.075 0.025 0 0.5 1

0.140 0.125 0.110 VGS = 10 V 15 V

0.095 0.080

0.065 0.050 0 0.5 1 1.5 3 2 2.5 ID, DRAIN CURRENT (AMPS) 3.5 4

1.5 3 2 2.5 ID, DRAIN CURRENT (AMPS)

3.5

Figure 3. OnResistance versus Drain Current and Temperature


2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 10 0 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 0.85 A I DSS , LEAKAGE (nA)

VGS = 0 V TJ = 125C

100

100C

10 15 20 25 30 35 40 45 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

55

60

Figure 5. OnResistance Variation with Temperature http://onsemi.com


630

Figure 6. DrainToSource Leakage Current versus Voltage

MMFT3055V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1100 1000 900 C, CAPACITANCE (pF) 800 700 C rss 600 500 400 300 200 100 0 10 5 VGS 0 VDS 5 Crss 10 15 20 25 Coss Ciss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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631

MMFT3055V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 Q3 2 4 6 8 10 VDS 12 QT, TOTAL CHARGE (nC) ID = 1.7 A TJ = 25C Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 14 1000 VDD = 30 V ID = 1.7 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

10

td(off) tf tr td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


2 1.8 I S , SOURCE CURRENT (AMPS) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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632

MMFT3055V
SAFE OPERATING AREA
10 I D , DRAIN CURRENT (AMPS) 60 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 ms 50 40 30 20 10 0 25 50 75 100 125 150 175 ID = 1.7 A

VGS = 20 V SINGLE PULSE TC = 25C

1 100 ms 0.1 500 ms 1s RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 dc 10 100

0.01

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

0.01

0.001 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

0.0001 1.0E-05

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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633

MMFT3055V INFORMATION FOR USING THE SOT223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT223 POWER DISSIPATION The power dissipation of the SOT223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 943 milliwatts 159C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 943 milliwatts.

The 159C/W for the SOT223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 943 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17.

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634

MMFT3055V
160 R JA , Thermal Resistance, Junction to Ambient (C/W) Board Material = 0.0625 G-10/FR-4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C

140

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.

80 0.0

Figure 15. Thermal Resistance versus Drain Pad Area for the SOT223 Package (Typical)

board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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635

MMFT3055V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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636

MMFT3055VL Power MOSFET 1 Amp, 60 Volts


NChannel SOT223
These Power MOSFETs are designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total PD @ TA = 25C mounted on 1 sq. Drain pad on FR4 bd material Total PD @ TA = 25C mounted on 0.70 sq. Drain pad on FR4 bd material Total PD @ TA = 25C mounted on min. Drain pad on FR4 bd material Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Ambient on 1 sq. Drain pad on FR4 bd material Junction to Ambient on 0.70 sq. Drain pad on FR4 bd material Junction to Ambient on min. Drain pad on FR4 bd material Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 20 1.5 1.2 5.0 2.1 1.7 0.94 6.3 TJ, Tstg EAS 58 C/W RJA RJA RJA TL 70 88 159
1 2 3 1

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1 AMPERE 60 VOLTS RDS(on) = 140 mW


NChannel D

Unit Vdc Vdc Vdc Vpk Adc Apk Watts


4

G S

MARKING DIAGRAM

2 3

TO261AA CASE 318E STYLE 3

TBD LWW

mW/C C mJ

55 to 175

L WW

= Location Code = Work Week

PIN ASSIGNMENT
4 Drain

260

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT3055VLT1 MMFT3055VLT3 Package SOT223 SOT223 Shipping 1000 Tape & Reel 4000 Tape & Reel

Semiconductor Components Industries, LLC, 2000

637

November, 2000 Rev. 2

Publication Order Number: MMFT3055VL/D

MMFT3055VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 0.75 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc, ID = 1.5 Adc) (VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 1.5 Adc, VGS = 5.0 Vdc) (VDD = 30 Vdc, ID = 1.5 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 1.5 Adc, VGS = 0 Vdc) (IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 1.5 1 5 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 4.5 nH nH ta tb QRR 0.82 0.68 41 29 12 0.066 1.2 C ns Vdc 9.5 18 35 22 9.0 1.0 4.0 3.5 20 40 70 40 10 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 350 110 29 490 150 60 pF (Cpk 2.0) (Note 3.) VGS(th) 1.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 1.0 3.5 0.25 0.24 mhos 1.5 3.7 0.125 2.0 0.14 Vdc mV/C Ohm Vdc (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 65 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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638

MMFT3055VL
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 8 2.5 V 4 I D , DRAIN CURRENT (AMPS) 3.5 3 2.5 2 1.5 1 0.5 10 0 0 25C TJ = -55C 0.5 1 1.5 2 100C 2.5 3 3.5 4 4.5 5 5.5 6 6.5

6V 4.5 V 3.5 V

TJ = 25C 3V

VDS 10 V

2V 9 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.25 0.2 0.15 0.1 0.05 0 TJ = 100C 25C -55C

0.225 0.175 0.125 0.075 0.025 0 0.5 1 1.5 3 2 2.5 ID, DRAIN CURRENT (AMPS)

VGS = 5 V

0.25 0.225 0.2 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 0

TJ = 25C

VGS = 10 V 15 V

3.5

0.5

1.5 3 2 2.5 ID, DRAIN CURRENT (AMPS)

3.5

Figure 3. OnResistance versus Drain Current and Temperature


2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 1 0 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 0.75 A I DSS , LEAKAGE (nA)

VGS = 0 V TJ = 125C

100

10

100C

10 30 40 20 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature http://onsemi.com


639

Figure 6. DrainToSource Leakage Current versus Voltage

MMFT3055VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1000 900 800 C, CAPACITANCE (pF) 700 500 400 300 200 100 0 10 5 VGS 0 VDS 5 10 15 20 Coss Crss 25 Ciss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

600 Crss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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640

MMFT3055VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 1 Q3 2 3 4 5 6 VDS 7 QT, TOTAL CHARGE (nC) Q1 Q2 VGS QT 30 27 24 21 18 15 12 9 ID = 1.5 A 6 TJ = 25C 3 0 8 9 10 1000 VDD = 30 V ID = 1.5 A VGS = 5 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

10

td(off) tf tr td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


1.6 1.4 I S , SOURCE CURRENT (AMPS) 1.2 1 0.8 0.6 0.4 0.2 0 0.6 0.625 0.65 0.675 0.7 0.725 0.75 0.775 0.8 0.825 0.85 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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641

MMFT3055VL
SAFE OPERATING AREA
10 I D , DRAIN CURRENT (AMPS) 60 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 ms 50 40 30 20 10 0 25 50 75 100 125 150 175 ID = 1.5 A

VGS = 15 V SINGLE PULSE TC = 25C

1 100 ms 0.1 500 ms 1s RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 dc 10 100

0.01

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

0.01

0.001 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

0.0001 1.0E-05

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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642

MMFT3055VL INFORMATION FOR USING THE SOT223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT223 POWER DISSIPATION The power dissipation of the SOT223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 943 milliwatts 159C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 943 milliwatts.

The 159C/W for the SOT223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 943 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17.

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MMFT3055VL
160 R JA , Thermal Resistance, Junction to Ambient (C/W) Board Material = 0.0625 G-10/FR-4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C

140

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.

80 0.0

Figure 15. Thermal Resistance versus Drain Pad Area for the SOT223 Package (Typical)

board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMFT3055VL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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645

MMFT5P03HD
Preferred Device

Power MOSFET 5 Amps, 30 Volts


PChannel SOT223
This miniature surface mount MOSFET features ultra low RDS(on) and true logic level performance. It is capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MMFT5P03HD devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SOT223 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified
1 2 3

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5 AMPERES 30 VOLTS RDS(on) = 100 m


PChannel D

G S

MARKING DIAGRAM

TO261AA CASE 318E STYLE 3

5P03H LWW

L WW

= Location Code = Work Week

PIN ASSIGNMENT
4 Drain

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT5P03HDT3 Package SOT223 Shipping 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

646

November, 2000 Rev. 3

Publication Order Number: MMFT5P03HD/D

MMFT5P03HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Negative sign for PChannel devices omitted for clarity Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous 1 SQ. FR4 or G10 PCB Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Symbol VDSS VDGR VGS RTHJA PD ID ID IDM RTHJA PD ID ID IDM TJ, Tstg EAS 250 Max 30 30 20 40 3.13 25 5.2 4.1 26 80 1.56 12.5 3.7 2.9 19 55 to 150 Unit V V V C/W Watts mW/C A A A C/W Watts mW/C A A A C mJ

10 seconds Minimum FR4 or G10 PCB

10 seconds

Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.5 mH, RG = 25 W) 1. Repetitive rating; pulse width limited by maximum junction temperature.

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MMFT5P03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) (Cpk 2.0) (Notes 2. & 4.) V(BR)DSS 30 IDSS IGSS 1.0 25 100 nAdc 28 Vdc mV/C Adc Symbol Min Typ Max Unit

Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS(1) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 5.2 Adc) (VGS = 4.5 Vdc, ID = 2.6 Adc) (Cpk 2.0) (Notes 2. & 4.)

VGS(th) 1.0 1.75 3.5 79 119 4.0 3.0 100 150

Vdc mV/C m

(Notes 2. & 4.)

RDS(on)

Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge

(Note 2.)

gFS

2.0

Mhos

Ciss (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Coss Crss

475 220 70

950 440 140

pF

td(on) (VDD = 15 Vdc, ID = 4.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 2.) tr td(off) tf td(on) (VDD = 15 Vdc, ID = 2.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) (Note 2.) tr td(off) tf QT (VDS = 24 Vdc, ID = 4.0 Adc, VGS = 10 Vdc) (Note 2.) Q1 Q2 Q3

12 24 47 46 19 55 30 40 17 1.7 6.3 4.6

24 48 94 92 38 110 60 80 24

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc) (Note 2.) (IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 4.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA ta tb QRR 1.1 0.89 39 20 19 0.042 1.5 C ns Vdc

Reverse Recovery Time

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MMFT5P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 8 6 4 2 0 10 I D , DRAIN CURRENT (AMPS) 8 6 4 2 0 TJ = 100C -55C 2 2.5 3 3.5 4 4.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

I D , DRAIN CURRENT (AMPS)

VGS = 10 V 8V 6V TJ = 25C

4.5 V 4.3 V 4.1 V 3.9 V 3.7 V 3.5 V 3.3 V 3.1 V 2.7 V

VDS 10 V

25C

0.4

0.8

1.2

1.6

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.3 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.3

Figure 2. Transfer Characteristics

ID = 4 A TJ = 25C

TJ = 25C

0.2

0.2 VGS = 4.5 V 0.1 10 V

0.1

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


2 VGS = 10 V ID = 2 A 1.5 1000 100 I DSS, LEAKAGE (nA) 10 1 0.1 00.1

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C 100C

25C

0.5

0 -50

-25

25

50

75

100

125

150

12

18

24

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MMFT5P03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1500 1200 C, CAPACITANCE (pF) 900 600 300 0 -10 VGS Ciss Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Ciss Coss Crss 0 VDS 10 20 30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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650

MMFT5P03HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT VDS VGS 24 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 15 V ID = 4 A VGS = 10 V TJ = 25C td(off) tf tr

16

t, TIME (ns)

100

Q1 4

Q2 ID = 4 A TJ = 25C 4 8 12 16

Q3 0 0 QG, TOTAL GATE CHARGE (nC)

0 20

10

td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
4 I S , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C 3

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0 0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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651

MMFT5P03HD
di/dt = 300 A/s Standard Cell Density trr High Cell Density trr tb ta

I S , SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 1 ms 100 s

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

250 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 200 150 100 50 0 25

10

VDD = 30 V VGS = 10 V IL = 12 Apk L = 3.5 mH

dc

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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652

MMFT5P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE ( C/W)

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

0.01

0.001 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

0.0001 1.0E-05

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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653

MMFT5P03HD INFORMATION FOR USING THE SOT223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT223 POWER DISSIPATION The power dissipation of the SOT223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 3.13 watts 40C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 3.13 watts.

The 40C/W for the SOT223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.13 watts. There are other alternatives to achieving higher power dissipation from the SOT223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

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654

MMFT5P03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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655

MMFT960T1
Preferred Device

Power MOSFET 300 mA, 60 Volts


NChannel SOT223
This Power MOSFET is designed for high speed, low loss power switching applications such as switching regulators, dcdc converters, solenoid and relay drivers. The device is housed in the SOT223 package which is designed for medium power surface mount applications. Silicon Gate for Fast Switching Speeds Low Drive Requirement The SOT223 Package can be soldered using wave or reflow. The formed leads absorb thermal stress during soldering eliminating the possibility of damage to the die.
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage GatetoSource Voltage NonRepetitive Drain Current Total Power Dissipation @ TA = 25C (Note 1.) Derate above 25C Operating and Storage Temperature Range Symbol VDS VGS ID PD Value 60 30 300 0.8 6.4 TJ, Tstg 65 to 150 Unit Volts Volts mAdc Watts mW/C C
1 4

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300 mA 60 VOLTS RDS(on) = 1.7 W


NChannel D

G S

MARKING DIAGRAM

THERMAL CHARACTERISTICS
Thermal Resistance JunctiontoAmbient Maximum Temperature for Soldering Purposes Time in Solder Bath RJA TL 156 260 10 C/W C Sec

2 3

TO261AA CASE 318E STYLE 3

FT960 LWW

FT960 L WW

= Device Code = Location Code = Work Week

1. Device mounted on a FR4 glass epoxy printed circuit board using minimum recommended footprint.

PIN ASSIGNMENT
4 Drain

Gate

Drain

Source

ORDERING INFORMATION
Device MMFT960T1 Package SOT223 Shipping 1000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

656

November, 2000 Rev. 4

Publication Order Number: MMFT960T1/D

MMFT960T1
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
DraintoSource Breakdown Voltage (VGS = 0, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 60 V, VGS = 0) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) V(BR)DSS IDSS IGSS 60 10 50 Vdc Adc nAdc

ON CHARACTERISTICS (Note 2.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.0 A) DraintoSource OnVoltage (VGS = 10 V, ID = 0.5 A) (VGS = 10 V, ID = 1.0 A) Forward Transconductance (VDS = 25 V, ID = 0.5 A) VGS(th) RDS(on) VDS(on) gfs 600 0.8 1.7 mmhos 1.0 3.5 1.7 Vdc Ohms Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Transfer Capacitance Total Gate Charge GateSource Charge GateDrain Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. (VGS = 10 V V, ID = 1.0 1 0 A, A VDS = 48 V) (VDS = 25 V V, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss Qg Qgs Qgd 65 33 7.0 3.2 1.2 2.0 nC pF

TYPICAL ELECTRICAL CHARACTERISTICS


5 TJ = 25C I D, DRAIN CURRENT (AMPS) VGS = 10 V 3 2 1 0 8V 7V 6V 5V 4V 0 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 10 0 0 2 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 I D, DRAIN CURRENT (AMPS) 4 0.8 0.6 0.4 VDS = 10 V 0.2 1 TJ = -55C TJ = 25C TJ = 125C

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TYPICAL ELECTRICAL CHARACTERISTICS

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657

MMFT960T1
5 VGS = 10 V 4 3 TJ = 125C 2 1 0 25C -55C 0 0.5 1 1.5 2 ID, DRAIN CURRENT (AMPS) 2.5 RDS(on) , DRAIN-SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN-SOURCE RESISTANCE (OHMS) 10 ID = 1 A VGS = 10 V

0.1 -75

-50

-25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 3. OnResistance versus Drain Current

Figure 4. OnResistance Variation with Temperature

250 225 I D, DRAIN CURRENT (AMPS) 200 1 C, CAPACITANCE (pF) 175 150 125 100 75 50 25 0 0.3 0.6 0.9 1.2 1.5 VSD, SOURCE-DRAIN DIODE FORWARD VOLTAGE (VOLTS) 0 0 5 Crss 10 15 20 25 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 30 Coss Ciss VGS = 0 V f = 1 MHz TJ = 25C

0.1

TJ = 125C

TJ = 25C

Figure 5. SourceDrain Diode Forward Voltage


10 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 Qg, TOTAL GATE CHARGE (nC) 3.5 4 ID = 1 A TJ = 25C gFS , TRANSCONDUCTANCE (mhos) 9

Figure 6. Capacitance Variation

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

2 VDS = 10 V 1.5

VDS = 30 V VDS = 48 V

TJ = -55C 25C

0.5

125C

0.5

1 1.5 ID, DRAIN CURRENT (AMPS)

2.5

Figure 7. Gate Charge versus GatetoSource Voltage

Figure 8. Transconductance

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658

MMFT960T1 INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5

0.091 2.3

0.248 6.3

0.059 1.5

inches mm

SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 0.8 watts 156C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.8 watts.

The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.8 watts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the collector pad. By increasing the area of the collector pad, the power dissipation can be increased. Although the power dissipation can almost be doubled with this method, area is taken up on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus collector pad area is shown in Figure 9.

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659

MMFT960T1
160 R JA , Thermal Resistance, Junction to Ambient (C/W) Board Material = 0.0625 G10/FR4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C

140

Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core

Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C.

80 0.0

Figure 9. Thermal Resistance versus Collector Pad Area for the SOT-223 Package (Typical)

board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.

SOLDERING PRECAUTIONS The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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660

MMFT960T1
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 10 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 10. Typical Solder Heating Profile

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661

MMSF10N02Z
Preferred Device

Power MOSFET 10 Amps, 20 Volts


NChannel SO8
EZFETst are an advanced series of Power MOSFETs which contain monolithic backtoback zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Zener Protected Gates Provide Electrostatic Discharge Protection Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 70C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Thermal Resistance Junction to Ambient Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg RJA Value 20 20 12 10 7.0 80 2.5 55 to 150 50 Unit Vdc Vdc Vdc Adc Apk Watts C C/W 8 1 L Y WW = Location Code = Year = Work Week SO8 CASE 751 STYLE 12 10N02Z LYWW

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10 AMPERES 20 VOLTS RDS(on) = 15 mW


NChannel D

G S

MARKING DIAGRAM

Maximum Temperature for Soldering TL 260 C 1. When mounted on 1 square FR4 or G10 board (VGS = 4.5 V, @ 10 Seconds)

PIN ASSIGNMENT
Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
Device MMSF10N02ZR2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

662

November, 2000 Rev. 3

Publication Order Number: MMSF10N02Z/D

MMSF10N02Z
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 10 Adc) (VGS = 2.7 Vdc, ID = 5.0 Adc) (Cpk 2.0) (Note 4.) VGS(th) 0.5 (Note 4.) RDS(on) gFS 11 13 16 14 15 19 Mhos 0.72 2.86 1.1 Vdc mV/C m (Cpk 2.0) (Note 4.) V(BR)DSS 20 IDSS IGSS 0.6 10 100 1.5 Adc 17 Vdc mV/C Adc Symbol Min Typ Max Unit

Forward Transconductance (VDS = 9.0 Vdc, ID = 5.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 10 Adc, VGS = 4.0 Vdc) (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 4.0 Vdc, RG = 10 ) (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz)

Ciss Coss Crss

1150 775 375

1225 810 480

pF

td(on) tr td(off) tf QT Q1 Q2 Q3

65 360 325 575 26 2.5 13 9.0

75 440 640 860 32

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 10 Ad Adc, VGS = 0 Vd Vdc, dIS/dt = 100 A/s) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA ta tb QRR 0.83 0.68 765 240 530 8.7 1.2 C ns Vdc

Reverse Recovery Time

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663

MMSF10N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
20 18 I D , DRAIN CURRENT (AMPS) 16 14 12 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 14 I D , DRAIN CURRENT (AMPS) 12 10 8 6 4 2 TJ = 25C 1.6 1.8 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 0 0.5 1 1.5 100C 25C TJ = -55C 2 2.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS = 12V 4.5 V

2.7 V 1.9 V 1.8 V 1.7 V 1.6 V 1.5 V

VDS 10 V TJ = 25C

10

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.03 ID = 10 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.03 0.025 0.02

Figure 2. Transfer Characteristics

TJ = 25C

0.025 0.02

VGS = 2.7 V 0.015 0.01 0.005 0 1 4.5 V

0.015 0.01

0.005 0

10

11

12

11

13

15

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 10000 1000 I DSS , LEAKAGE (nA) 100 10 1 0.1 0.01

Figure 4. OnResistance versus Drain Current and Gate Voltage

1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50

VGS =4.5 V ID = 5 A

VGS = 0 V

TJ = 125C 100C

25C

-25

25

50

75

100

125

150

2.5

7.5

10

12.5

15

17.5

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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664

MMSF10N02Z
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2000

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C VGS = 0 V

C, CAPACITANCE (pF)

1500 Ciss 1000 Coss Crss

500

10

12

14

16

18

20

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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665

MMSF10N02Z
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 8 VDS 16 14 12 QT 4 Q1 Q2 VGS 10 8 6 2 Q3 ID = 10 A TJ = 25C 10 15 20 25 4 2 0 1000 VDD = 10 V ID = 5 A VGS = 4 V TJ = 25C

tf tr td(off)

t, TIME (ns)

100 td(on)

10

Qg, TOTAL GATE CHARGE (nC)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
12 I S , SOURCE CURRENT (AMPS) 10 8 6 4 2 0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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666

MMSF10N02Z
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain to source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T C ) of 25 C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the off state and the on state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded, and that the transition time (t r, tf ) does not exceed 10 s. In addition
100 I D , DRAIN CURRENT (AMPS) VGS = 11 V SINGLE PULSE TC = 25C

the total power averaged over a complete switching cycle must not exceed (T J(MAX) T C )/(R JC ). A power MOSFET designated E FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non linearly with an increase of peak current in avalanche and peak junction temperature.

1 ms 10 ms

10 dc

1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.1

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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667

MMSF10N02Z
TYPICAL ELECTRICAL CHARACTERISTICS
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02

0.1

0.01

0.01

SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 1.0E+03

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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668

MMSF10N02Z INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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669

MMSF10N02Z
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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670

MMSF10N03Z
Preferred Device

Advance Information Power MOSFET 10 Amps, 30 Volts


NChannel SO8
EZFETst are an advanced series of Power MOSFETs contain monolithic backtoback zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Zener Protected Gates Provide Electrostatic Discharge Protection Designed to Withstand 200 V Machine Model and 2000 V Human Body Model Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
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10 AMPERES 30 VOLTS RDS(on) = 13 mW


NChannel D

MARKING DIAGRAM

8 1 L Y WW

SO8 CASE 751 STYLE 12

10N03Z LYWW

= Location Code = Year = Work Week

PIN ASSIGNMENT
Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

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ORDERING INFORMATION
Device MMSF10N03ZR2
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Package SO8

Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

671

November, 2000 Rev. 1

Publication Order Number: MMSF10N03Z/D

MMSF10N03Z
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C (Note 1.) Drain Current Continuous @ TA = 70C (Note 1.) Drain Current Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor @ TA = 25C (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, IL = 10 Apk, L = 20 mH, RG = 25 W) Symbol VDSS VDGR VGS ID ID IDM PD PD TJ, Tstg EAS 1000 Max 30 30 20 10 7.7 50 2.5 20 1.6 12 55 to 150 Unit Vdc Vdc Vdc Adc

Watts mW/C Watts mW/C C mJ

THERMAL RESISTANCE
Parameter JunctiontoAmbient (Note 1.) JunctiontoAmbient (Note 2.) Symbol RqJA Typ Max 50 80 Unit C/W

1. When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ 10 seconds). 2. When mounted on minimum recommended FR4 or G10 board (VGS = 10 V, @ Steady State). 3. Repetitive rating; pulse width limited by maximum junction temperature.

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MMSF10N03Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS(1) Gate Threshold Voltage (Cpk 2.0) (Notes 4. & 6.) (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) (Cpk 2.0) (Notes 4. & 6.) VGS(th) 1.0 RDS(on) gFS 7.0 10 13 13 13 18 Mhos 1.2 3.5 1.7 Vdc mV/C m (Cpk 2.0) (Notes 4. & 6.) V(BR)DSS 30 IDSS IGSS 1.0 10 3.0 Adc 65 Vdc mV/C Adc Symbol Min Typ Max Unit

Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) (Note 4.) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (Note 4.) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 4.) (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz)

Ciss Coss Crss

720 570 78

1010 800 110

pF

td(on) tr td(off) tf QT Q1 Q2 Q3

35 105 970 550 46 3.8 11 8.1

70 210 1940 1100 64

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 10 Adc, VGS = 0 Vdc) (Note 4.) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) VSD 0.80 0.70 460 180 280 4.2 1.1 C Vdc

Reverse Recovery Time (IS = 2.3 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA

trr ta tb QRR

ns

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673

MMSF10N03Z
TYPICAL ELECTRICAL CHARACTERISTICS
20 16 12 8.0 2.3 V 4.0 0 2.1 V 1.9 V 0 0.5 1.0 1.5 2.0 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 20 I D , DRAIN CURRENT (AMPS) VGS = 2.7 V TJ = 25C 15 VDS 10 V

10 V 4.5 V

3.1 V

I D , DRAIN CURRENT (AMPS)

2.5 V

10

25C TJ = 100C -55C

5.0

0.5

1.0

1.5

2.0

2.5

3.0

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.06 0.05 0.04 0.03 0.02 0.01 0 0 2.0 4.0 6.0 8.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 ID = 10 A TJ = 25C

0.020 TJ = 25C 0.015 4.5 V VGS = 10 V

0.010

0.005

5.0

10 15 ID, DRAIN CURRENT (AMPS)

20

Figure 3. OnResistance versus Drain Current


2.0 VGS = 10 V ID = 5.0 A I DSS , LEAKAGE (nA) 10,000 1000 100 10 1.0 0.1 0 -50 0.01

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C 100C

1.5

1.0

0.5

25C

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

8.0 4.0 16 12 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

20

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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674

MMSF10N03Z
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
5000 4000 C, CAPACITANCE (pF) 3000 2000 Crss 1000 0 -10 Coss Ciss Crss -5.0 0 5.0 10 15 20 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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675

MMSF10N03Z
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 VDS 8.0 6.0 Q1 4.0 2.0 0 Q3 0 5.0 10 15 20 25 30 35 40 45 50 TJ = 25C ID = 2.0 A Q2 VGS 15 12 18 10,000 V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS = 10 V VDD = 25 V ID = 1.0 A TJ = 25C

1000 t, TIME (ns)

td(off) tf tr td(on)

9.0 6.0 3.0 0

100

10

1.0

10 RG, GATE RESISTANCE (OHMS)

100

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
10 9.0 I S , SOURCE CURRENT (AMPS) 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0.4 0.5 0.6 0.7 0.8 TJ = 25C VGS = 0 V

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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676

MMSF10N03Z
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 ID, DRAIN CURRENT (AMPS) 100 mS 1.0 ms 10 ms 1.0 VGS = 10 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 dc

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.
1000 800 600 400 200 0 VDS = 30 V VGS = 10 V IL = 10 Apk L = 20 mH

10

0.1

0.01

EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

100

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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677

MMSF10N03Z
TYPICAL ELECTRICAL CHARACTERISTICS
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

0.1

0.01

0.01

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s)

t2 DUTY CYCLE, D = t1/t2 1.0E+00

t1

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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678

MMSF10N03Z INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.6 Watts.
PD = 150C 25C = 1.6 Watts 80C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 80C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.6 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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679

MMSF10N03Z
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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680

MMSF1308
Preferred Device

Power MOSFET 7 Amps, 30 Volts


NChannel SO8
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Low RDS(on) Provides Higher Efficiency and Extends Battery Life High Speed Switching Provides High Efficiency for DC/DC Converter Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed, With Soft Recovery
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Continuous Drain Current @ TA = 25C (Note 1.) Pulsed Drain Current (Note 2.) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Symbol VDSS VDGR VGS ID IDM PD TJ, Tstg Max 30 30 20 7.0 50 2.5 55 to 150 W C L Y WW = Location Code = Year = Work Week Unit Vdc Vdc Vdc Adc 1 8 SO8 CASE 751 STYLE 12 S1308 LYWW

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7 AMPERES 30 VOLTS RDS(on) = 30 mW


NChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT THERMAL RESISTANCE


JunctiontoAmbient (Note 1.) RJA 50 C/W 1. When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ 10 Seconds) 2. Repetitive rating; pulse width limited by maximum junction temperature. Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

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ORDERING INFORMATION
Device MMSF1308R2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

681

November, 2000 Rev. 1

Publication Order Number: MMSF1308/D

MMSF1308
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 4.5 Vdc, ID = 3.5 Adc) Forward Transconductance (VDS = 5.0 Vdc, ID = 1.0 Adc) (Note 3.) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 15 Vdc, ID = 7.0 Adc, VGS = 10 Vdc) (Note 3.) (VDD = 21 Vdc, ID = 7.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 3.) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 7.0 Adc, VGS = 0 Vdc) (Note 3.) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. 5. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA 6. Repetitive rating; pulse width limited by maximum junction temperature. ta tb QRR 0.85 0.71 35 20 15 0.03 1.0 C ns Vdc 7.5 24 30 46 20 2.5 6.0 8.0 15 48 60 92 30 nC ns (VDS = 24 Vd Vdc, VGS = 0 V V, f = 1.0 MHz) Ciss Coss Crss 690 290 90 970 410 130 pF VGS(th) 1.0 RDS(on) gFS 22 30 4.5 30 39 Mhos 1.6 4.3 2.5 Vdc mV/C m V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 30 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MMSF1308
TYPICAL ELECTRICAL CHARACTERISTICS
10 8 6 2.9 V 4 2.7 V 2 0 VGS = 2.3 V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 15 ID, DRAIN CURRENT (AMPS) 3.1 V TJ = 25C 12 9 6 3 0 VDS 10 V

10 V

3.5 V 4.5 V

ID , DRAIN CURRENT (AMPS)

TJ = 125C 25C -55C 0 1 2 3 4 5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DSon( W ) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.5 0.4 0.3 0.2 0.1 0 ID = 7.0 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.05 TJ = 25C 0.04 VGS = 4.5 V 0.03 0.02 0.01 0 10 V

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

2 3 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


2.0 VGS = 10 V ID = 7.0 A 1.5 IDSS , LEAKAGE (A) 1E-08 1E-07

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

TJ = 125C 100C

1.0

1E-09

25C

0.5

1E-10 VGS = 0 V 0 10 20 25 5 15 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30

0 -50

-25

25

50

75

100

125

150

1E-11

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MMSF1308
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2000 1800 1600 C, CAPACITANCE (pF) 1400 1200 Crss 1000 800 600 400 200 0 -10 Crss -5 0 5 VGS VDS 10 15 20 25 30 Coss Ciss VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MMSF1308
1000 TJ = 25C ID = 7.0 A VDD = 24 V VGS = 10 V tf td(off) tr 10 td(on)

100 t, TIME (ns) 1 1

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
10 IS , SOURCE CURRENT (AMPS) 8 6 4 2 0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.2

0.4

0.6

0.8

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 9. Diode Forward Voltage versus Current

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MMSF1308
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 10. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 ID , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

100 ms 1 ms 10 ms

10

0.1

0.01

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10

dc

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

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686

MMSF1308 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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MMSF1308
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 12. Typical Solder Heating Profile

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688

MMSF1310
Preferred Device

Power MOSFET 10 Amps, 30 Volts


NChannel SO8
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Low RDS(on) Provides Higher Efficiency and Extends Battery Life High Speed Switching Provides High Efficiency for DC/DC Converter Miniature SO8 Surface Mount Package Saves Board Space Diode Exhibits High Speed, With Soft Recovery
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Continuous Drain Current @ TA = 25C (Note 1.) Pulsed Drain Current (Note 2.) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Symbol VDSS VDGR VGS ID IDM PD TJ, Tstg Max 30 30 20 10 50 2.5 55 to 150 W C L Y WW = Location Code = Year = Work Week Unit Vdc Vdc Vdc Adc 1 8 SO8 CASE 751 STYLE 12 S1310 LYWW

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10 AMPERES 30 VOLTS RDS(on) = 15 mW


NChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT THERMAL RESISTANCE


JunctiontoAmbient (Note 1.) RJA 50 C/W 1. When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ 10 Seconds) 2. Repetitive rating; pulse width limited by maximum junction temperature. Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
Device MMSF1310R2 Package SO8 Shipping 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

689

November, 2000 Rev. 1

Publication Order Number: MMSF1310/D

MMSF1310
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) Forward Transconductance (VDS = 5.0 Vdc, ID = 1.0 Adc) (Note 3.) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 15 Vdc, ID = 10 Adc, VGS = 10 Vdc) (Note 3.) (VDD = 24 Vdc, ID = 10 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 3.) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 10 Adc, VGS = 0 Vdc) (Note 3.) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 10 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3.) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. 5. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA 6. Repetitive rating; pulse width limited by maximum junction temperature. ta tb QRR 0.82 0.67 52 23 30 0.05 1.0 C ns Vdc 10 36 82 95 48 3.0 4.0 7.0 20 72 164 190 68 nC ns (VDS = 24 Vd Vdc, VGS = 0 V V, f = 1.0 MHz) Ciss Coss Crss 1440 680 195 2020 960 280 pF VGS(th) 1.0 RDS(on) gFS 9.5 12.5 5.0 15 19 Mhos 1.3 4.4 2.5 Vdc mV/C m V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 27 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MMSF1310
TYPICAL ELECTRICAL CHARACTERISTICS
20 16 12 8 4 0 VGS = 2.3 V 20 TJ = 25C ID, DRAIN CURRENT (AMPS) 16 12 8 4 0 TJ = 125C 25C -55C VDS 10 V

10 V

3.1 V 3.5 V 4.5 V

2.9 V

ID , DRAIN CURRENT (AMPS)

2.7 V

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DSon( W ) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.05 0.04 0.03 0.02 0.01 0 ID = 10 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.02 TJ = 25C 0.015 VGS = 4.5 V 10 V

0.01

0.005

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

2 3 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


2.0 VGS = 10 V ID = 10 A 1.5 IDSS , LEAKAGE (A) 1E-06 1E-07 1E-08 1E-09 1E-10

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

TJ = 125C 100C

1.0

25C

0.5

0 -50

VGS = 0 V -25 0 25 50 75 100 125 150 1E-11 0 10 20 25 5 15 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MMSF1310
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4000 VDS = 0 V Ciss VGS = 0 V Coss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

C, CAPACITANCE (pF)

3000

2000

Crss

1000 Crss 0 -10 -5 0 5 VGS VDS 10 15 20 25 30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MMSF1310
1000 TJ = 25C ID = 10 A VDD = 24 V VGS = 10 V

100 t, TIME (ns)

tf td(off) tr td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
10 IS , SOURCE CURRENT (AMPS) 8 6 4 2 0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.2

0.4

0.6

0.8

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 9. Diode Forward Voltage versus Current

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MMSF1310
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 10. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 ID , DRAIN CURRENT (AMPS) 100 ms 10 1 ms VGS = 10 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 10 ms

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

0.1

dc

0.01

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

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694

MMSF1310 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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695

MMSF1310
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 12. Typical Solder Heating Profile

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696

MMSF2P02E
Preferred Device

Power MOSFET 2 Amps, 20 Volts


PChannel SO8
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed Avalanche Energy Specified Mounting Information for SO8 Package Provided IDSS Specified at Elevated Temperature
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)
Rating DraintoSource Voltage GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C (Note 2.) Continuous @ TA = 100C Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 12 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID ID IDM PD TJ, Tstg EAS Value 20 20 2.5 1.7 13 2.5 55 to 150 216 Unit Vdc Vdc Adc Apk Watts N C C mJ Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain 8 1 L Y WW = Location Code = Year = Work Week

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2 AMPERES 20 VOLTS RDS(on) = 250 mW


PChannel D

G S

MARKING DIAGRAM

SO8 CASE 751 STYLE 13

S4P01 LYWW

PIN ASSIGNMENT

Top View RJA TL 50 260 C/W C

ORDERING INFORMATION
Device MMSF2P02ER2 Package SO8 Shipping 2500 Tape & Reel

1. Negative sign for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

697

November, 2000 Rev. 5

Publication Order Number: MMSF2P02E/D

MMSF2P02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 4.) Reverse Recovery Time (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Negative sign for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta tb QRR 1.5 34 18 16 0.035 2.0 64 C Vdc ns 20 40 53 41 13 29 30 28 10 1.1 3.3 2.5 40 80 106 82 26 58 60 56 15 nC ns ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 340 220 75 475 300 150 pF VGS(th) 1.0 RDS(on) gFS 1.0 0.19 0.3 2.8 0.25 0.4 Mhos 2.0 4.7 3.0 Vdc mV/C Ohm V(BR)DSS 20 IDSS IGSS 1.0 10 100 nAdc 24.7 Vdc mV/C Adc Symbol Min Typ Max Unit

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698

MMSF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 4 I D , DRAIN CURRENT (AMPS)

VGS = 10 7 V

5V

4.7 V

4.5 V 4.3 V

TJ = 25C

VDS 10 V

3 100C 25C TJ = -55C

4.1 V 3.9 V

3.7 V 3.5 V 3.3 V 0 0.4 0.8 1.2 1.6 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0 2.5

3.5

4.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 1 A TJ = 25C 0.6 0.5 0.4 0.3 0.2 0.1

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 4.5

10 V 0 0.5 1 ID, DRAIN CURRENT (AMPS) 1.5 2

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus GatetoSource Voltage


2.0 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 10 V ID = 2 A I DSS , LEAKAGE (nA)

VGS = 0 V

1.5 TJ = 125C 10

1.0

0.5

100C

0 -50

-25

25

50

75

100

125

150

12

16

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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699

MMSF2P02E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve.
1000 800 C, CAPACITANCE (pF) 600 400 200 0 10 Crss VDS = 0 V Ciss VGS = 0 V TJ = 25C

During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
12 QT VDS VGS 16

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

12

Ciss Coss Crss

Q1

Q2

Q3

4 ID = 2 A TJ = 25C 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) 10

5 5 30 0 10 15 20 25 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0 12

Figure 7. Capacitance Variation

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge

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700

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

MMSF2P02E
100 VDD = 10 V ID = 2 A VGS = 10 V TJ = 25C 2 1.6 1.2 0.8 0.4 0 0.6 TJ = 25C VGS = 0 V

td(off) tr tf td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100

IS, SOURCE CURRENT (AMPS)

t, TIME (ns)

0.8 1 1.2 1.4 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

1.6

Figure 9. Resistive Switching Time Variation versus Gate Resistance

Figure 10. Diode Forward Voltage versus Current

di/dt = 300 A/s I S , SOURCE CURRENT

High Cell Density trr tb ta

I D , DRAIN CURRENT (AMPS)

Standard Cell Density trr

100

10

VGS = 20 V SINGLE PULSE TC = 25C

Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max.

10 ms 1 dc

1 ms

0.1

t, TIME

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Reverse Recovery Time (trr)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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701

MMSF2P02E
250 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 200 150 100 50 0 ID = 6 A

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry

custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

Normalized to ja at 10s.
Chip
0.0022 0.0210 0.2587 0.7023 0.6863

0.01

SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02

0.0020 F

0.0207 F

0.3517 F

3.1413 F

108.44 F

Ambient 1.0E+03

1.0E-01 t, TIME (s)

1.0E+00

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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702

MMSF2P02E INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C 50C/W = 2.5 Watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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703

MMSF2P02E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 13 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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704

MMSF3300 Advance Information Power MOSFET 11.5 Amps, 30 Volts


NChannel SO8
These Power MOSFETs are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. WaveFETt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.
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11.5 AMPERES 30 VOLTS RDS(on) = 12.5 mW


NChannel D

Characterized Over a Wide Range of Power Ratings Ultralow RDS(on) Provides Higher Efficiency and Extends Battery
Life in Portable Applications Logic Level Gate Drive Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Miniature SO8 Surface Mount Package Saves Board Space
8

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise specified)


Parameter DraintoSource Voltage DraintoGate Voltage GatetoSource Voltage GatetoSource Operating Voltage Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 18.8 mH, IL(pk) = 7.3 A, VDS = 30 Vdc) Symbol VDSS VDGR VGS VGS TJ, Tstg EAS Value 30 30 20 16 55 to 150 500 Unit Vdc Vdc Vdc Vdc C mJ 1 L Y WW

SO8 CASE 751 STYLE 12

S3300 LYWW

= Location Code = Year = Work Week

PIN ASSIGNMENT
Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
Device MMSF3300R2 Package SO8 Shipping 2500 Tape & Reel

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Semiconductor Components Industries, LLC, 2000

705

November, 2000 Rev. 5

Publication Order Number: MMSF3300/D

MMSF3300
POWER RATINGS (TJ = 25C unless otherwise specified)
Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoAmbient Continuous Source Current (Diode Conduction) Mounted on 1 inch square FR4 or G10 board VGS = 10 Vdc t 10 seconds Symbol ID ID IDM PD RJA IS Value 11.5 8.2 50 2.5 20 50 3.0 Unit Adc Adc Adc Watts mW/C C/W Adc

Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoAmbient Continuous Source Current (Diode Conduction) Mounted on 1 inch square FR4 or G10 board VGS = 10 Vdc Steady State

Symbol ID ID IDM PD RJA IS

Value 9.1 6.5 50 1.6 12.5 80 2.0

Unit Adc Adc Adc Watts mW/C C/W Adc

Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoAmbient Continuous Source Current (Diode Conduction) Mounted on minimum recommended FR4 or G10 board VGS = 10 Vdc t 10 seconds

Symbol ID ID IDM PD RJA IS

Value 9.1 6.5 50 1.6 12.5 80 2.0

Unit Adc Adc Adc Watts mW/C C/W Adc

Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoAmbient Continuous Source Current (Diode Conduction) Mounted on minimum recommended FR4 or G10 board VGS = 10 Vdc Steady State

Symbol ID ID IDM PD RJA IS

Value 6.7 4.7 50 0.8 6.7 150 1.0

Unit Adc Adc Adc Watts mW/C C/W Adc

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706

MMSF3300
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 3.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperatures. trr ta tb QRR VSD 0.78 0.60 40 21 19 0.043 1.1 C ns Vdc 21 45 40 40 12 12 55 39 45 5.1 14 13 40 90 80 80 25 25 110 80 60 nC ns ns (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1700 600 200 pF VGS(th) 1.0 RDS(on) gFS 3.0 10 16 18 12.5 20 Mhos 1.9 4.4 Vdc mV/C m V(BR)DSS 30 IDSS IGSS 0.004 0.5 1.0 10 100 nAdc 24 Vdc mV/C Adc Symbol Min Typ Max Unit

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707

MMSF3300
TYPICAL ELECTRICAL CHARACTERISTICS
10 9 ID , DRAIN CURRENT (AMPS) 8 7 6 5 4 3 2 1 0 0 0.25 0.50 0.75 1.00 1.25 1.50 3.5 V 10 ID, DRAIN CURRENT (AMPS) TJ = 25C 9 8 7 6 5 4 3 2 1 0 VDS 10 V 25C TJ = 125C -55C

10 V 6.0 V 4.5 V 4.1 V 3.7 V

3.3 V

3.1 V

2.9 V VGS = 2.7 V 1.75 2.00

2.0

2.5

3.0

3.5

4.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.30 0.25 0.20 0.15 0.10 0.05 0 2 3 4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 ID = 5.0 A TJ = 25C

0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0 10 V TJ = 25C VGS = 4.5 V

12 6 8 10 ID, DRAIN CURRENT (AMPS)

14

16

Figure 3. OnResistance versus GateToSource Voltage


2.0 VGS = 10 V ID = 10 A IDSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

TJ = 125C 100C

1.5

1.0

10 25C 1

0.5

0 -50

-25

25

50

75

100

125

150

0.1

TJ, JUNCTION TEMPERATURE (C)

20 25 10 15 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

30

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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708

MMSF3300
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4000 3500 C, CAPACITANCE (pF) 3000 2500 2000 1500 1000 500 0 10 5 0 5 VGS VDS 10 15 20 25 Coss Crss 30 Crss Ciss Ciss VDS = 0 VGS = 0 TJ = 25C

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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709

MMSF3300
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT VGS 10 8 6 4 2 0 0 Q1 Q3 VDS 10 30 20 QG, TOTAL GATE CHARGE (nC) 40 50 Q2 ID = 2.0 A TJ = 25C 18 1000 VDD = 25 V ID = 1.0 A VGS = 10 V TJ = 25C t, TIME (ns) 100 tr td(on) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

15 12 9 6 3 0

td(off) tf

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 16. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high
8 7 I S , SOURCE CURRENT (AMPS) 6 5 4 3 2 1 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 VGS = 0 V TJ = 25C

di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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710

MMSF3300
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 ID , DRAIN CURRENT (AMPS) 10 ms 1 ms 100 ms

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

500 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 300 200 100 0 ID = 7.3 A

10

dc 1 VGS = 10 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.1

0.01

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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711

MMSF3300
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE DUTY CYCLE MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT

100

D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE P(pk) t2 DUTY CYCLE, D = t1/t2 1E-03 1E-02 1E-01 t, TIME (seconds) 1E+00 t1

10

RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+02 1E+03

0.1

1E-05

1E-04

1E+01

Figure 14. Thermal Response Various Duty Cycles

10,000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE MIN PAD, ja 1 INCH, ja R C R C 1.242 0.073 0.075 0.412 19.55 0.84 1.11 5.16 242 6.2 123 14.6 982 74 706 28 18,050 39.8 65.3 14,646 MIN PAD, jl R C 0.016 0.060 0.17 0.57 2.1 6.4 158 5.3 6,256 2.7 CHIP JUNCTION R1 C1 R2 C2 R3 C3 R4 C4 R5 C5 AMBIENT Rthja, MIN PAD Rthja, 1 INCH PAD Rthjl, MIN PAD

1000

100

1 2 3 4 5

10

1E-03

1E-02

1E-01

1E+00 t, TIME (seconds)

1E+01

1E+02

1E+0

Figure 15. Thermal Response Various Mounting/Measurement Conditions


80

di/dt trr ta tp IS tb TIME 0.25 IS POWER (W) IS

60

40

20

0.01

0.1 t, TIME (seconds)

10

Figure 16. Diode Reverse Recovery Waveform

Figure 17. Single Pulse Power

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712

MMSF3300 INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. *Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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713

MMSF3300
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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714

MMSF3P02HD
Preferred Device

Power MOSFET 3 Amps, 20 Volts


PChannel SO8
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1.)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 14 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 20 20 20 5.6 3.6 30 2.5 55 to 150 567 Unit Vdc Vdc Vdc Adc Apk Watts N C C mJ Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain L Y WW = Location Code = Year = Work Week 8 1

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3 AMPERES 20 VOLTS RDS(on) = 75 mW


PChannel D

G S

MARKING DIAGRAM

SO8 CASE 751 STYLE 13

S3P02 LYWW

PIN ASSIGNMENT

Top View RJA TL 50 260 C/W C

ORDERING INFORMATION
Device MMSF3P02HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Negative sign for PChannel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

715

November, 2000 Rev. 6

Publication Order Number: MMSF3P02HD/D

MMSF3P02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3.)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 3.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 4.) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 3. Negative sign for PChannel device omitted for clarity. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. ta tb QRR 1.35 0.96 76 32 44 0.133 1.75 C ns Vdc 25 135 54 84 16 40 110 97 33 3.0 11 10 50 270 108 168 32 80 220 194 46 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1010 740 260 1400 920 490 pF VGS(th) 1.0 RDS(on) gFS 3.0 0.06 0.08 7.2 0.075 0.095 mhos 1.5 4.0 2.0 Vdc mV/C Ohm V(BR)DSS 20 IDSS IGSS 1.0 10 100 nAdc 24 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time S Fi See Figure 15

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716

MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
6 I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 6 TJ = 25C 3.1 V I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 -55C 1.6 1.8 2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 TJ = 100C 25C VDS 10 V

VGS = 10 V 4.5 V

3.5 V 3.7 V 3.9 V

3.3 V

2.9 V 2.7 V 2.5 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS) 0.6 ID = 1.5 A TJ = 25C 0.4 R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.09

TJ = 25C

0.08

VGS = 4.5 V

0.07

0.2

0.06

10 V

10

0.05

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


1.20 1000 VGS = 10 V ID = 3.0 A I DSS , LEAKAGE (nA)

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

1.10

TJ = 125C 100

1.00

0.90

0.80 -50

25

50

75

100

125

150

10

12

16

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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717

MMSF3P02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
3500 3000 C, CAPACITANCE (pF) 2500 2000 1500 1000 500 0 10 5 VGS 0 VDS Crss Coss Crss 5 10 15 20 Ciss VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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718

MMSF3P02HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 Q1 4 2 0 Q3 0 4 8 12 16 20 24 QT, TOTAL CHARGE (nC) VDS 28 32 36 Q2 ID = 3 A TJ = 25C QT VGS 24 20 16 12 8 4 0 1000 VDD = 10 V ID = 3 A VGS = 10 V TJ = 25C td(off) 100 tf tr VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
3 2.5 I S , SOURCE CURRENT (AMPS) 2 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

1.5 1

0.5 0 0.3 0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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719

MMSF3P02HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
600

10

1 ms

100 s

E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

ID = 9 A

450

300

0.1

150

0.01 0.1

10

100

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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720

MMSF3P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

Normalized to ja at 10s.
Chip
0.0163 0.0652 0.1988 0.6411 0.9502

0.01

0.0307 F

0.1668 F

0.5541 F

1.9437 F

72.416 F

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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721

MMSF3P02HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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722

MMSF3P02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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723

MMSF5N02HD
Preferred Device

Power MOSFET 5 Amps, 20 Volts


NChannel SO8
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
8

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5 AMPERES 20 VOLTS RDS(on) = 25 mW


NChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 6.0 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 20 20 20 8.2 5.6 41 2.5 55 to 150 675 Unit Vdc Vdc Vdc Adc Apk Watts C mJ

SO8 CASE 751 STYLE 13 1 L Y WW = Location Code = Year = Work Week

S5N02 LYWW

PIN ASSIGNMENT
N C Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

RJA TL

50 260

C/W C

ORDERING INFORMATION
Device MMSF5N02HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

724

November, 2000 Rev. 6

Publication Order Number: MMSF5N02HD/D

MMSF5N02HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 5.0 Adc, VGS = 0 Vdc) (IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 5.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.82 0.69 32 24 8.0 0.045 1.0 C ns Vdc 15 93 35 40 9.0 53 56 39 30.3 3.0 7.5 6.0 30 185 70 80 43 nC ns (VDS = 16 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1130 464 117 1582 650 235 pF VGS(th) 1.0 RDS(on) gFS 3.0 0.0185 0.0219 12 0.025 0.040 Mhos 1.5 4.0 2.0 Vdc mV/C Ohm V(BR)DSS 20 IDSS IGSS 0.02 1.0 10 100 nAdc 41 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time S Fi See Figure 15

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725

MMSF5N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 I D , DRAIN CURRENT (AMPS) 8 3.8 V 6 4 2 2.4 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1.5 1.7 1.9 2.1 2.3 2.5 2.7 10 I D , DRAIN CURRENT (AMPS) 8 6 4 TJ = 100C 2 -55C 2.9 3.1 3.3 25C

VGS = 10 V 4.5 V 3.1 V

TJ = 25C

VDS 10 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.2 0.16 0.12 0.08 0.04 0

ID = 2.5 A

0.023

TJ = 25C

VGS = 4.5 V

0.021

0.019 10 V

10

0.017

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


1.6 1.4 1.2 1 0.8 0.6 -50 1 VGS = 10 V ID = 2.5 A I DSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C

100C 25C

10

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

8 12 4 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

20

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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726

MMSF5N02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
3500 3000 C, CAPACITANCE (pF) 2500 2000 1500 1000 500 0 10 5 VGS 0 VDS Crss 5 10 15 20 Crss Coss Ciss VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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727

MMSF5N02HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 Q1 4 2 Q3 0 0 4 8 12 16 20 24 QT, TOTAL CHARGE (nC) VDS 28 32 Q2 VGS QT 24 20 16 12 8 4 0 1000 VDD = 10 V ID = 5 A VGS = 10 V TJ = 25C td(off) tf tr td(on) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

ID = 5 A TJ = 25C

t, TIME (ns)

100

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
5 4 3 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

2 1 0 0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


728

MMSF5N02HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
675 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

10

100 s 1 ms

575 475 375 275 175 75 -25 25 50 75 100

ID = 15 A

0.1

0.01 0.1

10

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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729

MMSF5N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

Normalized to ja at 10s.
Chip
0.0163 0.0652 0.1988 0.6411 0.9502

0.01

0.0307 F

0.1668 F

0.5541 F

1.9437 F

72.416 F

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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730

MMSF5N02HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C 50C/W = 2.5 Watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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731

MMSF5N02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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732

MMSF5N03HD
Preferred Device

Power MOSFET 5 Amps, 30 Volts


NChannel SO8
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
8

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5 AMPERES 30 VOLTS RDS(on) = 40 mW


NChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 30 30 20 6.5 4.4 33 2.5 55 to 150 450 Unit Vdc Vdc Vdc Adc Apk Watts C mJ

SO8 CASE 751 STYLE 13 1 L Y WW = Location Code = Year = Work Week

S5N03 LYWW

PIN ASSIGNMENT
N C Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

RJA TL

50 260

C/W C

ORDERING INFORMATION
Device MMSF5N03HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.
Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

733

November, 2000 Rev. 6

Publication Order Number: MMSF5N03HD/D

MMSF5N03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc) (VGS = 4.5 Vdc, ID = 2.5 Adc) Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 24 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 5.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.88 0.77 33 21 12 0.037 1.3 C ns Vdc 20 108 36 37 11 36 68 38 15.2 3.4 6.6 5.6 40 216 72 74 22 72 136 76 21 nC ns (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1207 354 62 1680 490 120 pF VGS(th) 1.0 RDS(on) gFS 3.0 0.033 0.04 8.0 0.040 0.050 Mhos 2.0 5.0 3.0 Vdc mV/C Ohms V(BR)DSS 30 IDSS IGSS 1.0 10 100 nAdc 34 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time S Fi See Figure 15

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734

MMSF5N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 I D , DRAIN CURRENT (AMPS) 8 6 4 2 2.4 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 2 2.2 2.4 2.6 2.8 3 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 TJ = 25C I D , DRAIN CURRENT (AMPS) 8 6 4 TJ = 100C 2 -55C 3.2 3.4 3.6 3.8 25C VDS 10 V

VGS = 10 V 4.5 V 3.8 V 3.1 V

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.2 ID = 2.5 A 0.16 0.12 0.08 0.04 0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.0425

Figure 2. Transfer Characteristics

TJ = 25C 0.04 VGS = 4.5 V 0.0375 0.035 10 V 0.0325 0.03

10

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


1.6 1.4 1.2 1 0.8 0.6 -50 1 VGS = 10 V ID = 5 A I DSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C

10

100C 25C

-25

25

50

75

100

125

150

10

20

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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735

MMSF5N03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
3500 3000 C, CAPACITANCE (pF) 2500 2000 1500 1000 500 0 10 5 0 VGS Coss Crss 5 10 VDS 15 20 25 30 Crss Ciss VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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736

MMSF5N03HD
VGS, GATETOSOURCE VOLTAGE (VOLTS) 12 10 VGS 8 6 4 2 0 Q3 0 2 4 6 8 10 QT, TOTAL CHARGE (nC) VDS 12 14 16 Q1 Q2 ID = 5 A TJ = 25C QT 25 20 1000 VDD = 15 V ID = 5 A VGS = 4.5 V TJ = 25C 100 tr td(off) tf td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100 VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

15 10

5 0

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

t, TIME (ns)

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
5 4 3 2 1 0 0.5 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


737

MMSF5N03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
450

10

100 s 1 ms

E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

ID = 15 A

300

150

0.1

0.01 0.1

10

100

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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738

MMSF5N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

Normalized to ja at 10s.
Chip
0.0163 0.0652 0.1988 0.6411 0.9502

0.01

0.0307 F

0.1668 F

0.5541 F

1.9437 F

72.416 F

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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739

MMSF5N03HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C 50C/W = 2.5 Watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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740

MMSF5N03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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741

MMSF7N03HD
Preferred Device

Power MOSFET 7 Amps, 30 Volts


NChannel SO8
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
8

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7 AMPERES 30 VOLTS RDS(on) = 28 mW


NChannel D

G S

MARKING DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 30 30 20 8.2 5.6 50 2.5 55 to 150 450 Unit Vdc Vdc Vdc Adc Apk Watts C mJ

SO8 CASE 751 STYLE 13 1 L Y WW = Location Code = Year = Work Week

S7N03 LYWW

PIN ASSIGNMENT
N C Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

RJA TL

50 260

C/W C

ORDERING INFORMATION
Device MMSF7N03HDR2 Package SO8 Shipping 2500 Tape & Reel

1. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10 sec. max.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

742

November, 2000 Rev. 4

Publication Order Number: MMSF7N03HD/D

MMSF7N03HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 4.5 Vdc, ID = 3.5 Adc) Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge S Fi See Figure 8 (VDS = 16 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) (VDD = 10 Vdc, ID = 5.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 7.0 Adc, VGS = 0 Vdc) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 7.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.82 0.69 32 24 8.0 0.045 1.0 C ns Vdc 15 93 35 40 9.0 53 56 39 30 3.0 7.5 6.0 43 nC 30 185 70 80 ns (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 931 371 89 1190 490 120 pF VGS(th) 1.0 RDS(on) gFS 3.0 0.023 0.029 12 0.028 0.040 Mhos 1.5 4.0 2.0 Vdc mV/C Ohms V(BR)DSS 30 IDSS IGSS 0.02 1.0 10 100 nAdc 41 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time S Fi See Figure 15

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743

MMSF7N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
7 I D , DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 0 0.25 0.5 0.75 1 2.5 V 7 I D , DRAIN CURRENT (AMPS) 6 5 4 3 2 1 1.5 1.75 2 0 1.5 2 2.5 TJ = 100C 25C -55C 3 3.5 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V 4.5 V 3.9 V 3.7 V 3.5 V 3.3 V 3.1 V

TJ = 25C 2.9 V

VDS 10 V TJ = 25C

2.7 V

1.25

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 3.5 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.05

Figure 2. Transfer Characteristics

TJ = 25C

0.04 VGS = 4.5 V 10 V 0.02

0.03

10

0.01

10

15

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GateToSource Voltage


2 VGS = 10 V ID = 3.5 A 10000 1000 I DSS , LEAKAGE (nA) 100 10 1 0.1

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

TJ = 125C

1.5

100C 25C

0.5

0 -50

-25

25

50

75

100

125

150

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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744

MMSF7N03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4000 3500 C, CAPACITANCE (pF) 3000 2500 2000 Crss 1500 1000 500 0 10 5 0 VGS Crss 5 10 VDS Ciss Coss VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

15

20

25

30

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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745

MMSF7N03HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 Q1 4 2 Q3 0 0 4 8 12 16 20 24 QT, TOTAL CHARGE (nC) VDS 28 32 Q2 VGS QT 24 20 16 12 8 4 0 1000 VDD = 10 V ID = 5 A VGS = 10 V TJ = 25C td(off) tf tr td(on) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

ID = 5 A TJ = 25C

t, TIME (ns)

100

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
8 7 I S , SOURCE CURRENT (AMPS) 6 5 4 3 2 1 0 0.5 0.6 0.7 0.8 0.9 1 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


746

MMSF7N03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided), 10s max.

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

480 10s 100 s 1 ms E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 440 400 360 320 280 240 200 160 120 80 40 0 25 50 75 100

10

ID = 9 A I pk = 9 A L = 4 mH

0.1

0.01 0.1

10

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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747

MMSF7N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

Normalized to ja at 10s.
Chip
0.0163 0.0652 0.1988 0.6411 0.9502

0.01

0.0307 F

0.1668 F

0.5541 F

1.9437 F

72.416 F

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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748

MMSF7N03HD INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C 50C/W = 2.5 Watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.

The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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749

MMSF7N03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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750

MMSF7N03Z Power MOSFET 7 Amps, 30 Volts


NChannel SO8
EZFETst are an advanced series of Power MOSFETs which contain monolithic backtoback zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Zener Protected Gates Provide Electrostatic Discharge Protection Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Designed to withstand 200V Machine Model and 2000V Human Body Model Logic Level Gate Drive Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO8 Package Provided
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7 AMPERES 30 VOLTS RDS(on) = 30 mW


NChannel D

G S

MARKING DIAGRAM

8 1 7N03Z L Y WW

SO8 CASE 751 STYLE 12

7N03Z LYWW

= Device Code = Location Code = Year = Work Week

PIN ASSIGNMENT
Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
Device MMSF7N03ZR2 Package SO8 Shipping 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2001

751

January, 2001 Rev. 1

Publication Order Number: MMSF7N03Z/D

MMSF7N03Z
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C (Note 1.) Continuous @ TA = 70C (Note 1.) Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor (Note 2.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 ) Thermal Resistance Junction to Ambient (Note 1.) Junction to Ambient (Note 2.) 1. When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ 10 Seconds) 2. When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature. Symbol VDSS VDGR VGS ID ID IDM PD PD TJ, Tstg EAS RJA Value 30 30 15 7.5 5.6 60 2.5 20 1.6 12 55 to 150 450 50 80 C/W Unit Vdc Vdc Vdc Adc Apk Watts mW/C Watts mW/C C mJ

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752

MMSF7N03Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 7.5 Adc) (VGS = 4.5 Vdc, ID = 3.8 Adc) (Cpk 2.0) (Notes 4. & 6.) VGS(th) 1.0 (Notes 4. & 6.) RDS(on) (Note 4.) gFS 4.0 22 30 9.5 30 40 Mhos 2.0 5.5 3.0 Vdc mV/C m (Cpk 2.0) (Notes 4. & 6.) V(BR)DSS 30 IDSS IGSS 0.03 0.15 1.3 2.0 10 5.0 Adc 35 Vdc mV/C Adc Symbol Min Typ Max Unit

Forward Transconductance (VDS = 3.0 Vdc, ID = 3.8 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge

Ciss (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Coss Crss

750 340 45

1500 680 90

pF

td(on) (VDS = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc, RG = 6 ) (Note 4.) tr td(off) tf td(on) (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 4.) tr td(off) tf QT (VDS = 24 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (Note 4.) Q1 Q2 Q3

40 90 470 170 120 350 430 140 34 3.5 9.5 6.5

80 180 940 340 240 700 860 280 48

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 4.) (IS = 7.5 Adc, VGS = 0 Vdc) (Note 4.) (IS = 7.5 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 7.5 7 5 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Storage Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA VSD trr ta tb QRR 0.83 0.67 110 22 90 0.17 1.6 C ns Vdc

Reverse Recovery Time

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753

MMSF7N03Z
TYPICAL ELECTRICAL CHARACTERISTICS
10 I D , DRAIN CURRENT (AMPS) 8 6 4 3.1 V 2 2.7 V 0 0 0.4 0.8 1.2 1.6 2 0 1.8 2.2 2.6 3 10 3.5 V I D , DRAIN CURRENT (AMPS) VGS = 10 V 4.5 V 3.8 V 8 6 4 2

TJ = 25C

VDS 10 V

3.3 V

100C 25C TJ = -55C 3.4 3.8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.1 0.08 0.06 0.04 0.02 0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.05 0.04 0.03 0.02 0.01 0

Figure 2. Transfer Characteristics

ID = 2.5 A TJ = 25C

TJ = 25C

VGS = 4.5 10 V

4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

10

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 4. OnResistance versus Drain Current and Gate Voltage

2.0

VGS = 10 V ID = 2.5 A

1000

VGS = 0 V

I DSS , LEAKAGE (nA)

1.5

100

TJ = 125C

1.0

10

100C

0.5

0 -50

-25

25

50

75

100

125

150

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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754

MMSF7N03Z
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2500 2000 C, CAPACITANCE (pF) 1500 1000 500 0 Coss Crss 0 6 12 18 24 30 Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C VGS = 0 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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755

MMSF7N03Z
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) 12 10 8 VDS 6 4 2 Q3 0 0 5 10 15 20 25 30 0 35 Qg, TOTAL GATE CHARGE (nC) Q1 Q2 ID = 5 A TJ = 25C VGS QT 24 20 16 12 8 4 1000 VDD = 15 V ID = 7.5 A VGS = 10 V TJ = 25C

td(off)

tf 100 tr td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

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756

MMSF7N03Z
5 4 3 2 1 0 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.5

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

di/dt = 300 A/s I S , SOURCE CURRENT

Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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757

MMSF7N03Z
100 I D , DRAIN CURRENT (AMPS) VGS = 15 V SINGLE PULSE TC = 25C 100 s 1 ms 1 10 ms 500 EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) ID = 15 A 400 300 200 100 0

10

0.1

0.01

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10

dc

100

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS


10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2 0.1 0.05 0.02 0.01

0.1

Normalized to ja at 10s.
Chip
0.0163 0.0652 0.1988 0.6411 0.9502

0.01

0.0307 F

0.1668 F

0.5541 F

1.9437 F

72.416 F

0.001 1.0E-05

SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02

Ambient 1.0E+03

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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758

MMSF7N03Z INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52

0.275 7.0

0.155 4.0

0.024 0.6

0.050 1.270
inches mm

SO8 POWER DISSIPATION The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.5 Watts.
PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 50C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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759

MMSF7N03Z
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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760

MPF930, MPF960, MPF990


Preferred Device

Small Signal MOSFET 2 Amps, 35, 60, 90 Volts


NChannel TO92
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 s) Drain Current Continuous (Note 1.) Pulsed (Note 2.) Total Device Dissipation @ TA = 25C Derate above 25C Operating and Storage Junction Temperature Range Thermal Resistance Symbol VDS VDG VGS VGSM MPF930 35 35 MPF960 60 60 20 40 MPF990 90 90 Unit Vdc Vdc Vdc Vpk

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2 AMPERES 35, 60, 90 VOLTS RDS(on) = 0.7 (MPF930) RDS(on) = 0.8 (MPF960) RDS(on) = 1.2 (MPF990)
NChannel D

Adc ID IDM PD 1.0 8.0 Watts mW/C 2.0 3.0 G

TJ, Tstg

55 to 150

C TO92 CASE 29 Style 22 12

JA 125 C/W 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%.

MARKING DIAGRAM & PIN ASSIGNMENT


MPF930 YWW

1 Source 2 Gate Y WW

3 Drain

= Year = Work Week

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 763 of this data sheet. Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

761

November, 2000 Rev. 3

Publication Order Number: MPF930/D

MPF930, MPF960, MPF990


ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 10 Adc) V(BR)DSX MPF930 MPF960 MPF990 IGSS 35 60 90 50 nAdc Vdc

Gate Reverse Current (VGS = 15 Vdc, VDS = 0)

ON CHARACTERISTICS (Note 3.)


ZeroGateVoltage Drain Current (VDS = Maximum Rating, VGS = 0) Gate Threshold Voltage (ID = 1.0 mAdc, VDS = VGS) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 0.5 Adc) MPF930 MPF960 MPF990 MPF930 MPF960 MPF990 MPF930 MPF960 MPF990 rDS(on) MPF930 MPF960 MPF990 ID(on) 1.0 0.9 1.2 1.2 2.0 1.4 1.7 2.0 Amps IDSS VGS(Th) VDS(on) 0.4 0.6 0.6 0.9 1.2 1.2 2.2 2.8 2.8 0.7 0.8 1.2 1.4 1.7 2.4 3.0 3.5 4.8 1.0 10 3.5 Adc Vdc Vdc

(ID = 1.0 Adc)

(ID = 2.0 Adc)

Static DrainSource On Resistance (VGS = 10 Vdc, ID = 1.0 Adc)

OnState Drain Current (VDS = 25 Vdc, VGS = 10 Vdc)

SMALLSIGNAL CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Output Capacitance (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) Forward Transconductance (VDS = 25 Vdc, ID = 0.5 Adc) Ciss Crss Coss gfs 200 70 20 49 380 pF pF pF mmhos

SWITCHING CHARACTERISTICS
TurnOn Time TurnOff Time 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. ton toff 7.0 7.0 15 15 ns ns

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762

MPF930, MPF960, MPF990


RESISTIVE SWITCHING
+25 V 23 PULSE GENERATOR 50 Vin 40 pF 1.0 M 20 dB 50 ATTENUATOR TO SAMPLING SCOPE 50 INPUT Vout OUTPUT V INVERTED out 90% 10 V INPUT Vin 50% 10% PULSE WIDTH 50% ton 90% toff 90% 10%

50

Figure 1. Switching Test Circuit

Figure 2. Switching Waveforms

ORDERING INFORMATION
Device
MPF930 MPF930RLRE MPF930A MPF930ARLRE MPF960 MPF960RLRA MPF990 MPF990RLRA MPF990RLRP

Package
TO92 TO92 TO92 TO92 TO92 TO92 TO92 TO92 TO92

Shipping
1000 Unit/Box 2000 Tape & Reel 1000 Unit/Box 2000 Tape & Reel 1000 Unit/Box 2000 Tape & Reel 1000 Unit/Box 2000 Tape & Reel 2000 Ammo Pack

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763

MPF930, MPF960, MPF990


V DS , DRAIN-SOURCE VOLTAGE (VOLTS) 10 5.0 C, CAPACITANCE (pF) VGS = 10 V 2.0 1.0 0.5 0.2 0.1 -55 -35 -15 85 105 +5.0 25 45 65 TJ, JUNCTION TEMPERATURE (C) 125 145 200 180 160 140 120 100 80 60 40 20 0 0 5.0 Crss 10 20 30 40 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 50 Ciss Coss VGS = 0 V

Figure 3. On Voltage versus Temperature

Figure 4. Capacitance Variation

2.4 ID(on), DRAIN CURRENT (AMPS) VDS = 10 V ID(on), DRAIN CURRENT (AMPS) 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, GATE-SOURCE VOLTAGE (VOLTS) 9.0 10

2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 0 5.0

VGS = 10 V 9.0 V 8.0 V 7.0 V 6.0 V 5.0 V 4.0 V 10 20 30 40 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) 50

Figure 5. Transfer Characteristic

Figure 6. Output Characteristic

2.8 ID(on), DRAIN CURRENT (AMPS) 2.4 2.0 1.6 1.2 0.8 0.4 0.2 0 0.5

VGS = 10 V 9.0 V 8.0 V 7.0 V 6.0 V 5.0 V 4.0 V 3.0 V

1.0 2.0 3.0 4.0 VDS, DRAIN-SOURCE VOLTAGE (VOLTS)

5.0

Figure 7. Saturation Characteristic

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764

MTB1306
Preferred Device

Power MOSFET 75 Amps, 30 Volts, Logic Level


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not Sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance JunctiontoCase JunctiontoAmbient JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5.0 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 30 30 20 20 75 59 225 150 1.2 2.5 55 to 150 280 MTB1306 Y WW = Device Code = Year = Work Week Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 1 Gate 2 Drain 3 Source 1 2 3 4 D2PAK CASE 418B STYLE 2

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75 AMPERES 30 VOLTS RDS(on) = 6.5 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTB1306 YWW

TJ, Tstg EAS

C/W RJC RJA RJA TL 0.8 62.5 50 260 C

ORDERING INFORMATION
Device MTB1306 MTB1306T4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

765

November, 2000 Rev.1

Publication Order Number: MTB1306/D

MTB1306
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 38 Adc) (VGS = 5.0 Vdc, ID = 38 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 38 Adc, TJ = 150C) Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) (VDD = 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 20 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. trr ta tb QRR VSD 0.75 0.64 84 35 53 0.13 1.1 C ns Vdc 17 170 68 145 50 8.3 25.3 17.2 35 340 136 290 70 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2560 1305 386 3584 1827 772 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 15 0.44 55 0.5 0.38 mhos 5.8 7.4 6.5 8.5 Vdc 1.5 2.0 mW Vdc V(BR)DSS 30 IDSS IGSS 10 100 100 nAdc Adc Vdc Symbol Min Typ Max Unit

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766

MTB1306
TYPICAL ELECTRICAL CHARACTERISTICS
150 125 TJ = 25C 100 75 50 25 0 180 5.0 V ID , DRAIN CURRENT (AMPS) 4.0 V 160 140 120 100 80 60 40 20 0 0.5 1.0 1.75 0.25 0.75 1.25 1.5 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2.0 0 2.0 125C TJ = -55C 2.5 3.0 3.5 4.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 4.5 25C VDS 10 V

VGS = 10 V

I D , DRAIN CURRENT (AMPS)

Figure 1. OnRegion Characteristics


0.010 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 TJ = 100C 25C -55C VGS 10 V RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.009 TJ = 25C 0.008 0.007 0.006 0.005 0.004 10 V VGS = 5.0 V

20

40

60 100 80 ID, DRAIN CURRENT (AMPS)

120

140

20 30 40

50

60 70 80 90 100 110 120 130 140 150 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


2.0 VGS = 10 V ID = 38 A I DSS , LEAKAGE (nA) 1.5 1000 10,000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

TJ = 125C

1.0

100

0.5

100C

0 -50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

10

5.0

10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

30

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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767

MTB1306
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
9000 8000 C, CAPACITANCE (pF) 7000 6000 5000 4000 3000 2000 1000 0 -10 -5.0 VGS 0 5.0 10 15 20 Ciss Coss Crss VDS 25 Crss VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

VGS OR VDS, GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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768

MTB1306
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 18 15 7.5 QT 5.0 Q1 2.5 Q3 0 0 10 VDS 20 30 40 QG, TOTAL GATE CHARGE (nC) Q2 VGS 12 10,000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 15 V ID = 75 A VGS = 5.0 V TJ = 25C

9.0 6.0 TJ = 25C ID = 75 A 50 60 3.0 0

t, TIME (ns)

1000

100

td(off) td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100

tr tf

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 18 IS , SOURCE CURRENT (AMPS) 16 14 12 10 8.0 6.0 4.0 2.0 0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.45

0.50

0.55

0.60

0.65

0.70

0.75

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


769

MTB1306
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

1000 I D , DRAIN CURRENT (AMPS)

EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

100

VGS = 10 V SINGLE PULSE TC = 25C 1.0 ms 10 ms dc

280 240 200 160 120 80 40 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 ID = 75 A

10

1.0

0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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770

MTB1306
1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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771

MTB20N20E
Preferred Device

Power MOSFET 20 Amps, 200 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not Sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted with the minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 200 200 20 40 20 12 60 125 1.0 2.5 Unit Vdc Vdc 1 Vdc Vpk Adc Apk Watts W/C Watts 2 3 4 D2PAK CASE 418B STYLE 2

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20 AMPERES 200 VOLTS RDS(on) = 160 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TJ, Tstg EAS

55 to 150 600

C mJ 1 Gate

T20N20E YWW

2 Drain

3 Source

C/W RJC RJA RJA TL 1.0 62.5 50 260 C

T20N20E Y WW

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB20N20E MTB20N20ET4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

772

November, 2000 Rev. 3

Publication Order Number: MTB20N20E/D

MTB20N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 160 Vdc, ID = 20 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 1.0 0.82 239 136 103 2.09 1.35 C ns Vdc 17 86 50 60 54 12 24 22 40 180 100 120 75 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1880 378 68 2700 535 100 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 8.0 11 3.84 3.36 mhos 7.0 0.12 4.0 0.16 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 10 100 100 nAdc 263 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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MTB20N20E
TYPICAL ELECTRICAL CHARACTERISTICS
40 I D , DRAIN CURRENT (AMPS) 40 I D , DRAIN CURRENT (AMPS) VGS = 10 V 8V 9V 7V 35 30 25 20 15 10 5 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8.5 100C

TJ = 25C

VDS 10 V

TJ = -55C

30

25C

20 6V 10 5V 0 0 1 2 3 4 5 6 7 8 9

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4 8 25C -55C 16 12 20 24 28 ID, DRAIN CURRENT (AMPS) 32 36 40 VGS = 10 V 0.17 0.16 0.15 0.14 0.13 0.12 0.11 0.10 0 4

Figure 2. Transfer Characteristics

TJ = 25C

TJ = 100C

VGS = 10 V

15 V

12 20 16 24 28 ID, DRAIN CURRENT (AMPS)

32

36

40

Figure 3. OnResistance versus Drain Current and Temperature


2.4 2.0 1.6 1.2 0.8 0.4 -50

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 10 A

10000

VGS = 0 V TJ = 125C 100C

I DSS , LEAKAGE (nA)

1000

100

25C

10

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

50 100 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

200

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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774

MTB20N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
5000 4000 C, CAPACITANCE (pF) 3000 2000 1000 0 10 Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

Crss Ciss

Coss Crss 5 VGS 0 VDS 5 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB20N20E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 Q1 8 6 4 2 0 Q3 0 10 VDS 20 30 40 QG, TOTAL GATE CHARGE (nC) 50 ID = 20 A TJ = 25C Q2 QT VGS 180 150 120 90 60 30 0 60 1000 VDD = 30 V ID = 20 A VGS = 10 V TJ = 25C 100 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

tr tf td(off) td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


20 16 12 8 4 0 0.5 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.55

0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

1.0

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTB20N20E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 600 10s 100s 1.0 1ms 10ms dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 100 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 500 400 300 200 100 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 ID = 20 A

10

VGS = 20 V SINGLE PULSE TC = 25C

0.01

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (ms) P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

1.0E+00

1.0E+01

Figure 13. Thermal Response


3.0 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1.0 0.5 0

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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MTB20N20E INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
70 R JA , Thermal Resistance, Junction to Ambient (C/W) 60

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

50 40 30 20 3.5 Watts 5 Watts

6 8 10 A, Area (square inches)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
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MTB20N20E
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB20N20E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joint.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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MTB23P06V
Preferred Device

Power MOSFET 23 Amps, 60 Volts


PChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 23 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 25 23 15 81 90 0.60 3.0 55 to 175 794 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C 1 2 3 C mJ D2PAK CASE 418B STYLE 2 G S

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23 AMPERES 60 VOLTS RDS(on) = 120 m


PChannel D

TJ, Tstg EAS

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 1.67 62.5 50 260 C

MTB23P06V YWW

1 Gate MTB23P06V Y WW

2 Drain

3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB23P06V MTB23P06VT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

781

November, 2000 Rev.2

Publication Order Number: MTB23P06V/D

MTB23P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 11.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 23 Adc) (VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150C) Forward Transconductance (VDS = 10.9 Vdc, ID = 11.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 23 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 23 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 23 Adc, VGS = 0 Vdc) (IS = 23 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 23 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 2.2 1.8 142 100 41 0.804 3.5 C ns Vdc 13.8 98.3 41 62 38 7.0 18 14 30 200 80 120 50 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1160 380 105 1620 530 210 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 5.0 11.5 2.1 3.3 3.2 Mhos 2.8 5.3 0.093 4.0 0.12 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 60.5 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTB23P06V
TYPICAL ELECTRICAL CHARACTERISTICS
50 I D , DRAIN CURRENT (AMPS) 40 30 20 10 0 6V 40 8V 9V 7V I D , DRAIN CURRENT (AMPS) 35 30 25 20 15 10 5 10 0 2 3 4 5 6 7 8

TJ = 25C

VGS = 10V

VDS 10 V

TJ = -55C 25C 100C

5V 4V 0 2 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0

VGS = 10 V

0.12 0.115 0.11 0.105 0.1 0.095 0.09 0.085 0.08 0

TJ = 100C

TJ = 25C

25C

VGS = 10 V

-55C

15 V

10

15 20 25 30 ID, DRAIN CURRENT (AMPS)

35

40

45

10

15 20 30 25 35 ID, DRAIN CURRENT (AMPS)

40

45

50

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 1 0 VGS = 10 V ID = 11.5 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

10

TJ = 125C

50 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTB23P06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4000 Ciss C, CAPACITANCE (pF) 3000 Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

2000 Ciss Coss 10 5 VGS 0 Crss VDS 5 10 15 20 25

1000

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB23P06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 5 Q3 10 15 20 VDS 25 30 TJ = 25C ID = 23 A 35 Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 40 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 23 A VDD = 30 V VGS = 10 V

t, TIME (ns)

100

tr tf td(off) td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


25 20 15 10 5 0 TJ = 25C VGS = 0 V

I S , SOURCE CURRENT (AMPS)

0.25

0.5

0.75

1.25

1.5

1.75

2.25

2.5

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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785

MTB23P06V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 800 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 700 600 500 400 300 200 100 0 25 50 75 100 125 150 175

VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms 10 ms dc

ID = 23 A

10

1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

0.1

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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786

MTB23P06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
787

MTB23P06V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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788

MTB23P06V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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789

MTB29N15E
Preferred Device

Power MOSFET 29 Amps, 150 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 29 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 150 150 20 40 29 19 102 125 1.0 2.5 55 to 150 421 1 Gate T29N15E Y WW Unit Vdc Vdc 4 Vdc Vpk Adc Apk Watts W/C Watts C mJ T29N15E YWW 1 2 3 D2PAK CASE 418B STYLE 2

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29 AMPERES 150 VOLTS RDS(on) = 70 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TJ, Tstg EAS

C/W RJC RJA RJA TL 1.0 62.5 50 260 C

2 Drain

3 Source

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB29N15E MTB29N15ET4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

790

November, 2000 Rev. 2

Publication Order Number: MTB29N15E/D

MTB29N15E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 14.5 Adc) DraintoSource OnVoltage (VGS = 10 Vdc) (ID = 29 Adc) (ID = 14.5 Adc, TJ = 125C) Forward Transconductance (VDS = 8.6 Vdc, ID = 14.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 120 Vdc, ID = 29 Adc, VGS = 10 Vdc) (VDD = 75 Vdc, ID = 29 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 29 Adc, VGS = 0 Vdc) (IS = 29 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 29 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH trr ta tb QRR VSD 0.92 0.84 174 126 48 1.4 1.3 C ns Vdc 19 95 90 85 83 12 37 23 40 190 180 170 120 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2300 450 130 3220 630 260 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 10 20 2.4 2.1 mhos 0.054 0.07 Vdc 2.7 5.4 4.0 Vdc mV/C Ohms V(BR)DSS 150 IDSS IGSS 10 100 100 nAdc 151 Vdc mV/C Adc Symbol Min Typ Max Unit

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791

MTB29N15E
TYPICAL ELECTRICAL CHARACTERISTICS
60 60 ID, DRAIN CURRENT (AMPS) 50 40 30 20 10 9 10 0 2 3 TJ = 100C -55C 4 5 6 7 8 25C

ID , DRAIN CURRENT (AMPS)

VGS = 10 V 9V 50 TJ = 25C 8V 40 30 20 10 0 0 1 2 3 4 5

7V

6.5 V

VDS 10 V

6V

5.5 V 5V 4.5 V 4V 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0

VGS = 10 V TJ = 100C

0.07 0.065 0.06 0.055 0.05 0.045 0.04 0 10 20 40 30 ID, DRAIN CURRENT (AMPS) 50 60 TJ = 25C VGS = 10 V 15 V

25C

-55C

10

20

30

40

50

60

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


2.25 2.0 1.75 1.5 1.25 1.0 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 0.1 0 VGS = 10 V ID = 14.5 A IDSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

TJ = 125C 100C

10

25C

20

TJ, JUNCTION TEMPERATURE (C)

100 120 140 60 80 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

160

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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792

MTB29N15E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
7500 VDS = 0 V VGS = 0 V 7000 C 6500 iss 6000 5500 5000 Crss 4500 4000 3500 3000 2500 2000 1500 1000 Crss 500 0 -10 -5 0 5 VGS VDS

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

C, CAPACITANCE (pF)

Ciss

Coss 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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793

MTB29N15E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 Q3 0 10 20 30 40 50 VDS 60 70 80 90 Qg, TOTAL GATE CHARGE (nC) TJ = 25C ID = 29 A Q1 Q2 QT VGS 120 100 80 60 40 20 0 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100 t, TIME (ns)

tf td(off) td(on)

tr

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
30 I S , SOURCE CURRENT (AMPS) 25 20 15 10 5 0 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


794

MTB29N15E
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
1000 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 100 ms 1 ms 10 ms dc

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.
450 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 29 A

100

10

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100

0.1

1000

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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795

MTB29N15E
TYPICAL ELECTRICAL CHARACTERISTICS
1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 1E-05 1E-04 1E-03 1E-02 t, TIME (seconds) P(pk) t2 DUTY CYCLE, D = t1/t2 1E-01 t1 RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+00 1E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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796

MTB29N15E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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797

MTB30N06VL
Preferred Device

Power MOSFET 30 Amps, 60 Volts, Logic Level


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 30 Apk, L = 0.342 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 20 30 20 105 90 0.6 3.0 55 to 175 154 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 2 3 TJ, Tstg EAS 4 D2PAK CASE 418B STYLE 2 G S

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30 AMPERES 60 VOLTS RDS(on) = 50 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 1.67 62.5 50 260 C 1 Gate

T30N06VL YWW

2 Drain

3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

T30N06VL = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device MTB30N06VL MTB30N06VLT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

798

November, 2000 Rev. 5

Publication Order Number: MTB30N06VL/D

MTB30N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 15 Adc) DraintoSource OnVoltage (VGS = 5 Vdc, ID = 30 Adc) (VGS = 5 Vdc, ID = 15 Adc, TJ = 150C) Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 5 Vdc) (VDD = 30 Vdc, ID = 30 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 30 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 4.5 nH nH ta tb QRR 0.98 0.89 86 49 37 0.228 1.6 C ns Vdc 14 260 54 108 27 5 17 15 30 520 110 220 40 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1130 360 95 1580 500 190 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 13 1.1 21 1.8 1.73 Mhos 1.5 4.0 0.033 2.0 0.05 Vdc mV/C Ohms Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 63 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTB30N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
60 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 3V 60 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 VDS 10 V

VGS = 10 V 8V 6V 5V

TJ = 25C

TJ = -55C 25C 100C

4V

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0

VGS = 10 V TJ = 100C

0.06 0.05 0.04 0.03 0.02 0.01 0

TJ = 25C

VGS = 5 V 10 V

25C

-55C

10

20 40 30 ID, DRAIN CURRENT (AMPS)

50

60

10

20 30 40 ID, DRAIN CURRENT (AMPS)

50

60

Figure 3. OnResistance versus Drain Current and Temperature


2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 1 0 VGS = 5 V ID = 15 A I DSS , LEAKAGE (nA)

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1000

VGS = 0 V TJ = 125C

100 100C 10

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature http://onsemi.com


800

Figure 6. DrainToSource Leakage Current versus Voltage

MTB30N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
5000 4500 C iss 4000 C, CAPACITANCE (pF) 3500 3000 2500 2000 1500 1000 500 0 10 5 VGS Crss 0 VDS 5 10 15 20 Ciss Coss 25 Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB30N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 5 10 15 Q3 VDS 20 QT, TOTAL CHARGE (nC) TJ = 25C ID = 30 A Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 25 1000 TJ = 25C ID = 30 A VDD = 30 V VGS = 5 V VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

tr tf td(off)

t, TIME (ns)

100

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


30 25 I S , SOURCE CURRENT (AMPS) 20 15 10 5 0 0.5 TJ = 25C VGS = 0 V

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTB30N06VL
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 160 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 140 120 100 80 60 40 20 0 25 50 75 100 125 150 175 ID = 30 A

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 s

100

10

100 s 1 ms 10 ms

dc 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

0.01 1.0E-05

1.0E+00

1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

TA, AMBIENT TEMPERATURE (C)

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MTB30N06VL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
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MTB30N06VL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB30N06VL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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MTB30P06V
Preferred Device

Power MOSFET 30 Amps, 60 Volts


PChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 25 30 19 105 125 0.83 3.0 55 to 175 450 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C 1 2 3 C mJ D2PAK CASE 418B STYLE 2 G S

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30 AMPERES 60 VOLTS RDS(on) = 80 m


PChannel D

TJ, Tstg EAS

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 1.2 62.5 50 260 C 1 Gate

MTB30P06V YWW

2 Drain

3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

MTB30P06V Y WW

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB30P06V MTB30P06VT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

807

November, 2000 Rev.2

Publication Order Number: MTB30P06V/D

MTB30P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 15 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 30 Adc) (VGS = 10 Vdc, ID = 15 Adc, TJ = 150C) Forward Transconductance (VDS = 8.3 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 30 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 30 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 2.3 1.9 175 107 68 0.965 3.0 C ns Vdc 14.7 25.9 98 52.4 54 9.0 26 20 30 50 200 100 80 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1562 524 154 2190 730 310 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 5.0 7.9 2.0 2.9 2.8 Mhos 2.6 5.3 0.067 4.0 0.08 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 62 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTB30P06V
TYPICAL ELECTRICAL CHARACTERISTICS
60 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 0 2 4 6 8 10 5V 4V 12 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6V 60 8V I D , DRAIN CURRENT (AMPS) 9V 7V 50 40 30 20 10 0 TJ = -55C

TJ = 25C VGS = 10V

VDS 10 V

100C 25C

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.12 0.1 0.08 0.06

VGS = 10 V

0.08

TJ = 100C

TJ = 25C VGS = 10 V 15 V

0.07

25C -55C

0.06

0.04 0.02 0

0.05

10

20 30 40 ID, DRAIN CURRENT (AMPS)

50

60

0.04

10

20 30 40 ID, DRAIN CURRENT (AMPS)

50

60

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 1 0 VGS = 10 V ID = 15 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C

10

100C

50 60 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

70

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTB30P06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 5000 C, CAPACITANCE (pF) 4000 3000 2000 1000 0 10 5 VGS 0 Crss VDS Ciss Coss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

10

15

20

25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB30P06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 Q3 10 20 30 VDS 40 TJ = 25C ID = 30 A 50 Q1 Q2 QT 30 VGS 27 24 21 18 15 12 9 6 3 0 60 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 30 A VDD = 30 V VGS = 10 V

t, TIME (ns)

100

td(off) tf tr td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


30 25 I S , SOURCE CURRENT (AMPS) 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 TJ = 25C VGS = 0 V

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTB30P06V
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 175

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

ID = 30 A

100 10 s 10 100 s 1 ms 10 ms dc 100

0.1

1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 0.05

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 9 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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812

MTB30P06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
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MTB30P06V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB30P06V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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MTB36N06V
Preferred Device

Power MOSFET 32 Amps, 60 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 50 s) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 32 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 32 22.6 112 90 0.6 3.0 55 to 175 205 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C Watts C mJ 1 2 3 D2PAK CASE 418B STYLE 2 G S

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32 AMPERES 60 VOLTS RDS(on) = 40 m


NChannel D

TJ, Tstg EAS

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 1.67 62.5 50 260 C

MTB36N06V YWW

1 Gate

2 Drain

3 Source = Device Code = Year = Work Week

1. When surface mounted to an FR4 board using the minimum recommended pad size.

MTB36N06V Y WW

ORDERING INFORMATION
Device MTB36N06V MTB36N06VT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

816

November, 2000 Rev. 3

Publication Order Number: MTB36N06V/D

MTB36N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 16 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 32 Adc) (VGS = 10 Vdc, ID = 16 Adc, TJ = 150C) Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 32 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 32 Adc, VGS = 0 Vdc) (IS = 32 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 32 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 nH nH ta tb QRR 1.03 0.94 92 64 28 0.332 2.0 C ns Vdc 14 138 54 91 39 7 17 13 30 270 100 180 50 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1220 337 74.8 1700 470 150 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 5.0 1.25 7.83 1.54 1.47 mhos 2.6 6.0 0.034 4.0 0.04 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 61 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTB36N06V
TYPICAL ELECTRICAL CHARACTERISTICS
72 I D , DRAIN CURRENT (AMPS) 72 I D , DRAIN CURRENT (AMPS) 7V VDS 10 V 54

TJ = 25C 9V 8V

VGS = 10 V

TJ = 100C 25C

54

36

6V

36

18

5V 4V

18 -55C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.1 0.08

VGS = 10 V

0.052

TJ = 25C

TJ = 100C 0.06 0.04 0.02 0 25C -55C

0.044 VGS = 10 V 15 V

0.036

18

36 54 ID, DRAIN CURRENT (AMPS)

72

0.028

18

36 54 ID, DRAIN CURRENT (AMPS)

72

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1 0.8 0.6 -50 1 VGS = 10 V ID = 16 A I DSS , LEAKAGE (nA)

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1000

VGS = 0 V TJ = 125C

100

100C

10

25C

-25

25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature http://onsemi.com


818

Figure 6. DrainToSource Leakage Current versus Voltage

MTB36N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4000 VDS = 0 V 3000 Ciss VGS = 0 V TJ = 25C

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

C, CAPACITANCE (pF)

2000 Crss 1000 Ciss Coss Crss 10 5 VGS 0 VDS 5 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB36N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 0 5 Q3 VDS 10 15 20 25 30 35 40 QT, TOTAL CHARGE (nC) TJ = 25C ID = 32 A VGS Q1 Q2 25 20 15 10 5 0 30 1000 TJ = 25C ID = 32 A VDD = 30 V VGS = 10 V VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


32 TJ = 25C VGS = 0 V

I S , SOURCE CURRENT (AMPS)

24

16

0 0.5 0.55

0.6 0.65

0.7 0.75

0.8 0.85 0.9

0.95

1.05

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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820

MTB36N06V
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 225 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 200 175 150 125 100 75 50 25 0 25 50 75 100 125 150 175 ID = 32 A

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

100 10 s

10

100 s 1 ms 10 ms

dc 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175
RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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821

MTB36N06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
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MTB36N06V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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823

MTB36N06V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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824

MTB40N10E
Preferred Device

Power MOSFET 40 Amps, 100 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, Peak IL = 40 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 100 100 20 40 40 29 140 169 1.35 2.5 55 to 150 800 1 Gate T40N10E Y WW Unit Vdc Vdc 4 Vdc Vpk Adc Apk Watts W/C Watts C mJ T40N10E YWW 1 2 3 D2PAK CASE 418B STYLE 2

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40 AMPERES 100 VOLTS RDS(on) = 40 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TJ, Tstg EAS

C/W RJC RJA RJA TL 0.74 62.5 50 260 C

2 Drain

3 Source

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB40N10E MTB40N10ET4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

825

November, 2000 Rev. 2

Publication Order Number: MTB40N10E/D

MTB40N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 20 Adc) DraintoSource OnVoltage (VGS = 10 Vdc) (ID = 40 Adc) (ID = 20 Adc, TJ = 125C) Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 40 Adc, VGS = 10 Vdc) (VDD = 50 Vdc, ID = 40 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 40 Adc, VGS = 0 Vdc) (IS = 40 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) (IS = 40 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Cpk + Max limit Typ 3 sigma LD LS 7.5 3.5 4.5 nH trr ta tb QRR VSD 0.96 0.88 152 117 35 1.0 1.0 C ns Vdc 19 165 75 97 80 15 40 29 40 330 150 190 110 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2305 620 205 3230 1240 290 pF (Cpk 2.0) (Note 4.) VGS(th) 2.0 (Cpk 2.0) (Note 4.) RDS(on) VDS(on) gFS 17 21 1.9 1.7 mhos 0.033 0.04 Vdc 2.9 6.7 4.0 Vdc mV/C Ohms V(BR)DSS (Cpk 2.0) (Note 4.) IDSS IGSS 10 100 100 nAdc 100 112 Vdc mV/C Adc Symbol Min Typ Max Unit

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826

MTB40N10E
TYPICAL ELECTRICAL CHARACTERISTICS
80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 1 3 4 5 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 5V 6V 80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 10 0 2 3 4 5 6 7 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8 TJ = -55C VDS 10 V 25C

VGS = 10 V

8V 9V

TJ = 25C 7V

100C

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0

VGS = 10 V TJ = 100C

0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS) 70 80 VGS = 10 V TJ = 25C

25C -55C

15 V

10

20

30

40

50

60

70

80

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 VGS = 10 V ID = 20 A I DSS , LEAKAGE (nA)

1000

VGS = 0 V

TJ = 125C

100 100C

10

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

1.0

10

20 30 40 60 70 80 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

90

100

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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827

MTB40N10E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 -10 -5 VGS 0 VDS Crss 5 10 15 20 Coss 25 Ciss Ciss Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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828

MTB40N10E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 10 Q3 20 30 40 VDS 50 60 70 80 QG, TOTAL GATE CHARGE (nC) ID = 40 A TJ = 25C Q1 Q2 QT VGS 80 72 64 56 48 40 32 24 16 8 0 10,000 VDD = 50 V ID = 40 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1000 t, TIME (ns)

100

tr tf td(off)

10

td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


40 35 I S , SOURCE CURRENT (AMPS) 30 25 20 15 10 5 0 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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829

MTB40N10E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 800 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 700 600 500 400 300 200 100 0 25 50 75 100 125 150 ID = 40 A

VGS = 20 V SINGLE PULSE TC = 25C 100 ms

100

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 ms

10

1.0 ms 10 ms

1.0

dc 0.1 1.0 10 100 1000 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.0 0.01 SINGLE PULSE 1.0E-05 1.0E-04 1.0E-03 P(pk)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

t2 DUTY CYCLE, D = t1/t2 1.0E-02 t, TIME (seconds) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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830

MTB40N10E INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
831

MTB40N10E
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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832

MTB40N10E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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833

MTB50N06V
Preferred Device

Power MOSFET 42 Amps, 60 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 42 Apk, L = 0.454 H, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 42 30 147 125 0.83 3.0 55 to 175 400 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C Watts C mJ 1 2 3 D2PAK CASE 418B STYLE 2 G S

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42 AMPERES 60 VOLTS RDS(on) = 28 m


NChannel D

TJ, Tstg EAS

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 1.2 62.5 50 260 C 1 Gate

MTB50N06V YWW

2 Drain

3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

MTB50N06V Y WW

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB50N06V MTB50N06VT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

834

November, 2000 Rev. 4

Publication Order Number: MTB50N06V/D

MTB50N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 21 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 42 Adc) (ID = 21 Adc, TJ = 150C) Forward Transconductance (VDS = 6.25 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 10 Vdc) (VDD = 25 Vdc, ID = 42 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 1.06 0.99 84 73 11 0.28 2.5 C ns Vdc 12 122 64 54 47 9 21 16 20 250 110 90 70 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1644 465 112 2320 660 230 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 16 1.4 23 1.7 1.6 mhos 2.7 3.0 0.025 4.0 0.028 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 69 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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835

MTB50N06V
TYPICAL ELECTRICAL CHARACTERISTICS
100 I D , DRAIN CURRENT (AMPS) 80 60 6V 40 20 0 5V 100 8V I D , DRAIN CURRENT (AMPS) 7V 80 60 40 20 0

TJ = 25C

VGS = 10 V

9V

VDS 10 V 100C 25C TJ = -55C

0.8

1.6

2.4

3.2

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.04

VGS = 10 V TJ = 100C 25C

0.033

TJ = 25C

0.034

0.03

0.028 0.022 0.016 0.01

0.027

VGS = 10 V

0.024

15 V

-55C 0 20 40 60 80 100

0.021

20

40

60

80

100

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.5 2 1.5 1 0.5 0 -50 VGS = 10 V ID = 21 A

1000

VGS = 0 V

TJ = 125C

I DSS , LEAKAGE (nA)

100 100C 10 25C 1

-25

25

50

75

100

125

150

175

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTB50N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 5000 C, CAPACITANCE (pF) 4000 3000 2000 1000 0 10 Crss Ciss Coss 10 15 20 25 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss 5 VGS 0 VDS 5

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB50N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 14 12 10 8 6 4 2 0 Q3 0 10 20 30 QT, TOTAL CHARGE (nC) VDS 40 Q1 QT VGS Q2 ID = 42 A TJ = 25C 56 48 40 32 24 16 8 0 50 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 25 V ID = 42 A VGS = 10 V TJ = 25C

t, TIME (ns)

100

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


50 40 30 20 10 0 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTB50N06V
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 400 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID = 42 A 320 240 160 80 0

VGS = 20 V SINGLE PULSE TC = 25C

100 10s 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100s 1ms 10ms 100

dc

25

150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 0.05 0.02 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

0.01 1.0E-05

1.0E-04

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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839

MTB50N06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
840

MTB50N06V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB50N06V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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842

MTB50N06VL
Preferred Device

Power MOSFET 42 Amps, 60 Volts, Logic Level


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 42 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 20 42 30 147 125 0.83 3.0 55 to 175 265 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 2 3 TJ, Tstg EAS 4 D2PAK CASE 418B STYLE 2 G S

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42 AMPERES 60 VOLTS RDS(on) = 32 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 1.2 62.5 50 260 C 1 Gate

T50N06VL YWW

2 Drain

3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

T50N06VL = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device MTB50N06VL MTB50N06VLT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

843

November, 2000 Rev. 3

Publication Order Number: MTB50N06VL/D

MTB50N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 21 Adc) DraintoSource OnVoltage (VGS = 5 Vdc, ID = 42 Adc) (VGS = 5 Vdc, ID = 21 Adc, TJ = 150C) Forward Transconductance (VDS = 6 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 5 Vdc) (VDD = 30 Vdc, ID = 42 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.03 0.94 91.1 63.8 27.3 0.299 2.5 C ns Vdc 16 355 80 160 40 11 20 16 30 701 160 320 60 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1570 508 135 2200 710 270 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 17 1.2 28 1.6 1.5 Mhos 1.4 4.3 0.025 2.0 0.032 Vdc mV/C Ohms Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 64 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTB50N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
90 80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3V 6V 90 80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 VDS 10 V TJ = -55C 25C 100C

TJ = 25C 8V 7V

VGS = 10 V

5V

4V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.06 0.05 0.04 0.03 0.02 0.01 0

VGS = 5 V TJ = 100C 25C -55C

0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0

TJ = 25C VGS = 5 V 10 V

18

36 45 54 63 27 ID, DRAIN CURRENT (AMPS)

72

81

90

10

20

40 50 30 60 ID, DRAIN CURRENT (AMPS)

70

80

90

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50

VGS = 5 V ID = 21 A I DSS , LEAKAGE (nA)

1000

VGS = 0 V

TJ = 125C 100

100C

-25

25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

10

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTB50N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 5000 C, CAPACITANCE (pF) 4000 3000 2000 1000 0 10 Ciss Coss VDS = 0 V 5 VGS 0 VDS 5 Crss 10 15 20 25 Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB50N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 0 Q3 10 20 VGS QT 30 25 20 15 TJ = 25C ID = 42 A VDS 30 40 10 5 0 50 1000 TJ = 25C ID = 42 A VDD = 30 V VGS = 5 V VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

tr tf td(off) td(on)

Q1

Q2

t, TIME (ns)

100

10

10 RG, GATE RESISTANCE (OHMS)

100

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


25 20 15 10 5 0 0.5 TJ = 25C VGS = 0 V

I S , SOURCE CURRENT (AMPS)

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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847

MTB50N06VL
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 300 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID = 42 A 250 200 150 100 50 0 25 150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 175

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 s

100

10

100 s 1 ms 10 ms dc 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

0.01 1.0E-05

1.0E+00

1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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848

MTB50N06VL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
849

MTB50N06VL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB50N06VL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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MTB50P03HDL
Preferred Device

Power MOSFET 50 Amps, 30 Volts, Logic Level


PChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not Sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 30 30 15 20 50 31 150 125 1.0 2.5 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts M50P03HDL YWW TJ, Tstg EAS 55 to 150 1250 C mJ 1 Gate M50P03HDL Y WW 2 Drain 3 Source 1 2 3 4 D2PAK CASE 418B STYLE 2

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50 AMPERES 30 VOLTS RDS(on) = 25 m


PChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 1.0 62.5 50 260 C

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB50P03HDL MTB50P03HDLT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

852

January, 2001 Rev. 4

Publication Order Number: MTB50P03HDL/D

MTB50P03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 25 Adc) DrainSource OnVoltage (VGS = 5.0 Vdc) (ID = 50 Adc) (ID = 25 Adc, TJ =125C) Forward Transconductance (VDS = 5.0 Vdc, ID = 25 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 24 Vdc, ID = 50 Adc, VGS = 5.0 Vdc) (VDD= 15 Vdc, ID = 50 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 2.3 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 50 Adc, VGS = 0 Vdc) (IS = 50 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 50 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 3.5 7.5 nH nH ta tb QRR 2.39 1.84 106 58 48 0.246 3.0 C ns Vdc 22 340 90 218 74 13.6 44.8 35 30 466 117 300 100 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) (Cpk 3.0) (Note 3.) (Cpk 2.0) (Note 3.) V(BR)DSS 30 IDSS IGSS 100 1.0 10 nAdc 26 Vdc mV/C Adc Symbol Min Typ Max Unit

VGS(th) 1.0 1.5 4.0 20.9 0.83 20 3500 1550 550 2.0 25

Vdc mV/C mOhm Vdc 1.5 1.3 mhos 15 4900 2170 770 pF

(Cpk 3.0) (Note 3.)

RDS(on) VDS(on)

gFS

Ciss Coss Crss

Reverse Recovery Time (S Figure (See Fi 15)

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MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
100 I D , DRAIN CURRENT (AMPS) 80 60 40 20 0 4.5 V 100 I D , DRAIN CURRENT (AMPS) 80 60 40 20 0 1.5

TJ = 25C

VGS = 10 V 8V 6V

5V

VDS 5 V

TJ = -55C 25C 100C

4V

3.5 V 3V 2.5 V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

1.9

2.3

2.7

3.1

3.5

3.9

4.3

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.029 0.027 0.025 0.023 0.021 0.019 0.017 0.015 0 20 40 -55C 60 80 100 25C VGS = 5 V RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.022 0.021 0.020 0.019 0.018 0.017 0.016 0.015 0

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 5 V

TJ = 100C

10 V

20

40

60

80

100

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1.35 1.25 VGS = 5 V ID = 25 A I DSS, LEAKAGE (nA) 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

1.15 1.05 0.95 0.85 -50

TJ = 125C 100

100C -25 0 25 50 75 100 125 150 10 0 5 10 15 20 25 30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MTB50P03HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
VDS = 0 V C 12000 iss C, CAPACITANCE (pF) 10000 8000 6000 4000 2000 0 10 5 VGS 0 VDS 5 Crss Ciss Coss Crss 10 15 20 25 14000 VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB50P03HDL
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 QT 5 4 3 2 1 Q3 0 0 10 20 30 40 50 60 QT, TOTAL GATE CHARGE (nC) VDS 70 ID = 50 A TJ = 25C Q1 Q2 VGS 25 20 15 10 5 0 80 30 1000 VDD = 30 V VGS = 10 V ID = 50 A TJ = 25C

tr tf td(off)

t, TIME (ns)

100

td(on)

10

1 RG, GATE RESISTANCE (Ohms)

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
50 I S , SOURCE CURRENT (AMPS) 40 30 20 10 0 0.4 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MTB50P03HDL
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

I D , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

1000

1400 1200 ID = 50 A

100

1000 800 600 400 200 0 25 50 75 100 125 150

10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10

10 ms dc

1 0.1

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 14. Thermal Response

3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. Diode Reverse Recovery Waveform

Figure 16. D2PAK Power Derating Curve

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858

MTB50P03HDL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
859

MTB50P03HDL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 18. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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860

MTB50P03HDL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 19. Typical Solder Heating Profile

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861

MTB52N06V
Preferred Device

Power MOSFET 52 Amps, 60 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 52 41 182 188 1.25 3.0 55 to 175 406 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C Watts C mJ 1 2 3 D2PAK CASE 418B STYLE 2 G S

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52 AMPERES 60 VOLTS RDS(on) = 22 m


NChannel D

TJ, Tstg EAS

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 0.8 62.5 50 260 C

MTB52N06V YWW

1 Gate MTB52N06V Y WW

2 Drain

3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB52N06V MTB52N06VT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

862

November, 2000 Rev. 4

Publication Order Number: MTB52N06V/D

MTB52N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 26 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 52 Adc) (VGS = 10 Vdc, ID = 26 Adc, TJ = 150C) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 52 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.0 0.98 100 80 20 0.341 1.5 C ns Vdc 12 298 70 110 125 10 30 40 20 600 140 220 175 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1900 580 150 2660 810 300 pF (Cpk 2.0) (Note 4.) VGS(th) 2.0 (Cpk 2.0) (Note 4.) RDS(on) VDS(on) gFS 17 24 1.4 1.2 mhos 0.019 0.022 Vdc 2.7 6.4 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 4.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 66 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure Fi 14) (See

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863

MTB52N06V
TYPICAL ELECTRICAL CHARACTERISTICS
110 100 I D , DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 5V 6V 110 100 I D , DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 TJ = -55C 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V 9V

8V

TJ = 25C 7V

VDS 10 V

100C 25C

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.035 0.03

VGS = 10 V TJ = 100C 25C

0.023 0.022 0.021 0.020 0.019 0.018 0.017 0.016 5

TJ = 25C

0.025 0.02

VGS = 10 V

0.015 0.01

-55C

15 V

0.005 0 0 10 20 30 40 50 60 70 80 90 100 110

0.015

15

25

35

45

55

65

75

85

95

105

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2 1.75 1.5 1.25 1 0.75 0.5 0.25 -50 -25 0 25 50 75 100 125 150 175 VGS = 10 V ID = 26 A I DSS , LEAKAGE (nA)

100

VGS = 0 V

TJ = 125C

10 100C

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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864

MTB52N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
7000 6000 C, CAPACITANCE (pF) 5000 4000 3000 2000 1000 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss Coss Crss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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865

MTB52N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 20 40 VDS 60 80 100 QT, TOTAL CHARGE (nC) 120 ID = 52 A TJ = 25C Q1 Q2 QT VGS 36 33 30 27 24 21 18 15 12 9 6 3 0 140 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 52 A VGS = 10 V TJ = 25C

tr tf td(off)

t, TIME (ns)

100

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


55 50 I S , SOURCE CURRENT (AMPS) 45 40 35 30 25 20 15 10 5 0 0.2 VGS = 0 V TJ = 25C

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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866

MTB52N06V
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) 175 ID = 52 A 10s

VGS = 20 V SINGLE PULSE TC = 25C

100

100s 10

1ms 10ms dc

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1

10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1.0E-05 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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867

MTB52N06V INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
868

MTB52N06V
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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869

MTB52N06V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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870

MTB52N06VL
Preferred Device

Power MOSFET 52 Amps, 60 Volts, Logic Level


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 25 52 41 182 188 1.25 3.0 55 to 175 406 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 1 2 3 4 D2PAK CASE 418B STYLE 2 G S

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52 AMPERES 60 VOLTS RDS(on) = 25 m


NChannel D

TJ, Tstg EAS

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

C/W RJC RJA RJA TL 0.8 62.5 50 260 C

MTB52N06VL YWW

1 Gate

2 Drain

3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

MTB52N06VL Y WW

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB52N06VL MTB52N06VLT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

871

November, 2000 Rev. 4

Publication Order Number: MTB52N06VL/D

MTB52N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 26 Adc) DraintoSource OnVoltage (VGS = 5 Vdc, ID = 52 Adc) (VGS = 5 Vdc, ID = 26 Adc, TJ = 150C) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 5 Vdc) (VDD = 30 Vdc, ID = 52 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150 C) VSD trr (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.03 0.9 104 63 41 0.28 1.5 C ns Vdc 15 500 100 200 62 4.0 31 16 30 1000 200 400 90 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1900 550 170 2660 770 340 pF (Cpk 2.0) (Note 4.) VGS(th) 1.0 (Cpk 2.0) (Note 4.) RDS(on) VDS(on) gFS 17 30 1.6 1.4 Mhos 0.022 0.025 Vdc 1.5 4.5 2.0 Vdc mV/C Ohm (Cpk 2.0) (Note 4.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 65 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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872

MTB52N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
110 I D , DRAIN CURRENT (AMPS) 110 100 I D , DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 0.5

100

VGS = 10 V 8V 90 7V 80 70 60 50 40 30 20 10 0

6V

TJ = 25C 5V

VDS 10 V

TJ = -55C 100C 25C

4V

3V 0 1 2 3 4 5 6 7 8 9 10

1.0

1.5

2.5

3.5

4.5

5.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) .070 .060 .050 .040 .030 .020 .010 0 0 10 20 30 40 50 60 70 80 90 100 110 TJ = 100C 25C -55C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

VGS = 5 V

.040 .035 .030 .025 .020 .015 .010 .005 0 0

TJ = 25C

VGS = 5 V 10 V

10

20

30

40

50

60

70

80

90

100 110

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 I DSS , LEAKAGE (nA) 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175 1 0 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 26 A

VGS = 0 V TJ = 125C

100C 10

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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873

MTB52N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS Crss 0 VDS 5 10 15 20 25 Ciss Coss Crss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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874

MTB52N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 Q3 10 20 VDS 30 40 50 QT, TOTAL CHARGE (nC) 60 ID = 52 A TJ = 25C Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 70 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 52 A VGS = 5 V TJ = 25C tr tf td(off)

t, TIME (ns)

100

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


55 50 I S , SOURCE CURRENT (AMPS) 45 40 35 30 25 20 15 10 5 0 0.5 0.55 VGS = 0 V TJ = 25C

0.6 0.65

0.7 0.75

0.8 0.85

0.9 0.95

1.05

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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875

MTB52N06VL
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) 175 10s ID = 52 A

VGS = 15 V SINGLE PULSE TC = 25C

100

10

100s 1ms 10ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 dc

10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1.0E-05 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response


3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150 175

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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876

MTB52N06VL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 3.0 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 3.0 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
877

MTB52N06VL
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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878

MTB52N06VL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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879

MTB55N06Z
Preferred Device

Power MOSFET 55 Amps, 60 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche mode and switch efficiently. This high energy device also offers a draintosource diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, PWM motor controls and other inductive loads, the avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Avalanche Energy Capability Specified at Elevated Temperature SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Low Stored Gate Charge for Efficient Switching Internal SourcetoDrain Diode Designed to Replace External Zener Transient SuppressorAbsorbs High Energy in the Avalanche Mode ESD Protected. Designed to Typically Withstand 400 V Machine Model and 4000 V Human Body Model.
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ TC = 25C Continuous @ TC = 100C Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 40 55 35.5 165 113 0.91 2.5 55 to 150 454 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C MTB55N06Z YWW 1 2 3 4 D2PAK CASE 418B STYLE 2

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55 AMPERES 60 VOLTS RDS(on) = 18 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TJ, Tstg EAS

C mJ 1 Gate MTB55N06Z Y WW C/W 2 Drain 3 Source

= Device Code = Year = Work Week

ORDERING INFORMATION
Device Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

RJC RJC RJA TL

1.1 62.5 50 260 C

MTB55N06Z MTB55N06ZT4

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

880

November, 2000 Rev. 2

Publication Order Number: MTB55N06Z/D

MTB55N06Z
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 27.5 Adc) DraintoSource OnVoltage (VGS = 10 Vdc) (ID = 55 Adc) (ID = 27.5 Adc, TJ = 125C) Forward Transconductance (VDS = 4.0 Vdc, ID = 27.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 55 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 55 Adc, VGS(on) Vdc, GS( ) = 10 Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 55 Adc, VGS = 0 Vdc) (IS = 55 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 55 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH ta tb QRR 0.93 0.82 57 32 25 0.11 1.1 C ns Vdc 27 157 116 126 40 7.0 18 15 54 314 232 252 56 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1390 520 119 1950 730 238 pF (Cpk 2.0) VGS(th) 2.0 (Cpk 2.0) RDS(on) VDS(on) gFS 12 0.825 0.74 15 1.2 1.0 Mhos 14 18 Vdc 3.0 6.0 4.0 Vdc mV/C m (Cpk 2.0) V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 53 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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881

MTB55N06Z
60 50 40 30 20 10 0 5.0 V VGS = 4.0 V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 V 9.0 V 8.0 V 7.0 V TJ = 25C ID , DRAIN CURRENT (AMPS) 6.0 V 60 VDS 10 V 50 40 30 20 10 0 2.0 2.4 2.8 3.2 3.6 4.0 4.4

ID , DRAIN CURRENT (AMPS)

100C 25C

TJ = -55C 4.8 5.2 5.6 6.0 6.4

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (m W )

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (m W )

24 VGS = 10 V 20 TJ = 100C

15.0 TJ = 25C 14.6 14.2 13.8 13.4 13.0 VGS = 10 V

16

25C

15 V

12 -55C 8.0 10 20 30 40 50 60

10

20

30

40

50

60

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 4. OnResistance versus Drain Current and Gate Voltage

1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 VGS = 10 V ID = 15 A

1000 100 IDSS , LEAKAGE (nA) 10 1.0 0.1 0.01

VGS = 0 V

125C 100C

TJ = 25C

-25

25

50

75

100

125

150

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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882

MTB55N06Z
VDS = 0 V Ciss VGS = 0 V VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C QT 40 VGS Q1 Q2 32 24 16 TJ = 25C ID = 30 A VDS 8.0 12 16 20 24 28 32 36 40 8.0 0 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 150 4000 3200 C, CAPACITANCE (pF) 2400 1600 800 0 -10 Crss Ciss Coss Crss -5.0 VGS 0 VDS 5.0 10 15 20 25 12 10 48

8.0

6.0 4.0 2.0 0 0

Q3 4.0

QG, TOTAL GATE CHARGE (nC)

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

Figure 8. GatetoSource and DraintoSource Voltage versus Total Charge


30 IS , SOURCE CURRENT (AMPS) TJ = 25C VGS = 0 V 20

1000

TJ = 25C ID = 30 A VDD = 30 V VGS = 10 V tr tf td(off)

t, TIME (ns)

100

10

td(on) 10

1.0

10 RG, GATE RESISTANCE (OHMS)

100

0.5 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90 0.94 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation versus Gate Resistance


100 500

Figure 10. Diode Forward Voltage versus Current

100 ms

10 ms

EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

ID , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TC = 25C 1.0 ms

ID = 30 A 400 300 200 100 0

10 10 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LMIT 0.1 0.1 1.0 10 100 dc

25

50

75

100

125

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

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883

MTB55N06Z
1.0 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.00001 0.0001 0.001 0.01 t, TIME (seconds) 0.1 1.0 10

0.01

Figure 13. Thermal Response

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884

MTB60N05HDL
Preferred Device

Power MOSFET 60 Amps, 50 Volts, Logic Level


NChannel D2PAK
The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced highcell density HDTMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not Sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 50 50 15 20 60 42 180 150 1.0 55 to 175 540 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ T60N05HDL YWW 1

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60 AMPERES 50 VOLTS RDS(on) = 14 m


NChannel D

G S 4 D2PAK CASE 418B STYLE 2

2 3

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

1 Gate T60N05HDL Y WW

2 Drain

3 Source

= Device Code = Year = Work Week

RJC RJA TL

1.0 62.5 260

C/W C

ORDERING INFORMATION
Device MTB60N05HD MTB60N05HDT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

885

November, 2000 Rev.2

Publication Order Number: MTB60N05HDL/D

MTB60N05HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 50 Vdc, VGS = 0 Vdc) (VDS = 50 Vdc, VGS = 0 Vdc, TJ = 25C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 30 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc) (ID = 60 Adc) (ID = 30 Adc, TJ = 125C) Forward Transconductance (VDS = 4.0 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge g (VDS = 40 Vdc, ID = 60 Adc, VGS = 5.0 Vdc) (VDD = 25 Vdc, ID = 60 Adc, VGS = 5.0 Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 60 Adc, VGS = 0 Vdc) (IS = 60 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 30 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.95 0.85 50 34 15 0.085 1.1 C ns Vdc 21 570 86 200 42 8.0 24 17 40 1150 170 400 62 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2775 750 150 4000 1070 300 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 15 48 1.0 0.75 mhos 0.010 0.014 Vdc 1.5 4.5 2.0 Vdc mV/C Ohms V(BR)DSS 50 IDSS IGSS 100 10 100 nAdc 55 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery y Time

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886

MTB60N05HDL
TYPICAL ELECTRICAL CHARACTERISTICS
120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 120 100 80 60 40 20 0 1.5 2.0 2.5

VGS = 10 V

4.5 V 8.0 V 6.0 V 5.0 V

4.0 V

TJ = 25C ID , DRAIN CURRENT (AMPS)

VDS 10 V

ID , DRAIN CURRENT (AMPS)

3.5 V

3.0 V 2.5 V 4.0 4.5 5.0

TJ = 125C -55C 3.0

25C

3.5

4.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.018 0.016 0.014 0.012 25C 0.010 0.008 0.006 0 10 20 30 40 0.014 0.013 0.012 0.011 0.010 0.009 0.008 0.007 0.006 0

Figure 2. Transfer Characteristics

TJ = 25C

TJ = 100C

VGS = 5.0 V

10 V

-55C 50 60 70 80 90 100 110 120

20

40

60

80

100

120

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 -25 0 25 50 75 100 125 150 VGS = 10 V ID = 5.0 A

10,000 VGS = 0 V IDSS, LEAKAGE (nA) 1000 TJ = 125C 100C 100

10 25C 1.0 5.0 10 15 20 25 30 35 40 45 50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MTB60N05HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
10,000 9000 8000 C, CAPACITANCE (pF) 7000 6000 5000 4000 3000 2000 1000 0 -10 Crss -5.0 0 VGS 5.0 VDS 10 Coss 15 20 25 Ciss Crss Ciss VDS = 0 VGS = 0

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTB60N05HDL
V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8.0 VGS 60 50 40 4.0 Q1 2.0 Q3 VDS 0 10 20 30 40 50 QG, TOTAL GATE CHARGE (nC) Q2 TJ = 60C ID = 5.0 A 30 20 10 0 1000 VDD = 25 V ID = 60 A VGS = 5.0 V TJ = 25C t, TIME (ns) tr tf td(off)

6.0

QT

100

td(on)

10

1.0

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
60 I S, SOURCE CURRENT (AMPS) 50 40 30 20 10 0 0.5 0.6 0.7 0.8 0.9 1.0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MTB60N05HDL
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

I D, DRAIN CURRENT (AMPS)

VGS = 5.0 V SINGLE PULSE TC = 25C

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

1000

600 500 400 300 200 100 0 25 50 75 100 125 150 175 ID = 60 A

100 1.0 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) dc

10

1.0

100

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MTB60N05HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.00001 0.0001 0.001 0.01 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 0.1 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0 10

0.01

Figure 14. Thermal Response

3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. Diode Reverse Recovery Waveform

Figure 16. D2PAK Power Derating Curve

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MTB60N05HDL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
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MTB60N05HDL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 18. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB60N05HDL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 19. Typical Solder Heating Profile

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MTB60N06HD
Preferred Device

Power MOSFET 60 Amps, 60 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not Sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 30 60 42.3 180 125 1.0 2.5 55 to 150 540 Unit Vdc Vdc 1 Vdc Vpk Adc Apk Watts W/C Watts C mJ T60N06HD YWW 2 3 4 D2PAK CASE 418B STYLE 2

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60 AMPERES 60 VOLTS RDS(on) = 14 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TJ, Tstg EAS

1 Gate

2 Drain

3 Source

C/W RJC RJA RJA TL 1.0 62.5 50 260 C

T60N06HD = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device MTB60N06HD MTB60N06HDT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

1. When mounted with the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

895

November, 2000 Rev.3

Publication Order Number: MTB60N06HD/D

MTB60N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 30 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 60 Adc) (ID = 30 Adc, TJ =125C) Forward Transconductance (VDS = 4.0 Vdc, ID = 30 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 60 Adc, VGS = 10 Vdc) (VDD= 30 Vdc, ID = 60 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 60 Adc, VGS = 0 Vdc) (IS = 60 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 60 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 4.5 7.5 nH nH ta tb QRR 0.99 0.89 60 36 24 0.143 1.0 C ns Vdc 14 197 50 124 51 12 24 21 26 394 102 246 71 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) (Cpk 3.0) (Note 4.) (Cpk 2.0) (Note 4.) V(BR)DSS 60 IDSS IGSS 100 10 100 nAdc 71 Vdc mV/C Adc Symbol Min Typ Max Unit

VGS(th) 2.0 3.0 7.0 0.011 20 1950 660 147 4.0 0.014

Vdc mV/C Ohm Vdc 1.0 0.9 mhos 15 2800 920 300 pF

(Cpk 3.0) (Note 4.)

RDS(on) VDS(on)

gFS

Ciss Coss Crss

Reverse Recovery Time (S Figure (See Fi 15)

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MTB60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
120 VGS = 10 V I D , DRAIN CURRENT (AMPS) 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 5V 120 I D , DRAIN CURRENT (AMPS) 100 80 60 40 100C 20 4.0 4.5 5.0 0 2.0 2.8 3.6 4.4 5.2 25C TJ = -55C 6.0 6.8 7.6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS 10 V

8V 9V

7V TJ = 25C

6V

3.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.020 VGS = 10 V TJ = 100C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.0132 0.0128 0.0124 0.0120 0.0116 0.0112 0.0108 0.0104 0.0100 0 10

Figure 2. Transfer Characteristics

0.018 0.016

TJ = 25C

0.014 0.012 25C

VGS = 10 V

0.010 0.008 0.006 0 10 20 30 40 -55C 50 60 70 80 90 100 110 120

15 V

20

30

40

50

60

70

80

90

100 110 120

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 -25 0 25 50 75 100 125 150 1 0 VGS = 10 V ID = 30 A I DSS, LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C

100C 10 25C

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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MTB60N06HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
5000 4000 C, CAPACITANCE (pF) 3000 Crss 2000 1000 0 10 Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 0 8 ID = 60 A TJ = 25C Q3 16 24 32 40 VDS 48 QT, TOTAL GATE CHARGE (nC) VGS Q1 Q2 50 40 30 20 10 0 56 60 1000 VDD = 30 V ID = 60 A VGS = 10 V TJ = 25C

tr tf td(off)

t, TIME (ns)

100

10

td(on) 1 10 RG, GATE RESISTANCE (Ohms) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
60 I S , SOURCE CURRENT (AMPS) 50 40 30 20 10 0 0.5 0.6 0.7 0.8 0.9 1.0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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899

MTB60N06HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

I D , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TC = 25C 10 s

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

1000

600 500 400 300 200 100 0 25 50 75 100 125 150 ID = 60 A

100

100 s 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 1 ms 10 ms dc 10 100

1 0.1

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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900

MTB60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00

1.0E+01

Figure 14. Thermal Response

3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. Diode Reverse Recovery Waveform

Figure 16. D2PAK Power Derating Curve

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901

MTB60N06HD INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 0 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
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MTB60N06HD
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 18. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB60N06HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 19. Typical Solder Heating Profile

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904

MTB75N03HDL
Preferred Device

Power MOSFET 75 Amps, 25 Volts, Logic Level


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 25 25 15 20 75 59 225 125 1.0 2.5 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 1 Gate T75N03HDL Y WW 2 Drain 3 Source 1 2 3

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75 AMPERES 25 VOLTS RDS(on) = 9 m


NChannel D

G S 4 D2PAK CASE 418B STYLE 2

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

T75N03HDL YWW

55 to 150 EAS 280

C/W RJC RJA RJA TL 1.0 62.5 50 260 C

= Device Code = Year = Work Week

ORDERING INFORMATION
Device MTB75N03HDL MTB75N03HDLT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

1. When mounted with the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

905

November, 2000 Rev. 3

Publication Order Number: MTB75N03HDL/D

MTB75N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 37.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) Forward Transconductance (VDS = 3 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) (VDS= 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 75 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA ta tb QRR 0.97 0.87 58 27 30 0.088 1.1 C ns Vdc 24 493 60 149 61 14 33 27 48 986 120 300 122 28 66 54 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 4025 1353 307 5635 1894 430 pF (Cpk 3.0) (Note 4.) VGS(th) 1.0 (Cpk 2.0) (Note 4.) RDS(on) VDS(on) gFS 15 55 0.68 0.6 mhos 6.0 9.0 Vdc 1.5 2.0 mV/C m Vdc (Cpk 2.0) (Note 4.) V(BR)DSS 25 IDSS IGSS 100 500 100 nAdc mV/C Adc Vdc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTB75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
150 I D , DRAIN CURRENT (AMPS) 120 90 3.5 V 60 30 0 3V 2.5 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1.8 2 150 I D , DRAIN CURRENT (AMPS) 120 90 60 30 0 1.5 100C 25C TJ = -55C 2 2.5 3 3.5 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 4.5

VGS = 10 V 8V 6V

5V

4.5 V TJ = 25C 4V

VDS 10 V

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.01 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

VGS = 5 V TJ = 100C

0.009 TJ = 25C 0.008 0.007 0.006 10 V 0.005 0.004

0.008

0.006

25C

VGS = 5 V

0.004

-55C

0.002

30

60

90

120

150

25

ID, DRAIN CURRENT (AMPS)

75 50 100 ID, DRAIN CURRENT (AMPS)

125

150

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2 1.6 1.2 0.8 0.4 0 VGS = 10 V ID = 37.5 A

10000

TJ = 125C 100C

I DSS , LEAKAGE (nA)

1000

100

10 25C 1 VGS = 0 V 0 5 10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30

-50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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907

MTB75N03HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
15000 12000 C, CAPACITANCE (pF) 9000 6000 3000 0 10 Crss Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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908

MTB75N03HDL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 7 6 5 4 3 2 1 0 Q3 0 10 TJ = 25C ID = 75 A VDS 50 20 30 40 QT, TOTAL GATE CHARGE (nC) 60 Q1 QT Q2 VGS 28 24 20 16 12 8 4 0 70 10000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 75 A VDD = 15 V VGS = 5 V

t, TIME (ns)

1000

tr

100

tf td(off) td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
75 60 45 30 15 0 0.5 TJ = 25C VGS = 0 V

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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909

MTB75N03HDL
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

1000 I D , DRAIN CURRENT (AMPS)

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C

280 240 200 160 120 80 40 0 25 50 75 100 125 150 ID = 75 A

100 100 s 10 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 dc

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

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910

MTB75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

0.01 1.0E-05

Figure 13. Thermal Response

3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 14. Diode Reverse Recovery Waveform

Figure 15. D2PAK Power Derating Curve

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911

MTB75N03HDL INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 16. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
912

MTB75N03HDL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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913

MTB75N03HDL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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914

MTB75N05HD
Preferred Device

Power MOSFET 75 Amps, 50 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not Sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (minimum footprint, FR4 board) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (minimum footprint, FR4 board) Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD Value 50 50 20 75 65 225 125 1.0 2.5 55 to 150 500 Amps Unit Volts 1 2 3 4 D2PAK CASE 418B STYLE 2

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75 AMPERES 50 VOLTS RDS(on) = 9.5 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

Watts W/C Watts C mJ 1 Gate C/W

TJ, Tstg EAS

MTB75N05HD YWW

2 Drain

3 Source

RJC RJA RJA TL

1.0 62.5 50 260 C

MTB75N05HD = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
Device MTB75N05HD MTB75N05HDT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

915

November, 2000 Rev.4

Publication Order Number: MTB75N05HD/D

MTB75N05HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) (VDS = 50 V, VGS = 0, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (Note 3.) (VGS = 10 Vdc, ID = 20 Adc) DraintoSource OnVoltage (VGS = 10 Vdc) (Note 3.) (ID = 75 A) (ID = 20 Adc, TJ = 125C) Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS (Note 2.) Input Capacitance Output Capacitance Transfer Capacitance V VGS = 0 0) (VDS = 25 V, 0, (Cpk 2 2.0) f = 1.0 MHz) ) (C ( pk ) k 2.0) (Cpk 2.0) ) (Cpk 1.5) (Note 2.) VGS(th) 2.0 (Cpk 3.0) (Note 2.) RDS(on) VDS(on) gFS Ciss Coss Crss td(on) (VDD = 25 V, ID = 75 A, VGS = 10 V V, RG = 9.1 ) tr td(off) tf QT (VDS = 40 V, ID = 75 A, VGS = 10 V) Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 75 A, VGS = 0) (Cpk 10) (IS = 20 A, VGS = 0) (IS = 20 A, VGS = 0, TJ = 125C) VSD trr (IS = 37.5 A, VGS = 0, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. 2. 3. 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Reflects Typical Values. Cpk = Absolute Value of (SPEC AVG) / 3 * SIGMA). For accurate measurements, good Kelvin contact required. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH ta tb QRR 0.97 0.80 0.68 57 40 17 0.17 1.00 C Vdc 15 0.63 2600 1000 230 15 170 70 100 71 13 33 26 0.34 3900 1300 300 30 340 140 200 100 nC ns mhos pF 7.0 9.5 Vdc 6.3 4.0 Vdc mV/C m (Cpk 2) (Note 2.) V(BR)DSS 50 IDSS IGSS 100 10 100 nAdc 54.9 Vdc mV/C Adc Symbol Min Typ Max Unit

SWITCHING CHARACTERISTICS (Note 4.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge

Reverse Recovery Time

ns

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916

MTB75N05HD
TYPICAL ELECTRICAL CHARACTERISTICS (Note 5.)
160 140 I D , DRAIN CURRENT (AMPS) 120 100 80 60 40 20 0 0 0.5 1 1.5 2 5V 2.5 3 3.5 4 4.5 5 6V 160 140 I D , DRAIN CURRENT (AMPS) 120 100 80 60 40 20 0 0 1 2 3 4 5 100C TJ = -55C 25C 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V

7V

TJ = 25C

VDS 10 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.014 0.012 0.01 0.008 0.006 0.004 0.002 25C -55C 0.009

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

TJ = 25C VGS = 10 V

0.008

0.007 15 V 0.006

20

40

60

80

100

120

140

0.005

20

40

60

80

100

120

140

160

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 10 V ID = 37.5 A

VGS = 0 V 1000 TJ = 125C

I DSS, LEAKAGE (nA)

1.5

100

100C

0.5

10 25C

0 -50

-25

25

50

75

100

125

150

10

15

20

25

30

35

40

45

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature


5. Pulse Tests: Pulse Width 250 s, Duty Cycle 2%.

Figure 6. DrainToSource Leakage Current versus Voltage

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917

MTB75N05HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in a RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS 0 VDS 5 Crss Ciss Coss Crss 10 15 20 25

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with boardmounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VDS = 0 Ciss

VGS = 0

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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918

MTB75N05HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 25 50 QG, TOTAL GATE CHARGE (nC) VDS Q1 Q2 TJ = 25C ID = 75 A QT VGS 60 50 40 30 20 10 0 75 1000 TJ = 25C ID = 75 A VDD = 35 V VGS = 10 V VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

tf tr td(off) td(on)

100 t, TIME (ns)

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
TJ = 25C 70 VGS = 0 V I S , SOURCE CURRENT (AMPS) 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 80

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
40 I S , SOURCE CURRENT (AMPS) 30 20 10 0 -10 -20 -30 -40 -120 -100 -80 -60 -40 -20 0 t, TIME (ns) 20 40 60 80

di/dt = 300 A/s

STANDARD CELL DENSITY trr HIGH CELL DENSITY trr tb ta

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

Figure 11. Reverse Recovery Time (trr)

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919

MTB75N05HD
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

1000 I D , DRAIN CURRENT (AMPS)

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

100

VGS = 20 V SINGLE PULSE TC = 25C

500 10 s 450 400 350 300 250 200 150 100 50 0 25

ID = 75 A

10

100 s

1 ms

10 ms dc

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

0.1 0.1

1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 t1 P(pk) RJC(t) = r(t) RJC RJC = 1.0C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E-01

1.0E+00

1.0E+01

Figure 14. Thermal Response http://onsemi.com


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MTB75N05HD
3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25 50 75 100 125 150
RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

TA, AMBIENT TEMPERATURE (C)

Figure 15. D2PAK Power Derating Curve

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921

MTB75N06HD
Preferred Device

Power MOSFET 75 Amps, 60 Volts


NChannel D2PAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured Not Sheared Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note NO TAG) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note NO TAG) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 30 75 50 225 125 1.0 2.5 Unit Vdc Vdc 1 Vdc Vpk Adc Apk Watts W/C Watts C mJ T75N06HD YWW 2 3 4 D2PAK CASE 418B STYLE 2

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75 AMPERES 60 VOLTS RDS(on) = 10 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

55 to 150 EAS 500

1 Gate

2 Drain

3 Source

RJC RJA RJA TL

1.0 62.5 50 260

C/W

T75N06HD = Device Code Y = Year WW = Work Week

ORDERING INFORMATION
C Device MTB75N06HD MTB75N06HDT4 Package D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

922

November, 2000 Rev.2

Publication Order Number: MTB75N06HD/D

MTB75N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 37.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 37.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 75 Adc, VGS = 10 Vdc) (VDS = 30 Vdc, ID = 75 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 75 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 3.5 7.5 nH nH ta tb QRR 0.97 0.88 56 44 12 0.103 1.1 C ns Vdc 18 218 67 125 71 16.3 31 29.4 26 306 94 175 100 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2800 928 180 3920 1300 252 pF (Cpk 5.0) (Note 4.) VGS(th) 2.0 (Cpk 2.0) (Note 4.) RDS(on) VDS(on) gFS 15 0.7 0.53 32 0.9 0.8 mhos 8.3 10 Vdc 3.0 8.38 4.0 Vdc mV/C m (Cpk 2.0) (Note 4.) V(BR)DSS 60 IDSS IGSS 5.0 10 100 100 nAdc 68 60.4 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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923

MTB75N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
150 125 I D , DRAIN CURRENT (AMPS) 100 75 50 25 0 0 0.5 1 1.5 6V 150 I D , DRAIN CURRENT (AMPS) 125 100 75 50 100C 25 0 TJ = -55C 2 3 4 5 6 7 8

TJ = 25C 9V

VGS = 10 V

8V

VDS 10 V

7V

25C

5V 2

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.016 0.014 0.012 0.010

TJ = 25C VGS = 10 V

0.012 0.011 0.010 0.009 0.008 0.007 0.006 0

TJ = 25C

TJ = 100C

VGS = 10 V

25C 0.008 0.006 0.004 0 25 50 -55C 75 100 125 150

15 V

25

50

75

100

125

150

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1000 VGS = 10 V ID = 37.5 A 1.6 I DSS, LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.9

VGS = 0 V

TJ = 125C

1.3

100C

10 25C

0.7 -50

-25

25

50

75

100

125

150

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTB75N06HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
7000 6000 C, CAPACITANCE (pF) 5000 4000 3000 2000 1000 0 10 5 VGS 0 VDS 5 10 Crss 15 20 25 Crss Ciss VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Coss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 VGS 8 6 4 2 Q3 0 0 10 20 30 40 50 60 ID = 75 A TJ = 25C VDS 70 QT, TOTAL GATE CHARGE (nC) Q1 Q2 40 30 20 10 0 80 QT 60 50 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 75 A VGS = 10 V TJ = 25C

tr tf td(off)

t, TIME (ns)

100

10

td(on) 1 10 RG, GATE RESISTANCE (Ohms) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
75 I S , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C 50

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

25

0 0.5

0.58

0.66

0.74

0.82

0.9

0.98

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MTB75N06HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
1000 VGS = 20 V SINGLE PULSE TC = 25C

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

500 ID = 75 A 375

I D , DRAIN CURRENT (AMPS)

100

10 s 100 s

250

10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1 ms 10 ms dc 100

125

1 0.1

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MTB75N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 14. Thermal Response

3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25

RJA = 50C/W Board material = 0.065 mil FR4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils

di/dt IS trr ta tp IS tb TIME 0.25 IS

50

75

100

125

150

TA, AMBIENT TEMPERATURE (C)

Figure 15. Diode Reverse Recovery Waveform

Figure 16. D2PAK Power Derating Curve

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MTB75N06HD INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

0.42 10.66

0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02

0.24 6.096

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 2.5 Watts 50C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts

The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 17.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts

TA = 25C

4 6 8 10 A, AREA (SQUARE INCHES)

12

14

16

Figure 17. Thermal Resistance versus Drain Pad Area for the D2PAK Package (Typical) http://onsemi.com
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MTB75N06HD
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 18 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 18. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTB75N06HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 19 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 19. Typical Solder Heating Profile

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931

MTD1302 Advance Information Power MOSFET 20 Amps, 30 Volts


NChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters, and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode Is Characterized for Use In Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case JunctiontoAmbient JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5.0 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 30 30 20 20 20 16 60 74 0.592 1.75 55 to 150 200 Unit Vdc Vdc 4 Vdc Vpk Adc Apk Watts W/C Watts C mJ 1 2 3 Y WW T CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET YWW T 1302

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20 AMPERES 30 VOLTS RDS(on) = 22 m


NChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT
TJ, Tstg EAS 4 Drain

C/W RJC RJA RJA TL 1.67 100 71.4 260 C

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD1302 MTD13021 MTD1302T4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

Semiconductor Components Industries, LLC, 2000

932

November, 2000 Rev. 1

Publication Order Number: MTD1302/D

MTD1302
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) Forward Transconductance (VDS = 10 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) (VDD = 15 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 10 Vdc) QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.83 0.79 38 19 20 36 1.1 C ns Vdc 7.2 52 45 73 14.5 2.2 8.8 6.8 27 2.2 10 7.2 15 104 90 146 21.8 40.5 nC nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 755 370 102 1162 518 204 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 10 16 0.38 0.5 0.33 Mhos 0.019 0.026 0.022 0.029 Vdc 1.5 2.0 Ohms Vdc V(BR)DSS 30 IDSS IGSS 100 10 100 nAdc Adc Vdc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTD1302
TYPICAL ELECTRICAL CHARACTERISTICS
40 35 ID, DRAIN CURRENT (AMPS) 30 25 20 15 10 5.0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VGS = 3.0 V TJ = 25C 30 4.0 V ID, DRAIN CURRENT (AMPS) 25 20 15 10 5.0 -55C 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

10 V

5.0 V

VDS 10 V

TJ = 125C

25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on), DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) 0.03 VGS = 10 V TJ = 100C RDS(on), DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 10

Figure 2. Transfer Characteristics

TJ = 25C VGS = 4.5 V

0.02

25C

10 V

-55C 0.01

10

15

20

25

30

35

40

15

20

25

30

35

40

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus Drain Current and Temperature


3.0 1000 ID = 10 A 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

2.0

IDSS, LEAKAGE (nA)

TJ = 125C 100C 25C

VGS = 10 V 1.0

10

1.0

-50

-25

25

50

75

100

125

150

0.1

5.0

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTD1302
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2500 2000 C, CAPACITANCE (pF) 1500 1000 500 0 -10 VDS = 0 V VGS = 0 V -5.0 5.0 0 VGS VDS Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

Crss Ciss Coss Crss 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTD1302
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 14 12 10 8.0 6.0 4.0 2.0 0 Q1 Q2 ID = 20 A TJ = 25C VDS VGS QT 18 15 12 9.0 6.0 3.0 1000 VDD = 15 V ID = 20 A VGS = 10 V TJ = 25C

100

tf tr td(off) td(on)

10

Q3

0 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 22 24 26 28 30 QG, TOTAL GATE CHARGE (nC)

1.0

1.0

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 18 I S , SOURCE CURRENT (AMPS) 16 14 12 10 8.0 6.0 4.0 2.0 0 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


936

MTD1302
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

100 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10

200 100 ms 1.0 ms 10 ms dc ID = 20 A 150

100

1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100

50

0.1

25

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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937

MTD1302
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 t2 DUTY CYCLE, D = t1/t2 0.0001 0.001 0.01 t, TIME (s) 0.1 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.00001

1.0

10

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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938

MTD1302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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939

MTD1302
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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940

MTD1302
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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941

MTD15N06V
Preferred Device

Power MOSFET 15 Amps, 60 Volts


NChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Single Pulse (tp 50 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted to minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 15 8.7 45 55 0.36 2.1 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts 4 1 2 3 Y WW T CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET YWW T 15N06V G S

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15 AMPERES 60 VOLTS RDS(on) = 120 m


NChannel D

MARKING DIAGRAM

TJ, Tstg EAS

55 to 175 113

C mJ

PIN ASSIGNMENT
C/W RJC RJA RJA TL 2.73 100 71.4 260 C 4 Drain

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD15N06V MTD15N06V1 MTD15N06VT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

942

November, 2000 Rev. 3

Publication Order Number: MTD15N06V/D

MTD15N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 15 Adc) (ID = 7.5 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 15 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 15 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 15 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 1.05 1.5 59.3 46 13.3 0.165 1.6 C ns Vdc 7.6 51 18 33 14.4 2.8 6.4 6.1 20 100 40 70 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 469 148 35 660 200 60 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 4.0 2.0 6.2 2.2 1.9 mhos 2.7 5.0 0.08 4.0 0.12 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 67 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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943

MTD15N06V
TYPICAL ELECTRICAL CHARACTERISTICS
30 I D , DRAIN CURRENT (AMPS) 25 20 15 10 5 0 5V 6V TJ = 25C 30 I D , DRAIN CURRENT (AMPS) 25 20 15 10 5 0 VDS 10 V 25C

VGS = 10 V 9V

8V 7V

100C

TJ = -55C

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.20 R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

0.13

TJ = 25C

0.15

0.11

0.10

25C -55C

0.09

VGS = 10 V 15 V

0.05

0.07

10 15 20 ID, DRAIN CURRENT (AMPS)

25

30

0.05

10

15

20

25

30

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


100 VGS = 10 V ID = 7.5 A I DSS , LEAKAGE (nA) 1.6

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

1.2

TJ = 125C

0.8

0.4 -50

-25

25

50

75

100

125

150

175

10

TJ, JUNCTION TEMPERATURE (C)

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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944

MTD15N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1500 1200 C, CAPACITANCE (pF) 900 600 300 0 Ciss Coss Crss 10 5 VGS 0 VDS 5 10 15 20 25 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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945

MTD15N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 0 Q3 3 VDS 6 9 12 QT, TOTAL CHARGE (nC) Q1 Q2 QT VGS 60 50 40 30 20 10 0 15 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 15 A VGS = 10 V TJ = 25C tr tf

t, TIME (ns)

100

td(off) 10

ID = 15 A TJ = 25C

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


15 12 9 6 3 0 0.5 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.7

0.9

1.1

1.3

1.5

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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946

MTD15N06V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 120 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 s 100 80 60 40 20 0 ID = 15 A

VGS = 10 V SINGLE PULSE TC = 25C

10 100 s 1 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms dc

0.1

25

50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E-04

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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947

MTD15N06V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 2.1 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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948

MTD15N06V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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949

MTD15N06V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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950

MTD15N06VL Power MOSFET 15 Amps, 60 Volts


NChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 25 15 12 53 60 0.4 2.1 55 to 175 113 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 4 1 2 3 Y WW T CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET YWW T 15N06VL G S

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15 AMPERES 60 VOLTS RDS(on) = 85 m


NChannel D

MARKING DIAGRAM

TJ, Tstg EAS

C/W RJC RJA RJA TL 2.5 100 71.4 260 C

PIN ASSIGNMENT
4 Drain

1. When surface mounted to an FR4 board using the minimum recommended pad size.

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD15N06VL MTD15N06VL1 MTD15N06VLT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2000

951

November, 2000 Rev. 3

Publication Order Number: MTD15N06VL/D

MTD15N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 7.5 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc, ID = 15 Adc) (VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 15 Adc, VGS = 5.0 Vdc) (VDD = 30 Vdc, ID = 15 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 15 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 0.96 0.85 63 42 21 0.140 1.6 C ns Vdc 11 150 27 70 12 3.0 7.0 11 50 210 160 140 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) (Cpk 2.0) (Note 4.) VGS(th) 1.0 (Cpk 2.0) (Note 4.) RDS(on) VDS(on) gFS Ciss Coss Crss 8.0 10 570 180 45 1.5 1.3 880 380 110 mhos pF 0.075 0.085 Vdc 1.5 4.0 2.0 Vdc mV/C Ohm (Cpk 2.0) (Note 4.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 68 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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952

MTD15N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
50 45 I D , DRAIN CURRENT (AMPS) 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 50 7V I D , DRAIN CURRENT (AMPS) 6V 5V 45 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 100C VDS 5 V TJ = -55C 25C

TJ = 25C

VGS = 10V

9V

8V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0

VGS = 5 V

0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0

TJ = 100C 25C -55C

TJ = 25C

VGS = 5 V 10 V

15 25 10 20 ID, DRAIN CURRENT (AMPS)

30

35

10

15 25 20 30 35 ID, DRAIN CURRENT (AMPS)

40

45

50

Figure 3. OnResistance versus Drain Current and Temperature


2.0 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 0 0 I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 7.5 A

VGS = 0 V

TJ = 125C

10

100C

10

15

20

25

30

35

40

45

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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953

MTD15N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2200 VDS = 0 V 2000 Ciss 1800 C, CAPACITANCE (pF) 1600 1400 1200 Crss 1000 800 600 400 200 0 10 Crss 0 5 5 VGS VDS Ciss Coss 10 15 20 25 VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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954

MTD15N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 Q3 5 10 15 VDS 20 25 Qg, TOTAL GATE CHARGE (nC) TJ = 25C ID = 15 A 30 Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 35 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 15 A VDD = 30 V VGS = 5 V

t, TIME (ns)

100

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


15 14 TJ = 25C 13 VGS = 0 V 12 11 10 9 8 7 6 5 4 3 2 1 0 0.5 0.55 0.6

I S , SOURCE CURRENT (AMPS)

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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955

MTD15N06VL
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 120 110 100 90 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 175

10 s

10 100 s 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

0.1

E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 15 V SINGLE PULSE TC = 25C

ID = 15 A

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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956

MTD15N06VL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 2.1 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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957

MTD15N06VL
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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958

MTD15N06VL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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959

MTD20N03HDL
Preferred Device

Power MOSFET 20 Amps, 30 Volts, Logic Level


NChannel DPAK
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C, when mounted with the minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 30 30 15 20 20 16 60 74 0.6 1.75 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C 1 2 3 20N03HL Y WW T 4 CASE 369A DPAK STYLE 2 = Device Code = Year = Work Week = MOSFET

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20 AMPERES 30 VOLTS RDS(on) = 35 m


NChannel D

G S

MARKING DIAGRAM
YWW T 20N03HL

PIN ASSIGNMENT
TJ, Tstg EAS 55 to 150 200 C mJ 4 Drain

C/W RJC RJA RJA TL 1.67 100 71.4 260 C

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD20N03HDL MTD20N03HDL1 MTD20N03HDLT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

960

November, 2000 Rev. 3

Publication Order Number: MTD20N03HDL/D

MTD20N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 5.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 24 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) (VDD = 15 Vdc, ID = 20 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Cpk 2.0) (Note 3.) Reverse Recovery Time (S Figure (See Fi 15) (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk = Absolute Value of Spec (SpecAVG/3.516 A). LD LS 7.5 4.5 nH nH (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.95 0.87 33 23 10 33 1.1 C ns Vdc 13 212 23 84 13.4 3.0 7.3 6.0 20 238 40 140 18.9 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 880 300 80 1260 420 150 pF (Cpk 2.0) (Note 3.) VGS(th) 1.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 10 13 0.55 0.8 0.7 mhos 0.034 0.030 0.040 0.035 Vdc 1.5 5.0 2.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 30 IDSS IGSS 100 10 100 nAdc 43 Vdc mV/C Adc Symbol Min Typ Max Unit

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961

MTD20N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
40 40

TJ = 25C

VGS = 10 V 8V

5V 6V

4.5 V 4V I D , DRAIN CURRENT (AMPS)

VDS 10 V

I D , DRAIN CURRENT (AMPS)

30

30

20

3.5 V

20

10

3V 2.5 V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

10

100C

25C TJ = -55C 3.0 3.4 3.8 4.2 4.6 5.0

0 1.0

1.4

1.8

2.2

2.6

VGS, GATE-TO-SOURCE VOLTAGE (Volts)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.052 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.036

Figure 2. Transfer Characteristics

VGS = 5 V TJ = 100C

TJ = 25C VGS = 5 V

0.044

0.032

0.036 25C 0.028 -55C 0.020 0 8 16 24 32 40

0.028

0.024

10 V

0.020

16

24

32

40

ID, DRAIN CURRENT (Amps)

ID, DRAIN CURRENT (Amps)

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 1 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 10 A

VGS = 0 V

TJ = 125C

I DSS, LEAKAGE (nA)

100 100C

10 25C

-25

25

50

75

100

125

150

12

18

24

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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962

MTD20N03HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2800 2400 C, CAPACITANCE (pF) 2000 1600 1200 800 400 0 10 5 VGS 0 VDS Crss 5 10 Coss 15 20 25 Crss Ciss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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MTD20N03HDL
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 14 12 10 8 6 4 2 0 0 2 Q1 Q2 QT 28 24 20 VGS 16 12 8 ID = 20 A TJ = 25C 4 VDS 4 6 8 10 12 QG, TOTAL GATE CHARGE (nC) 0 14 1000 VDD = 15 V ID = 20 A VGS = 5.0 V TJ = 25C tr 100 tf

t, TIME (ns)

Q3

td(off) 10 td(on) 1 10 RG, GATE RESISTANCE (Ohms) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 I S , SOURCE CURRENT (AMPS) 16 12 8 4 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 VSD, SOURCE-TO-DRAIN VOLTAGE (Volts) VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

1.0

Figure 10. Diode Forward Voltage versus Current

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MTD20N03HDL
di/dt = 300 A/s Standard Cell Density trr High Cell Density trr tb ta

I S , SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TC = 25C 100 s

200 ID = 20 A 160 120 80 40 0

10

1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 dc

1 0.1

100

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MTD20N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E-04

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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MTD20N03HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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MTD20N03HDL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTD20N03HDL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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MTD20N06HD
Preferred Device

Power MOSFET 20 Amps, 60 Volts


NChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 30 20 16 60 40 0.32 1.75 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts Y WW T = Year = Work Week = MOSFET 1 2 3 S

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20 AMPERES 60 VOLTS RDS(on) = 45 m


NChannel D

MARKING DIAGRAM
4 YWW T 20N06HD

CASE 369A DPAK STYLE 2

PIN ASSIGNMENT
TJ, Tstg EAS 55 to 150 60 C mJ 4 Drain

C/W RJC RJA RJA TL 3.13 100 71.4 260 C

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD20N06HD MTD20N06HD1 MTD20N06HDT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

970

November, 2000 Rev. 3

Publication Order Number: MTD20N06HD/D

MTD20N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) DraintoSource OnVoltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 7) (VDS = 48 Vdc, ID = 20 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Cpk 8.0) (Note 3.) Reverse Recovery Time (S Figure (See Fi 14) (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk = Absolute Value of Spec (SpecAVG/3.516 A). LD LS 7.5 4.5 nH nH (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.95 0.88 35.7 24 11.7 0.055 1.0 C ns Vdc 9.2 61.2 19 36 17 3.4 7.75 7.46 18 122 38 72 24 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 607 218 55 840 290 110 pF (Cpk 2.0) (Note 3.) VGS(th) 2.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 5.0 6.0 1.2 1.1 mhos 0.035 0.045 Vdc 7.0 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 100 10 100 nAdc 54 Vdc mV/C Adc Symbol Min Typ Max Unit

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MTD20N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
40 VGS = 10 V I D , DRAIN CURRENT (AMPS) 32 24 6V 16 8 0 40 7V I D , DRAIN CURRENT (AMPS) 30

9V 8V

VDS 10 V

TJ = 25C

20

5V

10 100C 0 25C TJ = -55C 2 3 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (Volts)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.052 0.048 0.044 0.040 0.036 0.032 0.028 0.024 0.020 0 10 -55C 25C 0.040 0.038 0.036 0.034 0.032 0.030 0.028 0

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

TJ = 25C VGS = 10 V

15 V

20 ID, DRAIN CURRENT (Amps)

30

40

10

20 ID, DRAIN CURRENT (Amps)

30

40

Figure 3. OnResistance versus Drain Current and Temperature


1.6 1.4 1.2 1.0 0.8 0.6 -50 VGS = 10 V ID = 10 A

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

-25

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

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MTD20N06HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1600 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Crss Ciss Coss Crss 15 20 25 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 6. Capacitance Variation

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MTD20N06HD
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 0 2 ID = 20 A TJ = 25C VGS Q1 Q2 50 40 30 20 10 VDS 6 8 10 12 14 16 QG, TOTAL GATE CHARGE (nC) 0 18 60 1000 VDD = 30 V ID = 20 A VGS = 10 V TJ = 25C

100 t, TIME (ns)

tr tf td(off) td(on)

10

Q3 4

10 RG, GATE RESISTANCE (Ohms)

100

Figure 7. GateToSource and DrainToSource Voltage versus Total Charge

Figure 8. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 18 I S , SOURCE CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0.50 0.58 0.66 0.74 0.82 0.90 0.98 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (Volts)

Figure 9. Diode Forward Voltage versus Current

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MTD20N06HD
di/dt = 300 A/s Standard Cell Density trr High Cell Density trr tb ta

I S , SOURCE CURRENT

t, TIME

Figure 10. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

60 50 40 30 20 10 0 25 50 75 100 125 150 ID = 20 A

10 s

10

1.0

0.1 0.1

1.0

10

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

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975

MTD20N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E-04

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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976

MTD20N06HD INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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977

MTD20N06HD
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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978

MTD20N06HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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979

MTD20N06HDL
Preferred Device

Power MOSFET 20 Amps, 60 Volts, Logic Level


NChannel DPAK
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for lowvoltage, highspeed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 20 20 12 60 40 0.32 1.75 55 to 150 200 1 Gate C/W RJC RJA RJA TL 3.13 100 71.4 260 C 2 Drain 3 Source Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 1 2 3 Y WW T 4 CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET

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20 AMPERES 60 VOLTS RDS(on) = 45 m


NChannel D

G S

MARKING DIAGRAM
YWW T 20N06HL

PIN ASSIGNMENT
4 Drain

TJ, Tstg EAS

ORDERING INFORMATION
Device MTD20N06HDL MTD20N06HDL1 MTD20N06HDLT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

980

November, 2000 Rev. 2

Publication Order Number: MTD20N06HDL/D

MTD20N06HDL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) DrainSource OnVoltage (VGS = 5.0 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) (VDS = 30 Vdc, ID = 20 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 20 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 4.5 nH nH ta tb QRR 0.95 0.88 22 12 34 0.049 1.1 C ns Vdc 11 151 34 75 14.6 3.25 7.75 7.0 15 190 35 98 22 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 863 216 53 1232 300 73 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 6.0 0.76 12 1.2 1.1 mhos 0.045 0.037 0.070 0.045 Vdc 1.5 6.0 2.0 Vdc mV/C Ohm V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 25 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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981

MTD20N06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
40 I D , DRAIN CURRENT (AMPS) 40 4V

TJ = 25C

I D , DRAIN CURRENT (AMPS)

30

8V 6V 5V 4.5 V

VGS = 10 V

VDS 10 V

30

20

3.5 V

20 100C 25C 0 1.5 TJ = -55C 2 2.5 3 3.5 4 4.5 VGS, GATE-TO-SOURCE VOLTAGE (Volts)

10

3V 2.5 V

10

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 10 20 ID, DRAIN CURRENT (Amps) 30 40 25C -55C VGS = 5 V TJ = 100C 0.05 0.045 0.04 0.035 0.03 0.025

Figure 2. Transfer Characteristics

TJ = 25C

5V

VGS = 10 V

10

20 ID, DRAIN CURRENT (Amps)

30

40

Figure 3. OnResistance versus Drain Current and Temperature


1.6 1.4 1.2 1.0 0.8 0.6 -50 1 VGS = 5 V ID = 10 A

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1000

VGS = 0 V

I DSS , LEAKAGE (nA)

100

TJ = 125C 100C

10

25C

-25

25

50

75

100

125

150

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DraintoSource Leakage Current versus Voltage

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982

MTD20N06HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
3000 2500 Ciss C, CAPACITANCE (pF) 2000 1500 C rss 1000 500 0 10 5 VGS 0 VDS Coss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss 5

10

15

20

25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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983

MTD20N06HDL
QT VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 Q1 4 2 0 0 2 Q3 4 6 8 10 12 14 Q2 ID = 20 A TJ = 25C VDS VGS 60 50 40 30 20 10 0 16 1000 VDD = 30 V ID = 20 A VGS = 5 V TJ = 25C

100 t, TIME (ns)

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (Ohms)

100

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 I S , SOURCE CURRENT (AMPS) 16 12 8 4 0 0.5 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.55

0.6

0.65

0.7

0.75

0.8

0.9

0.95

VSD, SOURCE-TO-DRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current

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984

MTD20N06HDL
di/dt = 300 A/s Standard Cell Density trr High Cell Density trr tb ta

I S , SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TC = 25C

200 ID = 20 A 150

10 s

100 s 10 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 dc 10 100

100

50

1.0 0.1

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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985

MTD20N06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 t2 DUTY CYCLE, D = t1/t2 0.001 0.01 t, TIME (s) 0.1 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.0001

1.0

10

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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986

MTD20N06HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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987

MTD20N06HDL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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988

MTD20N06HDL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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989

MTD20P03HDL
Preferred Device

Power MOSFET 20 Amps, 30 Volts, Logic Level


PChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
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20 AMPERES 30 VOLTS RDS(on) = 99 m


PChannel D

Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete


Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature

G S Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 3 20P03HL Y WW T 4 CASE 369A DPAK STYLE 2 = Device Code = Year = Work Week = MOSFET

MAXIMUM RATINGS (TC = 25C unless otherwise noted)


Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tpv10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 19 Apk, L = 1.1 mH, RG = 25 ) Thermal Resistance JunctiontoCase JunctiontoAmbient JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 30 30 "15 "20 19 12 57 75 0.6 1.75 55 to 150 200

MARKING DIAGRAM

YWW T 20P03HL

TJ, Tstg EAS

PIN ASSIGNMENT
4 Drain

C/W RJC RJA RJA TL 1.67 100 71.4 260 C 1 Gate 2 Drain 3 Source

ORDERING INFORMATION
Device MTD20P03HDL MTD20P03HDL1 MTD20P03HDLT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

990

November, 2000 Rev. 4

Publication Order Number: MTD20P03HDL/D

MTD20P03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 9.5 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc) (ID = 19 Adc) (ID = 9.5 Adc, TJ = 125C) Forward Transconductance (VDS = 8.0 Vdc, ID = 9.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure Fi 8) (See (VDS = 24 Vdc, ID =19 19 Adc, VGS = 5.0 Vdc) (VDD = 15 Vdc, ID = 19 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 1.3 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Cpk 2.0) (Note 4.) Reverse Recovery Time (S Figure (See Fi 15) (IS = 19 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Cpk = Absolute Value of Spec (SpecAVG/3.516 A). LD LS 7.5 4.5 nH nH (IS = 19 Adc, VGS = 0 Vdc) (IS = 19 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 3.1 2.56 78 50 28 0.209 3.4 C ns Vdc 18 178 21 72 15 3.0 11 8.2 25.2 246.4 26.6 98 22.4 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 770 360 130 1064 504 182 pF (Cpk 2.0) (Note 4.) VGS(th) 1.0 (Cpk 2.0) (Note 4.) RDS(on) VDS(on) gFS 5.0 0.94 6.0 2.2 1.9 mhos 120 90 99 Vdc 1.5 4.0 2.0 Vdc mV/C m (Cpk 2.0) (Note 4.) V(BR)DSS 30 IDSS IGSS 10 100 100 nAdc 15 Vdc mV/C Adc Symbol Min Typ Max Unit

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991

MTD20P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
40 32 24 16 8 0 40 5V 4.5 V 4V 3.5 V 3V 2.5 V 0 1 2 3 4 5 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ = 25C

VGS = 10 V 8V

6V I D , DRAIN CURRENT (AMPS)

VDS 5 V

TJ = -55C 25C 100C

I D , DRAIN CURRENT (AMPS)

32 24 16 8 0 1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.16 0.14 0.12 0.10 0.08 0.06 TJ = 100C 0.16 0.14 0.12 0.10 0.08 0.06

Figure 2. Transfer Characteristics

VGS = 5 V

TJ = 25C

25C -55C

VGS = 5 V

10 V 0 4 8 12 16 20 24 28 32 36 40 ID, DRAIN CURRENT (AMPS)

12

16

20

24

28

32

36

40

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1.3 1.2 1.1 1.0 0.9 0.8 -50 1 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 10 A

VGS = 0 V

TJ = 125C

I DSS, LEAKAGE (nA)

10

100C

-25

25

50

75

100

125

150

12

16

20

24

28

32

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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992

MTD20P03HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2800 2400 C, CAPACITANCE (pF) 2000 1600 1200 C rss 800 400 0 10 5 VGS 0 VDS 5 10 Ciss Coss Crss 15 20 25 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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993

MTD20P03HDL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 7 6 5 4 3 2 1 0 0 2 Q3 4 6 8 10 12 ID = 19 A TJ = 25C VDS 14 QG, TOTAL GATE CHARGE (nC) Q1 QT Q2 VGS 35 30 25 20 15 10 5 0 16 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 15 V ID = 19 A VGS = 5.0 V TJ = 25C

tr

t, TIME (ns)

100

tf td(off) td(on) 1 RG, GATE RESISTANCE (OHMS) 10

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 I S , SOURCE CURRENT (AMPS) 16 12 8 4 0 0.3 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.7

1.1

1.5

1.9

2.3

2.7

3.1

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


994

MTD20P03HDL
di/dt = 300 A/s Standard Cell Density trr High Cell Density trr tb ta

I S , SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 VGS = 20 V SINGLE PULSE TC = 25C

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
200 ID = 19 A 160 120 80 40 0

I D , DRAIN CURRENT (AMPS)

100 s 1 ms 10 ms dc

10

1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1.0 10 100

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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995

MTD20P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E-04

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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996

MTD20P03HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C 71.4C/W = 1.75 Watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20

4 6 A, AREA (SQUARE INCHES)

10

Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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997

MTD20P03HDL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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998

MTD20P03HDL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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999

MTD20P06HDL
Preferred Device

Power MOSFET 20 Amps, 60 Volts, Logic Level


PChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for lowvoltage, highspeed switching applications in power supplies, converters and PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. Ultra Low RDS(on), HighCell Density, HDTMOS Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Avalanche Energy Specified
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tpv10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tpv10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 15 Apk, L = 2.7 mH, RG = 25 ) Thermal Resistance JunctiontoCase JunctiontoAmbient JunctiontoAmbient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 "15 "20 15 9.0 45 72 0.58 1.75 55 to 150 300 Unit Vdc Vdc Vdc Vpk 4 Adc Apk Watts W/C Watts C mJ 1 2 3 20P06HL Y WW T CASE 369A DPAK STYLE 2 = Device Code = Year = Work Week = MOSFET

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20 AMPERES 60 VOLTS RDS(on) = 175 m


PChannel D

G S

MARKING DIAGRAM
YWW T 20P06HL

TJ, Tstg EAS

PIN ASSIGNMENT
4 Drain

C/W RJC RJA RJA TL 1.73 100 71.4 260 C 1 Gate 2 Drain 3 Source

1. When surface mounted to an FR4 board using the minimum recommended pad size.

ORDERING INFORMATION
Device MTD20P06HDL MTD20P06HDLT4 Package DPAK DPAK Shipping 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1000

November, 2000 Rev. 3

Publication Order Number: MTD20P06HDL/D

MTD20P06HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 7.5 Adc) DrainSource OnVoltage (VGS = 5.0 Vdc) (ID = 15 Adc) (ID = 7.5 Adc, TJ = 125C) Forward Transconductance (VDS = 10 Vdc, ID = 7.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 15 Adc, VGS = 5.0 Vdc) (VDS = 30 Vdc, ID = 15 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 15 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 2.5 1.9 64 50 14 0.177 3.0 C ns Vdc 19 175 41 68 20.6 3.7 7.6 8.4 38 350 82 136 29 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 850 210 66 1190 290 130 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 9.0 2.3 1.6 11 3.0 2.0 mhos 1.7 3.9 143 2.0 175 Vdc mV/C m Vdc V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc 81.3 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1001

MTD20P06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
30 25 I D , DRAIN CURRENT (AMPS) 20 15 10 5V 5 0 0 1 2 3 4 5 6 7 8 9 4V 10 30 8V I D , DRAIN CURRENT (AMPS) 7V 25 20 15 10 5 0 1 2 3 4 5 6 100C

TJ = 25C

VGS = 10 V

9V

VDS 5 V TJ = -55C 25C

6V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.40 0.32 0.24 TJ = 100C 0.16 0.08 0 25C -55C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.275 0.250 0.225 0.200 0.175 0.150 0.125 0.100 0

Figure 2. Transfer Characteristics

VGS = 5 V

TJ = 25C

VGS = 5 V 10 V 5 10 15 20 25 30

10

15

20

25

30

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


100

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50

VGS = 5 V ID = 7.5 A

VGS = 0 V

I DSS, LEAKAGE (nA)

TJ = 125C 10 100C

-25

25

50

75

100

125

150

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1002

MTD20P06HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2500 2000 C, CAPACITANCE (pF) 1500 1000 500 Crss 0 10 5 VGS 0 VDS 5 10 Crss Ciss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Coss 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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1003

MTD20P06HDL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 QT 5 4 VDS 3 Q1 2 1 0 0 Q3 4 8 12 16 20 Q2 VGS ID = 15 A TJ = 25C 50 45 40 35 30 25 20 15 10 5 0 24 1000 VDD = 30 V ID = 15 A VGS = 5.0 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100 t, TIME (ns)

tr tf td(off) td(on)

10

10 RG, GATE RESISTANCE (Ohms)

100

QG, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
15 I S , SOURCE CURRENT (AMPS) 12 9 6 3 0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.5

0.75

1.25

1.5

1.75

2.25

2.5

VSD, SOURCE-TO-DRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


1004

MTD20P06HDL
di/dt = 300 A/s Standard Cell Density trr High Cell Density trr tb ta

I S , SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms 10 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) dc

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
300 ID = 15 A 240 180 120 60 0

10

0.1 0.1

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1005

MTD20P06HDL
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1006

MTD20P06HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C 71.4C/W = 1.75 Watts

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 16.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20

4 6 A, AREA (SQUARE INCHES)

10

Figure 16. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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1007

MTD20P06HDL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 17 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 17. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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1008

MTD20P06HDL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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1009

MTD2955V Power MOSFET 12 Amps, 60 Volts


PChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 12 8.0 42 60 0.4 2.1 55 to 175 216 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 4 1 2 3 Y WW T CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET YWW T 2955V G S

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12 AMPERES 60 VOLTS RDS(on) = 230 m


PChannel D

MARKING DIAGRAM

TJ, Tstg EAS

C/W RJC RJA RJA TL 2.5 100 71.4 260 C

PIN ASSIGNMENT
4 Drain

1. When surface mounted to an FR4 board using the minimum recommended pad size.

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD2955V MTD2955V1 MTD2955VT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Semiconductor Components Industries, LLC, 2000

1010

November, 2000 Rev. 4

Publication Order Number: MTD2955V/D

MTD2955V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 12 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.8 1.5 115 90 25 0.53 3.0 C ns Vdc 15 50 24 39 19 4.0 9.0 7.0 30 100 50 80 30 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) (Cpk 2.0) (Note 4.) VGS(th) 2.0 (Cpk 1.5) (Note 4.) RDS(on) VDS(on) gFS Ciss Coss Crss 3.0 5.0 550 200 50 2.9 2.5 770 280 100 mhos pF 0.185 0.230 Vdc 2.8 5.0 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 4.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 58 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1011

MTD2955V
TYPICAL ELECTRICAL CHARACTERISTICS
25 I D , DRAIN CURRENT (AMPS) 20 15 10 5 0 7V 24 9V 8V I D , DRAIN CURRENT (AMPS) 21 18 15 12 9 6 3 10 0 2 3 4 5 6 7 8 9 10

TJ = 25C

VGS = 10 V

VDS 10 V

TJ = -55C 25C

100C

6V

5V 0 1 2 3 4 5 6 7 8 9

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.250

Figure 2. Transfer Characteristics

0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 3 6 9 15 18 12 ID, DRAIN CURRENT (AMPS) 21 24 25C -55C VGS = 10 V TJ = 100C

0.225 0.200 0.175

TJ = 25C VGS = 10 V

0.150 0.125 0.100 0.075 0.050 0 3 6

15 V

9 18 12 15 ID, DRAIN CURRENT (AMPS)

21

24

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 VGS = 10 V ID = 6 A I DSS , LEAKAGE (nA)

1000

VGS = 0 V

TJ = 125C 100 100C

10

10 20 30 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1012

MTD2955V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1800 1600 C, CAPACITANCE (pF) 1400 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Ciss Coss Crss 15 20 25 Ciss Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTD2955V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 2 Q3 4 6 8 10 12 14 VDS 16 18 QT, TOTAL CHARGE (nC) Q1 Q2 VGS QT 30 27 24 21 18 15 12 ID = 12 A 9 TJ = 25C 6 3 0 20 1000 VDD = 30 V ID = 12 A VGS = 10 V TJ = 25C tr tf td(off) td(on) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


12 11 I S , SOURCE CURRENT (AMPS) 10 9 8 7 6 5 4 3 2 1 0 0.5 VGS = 0 V TJ = 25C

0.7

0.9

1.1

1.3

1.5

1.7

1.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTD2955V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 225 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 200 175 150 125 100 75 50 25 0 25 50 75 100 125 150 175 ID = 12 A

VGS = 15 V SINGLE PULSE TC = 25C

10 100 s 1 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms dc

0.1

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1015

MTD2955V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 2.1 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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MTD2955V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTD2955V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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MTD3055V
Preferred Device

Power MOSFET 12 Amps, 60 Volts


NChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 20 25 12 7.3 37 48 0.32 1.75 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts 4 1 2 3 Y WW T CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET YWW T 3055V G S

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12 AMPERES 60 VOLTS RDS(on) = 150 m


NChannel D

MARKING DIAGRAM

TJ, Tstg EAS

55 to 175 72

C mJ

PIN ASSIGNMENT
C/W RJC RJA RJA TL 3.13 100 71.4 260 C 4 Drain

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD3055V MTD3055V1 MTD3055VT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1019

November, 2000 Rev. 3

Publication Order Number: MTD3055V/D

MTD3055V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 1.0 0.91 56 40 16 0.128 1.6 C ns Vdc 7.0 34 17 18 12.2 3.2 5.2 5.5 10 60 30 50 17 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 410 130 25 500 180 50 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 4.0 1.3 5.0 2.2 1.9 mhos 2.7 5.4 0.10 4.0 0.15 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 65 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 15)

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MTD3055V
TYPICAL ELECTRICAL CHARACTERISTICS
24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 4 0 5V 4V 0 1 2 3 4 5 6V 24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 4 0

TJ = 25C

VGS = 10 V 9V

8V

VDS 10 V

TJ = -55C 25C 100C

7V

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.3 0.25 0.2 0.15

VGS = 10 V

0.15 0.14 0.13 0.12 0.11 0.1 0.09 0.08 0

TJ = 25C

TJ = 100C 25C

VGS = 10 V

0.1 0.05 0 -55C

15 V

8 12 16 ID, DRAIN CURRENT (AMPS)

20

24

8 16 12 ID, DRAIN CURRENT (AMPS)

20

24

Figure 3. OnResistance versus Drain Current and Temperature


1.6 1.4 1.2 1.0 0.8 0.6 -50 1 VGS = 10 V ID = 6 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

10 TJ = 125C

-25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

10 20 30 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTD3055V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Coss Crss 15 20 25 VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

Crss

Ciss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTD3055V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 Q3 0 1 2 3 4 5 6 7 8 9 QT, TOTAL CHARGE (nC) 10 ID = 12 A TJ = 25C VDS 11 12 Q1 Q2 VGS 50 40 30 20 10 0 13 60 1000 VDD = 30 V ID = 12 A VGS = 10 V TJ = 25C tr td(off) 10 tf td(on) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


12 10 I S , SOURCE CURRENT (AMPS) 8 6 4 2 0 0.5 VGS = 0 V TJ = 25C

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1.0

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTD3055V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 75 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C

10 s

ID = 12 A

10 100 s 1 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 10 ms dc

50

25

0.1

100

25

50

75

100

125

150

175

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

1.0E-04

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1024

MTD3055V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 2.1 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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1025

MTD3055V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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1026

MTD3055V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 15. Typical Solder Heating Profile

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1027

MTD3055VL
Preferred Device

Power MOSFET 12 Amps, 60 Volts


NChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Single Pulse (tp 50 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 20 12 8.0 42 48 0.32 1.75 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts 1 2 3 CASE 369A DPAK (Bent Lead) STYLE 2 4 4 S G

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12 AMPERES 60 VOLTS RDS(on) = 180 m


NChannel D

12

CASE 369 DPAK (Straight Lead) STYLE 2

MARKING DIAGRAMS & PIN ASSIGNMENTS


4 Drain YWW T 3055VL 4 Drain YWW T 3055VL1

TJ, Tstg EAS

55 to 175 72

C mJ

C/W RJC RJA RJA TL 3.13 100 71.4 260 C 1 Gate 2 Drain 3 Source = Device Code = Year = Work Week = MOSFET 1 Gate 2 Drain 3 Source

3055VL Y WW T

ORDERING INFORMATION
Device MTD3055VL MTD3055VL1 MTD3055VLT4 Package DPAK DPAK (Straight Lead) DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

1028

March, 2001 Rev. 4

Publication Order Number: MTD3055VL/D

MTD3055VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 6.0 Adc) DrainSource OnVoltage (VGS = 5.0 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 5 Vdc) (VDD = 30 Vdc, ID = 12 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 7.5 nH nH ta tb QRR 0.97 0.86 55.7 37 18.7 0.116 1.3 C ns Vdc 9.0 85 14 43 8.1 1.8 4.2 3.8 20 190 30 90 10 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 410 114 21 570 160 40 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 5.0 1.6 8.8 2.6 2.5 mhos 1.6 3.0 0.12 2.0 0.18 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 62 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1029

MTD3055VL
TYPICAL ELECTRICAL CHARACTERISTICS
24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 3V 4 0 2.5 V 0 1 2 3 4 5 24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 4 0 2.0

TJ = 25C

VGS = 10 V

5V 4.5 V 4V 3.5 V

VDS 10 V

TJ = -55C 25C

100C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.32 0.26 0.20 0.14 0.08 0.02

VGS = 5 V

0.27

TJ = 25C

0.22

TJ = 100C 25C -55C

0.17

0.12

5V VGS = 10 V

8 12 16 ID, DRAIN CURRENT (AMPS)

20

24

0.07

8 12 16 ID, DRAIN CURRENT (AMPS)

20

24

Figure 3. OnResistance versus Drain Current and Temperature


100

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.0

VGS = 5 V ID = 6 A I DSS , LEAKAGE (nA)

VGS = 0 V

1.5

10

TJ = 125C

1.0

1.0

100C

0.5

0 -50

-25

25

50

75

100

125

150

175

0.1

TJ, JUNCTION TEMPERATURE (C)

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1030

MTD3055VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1400 1200 C, CAPACITANCE (pF) 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 Crss Ciss Coss Crss 10 15 20 25 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1031

MTD3055VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 QT 60 50 4 40 30 2 Q1 Q2 ID = 12 A TJ = 25C Q3 2 VDS 4 6 8 Qg, TOTAL GATE CHARGE (nC) 20 10 0 10 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 12 A VGS = 5 V TJ = 25C

VGS

t, TIME (ns)

100

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


12 10 I S , SOURCE CURRENT (AMPS) 8 6 4 2 0 0.50 0.55 0.60 0.65 0.70 VGS = 0 V TJ = 25C

0.75 0.80 0.85 0.90 0.95

1.0

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1032

MTD3055VL
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 75 10 s E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 5 V SINGLE PULSE TC = 25C

ID = 12 A

10 100 s 1 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 10 ms

50

dc

25

0.1

100

25

50

75

100

125

150

175

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1033

MTD3055VL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 2.1 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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1034

MTD3055VL
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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1035

MTD3055VL
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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1036

MTD3302 Advance Information Power MOSFET 18 Amps, 30 Volts


NChannel DPAK
This Power MOSFET is capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. These devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Characterized Over a Wide Range of Power Ratings Ultralow RDS(on) Provides Higher Efficiency and Extends Battery Life in Portable Applications Logic Level Gate Drive Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified
MAXIMUM RATINGS (TJ = 25C unless otherwise specified)
Parameter DraintoSource Voltage DraintoGate Voltage GatetoSource Voltage GatetoSource Operating Voltage Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, L = 20 mH, IL(pk) = 10 A, VDS = 30 Vdc) Symbol VDSS VDGR VGS VGS TJ, Tstg EAS 1000 1 Gate 2 Drain 3 Source Value 30 30 20 16 55 to 150 Unit Vdc Vdc Vdc Vdc C mJ

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18 AMPERES 30 VOLTS RDS(on) = 10 m


NChannel D

G S

MARKING DIAGRAM
4 1 2 3 Y WW T YWW T 3302

CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET

PIN ASSIGNMENT
4 Drain

ORDERING INFORMATION
Device MTD3302 MTD3302T4 Package DPAK DPAK Shipping 75 Units/Rail 2500 Tape & Reel

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Semiconductor Components Industries, LLC, 2000

1037

November, 2000 Rev. 2

Publication Order Number: MTD3302/D

MTD3302
POWER RATINGS (TJ = 25C unless otherwise specified)
Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoCase Continuous Source Current (Diode Conduction) Mounted on heat sink Tcase = 25C VGS = 10 Vdc Steady State Symbol ID ID IDM PD RJC IS Value 30 30 90 96 769 1.3 30 Unit Adc Adc Adc Watts mW/C C/W Adc

Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoAmbient Continuous Source Current (Diode Conduction) Mounted on 1 inch square FR4 or G10 board VGS = 10 Vdc t 10 seconds

Symbol ID ID IDM PD RJA IS

Value 18.3 11.2 60 5.0 40 25 6.4

Unit Adc Adc Adc Watts mW/C C/W Adc

Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoAmbient Continuous Source Current (Diode Conduction) Mounted on 1 inch square FR4 or G10 board VGS = 10 Vdc Steady State

Symbol ID ID IDM PD RJA IS

Value 11.2 8.6 40 1.9 15 67 2.5

Unit Adc Adc Adc Watts mW/C C/W Adc

Parameter Drain Current Continuous @ TA = 25C Drain Current Continuous @ TA = 100C Drain Current Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C Linear Derating Factor Thermal Resistance JunctiontoAmbient Continuous Source Current (Diode Conduction) Mounted on minimum recommended FR4 or G10 board VGS = 10 Vdc Steady State

Symbol ID ID IDM PD RJA IS

Value 8.3 5.2 30 1.0 8.3 120 1.4

Unit Adc Adc Adc Watts mW/C C/W Adc

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1038

MTD3302
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 15 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 4 4.5 5 Vdc Vdc, RG = 6.0 ) (VDD = 25 Vdc, ID = 1.0 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 2.3 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperatures. trr ta tb QRR VSD 0.87 0.72 41 21 20 0.047 1.1 C ns Vdc 10 30 65 58 20 86 44 48 47 4.8 16.7 11.2 20 60 130 110 40 170 80 90 60 nC ns ns (VDS = 24 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1760 610 185 pF VGS(th) 1.0 RDS(on) gFS 12 8.9 13 19 10 16 Mhos 1.9 4.6 Vdc mV/C m V(BR)DSS 30 IDSS IGSS 0.005 0.5 2 1.0 10 100 nAdc 33 23 Vdc mV/C Adc Symbol Min Typ Max Unit

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MTD3302
TYPICAL ELECTRICAL CHARACTERISTICS
60 ID , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 0 0.25 0.5 0.75 1 60 4.3 V 4.1 V 3.9 V 3.7 V 3.5 V 3.3 V 3.1 V 1.25 1.5 1.75 2 TJ = 25C ID, DRAIN CURRENT (AMPS) VDS 10 V 50 40 30 20 10 0 2 2.5 3

VGS = 10 V

6.0 V

4.5 V

TJ = 125C 25C -55C 3.5 4 4.5 5 5.5 6

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.3 ID = 5.0 A TJ = 25C 0.2

0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0 10 V TJ = 25C VGS = 4.5 V

0.1

10

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

30 40 20 ID, DRAIN CURRENT (AMPS)

50

60

Figure 3. OnResistance versus GateToSource Voltage


2.0 VGS = 10 V ID = 10 A 1.5 IDSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

TJ = 125C

100C 10 25C 1

1.0

0.5

0 -50

-25

25

50

75

100

125

150

0.1

TJ, JUNCTION TEMPERATURE (C)

10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

30

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTD3302
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4500 4000 C, CAPACITANCE (pF) 3500 3000 2500 2000 1500 1000 500 0 -10 -5 0 5 VGS VDS Crss 10 15 20 25 Coss Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C VGS = 0 V

VDS = 0 V Crss

Ciss

30

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTD3302
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 Q1 4 2 0 0 Q3 VDS 10 20 30 40 50 Qg, TOTAL GATE CHARGE (nC) Q2 TJ = 25C ID = 30 A VGS 15 12 9 6 3 0 18 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 1.0 A VDD = 25 V VGS = 10 V

td(off) tf tr

t, TIME (ns)

100

td(on) 10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
30 IS , SOURCE CURRENT (AMPS) 25 20 15 10 5 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MTD3302
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 ID , DRAIN CURRENT (AMPS) 100 ms

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.
1000 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 900 800 700 600 500 400 300 200 100 0 25 50 75 100 125 150 ID = 10 A

10

VGS = 10 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10

1 ms

10 ms dc

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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MTD3302
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE DUTY CYCLE 100 10 1 0.1 SINGLE PULSE 0.01 1E-05 1E-04 1E-03 1E-02 1E-01 t, TIME (seconds) D = 0.5 0.2 0.1 0.05 0.02 0.01

MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT

P(pk) t2 DUTY CYCLE, D = t1/t2 1E+00 t1

RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+02 1E+03

1E+01

Figure 14. Thermal Response Various Duty Cycles

10,000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1000 100 10 1 0.1 MIN PAD, ja 1 INCH PAD, ja R C R C 2.30 0.0256 0.753 0.0260 36.2 0.384 9.97 0.314 1521 25.0 230 5.07 5000 74.1 1300 19.6 85,400 41.7 17.9 7,500 CASE MOUNT, jc R C 0.0324 0.0002 0.0487 0.0006 0.0896 0.0014 0.464 0.0073 0.666 0.0482 CHIP JUNCTION

R1 C1

R2 C2

R3 C3

R4 C4

R5 C5 AMBIENT

1 2 3 4 5

Rthja, MIN PAD Rthja, 1 INCH PAD

Rthjc, Tcase = 25C 1E-05 1E-04 1E-03 1E-02 1E-01 t, TIME (seconds) 1E+00 1E+01 1E+02 1E+03

Figure 15. Thermal Response Various Mounting/Measurement Conditions

200 MOUNTED ON 2 SQ. FR4 BOARD (1 SQ. 2 OZ. CU 0.06 THICK SINGLE SIDED) 150 POWER (W) di/dt 100 IS trr 50 tp 0.01 0.1 t, TIME (seconds) 1 10 IS ta tb TIME 0.25 IS

Figure 16. Single Pulse Power http://onsemi.com


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Figure 17. Diode Reverse Recovery Waveform

MTD3302 INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. Note that these values may vary depending on the device type. Consult the maximum ratings table on the data sheet to find the actual PD and RqJA values for a particular device. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 18.
Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 18. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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MTD3302
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 19. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTD3302
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 20 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 20. Typical Solder Heating Profile

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MTD4N20E
Preferred Device

Power MOSFET 4 Amps, 200 Volts


NChannel DPAK
This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over time. In addition this advanced high voltage MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 200 200 20 40 4.0 2.6 12 40 0.32 1.75 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts 1 2 3 4N20E Y WW T 4 CASE 369A DPAK STYLE 2 = Device Code = Year = Work Week = MOSFET YWW T 4N20E

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4 AMPERES 200 VOLTS RDS(on) = 1.2


NChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT
4 Drain

TJ, Tstg EAS

55 to 150 80

C mJ

1 Gate

2 Drain

3 Source

C/W RJC RJA RJA TL 3.13 100 71.4 260 C

ORDERING INFORMATION
Device MTD4N20E MTD4N20E1 MTD4N20ET4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1048

November, 2000 Rev. 2

Publication Order Number: MTD4N20E/D

MTD4N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 4.0 Adc) (ID = 2.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 4.0 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 4.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 4.0 Adc, VGS = 0 Vdc) (IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr 4 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 4.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 0.92 0.82 123 82 41 0.58 C ns Vdc 10 4.0 15 6.0 9.2 2.4 4.1 5.6 17 26 29 18 14 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 311 66 11 430 80 20 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.5 3.5 2.1 5.8 5.0 mhos 3.0 7.0 0.98 4.0 1.2 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 10 100 100 nAdc 263 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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MTD4N20E
TYPICAL ELECTRICAL CHARACTERISTICS
8 7 I D , DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 0 2 4 6 8 10 12 5V 14 6V 8 I D , DRAIN CURRENT (AMPS) 9V 8V 7V 7 6 5 4 3 2 1 0 2 3 4 5 6 7 8 9 100C

TJ = 25C

VGS = 10 V

VDS 10 V

TJ = -55C 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 25C -55C 4 5 6 7 8 TJ = 100C 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 0 1

Figure 2. Transfer Characteristics

VGS = 10 V

TJ = 25C

VGS = 10 V 15 V

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


100

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.5 2.0 1.5 1.0 0.5 0 -50

VGS = 10 V ID = 4 A I DSS, LEAKAGE (nA)

VGS = 0 V

TJ = 125C 100C

10 25C

-25

25

50

75

100

125

150

50

100

150

200

250

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1050

MTD4N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
800 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

C, CAPACITANCE (pF)

600

400

Crss

Ciss

200

Coss Crss

10

10

15

20

25

VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1051

MTD4N20E
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) 18 QT 180 160 140 120 Q1 Q2 VGS 100 80 ID = 4 A TJ = 25C Q3 0 2 4 6 QT, TOTAL CHARGE (nC) VDS 8 60 40 20 0 10 100 VDD = 100 V ID = 4 A VGS = 10 V TJ = 25C td(off) td(on) tf

16 14 12 10 8 6 4 2 0

10

tr 1 10 RG, GATE RESISTANCE (OHMS) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


4.0 3.2 2.4 1.6 0.8 0 0.50 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1052

MTD4N20E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 80

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

10

VGS = 20 V SINGLE PULSE TC = 25C

ID = 4A

10 s 100 s 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

60

1.0

40

0.1

20

0.01 0.1

1.0

10

100

1000

25

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE t1

0.1

P(pk)

0.01 1.0E-05

t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

1.0E-04

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1053

MTD4N20E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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1054

MTD4N20E
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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1055

MTD4N20E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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1056

MTD5P06V
Preferred Device

Power MOSFET 5 Amps, 60 Volts


PChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 5 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 60 60 15 25 5 4 18 40 0.27 2.1 55 to 175 125 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ 4 1 2 3 Y WW T CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET YWW T 5P06V G S

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5 AMPERES 60 VOLTS RDS(on) = 450 m


PChannel D

MARKING DIAGRAM

TJ, Tstg EAS

PIN ASSIGNMENT
C/W RJC RJA RJA TL 3.75 100 71.4 260 C 1 Gate 2 Drain 3 Source 4 Drain

1. When surface mounted to an FR4 board using the minimum recommended pad size.

ORDERING INFORMATION
Device MTD5P06V MTD5P06V1 MTD5P06VT4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1057

November, 2000 Rev. 2

Publication Order Number: MTD5P06V/D

MTD5P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150C) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 5 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 5 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD LS 7.5 4.5 nH nH ta tb QRR 1.72 1.34 97 73 24 0.42 3.5 C ns Vdc 11 26 17 19 12 3.0 5.0 5.0 20 50 30 40 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 367 140 29 510 200 60 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.5 3.6 2.7 2.6 Mhos 2.8 4.7 0.34 4.0 0.45 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 61.2 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1058

MTD5P06V
TYPICAL ELECTRICAL CHARACTERISTICS
10 I D , DRAIN CURRENT (AMPS) 8 6 4 2 0 5V 4V 0 1 2 3 4 5 6 7 8 9 10 7V I D , DRAIN CURRENT (AMPS) 9 8 7 6 5 4 3 2 1 0 2 3 4 5 6 7 8

VGS = 10V TJ = 25C

9V

8V

VDS 10 V

TJ = -55C 25C 100C

6V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 1

VGS = 10 V TJ = 100C

0.4

TJ = 25C VGS = 10 V

0.35

25C

0.3

15 V

0.25

-55C 2 3 4 5 6 7 ID, DRAIN CURRENT (AMPS) 8 9 10

0.2

4 5 7 6 ID, DRAIN CURRENT (AMPS)

10

Figure 3. OnResistance versus Drain Current and Temperature


100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -50

VGS = 10 V ID = 2.5 A I DSS , LEAKAGE (nA)

VGS = 0 V

10

TJ = 125C

-25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

50 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1059

MTD5P06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1000 900 800 C, CAPACITANCE (pF) 700 600 500 400 300 200 100 0 VGS = 0 V 10 5 VGS 0 VDS 5 Crss 10 15 20 25 Coss Ciss Crss Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1060

MTD5P06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 2 4 6 Q3 VDS 8 10 TJ = 25C ID = 5 A 12 Q1 Q2 QT 60 VGS 54 48 42 36 30 24 18 12 6 0 14 100 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 5 A VDD = 30 V VGS = 10 V td(off) tf

tr

t, TIME (ns)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


5 4.5 I S , SOURCE CURRENT (AMPS) 4 3.5 3 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 TJ = 25C VGS = 0 V

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1061

MTD5P06V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 140 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 120 100 80 60 40 20 0 25 50 75 100 125 150 175

VGS = 20 V SINGLE PULSE TC = 25C

ID = 5 A

10 100 s 1 1 ms 10 ms dc

0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1

1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1062

MTD5P06V INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 175C 25C = 2.1 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.1 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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1063

MTD5P06V
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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1064

MTD5P06V
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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1065

MTD6N20E
Preferred Device

Power MOSFET 6 Amps, 200 Volts


NChannel DPAK
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 200 200 20 40 6.0 3.8 18 50 0.4 1.75 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts 1 2 3 Y WW T

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6 AMPERES 200 VOLTS RDS(on) = 700 m


NChannel D

G S

MARKING DIAGRAM
4 YWW T 6N20E

CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET

PIN ASSIGNMENT
TJ, Tstg EAS 55 to 150 54 C mJ 4 Drain

C/W RJC RJA RJA TL 2.50 100 71.4 260 C

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD6N20E MTD6N20E1 MTD6N20ET4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1066

November, 2000 Rev. 1

Publication Order Number: MTD6N20E/D

MTD6N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 6.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr 6 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 6.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 0.99 0.9 138 93 45 0.74 1.2 C ns Vdc 8.8 29 22 20 13.7 2.7 7.1 5.9 17.6 58 44 40.8 21 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 342 92 27 480 130 55 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.5 2.9 5.0 4.4 mhos 3.0 7.1 0.46 4.0 0.700 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 10 100 100 nAdc 689 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1067

MTD6N20E
TYPICAL ELECTRICAL CHARACTERISTICS
12 I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 6V 12 I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 9 0 2 3 4 5 6 7 8 9

TJ = 25C

VGS = 10 V

9V 8V 7V

VDS 10 V

TJ = -55C 25C 100C

5V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 VGS = 10 V TJ = 100C 25C -55C R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.70 0.65 0.60 0.55 0.50 0.45 0.40

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 10 V

15 V 0 2 4 6 8 10 12

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.5 2.0 1.5 1.0 0.5 0 - 50

VGS = 10 V ID = 3 A I DSS , LEAKAGE (nA)

100

VGS = 0 V

TJ = 125C 100C

10

25C

- 25

25

50

75

100

125

150

50

100

150

200

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1068

MTD6N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
900 750 C, CAPACITANCE (pF) 600 450 300 150 0 Crss 10 5 VGS 0 VDS 5 10 15 20 25 Coss Ciss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1069

MTD6N20E
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 2 4 VDS 6 8 10 QT, TOTAL CHARGE (nC) 12 Q1 Q2 QT VGS 60 45 30 15 0 14 90 75 1000 VDD = 100 V ID = 6 A VGS = 10 V TJ = 25C

100

ID = 6 A TJ = 25C

10

tr td(off) td(on)

tf

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


6 I S , SOURCE CURRENT (AMPS) 5 4 3 2 1 0 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1.0 VGS = 0 V TJ = 25C

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1070

MTD6N20E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 60 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 50 40 30 20 10 0

VGS = 20 V SINGLE PULSE TC = 25C 10 s 100 s

ID = 6 A

10

1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

1 ms 10 ms dc 1000

0.1 0.1

100 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

25

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

0.01 1.0E-05

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1071

MTD6N20E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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1072

MTD6N20E
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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1073

MTD6N20E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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1074

MTD6P10E
Preferred Device

Power MOSFET 6 Amps, 100 Volts


PChannel DPAK
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 100 100 15 20 6.0 3.9 18 50 0.4 1.75 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts 1 2 3 Y WW T

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6 AMPERES 100 VOLTS RDS(on) = 660 m


PChannel D

G S

MARKING DIAGRAM
4 YWW T 6P10E

CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET

PIN ASSIGNMENT
TJ, Tstg EAS 55 to 150 180 C mJ 4 Drain

C/W RJC RJA RJA TL 2.50 100 71.4 260 C

1 Gate

2 Drain

3 Source

ORDERING INFORMATION
Device MTD6P10E MTD6P10ET4 Package DPAK DPAK Shipping 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1075

November, 2000 Rev. 1

Publication Order Number: MTD6P10E/D

MTD6P10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) (VDD = 50 Vdc, ID = 6.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr 6 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 6.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 1.8 1.5 112 92 20 0.603 5.0 C ns Vdc 12 29 18 9 15.3 4.1 7.1 6.8 25 60 40 20 22 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 550 154 27 840 240 56 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.5 3.6 3.0 4.8 4.2 mhos 2.9 4.0 0.56 4.0 0.66 Vdc mV/C Ohm Vdc V(BR)DSS 100 IDSS IGSS 10 100 100 nAdc 124 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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MTD6P10E
TYPICAL ELECTRICAL CHARACTERISTICS
12 I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 7V 6V 5V 20 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 I D , DRAIN CURRENT (AMPS) 9V 8V 10 8 6 4 2 0 2 3 4 5 6 7 8 9 10

TJ = 25C

VGS = 10 V

VDS 10 V

TJ = -55C 25C 100C

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0 2 4 -55C 6 8 10 12 25C TJ = 100C VGS = 10 V R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 10 V

15 V

10

12

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 - 50

VGS = 10 V ID = 3 A I DSS , LEAKAGE (nA)

100 VGS = 0 V

TJ = 125C

- 25

25

50

75

100

125

150

10 - 120

- 100

- 80

- 60

- 40

- 20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTD6P10E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1600 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS Crss 5 10 Crss Ciss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Coss

15

20

25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTD6P10E
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 Q1 8 6 4 2 0 Q3 0 2 4 VDS 6 8 10 QT, TOTAL CHARGE (nC) 12 14 ID = 6 A TJ = 25C QT Q2 VGS 90 75 60 45 30 15 0 16 1000 VDD = 50 V ID = 6 A VGS = 10 V TJ = 25C

100

10

tr td(off) td(on) tf

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


6 I S , SOURCE CURRENT (AMPS) 5 4 3 2 1 0 0.50 0.75 1.0 1.25 1.50 1.75 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 2.0 VGS = 0 V TJ = 25C

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTD6P10E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 200 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 160 120 80 40 0

VGS = 10 V SINGLE PULSE TC = 25C

ID = 6 A

10 100 s 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc

1.0

0.1 0.1

1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

25

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

0.01 1.0E-05

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1080

MTD6P10E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
RJA , THERMAL RESISTANCE, JUNCTION TO AMBIENT (C/W) 100 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, AREA (SQUARE INCHES)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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MTD6P10E
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTD6P10E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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MTD9N10E
Preferred Device

Power MOSFET 9 Amps, 100 Volts


NChannel DPAK
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Replaces MTD6N10
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C, when mounted to minimum recommended pad size Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient, when mounted to minimum recommended pad size Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 100 100 20 30 9.0 5.0 27 40 0.32 1.75 Unit Vdc Vdc 4 Vdc Vpk Adc Apk Watts W/C Watts 1 2 3 Y WW T9 CASE 369A DPAK STYLE 2 = Year = Work Week = MOSFET YWW T9 N10E

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9 AMPERES 100 VOLTS RDS(on) = 250 m


NChannel D

G S

MARKING DIAGRAM

PIN ASSIGNMENT
4 Drain

TJ, Tstg EAS

55 to 150 40

C mJ 1 Gate C/W 2 Drain 3 Source

RJC RJA RJA TL

3.13 100 71.4 260 C

ORDERING INFORMATION
Device MTD9N10E MTD9N10E1 MTD9N10ET4 Package DPAK DPAK DPAK Shipping 75 Units/Rail 75 Units/Rail 2500 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

1084

February, 2001 Rev. 4

Publication Order Number: MTD9N10E/D

MTD9N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 4.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 9.0 Adc) (ID = 4.5 Adc, TJ = 125C) Forward Transconductance (VDS = 8.0 Vdc, ID = 4.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge g (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 9.0 Adc, VGS = 10 Vdc) (VDD = 50 Vdc, ID = 9.0 Adc, Vdc VGS = 10 Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 9.0 Adc, VGS = 0 Vdc) (IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 9.0 9 0 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 0.98 0.9 91 71 20 0.4 1.8 C ns Vdc 8.8 28 16 4.8 14 5.2 3.2 6.6 20 60 30 10 21 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 610 176 14 1200 400 30 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 4.0 2.43 2.40 mhos 6.0 0.17 4.0 0.25 Vdc mV/C Ohm Vdc V(BR)DSS 100 IDSS IGSS 10 100 100 nAdc 103 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery y Time (S Figure (See Fi 14)

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MTD9N10E
TYPICAL ELECTRICAL CHARACTERISTICS
18 16 I D , DRAIN CURRENT (AMPS) 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 5V 4V 7 8 9 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6V 18 16 I D , DRAIN CURRENT (AMPS) 14 12 10 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 100C VDS 10 V TJ = -55C 25C

VGS =10V 8V

TJ = 25C

7V

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -55C 0 2 4 10 6 8 12 ID, DRAIN CURRENT (AMPS) 14 16 18 25C TJ = 100C VGS = 10 V RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.25

Figure 2. Transfer Characteristics

TJ = 25C 0.23 0.21 0.19 0.17 15 V 0.15 0 2 4 8 10 6 12 ID, DRAIN CURRENT (AMPS) 14 16 18

VGS =10V

Figure 3. OnResistance versus Drain Current and Temperature


1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 0.1 30 VGS = 10 V ID =4.5 A I DSS , LEAKAGE (nA) 10 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS =0V TJ = 125C 100C

1.0 25C

40 60 50 70 80 90 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTD9N10E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 Crss Ciss Ciss VDS = 0

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0

TJ = 25C

Coss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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MTD9N10E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 Q1 6 4 2 Q3 0 0 2 4 6 8 10 QG, TOTAL GATE CHARGE (nC) VDS 12 ID = 9 A TJ = 25C 60 40 20 0 14 Q2 VGS QT 120 100 80 100 VDD = 50 V ID = 9 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

tr td(off) td(on) tf

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


9 8 I S , SOURCE CURRENT (AMPS) 7 6 5 4 3 2 1 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTD9N10E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 40 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID = 9 A 32 24 16 8 0 25

10

VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms 10 ms dc

10 s

1.0

0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 1.0 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

0.01 0.1

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t1 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1089

MTD9N10E INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE


RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.165 4.191

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.118 3.0 0.063 1.6

0.100 2.54

0.190 4.826

0.243 6.172

inches mm

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the drain pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) TA RJA PD = 150C 25C = 1.75 Watts 71.4C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a DPAK device, PD is calculated as follows.
100 R JA , Thermal Resistance, Junction to Ambient (C/W) 1.75 Watts

The 71.4C/W for the DPAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.75 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus drain pad area is shown in Figure 15.

Board Material = 0.0625 G-10/FR-4, 2 oz Copper TA = 25C

80

60

3.0 Watts

40

5.0 Watts

20 0

4 6 A, Area (square inches)

10

Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package (Typical)

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1090

MTD9N10E
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.

SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC59, SC70/SOT323, SOD123, SOT23, SOT143, SOT223, SO8, SO14, SO16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or tombstoning may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.

SOLDER PASTE OPENINGS

STENCIL

Figure 16. Typical Stencil for DPAK and D2PAK Packages

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.

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MTD9N10E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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1092

MTDF1N02HD
Preferred Device

Power MOSFET 1 Amp, 20 Volts

NChannel Micro8t, Dual


These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Miniature Micro8 Surface Mount Package Saves Board Space Extremely Low Profile (<1.1 mm) for thin applications such as PCMCIA cards Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for Micro8 Package Provided
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1 AMPERE 20 VOLTS RDS(on) = 120 mW


NChannel D

G S

MARKING DIAGRAM

Micro8, Dual CASE 846A STYLE 2 1

WW BA

WW

= Date Code

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View

ORDERING INFORMATION
Device MTDF1N02HDR2 Package Micro8 Shipping 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1093

November, 2000 Rev. 6

Publication Order Number: MTDF1N02HD/D

MTDF1N02HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous 1 SQ. FR4 or G10 PCB Figure 1 below 1 die operating Steady State Minimum FR4 or G10 PCB Figure 2 below 1 die operating Steady State Minimum FR4 or G10 PCB Figure 2 below 2 die operating Steady State Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Symbol VDSS VDGR VGS RTHJA PD ID ID IDM RTHJA PD ID ID IDM RTHJA PD ID ID IDM TJ, Tstg Typical 80 160 240 Max 20 20 8.0 100 1.25 10 2.8 2.3 23 200 0.63 5.0 1.7 1.6 16 300 0.42 3.33 1.6 1.3 13 55 to 150 Unit V V V C/W Watts mW/C A A A C/W Watts mW/C A A A C/W Watts mW/C A A A C

Operating and Storage Temperature Range 1. Repetitive rating; pulse width limited by maximum junction temperature.

Figure 1. 1, Square FR4 or G10 PCB

Figure 2. Minimum FR4 or G10 PCB

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1094

MTDF1N02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Cpk 2.0) (Notes 2. & 4.) V(BR)DSS 20 IDSS IGSS 1.0 25 100 nAdc 5.0 Vdc mV/C Adc Symbol Min Typ Max Unit

Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 1.7 Adc) (VGS = 2.7 Vdc, ID = 0.85 Adc) (Cpk 2.0) (Note 4.)

VGS(th) 0.7 0.9 2.5 99 133 1.1 120 160

Vdc mV/C m

(Note 4.)

RDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 1.7 Adc, VGS = 4.5 Vdc) (VDD = 10 Vdc, ID = 0.85 Adc, VGS = 2.7 Vdc, RG = 6 ) (Note 2.) (VDS = 10 Vdc, ID = 1.7 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz)

gFS

2.0

Mhos

Ciss Coss Crss

145 90 38

pF

td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3

8.0 27 23 34 16 79 24 31 3.9 0.4 1.7 1.5

5.5

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 1.7 Adc, VGS = 0 Vdc) (Note 2.) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA VSD trr ta tb QRR 0.84 0.71 29 14 15 0.018 1.0 C ns Vdc

Reverse Recovery Time

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1095

MTDF1N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
4.0 I D , DRAIN CURRENT (AMPS) VGS = 10 V 4.5 V 2.7 V 2.3 V 2.1 V 1.7 V 1.0 1.5 V 4.0 I D , DRAIN CURRENT (AMPS)

TJ = 25C

VDS 10 V

3.0

1.9 V

3.0

2.0

2.0 100C 1.0 25C TJ = -55C

0.4

0.8

1.2

1.6

0.5

1.0

1.5

2.0

2.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 0.15

Figure 4. Transfer Characteristics

ID = 1.7 A TJ = 25C

2.7 V 0.13 0.11 0.09 0.07 0.05 TJ = 25C

VGS = 4.5 V

2.0 4.0 6.0 8.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

1.0

2.0 ID, DRAIN CURRENT (AMPS)

3.0

4.0

Figure 5. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 6. OnResistance versus Drain Current and Gate Voltage

2.0 1.6 1.2 0.8 0.4

VGS = 4.5 V ID = 0.85 A

1000

VGS = 0 V

TJ = 125C 100C

I DSS , LEAKAGE (nA)

100

10 25C

1.0

0 -50

-25

25

50

75

100

125

150

0.1

5.0

10

15

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. OnResistance Variation with Temperature

Figure 8. DraintoSource Leakage Current versus Voltage

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MTDF1N02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
800 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

C, CAPACITANCE (pF)

600

400

Crss

200 Crss 5.0 VGS 0 VDS 5.0 10 15

Ciss Coss 20

0 10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 9. Capacitance Variation

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MTDF1N02HD
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6.0 5.0 4.0 3.0 2.0 1.0 0 ID = 1.7 A TJ = 25C 1.0 2.0 3.0 4.0 Qg, TOTAL GATE CHARGE (nC) VDS Q1 Q2 VGS QT 18 15 12 9.0 6.0 3.0 0 5.0 100 VDD = 10 V ID = 1.7 A VGS = 4.5 V TJ = 25C

tf tr td(off) td(on)

t, TIME (ns)

10

Q3 0

1.0

1.0

10 RG, GATE RESISTANCE (OHMS)

100

Figure 10. GateToSource and DrainToSource Voltage versus Total Charge

Figure 11. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 13. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2.0 I S , SOURCE CURRENT (AMPS) 1.6 1.2 0.8 0.4 0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 12. Diode Forward Voltage versus Current

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MTDF1N02HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 13. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curve (Figure 14) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use.
100 I D , DRAIN CURRENT (AMPS) VGS = 8 V SINGLE PULSE TC = 25C 10 ms 1.0 dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1 ms

Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC).

10

100 s

0.01 0.1

Figure 14. Maximum Rated Forward Biased Safe Operating Area

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1099

MTDF1N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE ( C/W) D = 0.5 0.2 0.1 0.05 0.02 0.01 1 SINGLE PULSE 0.1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) t1

100

10

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E+00

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

Figure 15. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 16. Diode Reverse Recovery Waveform

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1100

MTDF1N02HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

Micro8 POWER DISSIPATION The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.63 Watts.
PD = 150C 25C = 0.63 Watts 200C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 200C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.63 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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1101

MTDF1N02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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1102

MTDF1N02HD
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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1103

MTDF1N03HD
Preferred Device

Power MOSFET 1 Amp, 30 Volts

NChannel Micro8t, Dual


These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Miniature Micro8 Surface Mount Package Saves Board Space Extremely Low Profile (<1.1mm) for thin applications such as PCMCIA cards Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for Micro8 Package Provided
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1 AMPERE 30 VOLTS RDS(on) = 120 mW


NChannel D

G S

MARKING DIAGRAM

Micro8, Dual CASE 846A STYLE 2 1

WW BB

WW

= Date Code

PIN ASSIGNMENT
Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

Top View

ORDERING INFORMATION
Device MTDF1N03HDR2 Package Micro8 Shipping 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1104

November, 2000 Rev. 5

Publication Order Number: MTDF1N03HD/D

MTDF1N03HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Negative sign for PChannel devices omitted for clarity Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous 1 SQ. FR4 or G10 PCB Figure 1 below Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Symbol VDSS VDGR VGS RTHJA PD ID ID IDM RTHJA PD ID ID IDM RTHJA PD ID ID IDM TJ, Tstg EAS 200 Max 30 30 20 100 1.25 10 2.8 2.2 23 200 0.63 5.0 2.0 1.6 16 300 0.42 3.33 1.6 1.3 13 55 to 150 Unit V V V C/W Watts mW/C A A A C/W Watts mW/C A A A C/W Watts mW/C A A A C mJ

Steady State Minimum FR4 or G10 PCB Figure 2 below 1 die operating Steady State Minimum FR4 or G10 PCB Figure 2 below 2 die operating Steady State Operating and Storage Temperature Range

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 2.4 Apk, L = 69 mH, RG = 25 W) 1. Repetitive rating; pulse width limited by maximum junction temperature.

Figure 1. 1, Square FR4 or G10 PCB

Figure 2. Minimum FR4 or G10 PCB

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1105

MTDF1N03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Cpk 2.0) (Notes 2. & 4.) V(BR)DSS 30 IDSS IGSS 1.0 25 100 nAdc 29 Vdc mV/C Adc Symbol Min Typ Max Unit

Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.7 Adc) (VGS = 4.5 Vdc, ID = 0.85 Adc) (Cpk 2.0) (Note 4.)

VGS(th) 1.0 1.6 3.7 96 135 2.0 120 160

Vdc mV/C m

(Note 4.)

RDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge

(Note 2.)

gFS

1.0

Mhos

Ciss (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Coss Crss

140 70 30

pF

td(on) (VDS = 15 Vdc, ID = 1.7 Adc, VGS = 10 Vdc, RG = 6 ) (Note 2.) tr td(off) tf td(on) (VDD = 15 Vdc, ID = 0.85 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) tr td(off) tf QT (VDS = 24 Vdc, ID = 1.7 Adc, VGS = 10 Vdc) Q1 Q2 Q3

7.5 10 22 18 7.0 8.2 22 14.5 5.0 0.5 1.65 1.3

7.0

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 1.7 Adc, VGS = 0 Vdc) (Note 2.) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 1.7 1 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA VSD trr ta tb QRR 0.84 0.7 20 12 8.0 0.012 1.0 C ns Vdc

Reverse Recovery Time

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1106

MTDF1N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 4 VDS 10 V I D , DRAIN CURRENT (AMPS) 3

VGS = 10 V 3.9 V

6V 4.5 V 3.7 V

3.5 V 3.3 V 3.1 V 2.9 V

TJ = 25C

2.7 V 2.5 V 2.3 V 0 0.5 1 1.5 2 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100C

25C TJ = -55C

0 1.5

2.5

3.5

4.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.18

Figure 4. Transfer Characteristics

ID = 1.7 A TJ = 25C

TJ = 25C 0.16 0.14 0.12 0.1 0.08 10 V VGS = 4.5

4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

2 ID, DRAIN CURRENT (AMPS)

Figure 5. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.5 2.0 1.5 1.0 0.5 0 -50 0.1 100

Figure 6. OnResistance versus Drain Current and Gate Voltage

VGS = 10 V ID = 0.85 A I DSS , LEAKAGE (nA)

VGS = 0 V

TJ = 125C

10 100C

25C

-25

25

50

75

100

125

150

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. OnResistance Variation with Temperature

Figure 8. DraintoSource Leakage Current versus Voltage

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1107

MTDF1N03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
500 400 C, CAPACITANCE (pF) 300 200 100 0 10 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

Ciss Crss 5 VGS 0 VDS 5 10 15 Coss 20 25 30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 9. Capacitance Variation

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1108

MTDF1N03HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 Q1 2 0 0 VDS VGS QT 30 25 20 15 10 ID = 1.7 A TJ = 25C 1 4 2 3 Qg, TOTAL GATE CHARGE (nC) 5 6 5 0 100 VDD = 15 V ID = 1.7 A VGS = 10 V TJ = 25C

t, TIME (ns)

td(off) tf tr td(on)

10

Q2

Q3

10 RG, GATE RESISTANCE (OHMS)

100

Figure 10. GateToSource and DrainToSource Voltage versus Total Charge

Figure 11. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 13. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

1.5

0.5

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 12. Diode Forward Voltage versus Current http://onsemi.com


1109

MTDF1N03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 13. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curve (Figure 14) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 16). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
200 EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 160 120 80 40 0

10

10 s 100 s

VDD = 30 V VGS = 10 V IL = 2.4 A L = 69 mH

1 ms 10 ms

0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

dc 100

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 14. Maximum Rated Forward Biased Safe Operating Area

Figure 15. Maximum Avalanche Energy versus Starting Junction Temperature

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1110

MTDF1N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 1 SINGLE PULSE 0.1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) t1

100

10

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E+00

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

Figure 16. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 17. Diode Reverse Recovery Waveform

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1111

MTDF1N03HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

Micro8 POWER DISSIPATION The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.63 Watts.
PD = 150C 25C = 0.63 Watts 200C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 200C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.63 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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1112

MTDF1N03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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1113

MTDF1N03HD
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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1114

MTDF2N06HD
Preferred Device

Power MOSFET 2 Amps, 60 Volts

NChannel Micro8t, Dual


Micro8 devices are an advanced series of Power MOSFETs that contain monolithic backtoback zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Miniature Micro8 Surface Mount Package Saves Board Space Diode is Characterized for Use in Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Parameter DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Continuous Drain Current @ TA = 25C (Note 1.) Pulsed Drain Current (Note 2.) Total Power Dissipation @ TA = 25C (Note 1.) Operating and Storage Temperature Range Continuous Source Current (Diode Conduction) (Note 3.) Symbol VDSS VDGR VGS ID IDM PD TJ, Tstg IS Max 60 60 20 1.5 12 1.25 55 to 150 0.9 Unit Vdc Vdc Vdc Adc 1 8 Micro8, Dual CASE 846A STYLE 2 WW BA

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2 AMPERES 60 VOLTS RDS(on) = 220 mW


NChannel D

G S

MARKING DIAGRAM

W C

WW

= Date Code

PIN ASSIGNMENT
Adc Source1 Gate1 Source2 Gate2 1 2 3 4 8 7 6 5 Drain1 Drain1 Drain2 Drain2

THERMAL RESISTANCE
JunctiontoAmbient (Note 1.) RJA 100 C/W 1. When mounted on 1 square FR4 or G10 board (VGS = 10 V, @ 10 Seconds) 2. Repetitive rating; pulse width limited by maximum junction temperature. 3. When mounted on FR4 board, t 10 seconds

Top View

ORDERING INFORMATION
Device MTDF2N06HDR2 Package Micro8 Shipping 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1115

November, 2000 Rev. 1

Publication Order Number: MTDF2N06HD/D

MTDF2N06HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 0.75 Adc) (Cpk 2.0) (Notes 4. & 6.) (Cpk 2.0) (Notes 4. & 6.) VGS(th) 1.0 RDS(on) gFS 0.5 180 220 2.5 220 260 Mhos 1.6 3.0 m Vdc (Cpk 2.0) (Notes 4. & 6.) V(BR)DSS 60 IDSS IGSS 1.0 10 100 nAdc Adc Vdc Symbol Min Typ Max Unit

Forward Transconductance (VDS = 8.0 Vdc, ID = 1.0 Adc) (Note 4.) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VGS = 10 Vdc, ID = 1.5 Adc, VDD = 30 Vdc) (Note 4.) (VDD = 30 Vdc, ID = 1.5 Adc, VGS = 10 Vdc Vdc, RG = 6.0 ) (Note 4.) (VDS = 25 Vd Vdc, VGS = 0 V V, f = 1.0 MHz)

Ciss Coss Crss

140 40 12

200 60 18

pF

td(on) tr td(off) tf QT Q1 Q2 Q3

7.5 8.0 25 14.5 18 3.1 6.8 5.0

15 16 50 29 26

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 1.5 Adc, VGS = 0 Vdc) (Note 4.) (IS = 1.5 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 1.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperatures. 6. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA ta tb QRR 0.9 0.83 24 18 6.0 0.02 1.5 C ns Vdc

Reverse Recovery Time

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1116

MTDF2N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
4 6.0 V 4.5 V 4 VDS 10 V ID, DRAIN CURRENT (AMPS) 3

10 V

3.7 V 3.5 V 3.3 V

TJ = 25C

ID , DRAIN CURRENT (AMPS)

2 2.9 V 1 VGS = 2.5 V 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TJ = 125C 25C -55C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DSon( W ) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 1.0 0.8 0.6 0.4 0.2 0 ID = 1.5 A TJ = 25C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.30 TJ = 25C 0.26 0.22 10 V 0.18 0.14 0 VGS = 4.5 V

10

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

3 2 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current


2.0 VGS = 10 V ID = 1.5 A 1.5 IDSS , LEAKAGE (A) 1E-08 1E-07

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

TJ = 125C 100C

1.0

1E-09

25C

0.5

1E-10 VGS = 0 V 0 20 40 10 30 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 50

0 -50

-25

25

50

75

100

125

150

1E-11

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1117

MTDF2N06HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
500 400 C, CAPACITANCE (pF) 300 200 100 0 -10 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

Ciss Crss -5 0 5 VGS VDS 10 15 20 Coss 25 30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1118

MTDF2N06HD
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 0 Q1 Q3 5 10 Qg, TOTAL GATE CHARGE (nC) 15 Q2 TJ = 25C ID = 1.5 A VDS VGS 25 20 15 10 5 0 20 30 100 TJ = 25C ID = 1.5 A VDD = 30 V VGS = 10 V

td(off) tf tr td(on)

t, TIME (ns)

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2 IS , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

1.5

0.5

0.2

0.4

0.6

0.8

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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1119

MTDF2N06HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
100 ID , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C 100 ms 1 ms 10 ms 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.

10

dc 100

0.01

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

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1120

MTDF2N06HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

Micro8 POWER DISSIPATION The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.25 Watts.
PD = 150C 25C = 1.25 Watts 100C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 100C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.25 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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1121

MTDF2N06HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 13 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 13. Typical Solder Heating Profile

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1122

MTP10N10E
Preferred Device

Power MOSFET 10 Amps, 100 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers draintosource diodes with fast recovery times. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical, and offer additional safety margin against unexpected voltage transients. Internal SourcetoDrain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the Avalanche Mode Unclamped Inductive Switching (UIS) Energy Capability Specified at 100C Commutating Safe Operating Area (CSOA) Specified for Use in Half and Full Bridge Circuits SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Drain Current Continuous Drain Current Pulsed Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds Symbol VDSS VDGR VGS ID IDM PD TJ, Tstg Value 100 100 20 10 25 75 0.6 65 to 150 1.67 62.5 275 C Unit Vdc Vdc Vdc Adc Watts W/C C C/W RJC RJA TL MTP10N10E LL Y WW TO220AB CASE 221A STYLE 5 1 4

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10 AMPERES 100 VOLTS RDS(on) = 250 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP10N10E LLYWW 3 Source 2 Drain

1 Gate

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP10N10E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1123

November, 2000 Rev. 1

Publication Order Number: MTP10N10E/D

MTP10N10E
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = 0.8 Rated VDSS, VGS = 0, TJ = 125C) GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100C Static DrainSource OnResistance (VGS = 10 Vdc, ID = 5.0 Adc) DrainSource OnVoltage (VGS = 10 V) (ID = 10 Adc) (ID = 5.0 Adc, TJ = 100C) Forward Transconductance (VDS = 15 V, ID = 5.0 A) DRAINTOSOURCE AVALANCHE CHARACTERISTICS Unclamped DraintoSource Avalanche Energy See Figures 14 and 15 (ID = 25 A, VDD = 25 V, TC = 25C, Single Pulse, Nonrepetitive) (ID = 10 A, VDD = 25 V, TC = 25C, P.W. 200 s, Duty Cycle 1%) (ID = 4.0 A, VDD = 25 V, TC = 100C, P.W. 200 s, Duty Cycle 1%) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) S Fi See Figure 16 Ciss Coss Crss 600 400 100 pF WDSR 60 100 40 mJ VGS(th) 2.0 1.5 RDS(on) VDS(on) gFS 4.0 2.7 2.4 mhos 4.5 4.0 0.25 Ohm Vdc Vdc V(BR)DSS IDSS IGSSF IGSSR 10 80 100 100 nAdc nAdc 100 Vdc A Symbol Min Max Unit

SWITCHING CHARACTERISTICS (Note 1.) (TJ = 100C) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) S Figures See Fi 17 and d 18 (VDD = 25 V, ID = 5.0 A, RG = 50 ) See Figure 9 td(on) tr td(off) tf Qg Qgs Qgd 15 (Typ) 8.0 (Typ) 7.0 (Typ) 50 80 100 80 30 nC ns

SOURCEDRAIN DIODE CHARACTERISTICS (Note 1.) Forward OnVoltage Forward TurnOn Time Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. Ld 3.5 (Typ) 4.5 (Typ) Ls 7.5 (Typ) nH (IS = Rated R t d ID VGS = 0) VSD ton trr 1.4 (Typ) 1.7 Vdc

Limited by stray inductance 70 (Typ) ns

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1124

MTP10N10E
TYPICAL ELECTRICAL CHARACTERISTICS
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

20 16 12 8 4

VGS = 10 V

8V

7V

TJ = 25C

1.2 1.1 1 0.9 0.8 0.7 -50 VDS = VGS ID = 1 mA

I D, DRAIN CURRENT (AMPS)

6V

5V

4V 0 8 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 4 20

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 1. OnRegion Characteristics


VBR(DSS), DRAIN-TO-SOURCE BREAKDOWN VOLTAGE (NORMALIZED)

Figure 2. GateThreshold Voltage Variation With Temperature


2 1.6 1.2 0.8 0.4 0 -50 VGS = 0 V ID = 0.25 mA

20 16 12 8 4 0 +25C VDS = 10 V TJ = -55C VDS = 15 V 100C

I D, DRAIN CURRENT (AMPS)

4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

50

100

150

200

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.5 VGS = 10 V 0.4 0.3 0.2 0.1 TJ = 100C 25C -55C 2 1.6 1.2 0.8 0.4 0 -50

Figure 4. Breakdown Voltage Variation With Temperature


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 5 mA

10

50

100

150

200

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation With Temperature

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1125

MTP10N10E
SAFE OPERATING AREA INFORMATION
30 I D, DRAIN CURRENT (AMPS) 100 s 10 VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1 ms 10 ms dc 10 s I D, DRAIN CURRENT (AMPS) 40 TJ 150C

30

20

10

0.3

20 40 60 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 7. Maximum Rated Forward Biased Safe Operating Area

Figure 8. Maximum Rated Switching Safe Operating Area

FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal ResistanceGeneral Data and Its Use provides detailed instructions.

SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turnon and turnoff of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than:
TJ(max) TC RJC
1K 500 300 200 100 70 50 30 20 10 7 5 3 2 1 1 2 3 5 10 20 30 50 100 200 300 500 RG, GATE RESISTANCE (OHMS) 1K t, TIME (ns) VDD = 25 V ID = 5 A VGS = 10 V TJ = 25C td(off) tr tf td(on)

Figure 9. Resistive Switching Time versus Gate Resistance

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1126

MTP10N10E
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.05 0.01

D = 0.5 0.2 0.1 P(pk)

SINGLE PULSE 0.01 0.01 0.02 0.03 0.05

t2 DUTY CYCLE, D = t1/t2 0.1 0.2 0.3 0.5 1 2 3 5 t, TIME (ms) 10 20 30

t1

RJC(t) = r(t) RJC RJC = 1.67C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 50 100 200 300 500 100

Figure 10. Thermal Response

COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or half-bridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIs/dt is specified with a maximum value. Higher values of dIs/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak draintosource voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 80% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in ON Semiconductor s test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/s.
15 V 0 VGS IFM dls/dt trr ton IRM 0.25 IRM VDS(pk) VR VDS Vf dVDS/dt VdsL MAX. CSOA STRESS AREA

90% IS 10%

Figure 11. Commutating Waveforms

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1127

MTP10N10E
RGS DUT

30 IS , SOURCE CURRENT (AMPS) 25 20 15 10 5 0 0 100 20 40 60 80 VDS, DRAINTOSOURCE VOLTAGE (VOLTS) 120 V(BR)DSS Vds(t) IO L VDS ID C 4700 F 250 V VDD t RGS 50 VDD tP t, (TIME) dIs/dt 400 A/s + VR IFM + 20 V VR = 80% OF RATED VDS VdsL = Vf + Li dls/dt IS VDS Li

VGS

Figure 13. Commutating Safe Operating Area Test Circuit

Figure 12. Commutating Safe Operating Area (CSOA)

ID(t)

V(BR)DSS WDSR + 1 LIO2 2 V(BR)DSSVDD

Figure 14. Unclamped Inductive Switching Test Circuit

Figure 15. Unclamped Inductive Switching Waveforms

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1128

MTP10N10E
TJ = 25C Coss VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1250 1000 C, CAPACITANCE (pF) 750 500 250 0 20 Ciss 10 8 6 4 ID = RATED ID 2 0 VDS = 30 V 50 V 80 V TJ = 25C

Ciss Coss Crss VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 0 10 20 30

8 12 QG, TOTAL GATE CHARGE (nC)

16

20

Figure 16. Capacitance Variation

Figure 17. Gate Charge versus GateToSource Voltage

+18 V

VDD

1 mA Vin 15 V 47 k 2N3904 2N3904 100 k 47 k 100 FERRITE BEAD 10 V 100 k 0.1 F

SAME DEVICE TYPE AS DUT

DUT

Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10%

Figure 18. Gate Charge Test Circuit

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1129

MTP10N10EL
Preferred Device

Power MOSFET 10 Amps, 100 Volts, Logic Level


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ TC = 25C Continuous @ TC = 100C Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Total Power Dissipation @ TC = 25C (Note 1.) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 10 Adc, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Junction to Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 100 100 15 20 10 6.0 35 40 0.32 1.75 55 to 150 50 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ MTP10N10EL LL Y WW 1 2 3 TO220AB CASE 221A STYLE 5 4

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10 AMPERES 100 VOLTS RDS(on) = 22 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP10N10EL LLYWW 1 Gate 2 Drain 3 Source

TJ, Tstg EAS

= Device Code = Location Code = Year = Work Week

C/W RJC RJA RJA TL 3.13 100 71.4 260 C

ORDERING INFORMATION
Device MTP10N10EL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

1. When surface mounted to an FR4 board using the minimum recommended pad size.

Semiconductor Components Industries, LLC, 2000

1130

November, 2000 Rev. 1

Publication Order Number: MTP10N10EL/D

MTP10N10EL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 5.0 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125C) Forward Transconductance (VDS = 8.0 Vdc, ID = 5.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 80 Vdc, ID = 10 Adc, VGS = 5.0 Vdc) (VDD = 50 Vdc, ID = 10 Adc, VGS = 5.0 Vdc, Rg = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 2.) (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 0.98 0.898 124.7 86 38.7 0.539 1.6 C ns Vdc 11 74 17 38 9.3 2.56 4.4 4.6 20 150 30 80 15 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 1 0 MHz) Ciss Coss Crss 741 175 18.9 1040 250 40 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 5.0 1.85 7.9 2.6 2.3 mhos 1.45 4.0 0.17 2.0 0.22 Vdc mV/C Ohm Vdc V(BR)DSS 100 IDSS IGSS 10 100 100 nAdc 115 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery y Time Vdc (IS = 10 Adc Adc, VGS = 0 Vdc, dIS/dt = 100 A/s)

Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad.) 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 3. Switching characteristics are independent of operating junction temperature.

Ld Ls 7.5 4.5

nH

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1131

MTP10N10EL
TYPICAL ELECTRICAL CHARACTERISTICS
20 ID , DRAIN CURRENT (AMPS) 20 5V 4.5 V 4V 10 3.5 V 5 3V 2V 0 1 2 3 4 5 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) ID , DRAIN CURRENT (AMPS) 15 25C 10 TJ = 100C

TJ = 25C

VGS = 10 V

7V

VDS 5 V -55C

15

2 3 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.35

VGS = 5 V 100C

0.25 TJ = 25C

0.25

0.2

VGS = 5 V

TJ = 25C 0.15

-55C

0.15

10 V

0.05

10 ID, DRAIN CURRENT (AMPS)

15

20

0.1

10 ID, DRAIN CURRENT (AMPS)

15

20

Figure 3. OnResistance versus Drain Current and Temperature


2 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 5 A I DSS , LEAKAGE (nA)

VGS = 0 V

TJ = 125C

1.5

10

100C

0.5

0 -50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

20 40 60 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1132

MTP10N10EL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1800 1600 Ciss 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 Coss Crss 5 0 10 15 20 25 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Crss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Figure 7. Capacitance Variation

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1133

MTP10N10EL
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) 12 QT 8 VGS 90 75 60 45 4 Q1 Q2 TJ = 25C ID = 10 A VDS 4 6 8 30 15 0 10 1000 TJ = 25C ID = 10 A VDS = 100 V VGS = 5 V tr tf 10 td(off) td(on)

100

Q3 0 2 QG, TOTAL GATE CHARGE (nC)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


10 I S , SOURCE CURRENT (AMPS) 8 6 4 2 0 0.5 VGS = 0 V TJ = 25C

0.6

0.7

0.8

0.9

1.0

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1134

MTP10N10EL
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0

VGS = 20 V SINGLE PULSE TC = 25C 10 s 100 s

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

ID = 10A

10

1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10

1 ms 10 ms dc

0.1 0.1

100

25

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.0001 0.001 0.01 t, TIME (SECONDS) t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1 10

t2 DUTY CYCLE, D = t1/t2 0.1

0.01 0.00001

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1135

MTP12P10
Preferred Device

Power MOSFET 12 Amps, 100 Volts


PChannel TO220
This Power MOSFET is designed for medium voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers. Silicon Gate for Fast Switching Speeds Switching Times Specified at 100C Designers Data IDSS, VDS(on), VGS(th) and SOA Specified at Elevated Temperature Rugged SOA is Power Dissipation Limited SourcetoDrain Diode Characterized for Use With Inductive Loads
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Nonrepetitive (tp 50 s) Drain Current Continuous Drain Current Pulsed Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg Value 100 100 20 40 12 28 75 0.6 65 to 150 1.67 62.5 260 C 1 2 Unit Vdc Vdc S Vdc Vpk Adc Watts W/C C C/W RJC RJA TL TO220AB CASE 221A STYLE 5 4 G

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12 AMPERES 100 VOLTS RDS(on) = 300 m


PChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP12P10 LLYWW 3 Source 2 Drain

1 Gate

MTP12P10 LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP12P10 Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1136

November, 2000 Rev. 2

Publication Order Number: MTP12P10/D

MTP12P10
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = Rated VDSS, VGS = 0, TJ = 125C) GateBody Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) GateBody Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100C Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc) DrainSource OnVoltage (VGS = 10 V) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 100C) Forward Transconductance (VDS = 15 V, ID = 6.0 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) S Fi See Figure 10 Ciss Coss Crss 920 575 200 pF VGS(th) RDS(on) VDS(on) gFS 2.0 4.2 3.8 mhos 2.0 1.5 4.5 4.0 0.3 Vdc Ohm Vdc V(BR)DSS IDSS IGSSF IGSSR 10 100 100 100 nAdc nAdc 100 Vdc Adc Symbol Min Max Unit

SWITCHING CHARACTERISTICS (Note 1.) (TJ = 100C) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Total Gate Charge GateSource Charge GateDrain Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) S Fi See Figure 11 (VDD = 25 V, ID = 0.5 Rated ID, RG = 50 ) See Figures 12 and 13 td(on) tr td(off) tf Qg Qgs Qgd 33 (Typ) 16 (Typ) 17 (Typ) 50 150 150 150 50 nC ns

SOURCEDRAIN DIODE CHARACTERISTICS (Note 1.) Forward OnVoltage Forward TurnOn Time Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE (TO204) Internal Drain Inductance (Measured from the contact screw on the header closer to the source pin and the center of the die) Internal Source Inductance (Measured from the source pin, 0.25 from the package to the source bond pad) INTERNAL PACKAGE INDUCTANCE (TO220) Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. Ld 3.5 (Typ) 4.5 (Typ) Ls 7.5 (Typ) nH Ld 5.0 (Typ) nH (IS = Rated R t d ID, VGS = 0) VSD ton trr 4.0 (Typ) 5.5 Vdc

Limited by stray inductance 300 (Typ) ns

Ls

12.5 (Typ)

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1137

MTP12P10
TYPICAL ELECTRICAL CHARACTERISTICS
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)

20 18 -I D, DRAIN CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0 1

VGS = -20 V TJ = 25C

10 V

1.2 1.1 1 0.9 0.8 VDS = VGS ID = 1 mA

8V 7V 6V 5V

2 3 4 5 6 7 8 9 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

10

-50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 1. OnRegion Characteristics


VBR(DSS), DRAIN-TO-SOURCE BREAKDOWN VOLTAGE (NORMALIZED)

Figure 2. GateThreshold Voltage Variation With Temperature


2 1.6 1.2 0.8 0.4 0 -50 VGS = 0 ID = 0.25 mA

20 16 12 8 4 0

25C TJ = -55C 100C

I D, DRAIN CURRENT (AMPS)

VDS = 20 V

8 12 16 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

20

-75

25

50

75

100

125

150

TJ, JUNCTION TEMPERATURE (C)

Figure 3. Transfer Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 4. Normalized Breakdown Voltage versus Temperature


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

0.5 VGS = 15 V 0.4 0.3 0.2 0.1 0 TJ = 100C

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 VGS = 10 V ID = 6 A

25C -55C

12

16

20

24

28

32

36

40

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance versus Drain Current

Figure 6. OnResistance Variation With Temperature

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1138

MTP12P10
SAFE OPERATING AREA INFORMATION
50 10 s I D, DRAIN CURRENT (AMPS) 10 1 ms 10 ms VGS = 20 V SINGLE PULSE TC = 25C 1 dc 0.1 ms I D, DRAIN CURRENT (AMPS) 40 30 20 10 0 MTM/MTP12P06 MTM/MTP12P10 0 10 30 50 70 20 40 60 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 90 100

MTM/MTP12P06 RDS(on) LIMIT PACKAGE LIMIT THERMAL LIMIT MTM/MTP12P10 10 1 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Maximum Rated Forward Biased Safe Operating Area FORWARD BIASED SAFE OPERATING AREA

Figure 8. Maximum Rated Switching Safe Operating Area SWITCHING SAFE OPERATING AREA

The FBSOA curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, Transient Thermal ResistanceGeneral Data and Its Use provides detailed instructions.

The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turnon and turnoff of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than:
TJ(max) TC RJC

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.5 0.3 0.2 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 0.1 0.2 0.5 1 t2 DUTY CYCLE, D = t1/t2 2 5 t, TIME (ms) 10 20 t1 P(pk) RJC(t) = r(t) RJC RJC = 1.67C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 50 100 200 500 1000

0.05 0.03 0.02

0.01 0.01

SINGLE PULSE 0.02

0.05

Figure 9. Thermal Response

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1139

MTP12P10
1600 VGS, GATE SOURCE VOLTAGE (VOLTS) TC = 25C VGS = 0 f = 1 MHz Ciss 0 -2 -4 -6 -8 -10 -12 -14 -16 0 5 10 15 VDS = 30 V 50 V 80 V 20 25 30 35 40 45 50 Qg, TOTAL GATE CHARGE (nC) TJ = 25C ID = 12 A

C, CAPACITANCE (pF)

1200

800

400

Coss Crss

10 30 20 VDS, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

40

Figure 10. Capacitance Variation

Figure 11. Gate Charge versus GateToSource Voltage

RESISTIVE SWITCHING
VDD RL Vout PULSE GENERATOR Rgen 50 Vin z = 50 50 INPUT, Vin 10% PULSE WIDTH DUT OUTPUT, Vout 10% 90% 50% 50% td(on)

ton tr 90% td(off)

toff tf 90%

INVERTED

Figure 12. Switching Test Circuit

Figure 13. Switching Waveforms

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1140

MTP1302
Preferred Device

Power MOSFET 42 Amps, 30 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode Is Characterized for Use In Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 42 Apk, L = 0.25 mH, RG = 25 ) Thermal Resistance Junction to Case JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 30 30 20 20 42 20 126 74 0.592 55 to 150 220 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 TO220AB CASE 221A STYLE 5 S

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42 AMPERES 30 VOLTS RDS(on) = 22 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

MTP1302 LLYWW 3 Source 2 Drain

1 Gate

C/W RJC RJA TL 1.67 62.5 260 C MTP1302 LL Y WW = Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP1302 Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1141

November, 2000 Rev. 1

Publication Order Number: MTP1302/D

MTP1302
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) (VGS = 4.5 Vdc, ID = 5.0 Adc) (VGS = 10 Vdc, ID = 42 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) (VGS = 10 Vdc, ID = 42 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) (VDD = 15 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 Gate Charge (VDS = 24 Vdc, ID = 20 Adc, VGS = 10 Vdc) QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 20 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. ta tb QRR 0.83 0.79 38 19 20 36 1.1 C ns Vdc 7.2 52 45 73 14.5 2.2 8.8 6.8 27 2.2 10 7.2 15 104 90 146 21.8 40.5 nC nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 755 370 102 1162 518 204 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 10 16 0.38 0.82 0.5 0.33 Mhos 19 26 19.5 22 29 Vdc 1.5 2.0 mW Vdc V(BR)DSS 30 IDSS IGSS 100 10 100 nAdc Adc Vdc Symbol Min Typ Max Unit

Reverse Recovery Time

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1142

MTP1302
TYPICAL ELECTRICAL CHARACTERISTICS
40 35 ID, DRAIN CURRENT (AMPS) 30 25 20 15 10 5.0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VGS = 3.0 V TJ = 25C 30 4.0 V ID, DRAIN CURRENT (AMPS) 25 20 15 10 5.0 -55C 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

10 V

5.0 V

VDS 10 V

TJ = 125C

25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on), DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) 0.03 VGS = 10 V TJ = 100C RDS(on), DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 10 15

Figure 2. Transfer Characteristics

TJ = 25C VGS = 4.5 V

0.02

25C

10 V

-55C 0.01

10

15

20

25

30

35

40

20

25

30

35

40

45

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 3. OnResistance versus Drain Current and Temperature


3.0 1000 ID = 20 A 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

2.0

IDSS, LEAKAGE (nA)

TJ = 125C 100C 25C

VGS = 10 V 1.0

10

1.0

-50

-25

25

50

75

100

125

150

0.1

5.0

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1143

MTP1302
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2500 2000 C, CAPACITANCE (pF) 1500 1000 500 0 -10 VDS = 0 V VGS = 0 V -5.0 5.0 0 VGS VDS Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

Crss Ciss Coss Crss 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1144

MTP1302
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 14 12 10 8.0 6.0 4.0 2.0 0 Q1 Q2 ID = 20 A TJ = 25C VDS VGS QT 18 15 12 9.0 6.0 3.0 1000 VDD = 15 V ID = 20 A VGS = 10 V TJ = 25C

100

tf tr td(off) td(on)

10

Q3

0 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 22 24 26 28 30 QG, TOTAL GATE CHARGE (nC)

1.0

1.0

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 18 I S , SOURCE CURRENT (AMPS) 16 14 12 10 8.0 6.0 4.0 2.0 0 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


1145

MTP1302
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

1000 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID , DRAIN CURRENT (AMPS) VGS = 10 V SINGLE PULSE TC = 25C

220 200 180 160 140 120 100 80 60 40 20 0 ID = 42 A

100

10 ms 100 ms

10

1.0 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100

1.0

0.1

25

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1146

MTP1302
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 0.0001 0.001 0.01 t, TIME (s) 0.1 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.01

0.00001

1.0

10

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1147

MTP1306
Preferred Device

Power MOSFET 75 Amps, 30 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance JunctiontoCase JunctiontoAmbient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5.0 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS 280 MTP1306 LL Y WW Value 30 30 20 20 75 59 225 150 1.2 55 to 150 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 3 TO220AB CASE 221A STYLE 5 S

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75 AMPERES 30 VOLTS RDS(on) = 6.5 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

MTP1306 LLYWW 3 Source 2 Drain

1 Gate

C/W RJC RJA TL 0.8 62.5 260 C

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP1306 Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1148

November, 2000 Rev. 1

Publication Order Number: MTP1306/D

MTP1306
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 38 Adc) (VGS = 5.0 Vdc, ID = 38 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 75 Adc) (VGS = 10 Vdc, ID = 38 Adc, TJ = 150C) Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) (VDD = 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time Adc VGS = 0 Vdc, Vdc (IS = 20 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. trr ta tb QRR VSD 0.75 0.64 84 35 53 0.13 1.1 C ns Vdc 17 170 68 145 50 8.3 25.3 17.2 35 340 136 290 70 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2560 1305 386 3584 1827 772 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 15 0.44 55 0.5 0.38 mhos 5.8 7.4 6.5 8.5 Vdc 1.5 2.0 mW Vdc V(BR)DSS 30 IDSS IGSS 10 100 100 nAdc Adc Vdc Symbol Min Typ Max Unit

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1149

MTP1306
TYPICAL ELECTRICAL CHARACTERISTICS
150 125 TJ = 25C 100 75 50 25 0 180 5.0 V ID , DRAIN CURRENT (AMPS) 4.0 V 160 140 120 100 80 60 40 20 0 0.5 1.0 1.75 0.25 0.75 1.25 1.5 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2.0 0 2.0 125C TJ = -55C 2.5 3.0 3.5 4.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 4.5 25C VDS 10 V

VGS = 10 V

I D , DRAIN CURRENT (AMPS)

Figure 1. OnRegion Characteristics


0.010 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 TJ = 100C 25C -55C VGS 10 V RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.009 TJ = 25C 0.008 0.007 0.006 0.005 0.004 10 V VGS = 5.0 V

20

40

60 100 80 ID, DRAIN CURRENT (AMPS)

120

140

20 30 40

50

60 70 80 90 100 110 120 130 140 150 ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


2.0 VGS = 10 V ID = 38 A I DSS , LEAKAGE (nA) 1.5 1000 10,000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

TJ = 125C

1.0

100

0.5

100C

0 -50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

10

5.0

10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

30

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1150

MTP1306
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
9000 8000 C, CAPACITANCE (pF) 7000 6000 5000 4000 3000 2000 1000 0 -10 -5.0 VGS 0 5.0 10 15 20 Ciss Coss Crss VDS 25 Crss VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

VGS OR VDS, GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1151

MTP1306
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 18 15 7.5 QT 5.0 Q1 2.5 Q3 0 0 10 VDS 20 30 40 QG, TOTAL GATE CHARGE (nC) Q2 VGS 12 10,000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 15 V ID = 75 A VGS = 5.0 V TJ = 25C

9.0 6.0 TJ = 25C ID = 75 A 50 60 3.0 0

t, TIME (ns)

1000

100

td(off) td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100

tr tf

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
20 18 IS , SOURCE CURRENT (AMPS) 16 14 12 10 8.0 6.0 4.0 2.0 0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.45

0.50

0.55

0.60

0.65

0.70

0.75

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

http://onsemi.com
1152

MTP1306
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

1000 I D , DRAIN CURRENT (AMPS)

EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

100

VGS = 10 V SINGLE PULSE TC = 25C 1.0 ms 10 ms dc

280 240 200 160 120 80 40 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 ID = 75 A

10

1.0

0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1153

MTP1306
1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1154

MTP15N06V
Preferred Device

Power MOSFET 15 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Single Pulse (tp 50 s) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 20 25 15 8.7 45 55 0.5 55 to 175 113 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1 4 G S

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15 AMPERES 60 VOLTS RDS(on) = 120 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP15N06V LLYWW 1 Gate 2 Drain 3 Source

RJC RJA TL

2.73 62.5 260

C/W C

MTP15N06V LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP15N06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1155

November, 2000 Rev. 3

Publication Order Number: MTP15N06V/D

MTP15N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 15 Adc) (ID = 7.5 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 15 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 15 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 15 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 1.05 1.5 59.3 46 13.3 0.165 1.6 C ns Vdc 7.6 51 18 33 14.4 2.8 6.4 6.1 20 100 40 70 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 469 148 35 660 200 60 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 4.0 2.0 6.2 2.2 1.9 mhos 2.7 5.0 0.08 4.0 0.12 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 67 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1156

MTP15N06V
TYPICAL ELECTRICAL CHARACTERISTICS
30 I D , DRAIN CURRENT (AMPS) 25 20 15 10 5 0 5V 6V TJ = 25C 9V 30 I D , DRAIN CURRENT (AMPS) 25 20 15 10 5 0 VDS 10 V

VGS = 10 V

8V 7V

TJ = 100C 25C -55C

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.20

VGS = 10 V

0.13

TJ = 25C

0.14

TJ = 100C

0.11

0.09

VGS = 10 V

25C 0.08 -55C

0.07

15 V

0.02

10 15 20 ID, DRAIN CURRENT (AMPS)

25

30

0.05

10 15 20 ID, DRAIN CURRENT (AMPS)

25

30

Figure 3. OnResistance versus Drain Current and Temperature


100 VGS = 10 V ID = 7.5 A 1.6 I DSS , LEAKAGE (nA)

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

1.2

TJ = 125C

0.8

0.4 -50

-25

25

50

75

100

125

150

175

10

TJ, JUNCTION TEMPERATURE (C)

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1157

MTP15N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1500 1200 C, CAPACITANCE (pF) 900 600 300 0 Ciss Coss Crss 10 5 VGS 0 VDS 5 10 15 20 25 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1158

MTP15N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 0 Q3 3 VDS 6 9 12 QT, TOTAL CHARGE (nC) ID = 15 A TJ = 25C VGS Q1 Q2 QT 60 50 40 30 20 10 0 15 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 15 A VGS = 10 V TJ = 25C tr tf

t, TIME (ns)

100

td(off) 10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


15 12 9 6 3 0 0.5 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.7

0.9

1.1

1.3

1.5

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1159

MTP15N06V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 120 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 s 100 80 60 40 20 0 25 50 75 100 125 150 175 ID = 15 A

VGS = 10 V SINGLE PULSE TC = 25C

10 100 s 1 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms dc

0.1

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

0.1

P(pk)

t2 DUTY CYCLE, D = t1/t2 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1160

MTP15N06VL
Preferred Device

Power MOSFET 15 Amps, 60 Volts, Logic Level


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 25 15 12 53 60 0.40 55 to 175 113 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C C mJ 1 C/W C MTP15N06VL LL Y WW 2 S G

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15 AMPERES 60 VOLTS RDS(on) = 85 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TO220AB CASE 221A STYLE 5

MTP15N06VL LLYWW 1 Gate 2 Drain 3 Source

RJC RJA TL

2.5 62.5 260

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP15N06VL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1161

November, 2000 Rev. 2

Publication Order Number: MTP15N06VL/D

MTP15N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 7.5 Adc) DraintoSource OnVoltage (VGS = 5.0 Vdc, ID = 15 Adc) (VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 15 Adc, VGS = 5.0 Vdc) (VDD = 30 Vdc, ID = 15 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 15 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 15 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die.) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 0.96 0.85 63 42 21 0.140 1.6 C ns Vdc 11 150 27 70 32 3.0 7.0 11 20 300 50 140 40 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 570 180 45 800 250 90 pF (Cpk 2.0) (Note 3.) VGS(th) 1.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 8.0 10 1.5 1.3 mhos 0.075 0.085 Vdc 1.5 4.0 2.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 68 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1162

MTP15N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
50 45 I D , DRAIN CURRENT (AMPS) 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 50 7V I D , DRAIN CURRENT (AMPS) 6V 5V 45 40 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 100C VDS 5 V TJ = -55C 25C

TJ = 25C

VGS = 10V

9V

8V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0

VGS = 5 V

0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0

TJ = 100C 25C -55C

TJ = 25C

VGS = 5 V 10 V

15 25 10 20 ID, DRAIN CURRENT (AMPS)

30

35

10

15 25 20 30 35 ID, DRAIN CURRENT (AMPS)

40

45

50

Figure 3. OnResistance versus Drain Current and Temperature


2.0 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 0 0 I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 7.5 A

VGS = 0 V

TJ = 125C

10

100C

10

15

20

25

30

35

40

45

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1163

MTP15N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2200 VDS = 0 V 2000 Ciss 1800 C, CAPACITANCE (pF) 1600 1400 1200 Crss 1000 800 600 400 200 0 10 Crss 0 5 5 VGS VDS 10 15 Coss 20 25 VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Ciss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1164

MTP15N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 Q3 5 10 15 VDS 20 25 Qg, TOTAL GATE CHARGE (nC) TJ = 25C ID = 15 A 30 Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 35 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 15 A VDD = 30 V VGS = 5 V

t, TIME (ns)

100

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


15 14 TJ = 25C 13 VGS = 0 V 12 11 10 9 8 7 6 5 4 3 2 1 0 0.5 0.55 0.6

I S , SOURCE CURRENT (AMPS)

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1165

MTP15N06VL
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 120 110 100 90 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 175

10 s

10 100 s 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

0.1

E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 15 V SINGLE PULSE TC = 25C

ID = 15 A

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 0.05

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1166

MTP20N06V
Preferred Device

Power MOSFET 20 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 20 25 20 13 70 60 0.40 55 to 175 200 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 C/W RJC RJA TL 2.5 62.5 260 C MTP20N06V LL Y WW TO220AB CASE 221A STYLE 5 4 G S

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20 AMPERES 60 VOLTS RDS(on) = 80 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP20N06V LLYWW 1 Gate 2 Drain 3 Source

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP20N06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

1167

January, 2001 Rev. 3

Publication Order Number: MTP20N06V/D

MTP20N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 10 Adc, TJ = 150C) Forward Transconductance (VDS = 6.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 20 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 20 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.05 0.96 60 52 8.0 0.172 1.6 C ns Vdc 8.7 77 26 46 28 4.0 9.0 8.0 20 150 50 90 40 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 590 180 40 830 250 80 pF (Cpk 2.0) (Note 3.) VGS(th) 2.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 6.0 8.0 2.0 1.9 mhos 0.065 0.080 Vdc 2.8 5.0 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 69 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1168

MTP20N06V
TYPICAL ELECTRICAL CHARACTERISTICS
40 I D , DRAIN CURRENT (AMPS) 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 5V 4V 10 6V 40 8V I D , DRAIN CURRENT (AMPS) 7V 35 30 25 20 15 10 5 0 2 3 4 5 6 7 8 9 100C

VGS = 10V TJ = 25C

9V

VDS 10 V

TJ = -55C

25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0

VGS = 10 V

0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0

TJ = 25C

TJ = 100C 25C -55C

VGS = 10 V

15 V

10

15 25 20 30 ID, DRAIN CURRENT (AMPS)

35

40

10

20 30 15 25 ID, DRAIN CURRENT (AMPS)

35

40

Figure 3. OnResistance versus Drain Current and Temperature


2.0 VGS = 10 V ID = 10 A I DSS , LEAKAGE (nA) 35 30 25 20 15 10 5 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 0 0

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.75 1.5

VGS = 0 V TJ = 125C

1.25 1

0.75 0.5

0.25 0 -50

100C 50 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1169

MTP20N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1600 1400 Ciss C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 0 Crss VDS Coss 5 10 15 20 25 Ciss Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

VGS

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1170

MTP20N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 5 10 Q3 VDS 15 20 Qg, TOTAL GATE CHARGE (nC) TJ = 25C ID = 20 A 25 Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 30 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 20 A VDD = 30 V VGS = 10 V tr tf td(off) 10 td(on)

t, TIME (ns)

100

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


20 18 I S , SOURCE CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 TJ = 25C VGS = 0 V

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1171

MTP20N06V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 200 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 180 160 140 120 100 80 60 40 20 0 25 50 75 100 125 150 175

VGS = 20 V SINGLE PULSE TC = 25C 100 s

ID = 20 A

10 s

10

1 ms

10 ms dc

1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1

0.1

1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 0.05 P(pk)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1172

MTP20N15E
Preferred Device

Power MOSFET 20 Amps, 150 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 120 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 0.3 mH) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 150 150 20 32 20 12 60 112 0.9 55 to 150 60 Unit Vdc Vdc Vdc Adc TO220AB CASE 221A STYLE 5 1 4

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20 AMPERES 150 VOLTS RDS(on) = 130 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

Watts W/C C mJ 2 3

MTP20N15E LLYWW 3 Source 2 Drain

1 Gate

C/W RJC RJA TL 1.1 62.5 260 C

MTP20N15E LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP20N15E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

1173

January, 2001 Rev. 0

Publication Order Number: MTP20N15E/D

MTP20N15E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Collector Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 120 Vdc, ID = 20 Adc, VGS = 10 Vdc) (VDD = 75 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 20 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. ta tb QRR 160 123 36.5 1.1 1.5 C ns Vdc 11 77 33 49 39.1 7.5 22 17 25 153 67 97 55.9 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1133 332 105 1627 474 174 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 8.0 11 2.8 2.6 mhos TBD 0.12 4.0 0.13 Vdc mV/C Ohm Vdc V(BR)DSS 150 IDSS IGSS(f) IGSS(r) 10 100 100 100 nAdc TBD Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1174

MTP20N20E
Preferred Device

Power MOSFET 20 Amps, 200 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 200 200 20 40 20 12 60 125 1.0 55 to 150 600 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 3 TO220AB CASE 221A STYLE 5 4

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20 AMPERES 200 VOLTS RDS(on) = 160 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP20N20E LLYWW 3 Source 2 Drain

1 Gate

C/W RJC RJA TL 1.00 62.5 260 C

MTP20N20E LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP20N20E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1175

November, 2000 Rev. 3

Publication Order Number: MTP20N20E/D

MTP20N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 10 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 20 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 20 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 20 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 1.0 0.82 239 136 103 2.09 1.35 C ns Vdc 17 86 50 60 54 12 24 22 40 180 100 120 75 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1880 378 68 2700 535 100 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 8.0 11 3.84 3.36 mhos 7.0 0.12 4.0 0.16 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 10 100 100 nAdc 263 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure Fi 14) (See

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1176

MTP20N20E
TYPICAL ELECTRICAL CHARACTERISTICS
40 I D , DRAIN CURRENT (AMPS) 40 VGS = 10 V 9V 8V 7V I D , DRAIN CURRENT (AMPS) 35 30 25 20 15 10 5 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 100C

TJ = 25C

VDS 10 V

TJ = -55C 25C

30

20

6V

10

5V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.35 VGS = 10 V 0.30 0.25 0.20 0.15 0.10 0.05 0 4 8 25C TJ = 100C 0.17 0.16 0.15 0.14 0.13 0.12 0.11 0.10 0 4

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 10 V

15 V

-55C 16 24 12 20 28 ID, DRAIN CURRENT (AMPS) 32 36 40

12 16 20 24 28 ID, DRAIN CURRENT (AMPS)

32

36

40

Figure 3. OnResistance versus Drain Current and Temperature


2.4 2.0 1.6 1.2 0.8 0.4 -50 VGS = 10 V ID = 10 A I DSS , LEAKAGE (nA) 1000 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C 100C

100

25C

10

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

50 150 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

200

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1177

MTP20N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
5000 Ciss 4000 C, CAPACITANCE (pF) 3000 2000 1000 0 10

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VDS = 0 V

VGS = 0 V

TJ = 25C

Crss Ciss

Coss 5 0 5 10 15 20 25

VGS

VDS

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1178

MTP20N20E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT Q1 8 6 4 2 Q3 0 0 10 30 40 20 QG, TOTAL GATE CHARGE (nC) 50 VDS ID = 20 A TJ = 25C Q2 VGS 180 150 120 90 60 30 0 60 1000 VDD = 100 V ID = 20 A VGS = 10 V TJ = 25C t, TIME (ns) 100 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLT)

10

tr tf td(off) td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


20 16 12 8 4 0 0.50 0.55 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

1.0

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1179

MTP20N20E
SAFE OPERATING AREA
E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 600 500 400 300 200 100 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 ID = 20 A

10

10s 100s 1ms 10ms dc

1.0

0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 1.0 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000

0.01 0.1

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (ms) t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1180

MTP23P06V
Preferred Device

Power MOSFET 23 Amps, 60 Volts


PChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 23 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 25 23 15 81 90 0.60 55 to 175 794 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1 4 G S

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23 AMPERES 60 VOLTS RDS(on) = 120 m


PChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP23P06V LLYWW 3 Source 2 Drain

RJC RJA TL

1.67 62.5 260

C/W C

1 Gate

MTP23P06V LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP23P06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1181

November, 2000 Rev. 2

Publication Order Number: MTP23P06V/D

MTP23P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 11.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 23 Adc) (VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150C) Forward Transconductance (VDS = 10.9 Vdc, ID = 11.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 23 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 23 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 23 Adc, VGS = 0 Vdc) (IS = 23 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 23 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 2.2 1.8 142.2 100.5 41.7 0.804 3.5 C ns Vdc 13.8 98.3 41 62 38 7.0 18 14 30 200 80 120 50 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1160 380 105 1620 530 210 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 5.0 11.5 3.3 3.2 Mhos 2.8 5.3 0.093 4.0 0.12 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 60.5 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1182

MTP23P06V
TYPICAL ELECTRICAL CHARACTERISTICS
50 I D , DRAIN CURRENT (AMPS) 40 30 20 10 0 6V 40 8V 9V 7V I D , DRAIN CURRENT (AMPS) 35 30 25 20 15 10 5 10 0 2 3 4 5 6 7 8

TJ = 25C

VGS = 10V

VDS 10 V

TJ = -55C 25C 100C

5V 4V 0 2 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0

VGS = 10 V

0.12 0.115 0.11 0.105 0.1 0.095 0.09 0.085 0.08 0

TJ = 100C

TJ = 25C

25C

VGS = 10 V

-55C

15 V

10

15 20 25 30 ID, DRAIN CURRENT (AMPS)

35

40

45

10

15 20 30 35 25 ID, DRAIN CURRENT (AMPS)

40

45

50

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 1 0 VGS = 10 V ID = 11.5 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

10

TJ = 125C

50 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1183

MTP23P06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4000 Ciss C, CAPACITANCE (pF) 3000 Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

2000 Ciss Coss 10 5 VGS 0 Crss VDS 5 10 15 20 25

1000

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1184

MTP23P06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 5 Q3 10 15 20 VDS 25 30 TJ = 25C ID = 23 A 35 Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 40 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 23 A VDD = 30 V VGS = 10 V

t, TIME (ns)

100

tr tf td(off) td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


25 20 15 10 5 0 TJ = 25C VGS = 0 V

I S , SOURCE CURRENT (AMPS)

0.25

0.5

0.75

1.25

1.5

1.75

2.25

2.5

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1185

MTP23P06V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 800 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 700 600 500 400 300 200 100 0 25 50 75 100 125 150 175

VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms 10 ms dc

ID = 23 A

10

1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

0.1

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1186

MTP27N10E
Preferred Device

Power MOSFET 27 Amps, 100 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, IL = 27 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 100 100 20 40 27 17 95 104 0.83 55 to 150 109 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 3 TO220AB CASE 221A STYLE 5 4

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27 AMPERES 100 VOLTS RDS(on) = 70 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP27N10E LLYWW 3 Source 2 Drain

1 Gate

C/W RJC RJA TL 1.2 62.5 260 C

MTP27120E LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP27N10E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1187

November, 2000 Rev. 1

Publication Order Number: MTP27N10E/D

MTP27N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 13.5 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 27 Adc) (VGS = 10 Vdc, ID = 13.5 Adc, TJ = 125C) Forward Transconductance (VDS = 7.7 Vdc, ID = 13.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 27 Adc, VGS = 10 Vdc) (VDD = 50 Vdc, ID = 27 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 27 Adc, VGS = 0 Vdc) (IS = 27 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 27 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 3.5 4.5 7.5 nH nH ta tb QRR 1.0 0.94 126 98 28 0.685 1.5 C ns Vdc 13 142 29 59 41 9.0 25 22 30 280 60 120 60 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1131 468 186 1580 660 370 pF (Cpk 2.0) (Note 3.) VGS(th) 2.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 6.0 11 2.3 2.0 mhos 0.058 0.07 Vdc 3.1 7.0 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 100 IDSS IGSS 10 100 100 nAdc 120 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1188

MTP27N10E
TYPICAL ELECTRICAL CHARACTERISTICS
60 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 0 1 2 7V 6V 5V 3 5 7 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 9 10 60 I D , DRAIN CURRENT (AMPS) 9V 50 100C 40 30 20 10 0 TJ = -55C

TJ = 25C

VGS = 10 V

VDS 10 V

25C

8V

4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0 10 30 20 40 ID, DRAIN CURRENT (AMPS) 50 60 -55C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.08 0.075 0.07 0.065 0.06 0.055 0.05 0.045 0.04 0

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

TJ = 25C

VGS = 10 V

25C

15 V

10

20 30 40 ID, DRAIN CURRENT (AMPS)

50

60

Figure 3. OnResistance versus Drain Current and Temperature


2.4 2.2 2.0 1.8 I DSS , LEAKAGE (nA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 1 0 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 13.5 A

VGS = 0 V TJ = 125C

100C 10

2 4 6 8 3 5 7 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

10

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1189

MTP27N10E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
3500 3000 C, CAPACITANCE (pF) 2500 2000 1500 1000 500 0 15 Crss 10 5 VGS 0 VDS 5 10 15 20 25 Crss Ciss Coss Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1190

MTP27N10E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 5 Q3 10 VDS 25 15 20 30 35 QG, TOTAL GATE CHARGE (nC) 40 Q1 Q2 TJ = 25C ID = 27 A 60 QT VGS 54 48 42 36 30 24 18 12 6 0 45 1000 VDD = 50 V ID = 27 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

tr tf

10

td(off) td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


30 25 I S , SOURCE CURRENT (AMPS) 20 15 10 5 0 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 1.05 1.1 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1191

MTP27N10E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 100 10 1.0 0.1 120 10s E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 80 60 40 20 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150

VGS = 20 V SINGLE PULSE TC = 25C

ID = 27 A

100s 1ms 10ms

dc

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 1.0 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.02 P(pk) 0.05 t1 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.01 SINGLE PULSE 0.01 1.0E-05

t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

1.0E-04

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1192

MTP2955V
Preferred Device

Power MOSFET 12 Amps, 60 Volts


PChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 25 12 8.0 42 60 0.40 55 to 175 216 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1 C/W RJC RJA TL 2.5 62.5 260 C MTP2955V LL Y WW = Device Code = Location Code = Year = Work Week 4 G S

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12 AMPERES 60 VOLTS RDS(on) = 230 m


PChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP2955V LLYWW 3 Source 2 Drain

1 Gate

ORDERING INFORMATION
Device MTP2955V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1193

November, 2000 Rev. 4

Publication Order Number: MTP2955V/D

MTP2955V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 12 Adc) (VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150C) Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 12 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 4.5 nH nH ta tb QRR 1.8 1.5 115 90 25 0.53 3.0 C ns Vdc 15 50 24 39 19 4.0 9.0 7.0 30 100 50 80 30 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 550 200 50 700 280 100 pF (Cpk 2.0) (Note 3.) VGS(th) 2.0 (Cpk 1.5) (Note 3.) RDS(on) VDS(on) gFS 3.0 5.0 2.9 2.5 mhos 0.185 0.230 Vdc 2.8 5.0 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 58 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1194

MTP2955V
TYPICAL ELECTRICAL CHARACTERISTICS
25 I D , DRAIN CURRENT (AMPS) 20 15 10 5 0 7V 24 9V 8V I D , DRAIN CURRENT (AMPS) 21 18 15 12 9 6 3 10 0 2 3 4 5 6 7 8 9 10

TJ = 25C

VGS = 10 V

VDS 10 V

TJ = -55C 25C

100C

6V

5V 0 1 2 3 4 5 6 7 8 9

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 3 6 9 18 15 12 ID, DRAIN CURRENT (AMPS) 21 24 25C -55C VGS = 10 V TJ = 100C

0.250 0.225

TJ = 25C VGS = 10 V

0.200 0.175

0.150 0.125 0.100

15 V

0.075 0.050 0 3 6 9 18 12 15 ID, DRAIN CURRENT (AMPS) 21 24

Figure 3. OnResistance versus Drain Current and Temperature


2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 10 0 VGS = 10 V ID = 6 A I DSS , LEAKAGE (nA) 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

TJ = 125C 100 100C

10 30 40 20 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1195

MTP2955V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1800 1600 C, CAPACITANCE (pF) 1400 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 10 Ciss Coss Crss 15 20 25 Ciss Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1196

MTP2955V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 2 Q3 4 6 8 10 12 14 VDS 16 18 QT, TOTAL CHARGE (nC) Q1 Q2 VGS QT 30 27 24 21 18 15 12 ID = 12 A 9 TJ = 25C 6 3 0 20 1000 VDD = 30 V ID = 12 A VGS = 10 V TJ = 25C tr tf td(off) td(on) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


12 11 I S , SOURCE CURRENT (AMPS) 10 9 8 7 6 5 4 3 2 1 0 0.5 VGS = 0 V TJ = 25C

0.7

0.9

1.1

1.3

1.5

1.7

1.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1197

MTP2955V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 225 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 200 175 150 125 100 75 50 25 0 25 50 75 100 125 150 175 ID = 12 A

VGS = 15 V SINGLE PULSE TC = 25C

10 100 s 1 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms dc

0.1

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

P(pk)

0.01 1.0E-05

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1198

MTP29N15E
Preferred Device

Power MOSFET 29 Amps, 150 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 29 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 150 150 20 40 29 19 102 125 1.0 55 to 150 421 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 2 Drain C/W RJC RJA TL 1.0 62.5 260 C MTP29N15E LL Y WW = Device Code = Location Code = Year = Work Week 1 2 TO220AB CASE 221A STYLE 5 4 S

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29 AMPERES 150 VOLTS RDS(on) = 70 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP29N15E LLYWW 3 Source

1 Gate

ORDERING INFORMATION
Device MTP29N15E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1199

November, 2000 Rev. 2

Publication Order Number: MTP29N15E/D

MTP29N15E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ =125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 14.5 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 29 Adc) (VGS = 10 Vdc, ID = 14.5 Adc, TJ = 125C) Forward Transconductance (VDS = 8.6 Vdc, ID = 14.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 120 Vdc, ID = 29 Adc, VGS = 10 Vdc) (VDD = 75 Vdc, ID = 29 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 29 Adc, VGS = 0 Vdc) (IS = 29 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 29 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH trr ta tb QRR VSD 0.92 0.84 174 126 48 1.4 1.3 C ns Vdc 19 95 90 85 83 12 37 23 40 190 180 170 120 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2300 450 130 3220 630 260 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 10 20 2.4 2.1 mhos 0.054 0.07 Vdc 2.7 5.4 4.0 Vdc mV/C Ohms V(BR)DSS 150 IDSS IGSS 10 100 100 nAdc 151 Vdc mV/C Adc Symbol Min Typ Max Unit

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1200

MTP29N15E
TYPICAL ELECTRICAL CHARACTERISTICS
60 60 ID, DRAIN CURRENT (AMPS) 50 40 30 20 10 9 10 0 2 3 TJ = 100C -55C 4 5 6 7 8 25C

ID , DRAIN CURRENT (AMPS)

VGS = 10 V 9V 50 TJ = 25C 8V 40 30 20 10 0 0 1 2 3 4 5

7V

6.5 V

VDS 10 V

6V

5.5 V 5V 4.5 V 4V 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0

VGS = 10 V TJ = 100C

0.07 0.065 0.06 0.055 0.05 0.045 0.04 0 10 20 40 30 ID, DRAIN CURRENT (AMPS) 50 60 TJ = 25C VGS = 10 V 15 V

25C

-55C

10

20

30

40

50

60

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


2.25 2.0 1.75 1.5 1.25 1.0 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 0.1 0 VGS = 10 V ID = 14.5 A IDSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

TJ = 125C 100C

10

25C

20

TJ, JUNCTION TEMPERATURE (C)

100 120 140 60 80 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

160

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1201

MTP29N15E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
7500 VDS = 0 V VGS = 0 V 7000 C 6500 iss 6000 5500 5000 Crss 4500 4000 3500 3000 2500 2000 1500 1000 Crss 500 0 -10 -5 0 5 VGS VDS

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

C, CAPACITANCE (pF)

Ciss

Coss 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1202

MTP29N15E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 Q3 0 10 20 30 40 50 VDS 60 70 80 90 Qg, TOTAL GATE CHARGE (nC) TJ = 25C ID = 29 A Q1 Q2 QT VGS 120 100 80 60 40 20 0 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100 t, TIME (ns)

tf td(off) td(on)

tr

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
30 I S , SOURCE CURRENT (AMPS) 25 20 15 10 5 0 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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1203

MTP29N15E
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the
1000 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms 100 ms 1 ms 10 ms dc

total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature.
450 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 29 A

100

10

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100

0.1

1000

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1204

MTP29N15E
TYPICAL ELECTRICAL CHARACTERISTICS
1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 1E-05 1E-04 1E-03 1E-02 t, TIME (seconds) P(pk) t2 DUTY CYCLE, D = t1/t2 1E-01 t1 RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+00 1E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1205

MTP29N15E
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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1206

MTP2P50E
Preferred Device

Power MOSFET 2 Amps, 500 Volts


PChannel TO220
This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over time. In addition, this Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Robust High Voltage Termination Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 500 500 20 40 2.0 1.6 6.0 75 0.6 55 to 150 80 Unit Vdc 4 Vdc Vdc Vpk Adc Apk 1 Watts W/C C mJ MTP2P50E LL Y WW 2 3

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2 AMPERES 500 VOLTS RDS(on) = 6


PChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TO220AB CASE 221A STYLE 5

MTP2P50E LLYWW 3 Source 2 Drain

1 Gate

= Device Code = Location Code = Year = Work Week

C/W RJC RJA TL 1.67 62.5 260 C

ORDERING INFORMATION
Device MTP2P50E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1207

November, 2000 Rev. 3

Publication Order Number: MTP2P50E/D

MTP2P50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 2.0 Adc) (ID = 1.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 400 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 250 Vdc, ID = 2.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr 2 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 2.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 2.3 1.85 223 161 62 1.92 3.5 C ns Vdc 12 14 21 19 19 3.7 7.9 9.9 24 28 42 38 27 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 845 100 26 1183 140 52 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 0.5 9.5 14.4 12.6 mhos 3.0 4.0 4.5 4.0 6.0 Vdc mV/C Ohm Vdc V(BR)DSS 500 IDSS IGSS 10 100 100 nAdc 564 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1208

MTP2P50E
TYPICAL ELECTRICAL CHARACTERISTICS
4 3.5 I D , DRAIN CURRENT (AMPS) 3 2.5 2 1.5 1 0.5 0 0 4 8 12 16 20 5V 4 3.5 I D , DRAIN CURRENT (AMPS) 3 2.5 2 1.5 1 0.5 4V 24 28 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7

TJ = 25C

VGS = 10 V

7V 8V 6V

VDS 10 V 100C 25C

TJ = -55C

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS) R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

10 8 6 4

VGS = 10 V TJ = 100C

6 5.75 5.5 5.25 5 4.75 4.5 4.25 4 0

TJ = 25C

25C

VGS = 10 V 15 V

-55C 2

0.5

2 2.5 1.5 3 ID, DRAIN CURRENT (AMPS)

3.5

0.5

2 3 1.5 2.5 ID, DRAIN CURRENT (AMPS)

3.5

Figure 3. OnResistance versus Drain Current and Temperature


2 RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) VGS = 10 V ID = 1 A 1.5 I DSS , LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 0 V TJ = 125C 100C

10 25C

0.5 -50

-25

25

50

75

100

125

150

50

100

150

200

250

300

350

400

450

500

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1209

MTP2P50E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1800 1600 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 0 Crss 5 Coss 10 15 20 25 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 Crss Ciss VDS = 0 V Ciss C, CAPACITANCE (pF) 100 Coss 10 Crss VGS = 0 V TJ = 25C

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

1000

VGS = 0 V TJ = 25C

Ciss

VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance Variation

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1210

MTP2P50E
VGS, GATETOSOURCE VOLTAGE (VOLTS) 12 10 8 Q1 6 4 2 0 Q3 0 2 4 6 8 10 12 14 QT, TOTAL CHARGE (nC) VDS 16 18 Q2 ID = 2 A TJ = 25C 150 100 50 0 20 VGS 200 QT 300 250 1000 VDS , DRAINTOSOURCE VOLTAGE (VOLTS) VDD = 250 V ID = 2 A VGS = 10 V TJ = 25C

t, TIME (ns)

100 tf

td(off)

tr 10 1 10

td(on) 100

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


2 1.6 1.2 0.8 0.4 0 0.6 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.8

1.2

1.4

1.6

1.8

2.2

2.4

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1211

MTP2P50E
SAFE OPERATING AREA
10 I D , DRAIN CURRENT (AMPS) 80 10 s E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms

ID = 2 A

60

40

0.1

10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100

dc

20

0.01

1000

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.01 0.05 0.02 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

SINGLE PULSE 0.01 1.0E-05

1.0E-04

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1212

MTP3055V
Preferred Device

Power MOSFET 12 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Onresistance Area Product about Onehalf that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than EFET Predecessors Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Static Parameters are the Same for both TMOS V and TMOS EFET
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 20 25 12 7.3 37 48 0.32 55 to 175 72 Unit Vdc Vdc 4 Vdc Vpk Adc Apk Watts W/C C mJ MTP3055V LL Y WW TO220AB CASE 221A STYLE 5 1

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12 AMPERES 50 VOLTS RDS(on) = 150 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP3055V LLYWW 3 Source 2 Drain

1 Gate

RJC RJA TL

3.13 62.5 260

C/W C

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP3055V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

1213

February, 2001 Rev. 3

Publication Order Number: MTP3055V/D

MTP3055V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 6.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 12 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 1.0 0.91 56 40 16 0.128 1.6 C ns Vdc 7.0 34 17 18 12.2 3.2 5.2 5.5 10 60 30 50 17 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 410 130 25 500 180 50 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 4.0 1.3 5.0 2.2 1.9 mhos 2.7 5.4 0.10 4.0 0.15 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 65 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 15)

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1214

MTP3055V
TYPICAL ELECTRICAL CHARACTERISTICS
24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 5V 4 4V 0 0 1 2 3 4 5 0 2 3 4 5 6 7 8 9 10 24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 4

TJ = 25C

VGS = 10 V 9V

8V

VDS 10 V

TJ = -55C 25C

7V

100C

6V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.30 0.25 0.20 TJ = 100C 0.15 25C 0.10 0.05 0 -55C VGS = 10 V

0.15 0.14 0.13 0.12 0.11 0.10 0.09 0.08 0

TJ = 25C

VGS = 10 V

15 V

12 8 16 ID, DRAIN CURRENT (AMPS)

20

24

12 16 8 ID, DRAIN CURRENT (AMPS)

20

24

Figure 3. OnResistance versus Drain Current and Temperature


1.6 1.4 1.2 1.0 0.8 0.6 -50 1 VGS = 10 V ID = 6 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V

10

TJ = 125C

-25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

10 30 40 20 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1215

MTP3055V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10 5 VGS 0 VDS 5 10 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

Ciss Coss Crss 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1216

MTP3055V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 Q3 0 0 1 2 3 4 5 6 7 8 9 QT, TOTAL CHARGE (nC) VDS 10 Q1 Q2 VGS QT 60 50 40 30 20 ID = 12 A 10 TJ = 25C 11 12 0 13 1000 VDD = 30 V ID = 12 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100 tr td(off) tf td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


0.13 0.12 0.11 dIS/dt = 100 A/s VDD = 25 V TJ = 25C 12 10 I S , SOURCE CURRENT (AMPS) 8 6 4 2 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 VGS = 0 V TJ = 25C

QRR , STORED CHARGE ( C)

0.10 0.09 0.08

10

12

0.90 0.95

1.0

IS, SOURCE CURRENT (AMPS)

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Stored Charge

Figure 11. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1217

MTP3055V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 75 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C

ID = 12 A

10 100 s 1.0 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 dc

10 s

50

25

0.1

100

25

50

75

100

125

150

175

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

0.1

P(pk)

t2 DUTY CYCLE, D = t1/t2 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1218

MTP3055VL
Preferred Device

Power MOSFET 12 Amps, 60 Volts, Logic Level


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Single Pulse (tp 50 s) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 12 Apk, L = 1.0 mH, RG =25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 20 12 8.0 42 48 0.32 55 to 175 72 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1 4 S G

http://onsemi.com

12 AMPERES 60 VOLTS RDS(on) = 180 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP3055VL LLYWW 1 Gate 2 Drain 3 Source

C/W RJC RJA TL 3.13 62.5 260 C MTP3055VL LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP3055VL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1219

November, 2000 Rev. 3

Publication Order Number: MTP3055VL/D

MTP3055VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 6.0 Adc) DrainSource OnVoltage (VGS = 5.0 Vdc) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 12 Adc, VGS = 5.0 Vdc) (VDD = 30 Vdc, ID = 12 Adc, VGS = 5 5.0 0 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 12 Adc, VGS = 0 Vdc) (IS = 12 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 12 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 0.97 0.86 55.7 37 18.7 0.116 1.3 C ns Vdc 9.0 85 14 43 8.1 1.8 4.2 3.8 20 190 30 90 10 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 410 114 21 570 160 40 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 5.0 1.6 8.8 2.6 2.5 mhos 1.6 3.0 0.12 2.0 0.18 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 62 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1220

MTP3055VL
TYPICAL ELECTRICAL CHARACTERISTICS
24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 3V 4 0 2.5 V 0 1 2 3 4 5 24 I D , DRAIN CURRENT (AMPS) 20 16 12 8 4 0 2.0

TJ = 25C

VGS = 10 V

5V 4.5 V 4V 3.5 V

VDS 10 V

TJ = -55C 25C

100C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.32 0.26 0.20 0.14 0.08 0.02

VGS = 5 V

0.27

TJ = 25C

0.22

TJ = 100C 25C -55C

0.17 5V 0.12 VGS = 10 V

8 12 16 ID, DRAIN CURRENT (AMPS)

20

24

0.07

8 12 16 ID, DRAIN CURRENT (AMPS)

20

24

Figure 3. OnResistance versus Drain Current and Temperature


2.0 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 6 A I DSS , LEAKAGE (nA)

VGS = 0 V

1.5

10

TJ = 125C

1.0

1.0

100C

0.5

0 -50

-25

25

50

75

100

125

150

175

0.1

TJ, JUNCTION TEMPERATURE (C)

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1221

MTP3055VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1400 1200 C, CAPACITANCE (pF) 1000 800 600 400 200 0 10 5 VGS 0 VDS 5 Crss Ciss Coss Crss 10 15 20 25 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1222

MTP3055VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 QT 60 50 4 40 30 2 Q1 Q2 ID = 12 A TJ = 25C Q3 2 VDS 4 6 8 QT, TOTAL CHARGE (nC) 20 10 0 10 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 12 A VGS = 5 V TJ = 25C

VGS

t, TIME (ns)

100

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


12 10 I S , SOURCE CURRENT (AMPS) 8 6 4 2 0 0.50 0.55 0.60 0.65 0.70 VGS = 0 V TJ = 25C

0.75 0.80 0.85 0.90 0.95

1.0

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1223

MTP3055VL
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 75 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 5 V SINGLE PULSE TC = 25C

ID = 12 A

10 s 100 s 1 ms

10

50

1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0

10 ms

dc

25

0.1

10

100

25

50

75

100

125

150

175

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

0.1

P(pk)

0.01 1.0E-05

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1224

MTP30N06VL
Preferred Device

Power MOSFET 30 Amps, 60 Volts, Logic Level


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 30 Apk, L = 0.342 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 20 30 20 105 90 0.6 55 to 175 154 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C C mJ 1 C/W C MTP30N06VL LL Y WW 2 S G

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30 AMPERES 60 VOLTS RDS(on) = 50 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TO220AB CASE 221A STYLE 5

MTP30N06VL LLYWW 1 Gate 2 Drain 3 Source

RJC RJA TL

1.67 62.5 260

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP30N06VL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1225

November, 2000 Rev. 5

Publication Order Number: MTP30N06VL/D

MTP30N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 15 Adc) DraintoSource OnVoltage (VGS = 5 Vdc, ID = 30 Adc) (VGS = 5 Vdc, ID = 15 Adc, TJ = 150 C) Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 5 Vdc) (VDD = 30 Vdc, ID = 30 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150 C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 30 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 7.5 4.5 nH nH ta tb QRR 0.98 0.89 86.4 49.6 36.8 0.228 1.6 C ns Vdc 14 260 54 108 27 5 17 15 30 520 110 220 40 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1130 360 95 1580 500 190 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 13 21 1.8 1.73 Mhos 1.5 4.0 0.033 2.0 0.05 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 63 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1226

MTP30N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
60 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 3V 60 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 VDS 10 V

VGS = 10 V 8V 6V 5V

TJ = 25C

TJ = -55C 25C 100C

4V

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0

VGS = 10 V TJ = 100C

0.06 0.05 0.04 0.03 0.02 0.01 0

TJ = 25C

VGS = 5 V 10 V

25C

-55C

10

40 20 30 ID, DRAIN CURRENT (AMPS)

50

60

10

40 20 30 ID, DRAIN CURRENT (AMPS)

50

60

Figure 3. OnResistance versus Drain Current and Temperature


2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 1 0 VGS = 5 V ID = 15 A I DSS , LEAKAGE (nA)

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1000

VGS = 0 V TJ = 125C

100 100C 10

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature http://onsemi.com


1227

Figure 6. DrainToSource Leakage Current versus Voltage

MTP30N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
5000 4500 C iss 4000 C, CAPACITANCE (pF) 3500 3000 2500 2000 1500 1000 500 0 10 5 VGS Crss 0 VDS 5 10 15 20 Ciss Coss 25 Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1228

MTP30N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 5 10 15 Q3 VDS 20 QT, TOTAL CHARGE (nC) TJ = 25C ID = 30 A Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 25 1000 TJ = 25C ID = 30 A VDD = 30 V VGS = 5 V VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

tr tf td(off)

t, TIME (ns)

100

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


30 25 I S , SOURCE CURRENT (AMPS) 20 15 10 5 0 0.5 TJ = 25C VGS = 0 V

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1229

MTP30N06VL
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 160 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 140 120 100 80 60 40 20 0 25 50 75 100 125 150 175 ID = 30 A

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 s

100

10

100 s 1 ms 10 ms

dc 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.01 1.0E-05

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1230

MTP30P06V
Preferred Device

Power MOSFET 30 Amps, 60 Volts


PChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 25 30 19 105 125 0.83 55 to 175 450 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1 4 G S

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30 AMPERES 60 VOLTS RDS(on) = 80 m


PChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP30P06V LLYWW 3 Source 2 Drain

RJC RJA TL

1.2 62.5 260

C/W C

1 Gate

MTP30P06V LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP30P06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1231

November, 2000 Rev. 3

Publication Order Number: MTP30P06V/D

MTP30P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 15 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 30 Adc) (VGS = 10 Vdc, ID = 15 Adc, TJ = 150C) Forward Transconductance (VDS = 8.3 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 30 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 30 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 2.3 1.9 175 107 68 0.965 3.0 C ns Vdc 14.7 25.9 98 52.4 54 9.0 26 20 30 50 200 100 80 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1562 524 154 2190 730 310 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 5.0 7.9 2.0 2.9 2.8 Mhos 2.6 5.3 0.067 4.0 0.08 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 62 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1232

MTP30P06V
TYPICAL ELECTRICAL CHARACTERISTICS
60 I D , DRAIN CURRENT (AMPS) 50 40 30 20 10 0 0 2 4 6 8 10 5V 4V 12 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6V 60 8V I D , DRAIN CURRENT (AMPS) 9V 7V 50 40 30 20 10 0 TJ = -55C

TJ = 25C VGS = 10V

VDS 10 V

100C 25C

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.12 0.1 0.08 0.06

VGS = 10 V

0.08

TJ = 100C

TJ = 25C VGS = 10 V 15 V

0.07

25C -55C

0.06

0.04 0.02 0

0.05

10

20 30 40 ID, DRAIN CURRENT (AMPS)

50

60

0.04

10

20 30 40 ID, DRAIN CURRENT (AMPS)

50

60

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 1 0 VGS = 10 V ID = 15 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C

10

100C

50 60 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

70

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1233

MTP30P06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 5000 C, CAPACITANCE (pF) 4000 3000 2000 1000 0 10 5 VGS 0 Crss VDS Ciss Coss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

10

15

20

25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1234

MTP30P06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 Q3 10 20 30 VDS 40 TJ = 25C ID = 30 A 50 Q1 Q2 QT 30 VGS 27 24 21 18 15 12 9 6 3 0 60 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 30 A VDD = 30 V VGS = 10 V

t, TIME (ns)

100

td(off) tf tr td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


30 25 I S , SOURCE CURRENT (AMPS) 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 TJ = 25C VGS = 0 V

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1235

MTP30P06V
SAFE OPERATING AREA
450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 175

1000 I D , DRAIN CURRENT (AMPS)

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

ID = 30 A

100 10 s 10 100 s 1 ms 10 ms dc 100

0.1

1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 0.05

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1236

MTP36N06V
Preferred Device

Power MOSFET 32 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25 C Drain Current Continuous @ 100 C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25 C Derate above 25 C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 32 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 20 25 32 22.6 112 90 0.6 55 to 175 205 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1 4 G S

http://onsemi.com

32 AMPERES 60 VOLTS RDS(on) = 40 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP30N06V LLYWW 1 Gate 2 Drain 3 Source

RJC RJA TL

1.67 62.5 260

C/W C

MTP30N06V LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP36N06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1237

November, 2000 Rev. 3

Publication Order Number: MTP36N06V/D

MTP36N06V
ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150 C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 16 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 32 Adc) (VGS = 10 Vdc, ID = 16 Adc, TJ = 150 C) Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 32 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 32 Adc, VGS = 0 Vdc) (IS = 32 Adc, VGS = 0 Vdc, TJ = 150 C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 32 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.03 0.94 92 64 28 0.332 2.0 C ns Vdc 14 138 54 91 39 7.0 17 13 30 270 100 180 50 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1220 337 74.8 1700 470 150 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 5.0 1.25 7.83 1.54 1.47 mhos 2.6 6.0 0.034 4.0 0.04 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 61 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1238

MTP36N06V
TYPICAL ELECTRICAL CHARACTERISTICS
72 I D , DRAIN CURRENT (AMPS) 72 I D , DRAIN CURRENT (AMPS) 7V VDS 10 V 54

TJ = 25C 9V 8V

VGS = 10 V

TJ = 100C 25C

54

36

6V

36

18

5V 4V

18 -55C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.1 0.08

VGS = 10 V

0.052

TJ = 25C

TJ = 100C 0.06 0.04 0.02 0 25C -55C

0.044 VGS = 10 V 0.036 15 V

18

54 36 ID, DRAIN CURRENT (AMPS)

72

0.028

18

36 54 ID, DRAIN CURRENT (AMPS)

72

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.8 1.6 1.4 1.2 1 0.8 0.6 -50 VGS = 10 V ID = 16 A I DSS , LEAKAGE (nA)

1000

VGS = 0 V TJ = 125C

100

100C

10

25C

-25

25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature http://onsemi.com


1239

Figure 6. DrainToSource Leakage Current versus Voltage

MTP36N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
4000 VDS = 0 V 3000 Ciss VGS = 0 V TJ = 25C

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

C, CAPACITANCE (pF)

2000 Crss 1000 Ciss Coss Crss 10 5 VGS 0 VDS 5 10 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1240

MTP36N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 0 5 Q3 VDS 10 15 20 25 30 35 40 QT, TOTAL CHARGE (nC) TJ = 25C ID = 32 A VGS Q1 Q2 25 20 15 10 5 0 30 1000 TJ = 25C ID = 32 A VDD = 30 V VGS = 10 V VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

tr tf td(off)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


32 TJ = 25C VGS = 0 V

I S , SOURCE CURRENT (AMPS)

24

16

0 0.5 0.55

0.6 0.65

0.7 0.75

0.8 0.85 0.9

0.95

1.05

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1241

MTP36N06V
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 225 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 200 175 150 125 100 75 50 25 0 25 50 75 100 125 150 175 ID = 32 A

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

100 10 s

10

100 s 1 ms 10 ms

dc 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1242

MTP40N10E
Preferred Device

Power MOSFET 40 Amps, 100 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 75 Vdc, VGS = 10 Vdc, Peak IL = 40 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 100 100 20 40 40 29 140 169 1.35 55 to 150 800 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 2 Drain C/W RJC RJA TL 0.74 62.5 260 C MTP40N10E LL Y WW = Device Code = Location Code = Year = Work Week 1 2 TO220AB CASE 221A STYLE 5 4 S

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40 AMPERES 100 VOLTS RDS(on) = 40 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP40N10E LLYWW 3 Source

1 Gate

ORDERING INFORMATION
Device MTP40N10E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1243

November, 2000 Rev. 2

Publication Order Number: MTP40N10E/D

MTP40N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ =125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 20 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 40 Adc) (VGS = 10 Vdc, ID = 20 Adc, TJ = 125C) Forward Transconductance (VDS = 8.4 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 40 Adc, VGS = 10 Vdc) (VDD = 50 Vdc, ID = 40 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 40 Adc, VGS = 0 Vdc) (IS = 40 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (S Figure (See Fi 14) (IS = 40 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Cpk + Max limit Typ 3 sigma LD LS 7.5 3.5 4.5 nH trr ta tb QRR VSD 0.96 0.88 152 117 35 1.0 1.0 C ns Vdc 19 165 75 97 80 15 40 29 40 330 150 190 110 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2305 620 205 3230 1240 290 pF (Cpk 2.0) (Note 3.) VGS(th) 2.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 17 21 1.9 1.7 mhos 0.033 0.04 Vdc 2.9 6.7 4.0 Vdc mV/C Ohms V(BR)DSS (Cpk 2.0) (Note 3.) IDSS IGSS 10 100 100 nAdc 100 112 Vdc mV/C Adc Symbol Min Typ Max Unit

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1244

MTP40N10E
TYPICAL ELECTRICAL CHARACTERISTICS
80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 1 3 4 5 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 5V 6V 80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 10 0 2 3 4 5 6 7 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 8 TJ = -55C VDS 10 V 25C

VGS = 10 V

8V 9V

TJ = 25C 7V

100C

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 10 20 30 40 50 60 70 80 -55C 25C R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS) 70 80 VGS = 10 V TJ = 25C

15 V

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 VGS = 10 V ID = 20 A I DSS , LEAKAGE (nA)

1000

VGS = 0 V

TJ = 125C

100 100C

10

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

1.0

10

20 30 40 60 70 80 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

90

100

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1245

MTP40N10E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 -10 -5 VGS 0 VDS Crss 5 10 15 20 Coss 25 Ciss Ciss Crss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1246

MTP40N10E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 10 Q3 20 30 40 VDS 50 60 70 80 QG, TOTAL GATE CHARGE (nC) ID = 40 A TJ = 25C Q1 Q2 QT VGS 80 72 64 10,000 VDD = 50 V ID = 40 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

48 40 32 24 16 8 0

t, TIME (ns)

56

1000

100

tr tf td(off)

10

td(on) 1.0 10 RG, GATE RESISTANCE (OHMS) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


40 35 I S , SOURCE CURRENT (AMPS) 30 25 20 15 10 5 0 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1247

MTP40N10E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 800 EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 700 600 500 400 300 200 100 0 25 50 75 100 125 150 ID = 40 A

VGS = 20 V SINGLE PULSE TC = 25C 100 ms

100

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 ms

10

1.0 ms 10 ms

1.0

dc 0.1 1.0 10 100 1000 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.0 0.01 SINGLE PULSE 1.0E-05 1.0E-04 1.0E-03 P(pk)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

t2 DUTY CYCLE, D = t1/t2 1.0E-02 t, TIME (seconds) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1248

MTP50N06V
Preferred Device

Power MOSFET 42 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Onresistance Area Product about Onehalf that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology Faster Switching than EFET Predecessors Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature Static Parameters are the Same for both TMOS V and TMOS EFET
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc IL = 42 Apk, L = 0.454 H, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 20 25 42 30 147 125 0.83 55 to 175 400 Unit Vdc Vdc 4 Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1

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42 AMPERES 60 VOLTS RDS(on) = 28 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP50N06V LLYWW 3 Source 2 Drain

1 Gate

RJC RJA TL

1.2 62.5 260

C/W C

MTP50N06V = Device Code LL = Location Code Y = Year WW = Work Week

ORDERING INFORMATION
Device MTP50N06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

1249

February, 2001 Rev. 4

Publication Order Number: MTP50N06V/D

MTP50N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 21 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 42 Adc) (ID = 21 Adc, TJ = 150C) Forward Transconductance (VDS = 6.25 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 10 Vdc) (VDD = 25 Vdc, ID = 42 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 1.06 0.99 84 73 11 0.28 2.5 C ns Vdc 12 122 64 54 47 9 21 16 20 250 110 90 70 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1644 465 112 2320 660 230 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 16 1.4 23 1.7 1.6 mhos 2.7 3.0 0.025 4.0 0.028 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 69 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1250

MTP50N06V
TYPICAL ELECTRICAL CHARACTERISTICS
100 I D , DRAIN CURRENT (AMPS) 80 60 6V 40 20 0 5V 100 I D , DRAIN CURRENT (AMPS) 80 60 40 20 0

TJ = 25C 9V

VGS = 10 V

8V 7V

VDS 10 V 25C

100C

TJ = -55C

0.8

1.6

2.4

3.2

4.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.04

VGS = 10 V TJ = 100C 25C

0.033

TJ = 25C

0.034 0.028

0.030

0.027

VGS = 10 V

0.022 0.016 0.01

0.024

15 V

-55C 0 20 40 60 ID, DRAIN CURRENT (AMPS) 80 100

0.021

20

40 60 ID, DRAIN CURRENT (AMPS)

80

100

Figure 3. OnResistance versus Drain Current and Temperature


1000 VGS = 10 V ID = 21 A I DSS , LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.5 2 1.5 1 0.5 0 -50

VGS = 0 V TJ = 125C

100C 10 25C

-25

25

50

75

100

125

150

175

TJ, JUNCTION TEMPERATURE (C)

10 30 40 20 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1251

MTP50N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 5000 C, CAPACITANCE (pF) 4000 3000 2000 1000 0 10 5 VGS 0 VDS Crss Ciss Coss 10 15 20 25 VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss 5

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1252

MTP50N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 14 12 10 8 6 4 2 0 0 Q3 10 20 30 Q1 Q2 QT VGS 56 48 40 32 24 ID = 42 A TJ = 25C 8 40 0 50 16 1000 VDD = 60 V ID = 42 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

td(off) 10

tr tf

td(on)

VDS QT, TOTAL CHARGE (nC)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


50 40 30 20 10 0 0.5 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

0.6

0.7

0.8

0.9

1.0

1.1

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1253

MTP50N06V
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 400 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID = 42 A 320 240 160 80 0

VGS = 20 V SINGLE PULSE TC = 25C 10 s

100

10

100 s

1 ms 10 ms 10

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0

dc 100

25

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1

0.1

P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

0.01 1.0E-05

1.0E-04

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1254

MTP50N06VL
Preferred Device

Power MOSFET 42 Amps, 60 Volts, Logic Level


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 42 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 20 42 30 147 125 0.83 55 to 175 265 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C C mJ 1 C/W C MTP50N06VL LL Y WW 2 S G

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42 AMPERES 60 VOLTS RDS(on) = 32 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TO220AB CASE 221A STYLE 5

MTP50N06VL LLYWW 1 Gate 2 Drain 3 Source

RJC RJA TL

1.2 62.5 260

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP50N06VL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1255

November, 2000 Rev. 3

Publication Order Number: MTP50N06VL/D

MTP50N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 21 Adc) DraintoSource OnVoltage (VGS = 5 Vdc, ID = 42 Adc) (VGS = 5 Vdc, ID = 21 Adc, TJ = 150C) Forward Transconductance (VDS = 6 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 42 Adc, VGS = 5 Vdc) (VDD = 30 Vdc, ID = 42 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 42 Adc, VGS = 0 Vdc) (IS = 42 Adc, VGS = 0 Vdc, TJ = 150 C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 42 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.03 0.94 91.1 63.8 27.3 0.299 2.5 C ns Vdc 16 355 80 160 40 11 20 16 30 701 160 320 60 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1570 508 135 2200 710 270 pF VGS(th) 1.0 RDS(on) VDS(on) gFS 17 28 1.6 1.5 Mhos 1.4 4.3 0.025 2.0 0.032 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 64 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1256

MTP50N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
90 80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3V 6V 90 80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 VDS 10 V TJ = -55C 25C 100C

TJ = 25C 8V 7V

VGS = 10 V

5V

4V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.06 0.05 0.04 0.03 0.02 0.01 0

VGS = 5 V TJ = 100C 25C -55C

0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0

TJ = 25C VGS = 5 V 10 V

18

36 45 54 63 27 ID, DRAIN CURRENT (AMPS)

72

81

90

10

20

40 50 30 60 ID, DRAIN CURRENT (AMPS)

70

80

90

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50

VGS = 5 V ID = 21 A I DSS , LEAKAGE (nA)

1000

VGS = 0 V

TJ = 125C 100

100C

-25

25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

10

30 10 20 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1257

MTP50N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
6000 5000 C, CAPACITANCE (pF) 4000 3000 2000 1000 0 10 Ciss Coss VDS = 0 V 5 VGS 0 VDS 5 Crss 10 15 20 25 Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1258

MTP50N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 0 Q3 10 20 VGS QT 30 25 20 15 TJ = 25C ID = 42 A VDS 30 40 10 5 0 50 1000 TJ = 25C ID = 42 A VDD = 30 V VGS = 5 V VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

tr tf td(off) td(on)

Q1

Q2

t, TIME (ns)

100

10

10 RG, GATE RESISTANCE (OHMS)

100

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


25 20 15 10 5 0 0.5 TJ = 25C VGS = 0 V

I S , SOURCE CURRENT (AMPS)

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1259

MTP50N06VL
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 300 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID = 42 A 250 200 150 100 50 0 25 150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 175

VGS = 20 V SINGLE PULSE TC = 25C

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 s

100

10

100 s 1 ms 10 ms dc 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.00 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.01 1.0E-05

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1260

MTP50P03HDL
Preferred Device

Power MOSFET 50 Amps, 30 Volts, Logic Level


PChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient, when mounted with the minimum recommended pad size Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 30 30 15 20 50 31 150 125 1.0 55 to 150 1250 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 TO220AB CASE 221A STYLE 5

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50 AMPERES 30 VOLTS RDS(on) = 25 m


PChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

MTP50N03HDL LLYWW 1 Gate 2 Drain 3 Source

C/W RJC RJA TL 1.0 62.5 260 C

MTP50N03HDL LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP50N03HDL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1261

November, 2000 Rev. 3

Publication Order Number: MTP50P03HDL/D

MTP50P03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5.0 Vdc, ID = 25 Adc) DraintoSource OnVoltage (VGS = 10 Vdc) (ID = 50 Adc) (ID = 25 Adc, TJ = 125C) Forward Transconductance (VDS = 5.0 Vdc, ID = 25 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge g (S Figure (See Fi 8) (VDD = 15 Vdc, ID = 50 Adc, VGS = 5 5.0 Vdc, 0 Vdc RG = 2.3 ) td(on) tr td(off) tf QT (VDS = 24 Vdc, ID = 50 Adc, VGS = 5.0 Vdc) Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS =50 Adc, VGS = 0 Vdc) (IS = 50 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 50 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) ta tb QRR LD LS 7.5 3.5 4.5 nH 2.39 1.84 106 58 48 0.246 3.0 C nH ns Vdc 22 340 90 218 74 13.6 44.8 35 30 466 117 300 100 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 3500 1550 550 4900 2170 770 pF (Cpk 3.0) (Note 3.) VGS(th) 1.0 (Cpk 3.0) (Note 3.) RDS(on) VDS(on) gFS 15 20 0.83 1.5 1.3 mhos 0.020 0.025 Vdc 1.5 4.0 2.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 30 IDSS IGSS 100 1.0 10 nAdc 26 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery y Time (S Figure (See Fi 15)

Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA

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1262

MTP50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
100 I D , DRAIN CURRENT (AMPS) 80 60 40 20 0 100 I D , DRAIN CURRENT (AMPS) 80 60 40 20 0 1.5

TJ = 25C

VGS = 10 V 8V 6V

5V 4.5 V 4V

VDS 10 V

TJ = -55C 25C 100C

3.5 V

3V 2.5 V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

1.9

2.3

2.7

3.1

3.5

3.9

4.3

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.029 0.027 0.025 0.023 0.021 0.019 0.017 0.015 0 20 40 -55C 0.022 0.021 0.020 0.019 0.018 0.017 0.016 0.015 0

Figure 2. Transfer Characteristics

VGS = 5.0 V

TJ = 25C

VGS = 5 V

TJ = 100C 25C

10 V

60

80

100

20

40

60

80

100

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1.35 1.25 1.15 1.05 0.95 0.85 -50 10 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 25 A

VGS = 0 V

I DSS, LEAKAGE (nA)

TJ = 125C 100

100C -25 0 25 50 75 100 125 150 0 5 10 15 20 25 30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1263

MTP50P03HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
14000 12000 C, CAPACITANCE (pF) 10000 8000 6000 C rss 4000 2000 0 10 5 VGS 0 VDS 5 Crss 10 Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

Ciss Coss

15

20

25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1264

MTP50P03HDL
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 QT 5 Q1 4 3 2 1 0 0 10 ID = 50 A TJ = 25C Q3 20 30 40 50 60 VDS 70 QT, TOTAL GATE CHARGE (nC) Q2 VGS 25 20 15 10 5 0 80 30 1000 VDD = 30 V VGS = 10 V ID = 50 A TJ = 25C

tr tf td(off)

t, TIME (ns)

100

td(on)

10

1 RG, GATE RESISTANCE (Ohms)

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
50 I S , SOURCE CURRENT (AMPS) 40 30 20 10 0 0.4 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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1265

MTP50P03HDL
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
VGS = 20 V SINGLE PULSE TC = 25C 100 s 1 ms 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 ms dc EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 1000

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

1400 1200 1000 800 600 400 200 0 25 50 75 100 125 150 ID = 50 A

I D , DRAIN CURRENT (AMPS)

100

1 0.1

100

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1266

MTP50P03HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk) 0.1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1267

MTP52N06V
Preferred Device

Power MOSFET 52 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 20 25 52 41 182 188 1.25 55 to 175 406 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 C/W RJC RJA TL 0.8 62.5 260 C MTP52N06V LL Y WW TO220AB CASE 221A STYLE 5 4 G S

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52 AMPERES 60 VOLTS RDS(on) = 22 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP52N06V LLYWW 1 Gate 2 Drain 3 Source

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP52N06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1268

November, 2000 Rev. 4

Publication Order Number: MTP52N06V/D

MTP52N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 26 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 52 Adc) (VGS = 10 Vdc, ID = 26 Adc, TJ = 150C) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 52 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.0 0.98 100 80 20 0.341 1.5 C ns Vdc 12 298 70 110 125 10 30 40 20 600 140 220 175 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1900 580 150 2660 810 300 pF (Cpk 2.0) (Note 3.) VGS(th) 2.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 17 24 1.4 1.2 mhos 0.019 0.022 Vdc 2.7 6.4 4.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 66 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure Fi 14) (See

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1269

MTP52N06V
TYPICAL ELECTRICAL CHARACTERISTICS
110 100 I D , DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 5V 6V 110 100 I D , DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 TJ = -55C 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V 9V

8V

TJ = 25C 7V

VDS 10 V

100C 25C

10

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.035 0.03

VGS = 10 V TJ = 100C 25C

0.023 0.022 0.021 0.020 0.019 0.018 0.017 0.016 5

TJ = 25C

0.025 0.02

VGS = 10 V

0.015 0.01

-55C

15 V

0.005 0 0 10 20 30 40 50 60 70 80 90 100 110

0.015

15

25

35

45

55

65

75

85

95

105

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2 1.75 1.5 1.25 1 0.75 0.5 0.25 -50 -25 0 25 50 75 100 125 150 175 VGS = 10 V ID = 26 A I DSS , LEAKAGE (nA)

100

VGS = 0 V

TJ = 125C

10 100C

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1270

MTP52N06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
7000 6000 C, CAPACITANCE (pF) 5000 4000 3000 2000 1000 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss Coss Crss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1271

MTP52N06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 20 40 VDS 60 80 100 QT, TOTAL CHARGE (nC) 120 ID = 52 A TJ = 25C Q1 Q2 QT VGS 36 33 30 27 24 21 18 15 12 9 6 3 0 140 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 52 A VGS = 10 V TJ = 25C

tr tf td(off)

t, TIME (ns)

100

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


55 50 I S , SOURCE CURRENT (AMPS) 45 40 35 30 25 20 15 10 5 0 0.2 VGS = 0 V TJ = 25C

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1272

MTP52N06V
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) 175 ID = 52 A 10s

VGS = 20 V SINGLE PULSE TC = 25C

100

100s 10

1ms 10ms dc

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1

10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1.0E-05 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1273

MTP52N06VL
Preferred Device

Power MOSFET 52 Amps, 60 Volts, Logic Level


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5 Vdc, Peak IL = 52 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 25 52 41 182 188 1.25 55 to 175 406 Unit Vdc Vdc Vdc Vpk Adc 4 Apk Watts W/C C mJ 1 C/W C MTP52N06VL LL Y WW 2 S G

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52 AMPERES 60 VOLTS RDS(on) = 25 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TO220AB CASE 221A STYLE 5

MTP52N06VL LLYWW 1 Gate 2 Drain 3 Source

RJC RJA TL

0.8 62.5 260

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP52N06VL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1274

November, 2000 Rev. 4

Publication Order Number: MTP52N06VL/D

MTP52N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = .25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 5 Vdc, ID = 26 Adc) DraintoSource OnVoltage (VGS = 5 Vdc, ID = 52 Adc) (VGS = 5 Vdc, ID = 26 Adc, TJ = 150C) Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 52 Adc, VGS = 5 Vdc) (VDD = 30 Vdc, ID = 52 Adc, VGS = 5 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 150 C) VSD trr (IS = 52 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 1.03 0.9 104 63 41 0.28 1.5 C ns Vdc 15 500 100 200 62 4.0 31 16 30 1000 200 400 90 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 1900 550 170 2660 770 340 pF (Cpk 2.0) (Note 3.) VGS(th) 1.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 17 30 1.6 1.4 Mhos 0.022 0.025 Vdc 1.5 4.5 2.0 Vdc mV/C Ohm (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 65 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1275

MTP52N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
110 I D , DRAIN CURRENT (AMPS) 110 100 I D , DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 0.5

100

VGS = 10 V 8V 90 7V 80 70 60 50 40 30 20 10 0

6V

TJ = 25C 5V

VDS 10 V

TJ = -55C 100C 25C

4V

3V 0 1 2 3 4 5 6 7 8 9 10

1.0

1.5

2.5

3.5

4.5

5.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) .070 .060 .050 .040 .030 .020 .010 0 0 10 20 30 40 50 60 70 80 90 100 110 TJ = 100C 25C -55C R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

VGS = 5 V

.040 .035 .030 .025 .020 .015 .010 .005 0 0

TJ = 25C

VGS = 5 V 10 V

10

20

30

40

50

60

70

80

90

100 110

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 I DSS , LEAKAGE (nA) 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175 1 0 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 5 V ID = 26 A

VGS = 0 V TJ = 125C

100C 10

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1276

MTP52N06VL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS Crss 0 VDS 5 10 15 20 25 Ciss Coss Crss Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1277

MTP52N06VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 Q3 10 20 VDS 30 40 50 QT, TOTAL CHARGE (nC) 60 ID = 52 A TJ = 25C Q1 Q2 QT VGS 30 27 24 21 18 15 12 9 6 3 0 70 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 52 A VGS = 5 V TJ = 25C tr tf td(off)

t, TIME (ns)

100

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


55 50 I S , SOURCE CURRENT (AMPS) 45 40 35 30 25 20 15 10 5 0 0.5 0.55 VGS = 0 V TJ = 25C

0.6 0.65

0.7 0.75

0.8 0.85

0.9 0.95

1.05

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1278

MTP52N06VL
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 450 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) 175 ID = 52 A 10s

VGS = 15 V SINGLE PULSE TC = 25C

100

10

100s 1ms 10ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 dc

10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1.0E-05 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1279

MTP5P06V
Preferred Device

Power MOSFET 5 Amps, 60 Volts


PChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Nonrepetitive (tp 10 ms) Drain Current Continuous @ 25C Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 5 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 15 25 5 4 18 40 0.27 55 to 175 125 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ TO220AB CASE 221A STYLE 5 1 4 G S

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5 AMPERES 60 VOLTS RDS(on) = 450 m


PChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP5P06V LLYWW 3 Source 2 Drain

RJC RJA TL

3.75 62.5 260

C/W C

1 Gate

MTP5P06V LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP5P06V Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1280

November, 2000 Rev. 2

Publication Order Number: MTP5P06V/D

MTP5P06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 2.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc, ID = 5 Adc) (VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150C) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 48 Vdc, ID = 5 Adc, VGS = 10 Vdc) (VDD = 30 Vdc, ID = 5 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 5 Adc, VGS = 0 Vdc) (IS = 5 Adc, VGS = 0 Vdc, TJ = 150C) VSD trr (IS = 5 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 3.5 4.5 7.5 nH nH ta tb QRR 1.72 1.34 97 73 24 0.42 3.5 C ns Vdc 11 26 17 19 12 3.0 5.0 5.0 20 50 30 40 20 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 367 140 29 510 200 60 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.5 3.6 2.7 2.6 Mhos 2.8 4.7 0.34 4.0 0.45 Vdc mV/C Ohm Vdc V(BR)DSS 60 IDSS IGSS 10 100 100 nAdc 61.2 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1281

MTP5P06V
TYPICAL ELECTRICAL CHARACTERISTICS
10 I D , DRAIN CURRENT (AMPS) 8 6 4 2 0 5V 4V 0 1 2 3 4 5 6 7 8 9 10 7V I D , DRAIN CURRENT (AMPS) 9 8 7 6 5 4 3 2 1 0 2 3 4 5 6 7 8

VGS = 10V TJ = 25C

9V

8V

VDS 10 V

TJ = -55C 25C 100C

6V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 1

VGS = 10 V TJ = 100C

0.4

TJ = 25C VGS = 10 V

0.35

25C

0.3

15 V

0.25

-55C 2 3 4 5 6 7 ID, DRAIN CURRENT (AMPS) 8 9 10

0.2

4 5 7 6 ID, DRAIN CURRENT (AMPS)

10

Figure 3. OnResistance versus Drain Current and Temperature


100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -50

VGS = 10 V ID = 2.5 A I DSS , LEAKAGE (nA)

VGS = 0 V

10

TJ = 125C

-25

0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C)

150

175

50 10 20 30 40 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

60

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1282

MTP5P06V
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1000 900 800 C, CAPACITANCE (pF) 700 600 500 400 300 200 100 0 VGS = 0 V 10 5 VGS 0 VDS 5 Crss 10 15 20 25 Coss Ciss Crss Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1283

MTP5P06V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 2 4 6 Q3 VDS 8 10 TJ = 25C ID = 5 A 12 Q1 Q2 QT 60 VGS 54 48 42 36 30 24 18 12 6 0 14 100 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 5 A VDD = 30 V VGS = 10 V td(off) tf

tr

t, TIME (ns)

10

td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Qg, TOTAL GATE CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


5 4.5 I S , SOURCE CURRENT (AMPS) 4 3.5 3 2.5 2 1.5 1 0.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 TJ = 25C VGS = 0 V

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1284

MTP5P06V
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 140 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 s 120 100 80 60 40 20 0 25 50 75 100 125 150 175

VGS = 20 V SINGLE PULSE TC = 25C

ID = 5 A

10 100 s 1 ms 1 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100

0.1

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 0.05

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1285

MTP60N06HD
Preferred Device

Power MOSFET 60 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 60 60 20 30 60 42.3 180 150 1.0 55 to 175 540 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 TO220AB CASE 221A STYLE 5 S

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60 AMPERES 60 VOLTS RDS(on) = 14 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

MTP60N06HD LLYWW 1 Gate 2 Drain 3 Source

C/W RJC RJA TL 1.0 62.5 260 C

MTP60N06HD LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP60N06HD Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1286

November, 2000 Rev. 3

Publication Order Number: MTP60N06HD/D

MTP60N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 30 Adc) DraintoSource OnVoltage (VGS = 10 Vdc) (ID = 60 Adc) (ID = 30 Adc, TJ = 125C) Forward Transconductance (VDS = 5.0 Vdc, ID = 30 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge g (S Figure (See Fi 8) (VDD = 30 Vdc, ID = 60 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT (VDS = 48 Vdc, ID = 60 Adc, VGS = 10 Vdc) Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 60 Adc, VGS = 0 Vdc) (IS = 60 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 60 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) ta tb QRR LD LS 7.5 3.5 4.5 nH 0.99 0.89 60 36 24 0.143 1.2 C nH ns Vdc 14 197 50 124 51 12 24 21 26 394 102 246 71 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) (Cpk 3.0) (Note 3.) (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS VGS(th) 2.0 (Cpk 3.0) (Note 3.) RDS(on) VDS(on) gFS 15 Ciss Coss Crss 20 1950 660 147 2800 924 300 pF 1.0 0.9 mhos 0.011 0.014 Vdc 3.0 7.0 4.0 100 Vdc mV/C Ohm 10 100 nAdc 71 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery y Time (S Figure (See Fi 15)

Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA

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1287

MTP60N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
120 I D , DRAIN CURRENT (AMPS) 100 80 60 40 20 0 5V 120 I D , DRAIN CURRENT (AMPS) 100 80 60 40 20 4.5 5.0 0 2.0 2.8 3.6 100C 25C TJ = -55C 4.4 5.2 6.0 6.8 7.6 VGS, GATE-TO-SOURCE VOLTAGE (Volts)

VGS = 10 V

8V 9V

7V

VDS 10 V

TJ = 25C 6V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0 10 20 30 40 50 -55C 25C VGS = 10 V TJ = 100C RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.0132 0.0128 0.0124 0.0120 0.0116 0.0112 0.0108 0.0104 0.0100 0 10

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 10 V

15 V 20 30 40 50 60 70 80 90 100 110 120

60

70

80

90

100 110 120

ID, DRAIN CURRENT (Amps)

ID, DRAIN CURRENT (Amps)

Figure 3. OnResistance versus Drain Current and Temperature


1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 -25 0 25 50 75 100 125 150 1 0 VGS = 10 V ID = 30 A I DSS, LEAKAGE (nA) 100 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V TJ = 125C

100C 25C 10

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1288

MTP60N06HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
5000 4000 C, CAPACITANCE (pF) 3000 Crss 2000 1000 0 10 Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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1289

MTP60N06HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 0 8 ID = 60 A TJ = 25C Q3 16 24 32 40 VDS 48 QT, TOTAL GATE CHARGE (nC) VGS Q1 Q2 50 40 30 20 10 0 56 60 1000 VDD = 30 V ID = 60 A VGS = 10 V TJ = 25C

tr tf td(off)

t, TIME (ns)

100

10

td(on) 1 10 RG, GATE RESISTANCE (Ohms) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
60 I S , SOURCE CURRENT (AMPS) 50 40 30 20 10 0 0.5 0.6 0.7 0.8 0.9 1.0 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

VSD, SOURCE-TO-DRAIN VOLTAGE (Volts)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


1290

MTP60N06HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
1000 VGS = 20 V SINGLE PULSE TC = 25C 10 s

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

600 500 400 300 200 100 0 25 50 75 100 125 150 ID = 60 A

I D , DRAIN CURRENT (AMPS)

100

100 s 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 1 ms 10 ms dc 10 100

1 0.1

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1291

MTP60N06HD
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1292

MTP6P20E
Preferred Device

Power MOSFET 6 Amps, 200 Volts


PChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 200 200 20 40 6.0 3.9 21 75 0.6 55 to 150 180 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 TO220AB CASE 221A STYLE 5 S

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6 AMPERES 200 VOLTS RDS(on) = 1


PChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

MTP6P20E LLYWW 3 Source 2 Drain

1 Gate

C/W RJC RJA TL 1.67 62.5 260 C

MTP6P20E LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP6P20E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1293

November, 2000 Rev. 1

Publication Order Number: MTP6P20E/D

MTP6P20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 125C) Forward Transconductance (VDS = 8.0 Vdc, ID = 3.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 6.0 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr 6 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 6.0 dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH nH ta tb QRR 2.8 2.6 188 152 36 1.595 4.0 C ns Vdc 12 32 24 16 22 4.0 11 9.0 25 65 50 30 30 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 540 128 40 750 180 90 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.5 6.0 3.8 7.2 6.3 mhos 3.1 4.0 0.81 4.0 1.0 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 10 100 100 nAdc 211 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1294

MTP6P20E
TYPICAL ELECTRICAL CHARACTERISTICS
12 I D , DRAIN CURRENT (AMPS) 12 I D , DRAIN CURRENT (AMPS) 8V 10 8 6 4 2 16 0 1 3 5 7 9

TJ = 25C 9V

VGS = 10 V

VDS 10 V 25C TJ = -55C 100C

8 7V 4

6V 5V

10

12

14

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

2.0 1.6 1.2 0.8

VGS = 10 V TJ = 100C

1.4

TJ = 25C

1.2

25C

-55C 0.4 0

1.0

VGS = 10 V 15 V

4 6 8 ID, DRAIN CURRENT (AMPS)

10

12

0.8

10

12

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2.0

VGS = 10 V ID = 3.0 A I DSS , LEAKAGE (nA)

1000

VGS = 0 V 125C

1.5

100

1.0

100C 10

0.5

0 -50

-25

25

50

75

100

125

150

1 -200

-160

-120

-80

-40

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1295

MTP6P20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2000 1600 C, CAPACITANCE (pF) 1200 800 400 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Crss Ciss Coss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1296

MTP6P20E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 0 ID = 6.0 A TJ = 25C Q3 5 VDS 10 15 Qg, TOTAL GATE CHARGE (nC) 20 25 Q1 Q2 80 VGS 160 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 100 V ID = 6.0 A VGS = 10 V TJ = 25C

120

100 t, TIME (ns)

10

tr td(off) tf

td(on)

40

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


6 I S , SOURCE CURRENT (AMPS) 5 4 3 2 1 0 0.5 1.0 1.5 2.0 2.5 3.0 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1297

MTP6P20E
SAFE OPERATING AREA
100 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 100 s 1.0 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 1000 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 180 144 108 72 36 0 ID = 6.0 A

10

0.1

0.01

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t,TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1298

MTP75N03HDL
Preferred Device

Power MOSFET 75 Amps, 25 Volts, Logic Level


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for lowvoltage, highspeed switching applications in power supplies, converters and PWM motor controls, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. SPICE Parameters Available Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Avalanche Energy Specified
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Single Pulse (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 25 25 15 20 75 59 225 150 1.0 55 to 175 280 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C 1 mJ 2 3 TO220AB CASE 221A STYLE 5

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75 AMPERES 25 VOLTS RDS(on) = 9 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

MTP75N03HDL LLYWW 1 Gate 2 Drain 3 Source

C/W RJC RJA TL 1.0 62.5 260 C MTP75N03HDL LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP75N03HDL Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1299

November, 2000 Rev. 3

Publication Order Number: MTP75N03HDL/D

MTP75N03HDL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mA) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 25 Vdc, VGS = 0 Vdc) (VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 37.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) Forward Transconductance (VDS = 3.0 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 24 Vdc, ID = 75 Adc, VGS = 5.0 Vdc) (VDS = 15 Vdc, ID = 75 Adc, VGS = 5 5.0 0 Vdc Vdc, Rg = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 75 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA ta tb QRR 0.97 0.87 58 27 30 0.088 1.1 C ns Vdc 24 493 60 149 61 14 33 27 48 986 120 300 122 28 66 54 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 4025 1353 307 5635 1894 430 pF (Cpk 3.0) (Note 3.) VGS(th) 1.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 15 55 0.68 0.6 mhos 6.0 9.0 Vdc 1.5 2.0 mV/C m Vdc (Cpk 2.0) (Note 3.) V(BR)DSS 25 IDSS IGSS 100 500 100 nAdc mV/C Adc Vdc Symbol Min Typ Max Unit

Reverse Recovery Time

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1300

MTP75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
150 I D , DRAIN CURRENT (AMPS) 120 90 3.5 V 60 30 0 3V 2.5 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1.8 2 150 I D , DRAIN CURRENT (AMPS) 120 90 60 30 0 1.5 100C 25C TJ = -55C 2 2.5 3 3.5 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 4.5

VGS = 10 V 8V 6V

5V

4.5 V TJ = 25C 4V

VDS 10 V

Figure 1. OnRegion Characteristics


R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.01

VGS = 5 V TJ = 100C

0.009 TJ = 25C 0.008 0.007 0.006 10 V 0.005 0.004

0.008

0.006

25C

VGS = 5 V

0.004

-55C

0.002

30

60

90

120

150

25

ID, DRAIN CURRENT (AMPS)

75 50 100 ID, DRAIN CURRENT (AMPS)

125

150

Figure 3. OnResistance versus Drain Current and Temperature

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

2 1.6 1.2 0.8 0.4 0 VGS = 10 V ID = 37.5 A

10000

TJ = 125C 100C

I DSS , LEAKAGE (nA)

1000

100

10 25C 1 VGS = 0 V 0 5 10 15 20 25 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30

-50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1301

MTP75N03HDL
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
15000 12000 C, CAPACITANCE (pF) 9000 6000 3000 0 10 Crss Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss VDS = 0 V VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1302

MTP75N03HDL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 7 6 5 4 3 2 1 0 Q3 0 10 TJ = 25C ID = 75 A VDS 50 20 30 40 QT, TOTAL GATE CHARGE (nC) 60 Q1 QT Q2 VGS 28 24 20 16 12 8 4 0 70 10000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 75 A VDD = 15 V VGS = 5 V

t, TIME (ns)

1000

tr

100

tf td(off) td(on)

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
75 60 45 30 15 0 0.5 TJ = 25C VGS = 0 V

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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1303

MTP75N03HDL
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

1000 I D , DRAIN CURRENT (AMPS)

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C

280 240 200 160 120 80 40 0 25 50 75 100 125 150 ID = 75 A

100 100 s 10 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 dc

100

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

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1304

MTP75N03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 P(pk)

0.1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

SINGLE PULSE 0.01 1.0E-05 1.0E-04

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1305

MTP75N05HD
Preferred Device

Power MOSFET 75 Amps, 50 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energyefficient design also offers a draintosource diode with a fast recovery time. Designed for lowvoltage, highspeed switching applications in power supplies, converters and PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. SPICE Parameters Available Diode is Characterized for Use in Bridge Circuits Diode Exhibits High Speed, Yet Soft Recovery IDSS and VDS(on) Specified at Elevated Temperature Avalanche Energy Specified
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vpk, IL = 75 Apk, L = 0.177 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 50 50 20 75 65 225 150 1 55 to 175 500 Unit Vdc Vdc Vdc Adc Apk Watts W/C C mJ 1 2 TO220AB CASE 221A STYLE 5 4

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75 AMPERES 50 VOLTS RDS(on) = 9.5 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

MTP75N05HD LLYWW 1 Gate 2 Drain 3 Source

C/W RJC RJA TL 1.00 62.5 260 C MTP75N05HD LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP75N05HD Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1306

November, 2000 Rev. 4

Publication Order Number: MTP75N05HD/D

MTP75N05HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 V, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 50 Vdc, VGS = 0) (VDS = 50 Vdc, VGS = 0, TJ = 150C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 37.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 150C) Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 40 Vdc, ID = 75 Adc, VGS = 10 Vdc) (VDD = 25 Vdc, ID = 75 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 75 Adc, VGS = 0) (IS = 75 Adc, VGS = 0, TJ = 150C) (Cpk 10)(2) VSD trr (IS = 37.5 Adc, VGS = 0, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 7.5 3.5 4.5 nH nH ta tb QRR 0.97 0.88 57 40 17 0.17 1.1 C ns Vdc 15 170 70 100 71 13 33 26 30 340 140 200 100 nC ns (VDS = 25 Vdc, VGS = 0, f = 1.0 MHz) (Cpk 2.0) 2 0)(2) Ciss Coss Crss 2600 1000 230 3900 1300 300 pF (Cpk 1.5) (Note 3.) VGS(th) 2.0 (Cpk 3.0) (Note 3.) RDS(on) VDS(on) gFS 15 0.86 0.64 mhos 7.0 9.5 Vdc 6.3 4.0 Vdc mV/C mW (Cpk 2.0) (Note 3.) V(BR)DSS 50 IDSS IGSS 10 100 100 nAdc 54.9 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1307

MTP75N05HD
TYPICAL ELECTRICAL CHARACTERISTICS (Note 4.)
160 140 I D , DRAIN CURRENT (AMPS) 120 100 80 60 40 20 0 0 0.5 1 1.5 2 5V 2.5 3 3.5 4 4.5 5 6V 160 140 I D , DRAIN CURRENT (AMPS) 120 100 80 60 40 20 0 0 1 2 3 4 5 100C TJ = -55C 25C 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V

7V

TJ = 25C

VDS 10 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.014 0.012 0.01 0.008 0.006 0.004 0.002 0 20 40 60 80 100 120 140 25C 0.009

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

TJ = 25C VGS = 10 V

0.008

0.007 15 V 0.006

-55C

0.005

20

40

60

80

100

120

140

160

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 10 V ID = 37.5 A

VGS = 0 V TJ = 125C

I DSS, LEAKAGE (nA)

1.5

1000

100

100C

0.5

10 25C

0 -50

-25

25

50

75

100

125

150

10

15

20

25

30

35

40

45

50

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature


4. Pulse Tests: Pulse Width 250 s, Duty Cycle 2%.

Figure 6. DrainToSource Leakage Current versus Voltage

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1308

MTP75N05HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS 0 VDS 5 10 15 Crss Ciss Coss Ciss VDS = 0 VGS = 0

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with boardmounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

20

25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1309

MTP75N05HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 25 50 QT, TOTAL GATE CHARGE (nC) Q1 QT VGS Q2 60 50 40 30 20 TJ = 25C ID = 75 A 10 0 75 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C ID = 75 A VDD = 35 V VGS = 10 V

t, TIME (ns)

100

tr tf td(off) td(on)

VDS

10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
80 I S , SOURCE CURRENT (AMPS) 70 I S , SOURCE CURRENT (AMPS) 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 TJ = 25C VGS = 0 V

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
40 30 20 10 0 -10 -20 -30 -40 -120 -100 -80 -60 -40 -20 0 t, TIME (ns) 20 40 60 80

di/dt = 300 A/s

STANDARD CELL DENSITY trr HIGH CELL DENSITY trr tb ta

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


1310

Figure 11. Reverse Recovery Time (trr)

MTP75N05HD
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr,tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
1000 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

500 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 s ID = 75 A 400 300 200 100 0

100

10

100 s

1 ms

10 ms dc

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT

0.1 0.1

1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

25

50

75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1311

MTP75N05HD
1 D = 0.5 r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.2 0.1 0.1 0.05 0.02 P(pk) RJC(t) = r(t) RJC RJC = 1.0C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

0.01 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 t, TIME (s)

t2 DUTY CYCLE, D = t1/t2 1.0E-01

t1

0.01 1.0E-05

Figure 14. Thermal Response

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1312

MTP75N06HD
Preferred Device

Power MOSFET 75 Amps, 60 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for lowvoltage, highspeed switching applications in power supplies, converters and PWM motor controls, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Avalanche Energy Specified
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous GateSource Voltage Single Pulse Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 60 60 20 30 75 50 225 150 1.0 55 to 175 500 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 3 4

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75 AMPERES 60 VOLTS RDS(on) = 10 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

TO220AB CASE 221A STYLE 5

MTP75N06HD LLYWW 1 Gate 2 Drain 3 Source

C/W RJC RJA TL 1.0 62.5 260 C MTP75N06HD LL Y WW

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP75N06HD Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1313

November, 2000 Rev. 2

Publication Order Number: MTP75N06HD/D

MTP75N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 V) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 37.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 75 Adc) (ID = 37.5 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 37.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 75 Adc, VGS = 10 Vdc) (VDS = 30 Vdc, ID = 75 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 75 Adc, VGS = 0 Vdc) (IS = 75 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 75 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. 3. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA LD LS 3.5 7.5 nH nH ta tb QRR 0.97 0.88 56 44 12 0.103 1.1 C ns Vdc 18 218 67 125 71 16.3 31 29.4 26 306 94 175 100 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 2800 928 180 3920 1300 252 pF (Cpk 5.0) (Note 3.) VGS(th) 2.0 (Cpk 2.0) (Note 3.) RDS(on) VDS(on) gFS 15 0.7 0.53 32 0.9 0.8 mhos 8.3 10 Vdc 3.0 8.38 4.0 Vdc mV/C m (Cpk 2.0) (Note 3.) V(BR)DSS 60 IDSS IGSS 5.0 10 100 100 nAdc 68 60.4 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1314

MTP75N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
150 125 I D , DRAIN CURRENT (AMPS) 100 75 50 25 0 0 0.5 1 1.5 6V 150 I D , DRAIN CURRENT (AMPS) 125 100 75 50 100C 25 0 TJ = -55C 2 3 4 5 6 7 8

TJ = 25C 9V

VGS = 10 V

8V

VDS 10 V

7V

25C

5V 2

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.016 0.014 0.012 0.010 25C 0.008 0.006 0.004 0 25 50 -55C 75 100 125 150 0.012 0.011 0.010 0.009 0.008 0.007 0.006 0

Figure 2. Transfer Characteristics

TJ = 25C VGS = 10 V

TJ = 25C

TJ = 100C

VGS = 10 V

15 V

25

50

75

100

125

150

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


1000 VGS = 10 V ID = 37.5 A 1.6 I DSS, LEAKAGE (nA) 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

1.9

VGS = 0 V

TJ = 125C

1.3

100C

10 25C

0.7 -50

-25

25

50

75

100

125

150

10

20

30

40

50

60

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1315

MTP75N06HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
7000 6000 C, CAPACITANCE (pF) 5000 4000 3000 2000 1000 0 10 5 VGS 0 VDS 5 10 Crss 15 20 25 Crss Ciss VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

Coss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1316

MTP75N06HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 VGS 8 6 4 2 Q3 0 0 10 20 30 40 50 60 ID = 75 A TJ = 25C VDS 70 QT, TOTAL GATE CHARGE (nC) Q1 Q2 40 30 20 10 0 80 QT 60 50 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDS = 30 V ID = 75 A VGS = 10 V TJ = 25C

tr tf td(off)

t, TIME (ns)

100

10

td(on) 1 10 RG, GATE RESISTANCE (Ohms) 100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 12. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
75 I S , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C 50

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

25

0 0.5

0.58

0.66

0.74

0.82

0.9

0.98

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current http://onsemi.com


1317

MTP75N06HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
1000 VGS = 20 V SINGLE PULSE TC = 25C

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

500 ID = 75 A 375

I D , DRAIN CURRENT (AMPS)

100

10 s 100 s

250

10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1 ms 10 ms dc 100

125

1 0.1

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1318

MTP75N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E-01 t1 P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

1.0E+00

1.0E+01

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1319

MTP7N20E
Preferred Device

Power MOSFET 7 Amps, 200 Volts


NChannel TO220
This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Total Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Adc, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS 74 MTP7N20E LL Y WW Value 200 200 20 40 7.0 3.8 21 50 0.4 55 to 150 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ 1 2 3 TO220AB CASE 221A STYLE 5 S

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7 AMPERES 200 VOLTS RDS(on) = 700 m


NChannel D

MARKING DIAGRAM & PIN ASSIGNMENT


4 4 Drain

MTP7N20E LLYWW 3 Source 2 Drain

1 Gate

RJC RJA TL

2.5 62.5 260

C/W

= Device Code = Location Code = Year = Work Week

ORDERING INFORMATION
Device MTP7N20E Package TO220AB Shipping 50 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1320

November, 2000 Rev. 1

Publication Order Number: MTP7N20E/D

MTP7N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.5 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 7.0 Adc) (VGS = 10 Vdc, ID = 3.5 Adc, TJ = 125C) Forward Transconductance (VDS = 14 Vdc, ID = 3.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 160 Vdc, ID = 7.0 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 7.0 Adc, VGS = 10 Vdc, Rg = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 7.0 Adc, VGS = 0 Vdc) (IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR 1.02 0.9 138 93 45 0.74 1.2 C ns Vdc 8.8 29 22 20 13.7 3.3 6.6 5.9 17.6 58 44 40.8 21 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 1 0 MHz) Ciss Coss Crss 342 92 27 480 130 55 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 1.5 3.4 5.9 5.1 mhos 3.1 7.1 0.46 4.0 0.7 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 10 100 100 nAdc 689 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery y Time (See Figure 14) 7 0 Adc, Adc VGS = 0 Vdc, Vdc (IS = 7.0 dIS/dt = 100 A/s)

Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad.) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 2. Switching characteristics are independent of operating junction temperature.

Ld Ls 7.5 3.5 4.5

nH

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1321

MTP7N20E
TYPICAL ELECTRICAL CHARACTERISTICS
14 ID , DRAIN CURRENT (AMPS) 12 10 8 6 4 2 0 0 2 4 6 8 10 6V 5V 12 7V 14 ID , DRAIN CURRENT (AMPS) 12 10 8 6 4 2 0 2 3 4 6 8 5 7 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10

TJ = 25C

VGS = 10 V

9V 8V

VDS 10 V

-55C TJ = 100C 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

1.2 VGS = 10 V 100C 1.0 0.8 0.6 0.4 0.2 0

0.7 TJ = 25C 0.65 0.6 0.55 0.5 0.45 0.4 15 V VGS = 10 V

TJ = 25C -55C

10

12

14

ID, DRAIN CURRENT (AMPS)

10

12

14

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


2.5 2 1.5 1 0.5 0 -50 1 100

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 3.5 A I DSS , LEAKAGE (nA)

VGS = 0 V

TJ = 125C

100C 10

25C

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

50 100 150 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

200

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1322

MTP7N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
900 750 C, CAPACITANCE (pF) 600 450 300 150 0 10 VDS = 0 V 5 Crss Coss Crss Ciss Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

5 0 10 15 20 25 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1323

MTP7N20E
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) 12 10 8 6 4 2 0 0 2 TJ = 25C ID = 7 A VDS 4 6 8 10 12 14 QG, TOTAL GATE CHARGE (nC) QT VGS Q1 Q2 180 150 120 90 60 30 0 1000 TJ = 25C ID = 7 A VDS = 100 V VGS = 10 V tr td(off) 10 td(on) tf

100

Q3

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


7 I S , SOURCE CURRENT (AMPS) 6 5 4 3 2 1 0 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1324

MTP7N20E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150

VGS = 20 V SINGLE PULSE TC = 25C 10 s 100 s

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

ID = 7A

10

1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100

1 ms 10 ms dc 1000

0.1 0.1

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1 10

t2 DUTY CYCLE, D = t1/t2 0.0001 0.001 0.01 t, TIME (SECONDS) 0.1

0.01 0.00001

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1325

MTSF1P02HD
Preferred Device

Advance Information Power MOSFET 1 Amp, 20 Volts


PChannel Micro8t
These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Miniature Micro8 Surface Mount Package Saves Board Space Extremely Low Profile (<1.1mm) for thin applications such as PCMCIA cards Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for Micro8 Package Provided
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1 AMPERE 20 VOLTS RDS(on) = 160 mW


PChannel D

G S

MARKING DIAGRAM

Micro8 CASE 846A STYLE 1 1

WW AB

WW

= Date Code

PIN ASSIGNMENT
Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
Device MTSF1P02HDR2 Package Micro8 Shipping 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value. This document contains information on a new product. Specifications and information herein are subject to change without notice.

Semiconductor Components Industries, LLC, 2000

1326

November, 2000 Rev. 2

Publication Order Number: MTSF1P02HD/D

MTSF1P02HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) *
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous Drain Current Continuous @ TA = 25C (Note 2.) Drain Current Continuous @ TA = 70C (Note 2.) Drain Current Pulsed Drain Current (Note 3.) Total Power Dissipation @ TA = 25C (Note 1.) Linear Derating Factor (Note 1.) Total Power Dissipation @ TA = 25C (Note 2.) Linear Derating Factor (Note 2.) Operating and Storage Temperature Range Symbol VDSS VDGR VGS ID ID IDM PD PD TJ, Tstg Symbol RJA RJA Typ. 55 125 Value 20 20 8.0 1.8 1.6 14.4 1.8 14.3 0.78 6.25 55 to 150 Max. 70 160 Unit Vdc Vdc Vdc Adc Apk Watts mW/C Watts mW/C C Unit C/W

THERMAL RESISTANCE
Rating Thermal Resistance Junction to Ambient, PCB Mount (Note 1.) Thermal Resistance Junction to Ambient, PCB Mount (Note 2.)

*Negative signs for PChannel device omitted for clarity. 1. When mounted on 1 square FR4 or G10 board (VGS = 4.5 V, @ Steady State) 2. When mounted on minimum recommended FR4 or G10 board (VGS = 4.5 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature.

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1327

MTSF1P02HD
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) (Note 4.)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Cpk 2.0) (Notes 4. & 6.) V(BR)DSS 20 IDSS IGSS 1.0 10 100 nAdc 12.8 Vdc mV/C Adc Symbol Min Typ Max Unit

Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 5.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 1.8 Adc) (VGS = 2.7 Vdc, ID = 0.9 Adc) Forward Transconductance (VDS = 10 Vdc, ID = 0.9 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 6.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vdc, ID = 1.8 Adc, VGS = 4.5 Vdc) (VDD = 10 Vdc, ID = 0.9 Adc, VGS = 2.7 Vdc, RG = 6.0 ) (Note 4.) (VDS = 10 Vdc, ID = 1.8 Adc, VGS = 4.5 Vdc, RG = 6.0 ) (Note 4.) (VDS = 10 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) (Note 6.)

VGS(th) 0.6 0.8 2.5 120 160 4.0 160 190

Vdc mV/C m

(Note 6.)

RDS(on)

(Note 4.)

gFS

2.0

Mhos

Ciss Coss Crss

440 300 150

pF

td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3

15 35 55 75 20 93 50 75 11 0.7 5.5 3.8

22

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 1.8 Adc, VGS = 0 Vdc) (Note 4.) (IS = 1.8 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 1.8 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. 6. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA ta tb QRR 1.24 0.9 120 33 87 0.223 2.0 C ns Vdc

Reverse Recovery Time

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1328

MTSF1P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
2 I D , DRAIN CURRENT (AMPS) 1.6 1.2 1.6 V 0.8 1.5 V 0.4 1.4 V 0 0 0.4 0.8 1.2 1.6 2 0 0.4 0.8 1.2 2 I D , DRAIN CURRENT (AMPS) TJ = 25C 1.7 V 1.6 1.2 0.8 0.4 TJ = 100C 25C -55C 1.6 2

VGS = 4.5 V 2.7 V 2V 1.9 V

1.8 V

VDS 10 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 ID = 1.8 A TJ = 25C 0.18

Figure 2. Transfer Characteristics

TJ = 25C 2.7 V

0.16

0.14 4.5 V

0.12

0.1

0.5

1 ID, DRAIN CURRENT (AMPS)

1.5

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnResistance versus GateToSource Voltage


2.0 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 2.7 V ID = 1.8 A

VGS = 0 V

TJ = 125C

1.5 I DSS , LEAKAGE (nA) 100

100C

1.0

10

25C

0.5

0 -50

-25

25

50

75

100

125

150

12

16

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTSF1P02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2000 Ciss C, CAPACITANCE (pF) 1500 VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

1000

Crss Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20

500

0 10

VDS, DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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1330

MTSF1P02HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 5 4 3 2 1 0 Q1 Q2 VDS QT 18 15 VGS 12 9 6 ID = 1.8 A TJ = 25C 3 6 Qg, TOTAL GATE CHARGE (nC) 9 3 0 12 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 10 V ID = 1.8 A VGS = 4.5 V TJ = 25C

t, TIME (ns)

100

tf td(off) tr td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100

Q3 0

10

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
2 1.6 1.2 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.8 0.4 0 0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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1331

MTSF1P02HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curve (Figure 12) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 8 V SINGLE PULSE TC = 25C 10 ms 1 dc 0.1

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

360 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 320 280 240 200 160 120 80 40 0 25 50 75 100

10

1 ms

VDD = 16 V VGS = 5 V IL = 6 A L = 20 mH

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 12. Maximum Rated Forward Biased Safe Operating Area

Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature

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1332

MTSF1P02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 1 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E+00 t1

100

10

P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

0.1 1.0E-05

Figure 14. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 15. Diode Reverse Recovery Waveform

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1333

MTSF1P02HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

Micro8 POWER DISSIPATION The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 1.8 Watts.
PD = 150C 25C = 1.8 Watts 70C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 70C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.8 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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1334

MTSF1P02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 16. Typical Solder Heating Profile

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1335

MTSF1P02HD
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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1336

MTSF3N02HD
Preferred Device

Power MOSFET 3 Amps, 20 Volts


NChannel Micro8t
These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Miniature Micro8 Surface Mount Package Saves Board Space Extremely Low Profile (<1.1mm) for thin applications such as PCMCIA cards Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for Micro8 Package Provided
8

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3 AMPERES 20 VOLTS RDS(on) = 40 mW


NChannel D

G S

MARKING DIAGRAM

Micro8 CASE 846A STYLE 1 1

WW AC

WW

= Date Code

PIN ASSIGNMENT
Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
Device MTSF3N02HDR2 Package Micro8 Shipping 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1337

November, 2000 Rev. 5

Publication Order Number: MTSF3N02HD/D

MTSF3N02HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous 1 SQ. FR4 or G10 PCB Figure 1 below Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Symbol VDSS VDGR VGS RTHJA PD ID ID IDM RTHJA PD ID ID IDM TJ, Tstg Max 20 20 8.0 70 1.79 14.29 6.1 4.9 49 160 0.78 6.25 4.0 3.2 32 55 to 150 Unit V V V C/W Watts mW/C A A A C/W Watts mW/C A A A C

Steady State Minimum FR4 or G10 PCB Figure 2 below

Steady State

Operating and Storage Temperature Range 1. Repetitive rating; pulse width limited by maximum junction temperature.

Figure 1. 1, Square FR4 or G10 PCB

Figure 2. Minimum FR4 or G10 PCB

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1338

MTSF3N02HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Cpk 2.0) (Notes 2. & 4.) V(BR)DSS 20 IDSS IGSS 1.0 25 100 nAdc 16 Vdc mV/C Adc Symbol Min Typ Max Unit

Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 8.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 4.5 Vdc, ID = 3.8 Adc) (VGS = 2.7 Vdc, ID = 1.9 Adc) (Cpk 2.0) (Note 4.)

VGS(th) 0.7 0.98 2.65 30 40 7.5 1.1 40 50

Vdc mV/C m

(Note 4.)

RDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge

(Note 2.)

gFS

4.0

Mhos

Ciss (VDS = 15 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Coss Crss

475 255 110

pF

td(on) (VDS = 10 Vdc, ID = 3.8 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) tr td(off) tf td(on) (VDD = 10 Vdc, ID = 1.9 Adc, VGS = 2.7 Vdc, RG = 6 ) (Note 2.) tr td(off) tf QT (VDS = 16 Vdc, ID = 3.8 Adc, VGS = 4.5 Vdc) Q1 Q2 Q3

9.5 45 50 62 19 130 38 47 12 1.0 5.0 3.5

17

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 3.8 Adc, VGS = 0 Vdc) (Note 2.) (IS = 3.8 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 3.8 3 8 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA VSD trr ta tb QRR 0.83 0.68 46 23 23 0.05 1.0 C ns Vdc

Reverse Recovery Time

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1339

MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
8 I D , DRAIN CURRENT (AMPS) 7 6 5 4 3 2 1 0 0 0.4 0.8 1.2 1.6 2 1.5 V 8 I D , DRAIN CURRENT (AMPS) 7 6 5 4 3 2 1 0 1 1.2 1.4 TJ = -55C 25C 100C 1.6 1.8 2 VDS 10 V

VGS = 10 V 4.5 V 2.9 V 2.5 V 2.3 V 2.1 V

TJ = 25C 1.9 V

1.7 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.06 0.05 0.04 0.03 0.02 0.01 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.06 0.05 0.04 0.03 0.02 0.01

Figure 4. Transfer Characteristics

VGS = 3.8 V TJ = 25C

TJ = 25C

VGS = 2.7 V 4.5 V

6 2 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

Figure 5. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 6. OnResistance versus Drain Current and Gate Voltage

2.0

VGS = 4.5 V ID = 1.9 A

1000

VGS = 0 V

TJ = 125C 100C

1.0

I DSS , LEAKAGE (nA)

1.5

100

10

0.5

25C

0 -50

-25

25

50

75

100

125

150

0.1

12

16

20

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. OnResistance Variation with Temperature

Figure 8. DraintoSource Leakage Current versus Voltage

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1340

MTSF3N02HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
2500 2000 C, CAPACITANCE (pF) 1500 1000 500 0 Crss 4 VDS Ciss Coss 8 4 VGS 0 8 12 16 20 Ciss Crss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C VGS = 0 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 9. Capacitance Variation

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1341

MTSF3N02HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 5 4 3 2 1 Q3 0 0 3 6 9 Qg, TOTAL GATE CHARGE (nC) 12 ID = 3.8 A TJ = 25C Q1 VDS Q2 QT VGS 18 15 12 9 6 3 0 15 1000 VDD = 10 V ID = 3.8 A VGS = 4.5 V TJ = 25C tf tr

100 t, TIME (ns)

td(off) 10 td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 10. GateToSource and DrainToSource Voltage versus Total Charge

Figure 11. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
4 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0 0.4

0.5

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 12. Diode Forward Voltage versus Current

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1342

MTSF3N02HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 13. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use.
100 I D , DRAIN CURRENT (AMPS) VGS = 8 V SINGLE PULSE TC = 25C 10 ms

Switching between the off state and the on state may traverse any load line provided neither rated peak current (I DM ) nor rated voltage (V DSS ) is exceeded, and that the transition time (t r, tf ) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (T J(MAX) T C )/(R JC ).

10

1 ms

100 s

1 dc 0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 14. Maximum Rated Forward Biased Safe Operating Area

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1343

MTSF3N02HD
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE ( C/W) D = 0.5 0.2 0.1 0.05 0.02 0.01 1.0 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E+00 t1

100

10

P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

0.1 1.0E-05

Figure 15. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 16. Diode Reverse Recovery Waveform

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1344

MTSF3N02HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

Micro8 POWER DISSIPATION The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.78 Watts.
PD = 150C 25C = 0.78 Watts 160C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 160C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.78 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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1345

MTSF3N02HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 14 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 17. Typical Solder Heating Profile

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1346

MTSF3N02HD
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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1347

MTSF3N03HD
Preferred Device

Power MOSFET 3 Amps, 30 Volts


NChannel Micro8t
These Power MOSFET devices are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. Micro8 devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Miniature Micro8 Surface Mount Package Saves Board Space Extremely Low Profile (<1.1 mm) for thin applications such as PCMCIA cards Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive Can Be Driven by Logic ICs Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for Micro8 Package Provided
8

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3 AMPERES 30 VOLTS RDS(on) = 40 mW


NChannel D

G S

MARKING DIAGRAM

Micro8 CASE 846A STYLE 1 1

WW AA

WW

= Date Code

PIN ASSIGNMENT
Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain

Top View

ORDERING INFORMATION
Device MTSF3N03HDR2 Package Micro8 Shipping 4000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1348

November, 2000 Rev. 4

Publication Order Number: MTSF3N03HD/D

MTSF3N03HD
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous 1 SQ. FR4 or G10 PCB Figure 1 below Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Thermal Resistance Junction to Ambient Total Power Dissipation @ TA = 25C Linear Derating Factor Drain Current Continuous @ TA = 25C Continuous @ TA = 70C Pulsed Drain Current (Note 1.) Symbol VDSS VDGR VGS RTHJA PD ID ID IDM RTHJA PD ID ID IDM TJ, Tstg EAS 200 Max 30 30 20 70 1.79 14.29 5.7 4.5 45 160 0.78 6.25 3.8 3.0 30 55 to 150 Unit V V V C/W Watts mW/C A A A C/W Watts mW/C A A A C mJ

Steady State Minimum FR4 or G10 PCB Figure 2 below

Steady State Operating and Storage Temperature Range

Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 5.0 mH, RG = 25 W) 1. Repetitive rating; pulse width limited by maximum junction temperature.

Figure 1. 1, Square FR4 or G10 PCB

Figure 2. Minimum FR4 or G10 PCB

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1349

MTSF3N03HD
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) (Cpk 2.0) (Notes 2. & 4.) V(BR)DSS 30 IDSS IGSS 1.0 25 100 nAdc 27 Vdc mV/C Adc Symbol Min Typ Max Unit

Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2.) Gate Threshold Voltage (Cpk 2.0) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.8 Adc) (VGS = 4.5 Vdc, ID = 1.9 Adc) (Cpk 2.0) (Note 4.)

VGS(th) 1.0 1.5 4.5 35 45 40 60

Vdc mV/C m

(Note 4.)

RDS(on)

Forward Transconductance (VDS = 10 Vdc, ID = 1.9 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 24 Vdc, ID = 3.7 Adc, VGS = 10 Vdc) (VDD = 15 Vdc, ID = 1.9 Adc, VGS = 4.5 Vdc, RG = 6 ) (Note 2.) (VDS = 15 Vdc, ID = 3.7 Adc, VGS = 10 Vdc, RG = 6 ) (Note 2.) (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz)

gFS

2.0

Mhos

Ciss Coss Crss

420 190 65

pF

td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3

7.0 19 32 36 7.0 11 29 23 18.5 1.4 5.5 7.1

26

ns

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 3.7 Adc, VGS = 0 Vdc) (Note 2.) (IS = 3.7 Adc, VGS = 0 Vdc, TJ = 125C) (IS = 3.7 3 7 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/s) (Note 2.) Reverse Recovery Storage Charge 2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. 4. Reflects typical values. Max limit Typ Cpk = 3 x SIGMA VSD trr ta tb QRR 0.82 0.7 28 14 14 0.028 1.0 C ns Vdc

Reverse Recovery Time

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1350

MTSF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
6 I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0 6 VDS 10 V I D , DRAIN CURRENT (AMPS) 5 4 3 2 1 0

VGS = 10 V 4.5 V 3.3 V 3.1 V

2.9 V

TJ = 25C

2.7 V

100C 25C TJ = -55C

2.5 V 2.3 V 2.1 V 0 0.5 1 1.5 2

1.5

2.5

3.5

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 0.06

Figure 4. Transfer Characteristics

ID = 3.8 A TJ = 25C

TJ = 25C 0.055 0.05 0.045 0.04 0.035 0.03 VGS = 4.5

10 V

4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

10

ID, DRAIN CURRENT (AMPS)

Figure 5. OnResistance versus GatetoSource Voltage


RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

Figure 6. OnResistance versus Drain Current and Gate Voltage

2.0

VGS = 10 V ID = 1.9 A

1000

VGS = 0 V

TJ = 125C

I DSS , LEAKAGE (nA)

1.5

100 100C 10 25C 1

1.0

0.5

0 -50

-25

25

50

75

100

125

150

0.1

10

15

20

25

30

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. OnResistance Variation with Temperature

Figure 8. DraintoSource Leakage Current versus Voltage

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1351

MTSF3N03HD
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1500 1200 C, CAPACITANCE (pF) 900 Crss 600 300 0 10 Ciss Crss 5 VGS 0 VDS 5 10 15 Coss VDS = 0 V Ciss VGS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 11) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

TJ = 25C

20

25

30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 9. Capacitance Variation

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1352

MTSF3N03HD
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 Q1 2 0 0 Q3 3 6 9 12 15 Qg, TOTAL GATE CHARGE (nC) Q2 ID = 3.7 A TJ = 25C 18 5 0 21 VDS VGS QT 30 25 20 15 10 1000 VDD = 15 V ID = 3.7 A VGS = 10 V TJ = 25C

100 t, TIME (ns)

10

tf td(off) tr td(on)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 10. GateToSource and DrainToSource Voltage versus Total Charge

Figure 11. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 13. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by
4 VGS = 0 V TJ = 25C

high di/dts. The diodes negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

I S , SOURCE CURRENT (AMPS)

0.5

0.6

0.7

0.8

0.9

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 12. Diode Forward Voltage versus Current

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1353

MTSF3N03HD
di/dt = 300 A/s I S , SOURCE CURRENT Standard Cell Density trr High Cell Density trr tb ta

t, TIME

Figure 13. Reverse Recovery Time (trr)

SAFE OPERATING AREA The Forward Biased Safe Operating Area curve (Figure 14) defines the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal Resistance General Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 ms

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 15). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

250 100 s EAS, SINGLE PULSE DRAINTOSOURCE AVALANCHE ENERGY (mJ) 200 150 100 50 0 VDD = 30 V VGS = 5 V IL = 9 A L = 5 mH

10

1 ms

1 dc 0.1

0.01 0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

25

50

75

100

125

150

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 14. Maximum Rated Forward Biased Safe Operating Area

Figure 15. Maximum Avalanche Energy versus Starting Junction Temperature

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1354

MTSF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE ( C/W) D = 0.5 0.2 0.1 0.05 0.02 0.01 1.0 SINGLE PULSE 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) t2 DUTY CYCLE, D = t1/t2 1.0E+00 t1

100

10

P(pk)

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+01 1.0E+02 1.0E+03

0.1 1.0E-05

Figure 16. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 17. Diode Reverse Recovery Waveform

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1355

MTSF3N03HD INFORMATION FOR USING THE Micro8 SURFACE MOUNT PACKAGE


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65
inches mm

Micro8 POWER DISSIPATION The power dissipation of the Micro8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the Micro8 package, PD can be calculated as follows:
PD = TJ(max) TA RJA

into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 0.78 Watts.
PD = 150C 25C = 0.78 Watts 160C/W

The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values

The 160C/W for the Micro8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 0.78 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

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1356

MTSF3N03HD
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 PREHEAT ZONE 1 RAMP 200C

STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP

STEP 4 HEATING ZONES 3 & 6 SOAK

DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C

160C

STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C SPIKE PEAK AT 170C SOLDER JOINT

150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

TIME (3 TO 7 MINUTES TOTAL)

TMAX

Figure 18. Typical Solder Heating Profile

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1357

MTSF3N03HD
TAPE & REEL INFORMATION
Micro8 Dimensions are shown in millimeters (inches)

2.05 (.080) 1.95 (.077) PIN NUMBER 1 4.10 (.161) 3.90 (.154) B B A

1.60 (.063) 1.50 (.059) 1.85 (.072) 1.65 (.065) 0.35 (.013) 0.25 (.010)

12.30 11.70 (.484) (.461)

5.55 (.218) 5.45 (.215) 3.50 (.137) 3.30 (.130)

FEED DIRECTION
5.40 (.212) 5.20 (.205)

8.10 (.318) 7.90 (.312)

1.60 (.063) 1.50 (.059) TYP.

1.50 (.059) 1.30 (.052)

SECTION AA

SECTION BB
NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER.

18.4 (.724) MAX. NOTE 3

13.2 (.52) 12.8 (.50) 330.0 (13.20) MAX. 50.0 (1.97) MIN.

NOTES: 1. CONFORMS TO EIA4811. 2. CONTROLLING DIMENSION: MILLIMETER. 3. INCLUDES FLANGE DISTORTION AT OUTER EDGE. 4. DIMENSION MEASURED AT INNER HUB.

14.4 (.57) 12.4 (.49) NOTE 4

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1358

MTW32N20E
Preferred Device

Power MOSFET 32 Amps, 200 Volts


NChannel TO247
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Isolated Mounting Hole
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vpk, IL = 32 Apk, L = 1.58 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 200 200 20 32 19 128 180 1.44 55 to 150 810 Unit Vdc Vdc Vdc Adc Apk Watts W/C C mJ MTW32N20E LLYWW 1 2 3 TO247AE CASE 340K Style 1

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32 AMPERES 200 VOLTS RDS(on) = 75 m


NChannel D

G S 4

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

RJC RJA TL

0.7 40 260

C/W C LL Y WW

1 Gate 2 Drain

3 Source

= Location Code = Year = Work Week

ORDERING INFORMATION
Device MTW32N20E Package TO247 Shipping 30 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1359

November, 2000 Rev. 4

Publication Order Number: MTW32N20E/D

MTW32N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 V, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0) (VDS = 200 Vdc, VGS = 0, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 16 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 32 Adc) (ID = 16 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 1. & 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 160 Vdc, ID = 32 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 6.2 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS (Note 1.) Forward On-Voltage (IS = 32 Adc, VGS = 0) (IS = 16 Adc, VGS = 0, TJ = 125C) VSD trr (IS = 32 Adc, VGS = 0, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 5.0 13 nH nH ta tb QRR 1.1 0.9 280 195 85 2.94 2.0 C ns Vdc 25 120 75 91 85 12 40 30 50 240 150 182 120 nC ns (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 3600 130 690 5000 250 1000 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 12 3.0 2.7 mhos 8.0 0.064 4.0 0.075 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 250 1000 100 nAdc 247 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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1360

MTW32N20E
TYPICAL ELECTRICAL CHARACTERISTICS
100 I D , DRAIN CURRENT (AMPS) 80 60 40 6V 20 5V 0 0 2 4 6 8 10 0 0 2 4 6 8 10 50 I D , DRAIN CURRENT (AMPS) 40 30 20 10 VDS 10 V

TJ = 25C

VGS = 10 V

9V 8V 7V

TJ = -55C

100C 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0 8 16 24 32 40 48 56 64 -55C 25C 0.1

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

TJ = 25C 0.09 0.08 0.07 0.06 0.05 VGS = 10 V 15 V

16

24

32

40

48

56

64

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


2.5 VGS = 10 V ID = 16 A 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 0 V I DSS, LEAKAGE (mA) 2000 1000 TJ = 125C

1.5

200 100 100C 20 25C 0 50 100 150 200 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

0.5 -50

-25

25

50

75

100

125

150

10

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1361

MTW32N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
10000 8000 C, CAPACITANCE (pF) Crss 6000 4000 2000 Coss 0 10 5 VGS 0 VDS 5 10 15 20 25 Ciss VDS = 0

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by L di/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1362

MTW32N20E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 20 16 12 8 4 0 Q3 0 10 20 30 40 50 60 70 QT, TOTAL CHARGE (nC) 80 90 TJ = 25C ID = 32 A VDS = 160 V QT Q1 Q2 200 180 160 140 120 100 80 VGS 60 40 20 0 100 1000 TJ = 25C ID = 32 A VDD = 100 V VGS = 10 V td(off) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) tr tf

VDS

200 t, TIME (ns) 100

td(on)

20 10

2 1 1 2 20 10 RG, GATE RESISTANCE (OHMS) 100

Figure 9. GateToSource and DrainToSource Voltage versus Total Charge

Figure 8. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


TJ = 25C VGS = 0 V

30 I S , SOURCE CURRENT (AMPS)

20

10

0.2 0.4 0.6 0.8 1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1363

MTW32N20E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 200 100 20 10 2 1 0.2 0.1

EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C

750 600 450 300 150 0 25

ID = 32 A

10 s .1 1 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc

100 200 10 20 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1000

50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)

150

Figure 13. Maximum Rated Forward Biased Safe Operating Area


1 r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 0.1 0.05 0.02 0.02 0.01 0.01 SINGLE PULSE P(pk)

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

0.2 0.1

0.002 0.001 0.01

t2 DUTY CYCLE, D = t1/t2 0.02 0.1 0.2 1 2 t, TIME (ms) 10 20

t1

RJC(t) = r(t) RJC RJC = 0.7C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 100 200 1000

Figure 11. Thermal Response

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1364

MTW32N25E
Preferred Device

Power MOSFET 32 Amps, 250 Volts


NChannel TO247
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Isolated Mounting Hole Reduces Mounting Hardware
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 250 250 20 40 32 25 96 250 2.0 55 to 150 600 Unit Vdc Vdc 1 Vdc Vpk Adc Apk Watts W/C C mJ 1 Gate RJC RJA TL 0.50 40 260 C/W C 2 Drain LL Y WW = Location Code = Year = Work Week 3 Source MTW32N25E LLYWW 2 4 TO247AE CASE 340K Style 1 3

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32 AMPERES 250 VOLTS RDS(on) = 80 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

ORDERING INFORMATION
Device MTW32N25E Package TO247 Shipping 30 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1365

November, 2000 Rev. 3

Publication Order Number: MTW32N25E/D

MTW32N25E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 250 Vdc, VGS = 0 Vdc) (VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 16 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 32 Adc) (ID = 16 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 200 Vdc, ID = 32 Adc, VGS = 10 Vdc) (VDD= 125 Vdc, ID = 32 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 32 Adc, VGS = 0 Vdc) (IS = 32 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 32 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 13 nH nH ta tb QRR 1.0 0.92 312 220 93 3.6 1.5 C ns Vdc 31 133 93 108 97 22 43 41 60 266 186 216 136 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 3800 726 183 5350 1020 370 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 11 2.2 20 2.6 2.5 mhos 7.0 0.07 4.0 0.08 Vdc mV/C Ohm Vdc V(BR)DSS 250 IDSS IGSS 10 100 100 nAdc 300 380 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1366

MTW32N25E
TYPICAL ELECTRICAL CHARACTERISTICS
64 I D , DRAIN CURRENT (AMPS) 56 48 40 32 24 16 8 0 0 1 2 3 4 5 6 7 8 5V 6V 64 I D , DRAIN CURRENT (AMPS) 56 48 40 32 24 16 8 10 0 2 3 4 5 6 7 8 100C

TJ = 25C 9V

VGS = 10 V 8V

7V

VDS 10 V

TJ = -55C 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0

VGS = 10 V TJ = 100C

0.084 0.08 0.076

TJ = 25C

25C

VGS = 10 V 0.072 15 V 0.068 0.064

-55C

16

32 48 24 40 ID, DRAIN CURRENT (AMPS)

56

64

16

24 40 32 48 ID, DRAIN CURRENT (AMPS)

56

64

Figure 3. OnResistance versus Drain Current and Temperature


2.0 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 2.0 A

VGS = 0 V

TJ = 125C 100C

I DSS , LEAKAGE (nA)

1.6

1000

1.2

100

0.8

10

25C

0.4 -50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

50 150 100 200 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

250

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1367

MTW32N25E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS 0 VDS 5 Crss 10 Coss 15 20 25 Crss Ciss VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1368

MTW32N25E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 0 10 ID = 32 A TJ = 25C 70 80 90 VGS Q1 Q2 QT 300 250 200 150 100 50 0 100 1000 VDD = 125 V ID = 32 A VGS = 10 V TJ = 25C 100 tr tf td(off) td(on) 10 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Q3 20 30 40 50

VDS 60 QT, TOTAL CHARGE (nC)

t, TIME (ns)

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


32 VGS = 0 V TJ = 25C

I S , SOURCE CURRENT (AMPS)

24

16

0 0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1.0

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1369

MTW32N25E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 600 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 s 500 400 300 200 100 0 25 50 75 100 125 150 ID = 32 A

VGS = 20 V SINGLE PULSE TC = 25C

10 1 ms 10 ms 1.0 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1.0 10 100 1000 dc

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 14. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 0.2

0.1

0.1 0.05 0.02 P(pk) 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 t1 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.01

0.001 1.0E-05

1.0E-04

1.0E-03

1.0E-02 t, TIME (s)

1.0E-01

1.0E+00

1.0E+01

Figure 12. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 13. Diode Reverse Recovery Waveform

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1370

MTW35N15E
Preferred Device

Power MOSFET 35 Amps, 150 Volts


NChannel TO247
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Isolated Mounting Hole Reduces Mounting Hardware
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 150 150 20 40 35 26.9 105 180 1.45 55 to 150 600 Unit Vdc Vdc 1 Vdc Vpk Adc Apk Watts W/C C mJ 1 Gate RJC RJA TL 0.70 62.5 260 C/W C 2 Drain LL Y WW = Location Code = Year = Work Week 3 Source MTW35N15E LLYWW 2 4 TO247AE CASE 340K Style 1 3

http://onsemi.com

35 AMPERES 150 VOLTS RDS(on) = 50 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

ORDERING INFORMATION
Device MTW35N15E Package TO247 Shipping 30 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1371

November, 2000 Rev. 4

Publication Order Number: MTW35N15E/D

MTW35N15E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 150 Vdc, VGS = 0 Vdc) (VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 17.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 35 Adc) (ID = 17.5 Adc, TJ = 125C) Forward Transconductance (VDS = 10 Vdc, ID = 17.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 120 Vdc, ID = 35 Adc, VGS = 10 Vdc) (VDD = 75 Vdc, ID = 35 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 35 Adc, VGS = 0 Vdc) (IS = 35 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 35 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 13 nH nH ta tb QRR 0.95 0.9 200 167 32 1.63 1.5 C ns Vdc 28 170 90 103 98 19 49 40 56 346 180 210 137 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 3600 855 165 5040 1170 330 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 11 1.45 18 1.8 1.7 mhos 7.0 4.0 0.05 Vdc mV/C Ohm Vdc V(BR)DSS 150 IDSS IGSS 10 100 100 nAdc 210 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1372

MTW35N15E
TYPICAL ELECTRICAL CHARACTERISTICS
70 I D , DRAIN CURRENT (AMPS) 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 5.0 V 3.5 4.0 6.0 V TJ = 25C 70 I D , DRAIN CURRENT (AMPS) 8.0 V 7.0 V 60 50 40 30 20 10 0 2.0 3.0 4.0

VGS = 10 V 9.0 V

VDS 10 V

100C TJ = -55C 5.0 6.0

25C

7.0

8.0

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS) 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 10 20 50 30 40 ID, DRAIN CURRENT (AMPS) 60 70 25C RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

VGS = 10 V TJ = 100C

0.047 0.045 0.043 0.041 0.039 0.037 0.035

TJ = 25C

VGS = 10 V

-55C

15 V

10

20 30 40 50 ID, DRAIN CURRENT (AMPS)

60

70

Figure 3. OnResistance versus Drain Current and Temperature


2.5 RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED) 2.0 1.5 1.0 0.5 0 -50 1000

Figure 4. OnResistance versus Drain Current and Gate Voltage

VGS = 10 V ID = 17.5 A

VGS = 0 V

TJ = 125C 100C

I DSS , LEAKAGE (nA)

100

10

1.0 25C 0.1

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

100 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

150

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1373

MTW35N15E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
10000 8000 C, CAPACITANCE (pF) 6000 Crss 4000 2000 0 10 Crss 5 VGS 0 VDS 5 10 Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

Coss 15 20 25

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1374

MTW35N15E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8.0 6.0 4.0 2.0 0 Q3 0 20 40 60 80 QT, TOTAL CHARGE (nC) TJ = 25C ID = 35 A VDS Q1 Q2 QT VGS 120 100 80 60 40 20 0 100 1000 VDD = 75 V ID = 35 A VGS = 10 V TJ = 25C tr 100 tf td(off) td(on) 10 0 10 RG, GATE RESISTANCE (OHMS) 100 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

t, TIME (ns)

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


35 I S , SOURCE CURRENT (AMPS) 30 25 20 15 10 5 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VGS = 0 V TJ = 25C

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1375

MTW35N15E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 600 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 500 400 300 200 100 0 25 50 75 100 125 150 ID = 35 A

VGS = 20 V SINGLE PULSE TC = 25C

100 10 s 10 100 s 1 ms 1.0 10 ms DC

0.1

1.0

10

100

1000

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.05 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E-05 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1.0E+00 1.0E+01

t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

1.0E-04

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1376

MTW45N10E
Preferred Device

Power MOSFET 45 Amps, 100 Volts


NChannel TO247
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Isolated Mounting Hole Reduces Mounting Hardware
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 45 Apk, L = 0.8 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS Value 100 100 20 40 45 34.6 135 180 1.44 55 to 150 810 Unit Vdc Vdc 1 Vdc Vpk Adc Apk Watts W/C C mJ 1 Gate RJC RJA TL 0.70 62.5 260 C/W C 2 Drain LL Y WW = Location Code = Year = Work Week 3 Source MTW45N10E LLYWW 2 4 TO247AE CASE 340K Style 1 3

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45 AMPERES 100 VOLTS RDS(on) = 35 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT


4 Drain

ORDERING INFORMATION
Device MTW45N10E Package TO247 Shipping 30 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1377

November, 2000 Rev. 3

Publication Order Number: MTW45N10E/D

MTW45N10E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 22.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 45 Adc) (ID = 22.5 Adc, TJ = 125C) Forward Transconductance (VDS = 10 Vdc, ID = 22.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 80 Vdc, ID = 45 Adc, VGS = 10 Vdc) (VDD= 50 Vdc, ID = 45 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (Note 1.) (IS = 45 Adc, VGS = 0 Vdc) (IS = 45 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr Adc VGS = 0 Vdc, Vdc (IS = 45 Adc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 7.5 nH nH ta tb QRR 1.09 1.04 166 118 48 1.1 1.635 C ns Vdc 25 234 83 116 106 26 54 44 50 470 170 240 220 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1.0 MHz) Ciss Coss Crss 3480 1240 315 5000 2000 650 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 12 1.13 2.16 1.53 mhos 7.0 0.027 4.0 0.035 Vdc mV/C Ohm Vdc V(BR)DSS 100 IDSS IGSS 10 100 100 nAdc 116 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure (See Fi 14)

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1378

MTW45N10E
TYPICAL ELECTRICAL CHARACTERISTICS
90 80 I D , DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5V 4V 4.5 5.0 6V 90 7V I D , DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 100C

TJ = 25C

VGS = 10 V 9V

8V

VDS 10 V

TJ = -55C 25C

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

Figure 2. Transfer Characteristics

0.05

VGS = 10 V TJ = 100C

0.032 0.030

TJ = 25C

0.04

VGS = 10 V 0.028 0.026 0.024 0.022 15 V

0.03

25C

0.02

-55C

0.01

10

20

30 50 40 60 ID, DRAIN CURRENT (AMPS)

70

80

90

10

20

30 50 40 60 ID, DRAIN CURRENT (AMPS)

70

80

90

Figure 3. OnResistance versus Drain Current and Temperature


2.0 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 22.5 A

VGS = 0 V TJ = 125C

I DSS , LEAKAGE (nA)

1.6

1000

1.2

100

100C

0.8

10 25C

0.4 -50

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

1.0

20 40 60 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1379

MTW45N10E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
10000 8000 C, CAPACITANCE (pF) 6000 4000 2000 0 10 Crss Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25 VDS = 0 V Ciss

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1380

MTW45N10E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 Q1 6 4 2 0 0 10 VDS 30 40 50 60 70 80 ID = 45 A TJ = 25C 90 100 60 40 20 0 110 Q2 VGS 80 QT 120 100 1000 VDD = 50 V ID = 45 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

tr tf td(off) td(on)

100

Q3 20

10

10 RG, GATE RESISTANCE (OHMS)

100

QT, TOTAL CHARGE (nC)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


VGS = 0 V 40 T = 25C J 35 30 25 20 15 10 5 0 0.5 0.56 0.62 0.68 0.74 0.80 0.86 0.92 0.98 1.04 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1.1 45

I S , SOURCE CURRENT (AMPS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1381

MTW45N10E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 1000 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) ID = 45 A 800 600 400 200 0

VGS = 20 V SINGLE PULSE TC = 25C 10 s

100

10

100 s

1 ms 10 ms DC 10 100

1.0

0.1

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1.0 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.01 1.0E-05

1.0E-04

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1382

MTY55N20E
Preferred Device

Power MOSFET 55 Amps, 200 Volts


NChannel TO264
This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a draintosource diode with fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters, PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. Avalanche Energy Specified Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1 M) GateSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous @ TC = 25C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 110 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg EAS Value 200 200 20 40 55 165 300 2.38 55 to 150 3000 Unit Vdc Vdc Vdc Vpk 1 Adc Apk Watts W/C C mJ MTY55N20E LLYWW 2 3 TO264 CASE 340G Style 1

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55 AMPERES 200 VOLTS RDS(on) = 28 m


NChannel D

G S

MARKING DIAGRAM & PIN ASSIGNMENT

RJC RJA TL

0.42 40 260

C/W C

1 Gate 2 Drain LL Y WW

3 Source

= Location Code = Year = Work Week

ORDERING INFORMATION
Device MTY55N20E Package TO264 Shipping 25 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1383

November, 2000 Rev. 3

Publication Order Number: MTY55N20E/D

MTY55N20E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0, ID = 250 A) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 200 Vdc, VGS = 0 Vdc) (VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 27.5 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 55 Adc) (ID = 27.5 Adc, TJ = 125C) Forward Transconductance (VDS = 10 Vdc, ID = 27.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (S Figure (See Fi 8) (VDS = 160 Vdc, ID = 55 Adc, VGS = 10 Vdc) (VDD = 100 Vdc, ID = 55 Adc, VGS = 10 Vdc Vdc, RG = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (IS = 55 Adc, VGS = 0 Vdc) (IS = 55 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 55 Adc, Adc VGS = 0 Vdc, Vdc dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 4.5 13 nH nH ta tb QRR 0.75 1.1 310 220 90 4.6 1.2 C ns Vdc 33 200 150 170 245 33 128 79 66 400 300 340 343 nC ns (VDS = 25 Vd Vdc, VGS = 0 Vd Vdc, f = 1 MHz) Ciss Coss Crss 7200 1800 460 10080 2520 920 pF VGS(th) 2 RDS(on) VDS(on) gFS 30 1.3 37 1.6 1.8 mhos 7 4 0.028 Vdc mV/C Ohm Vdc V(BR)DSS 200 IDSS IGSS 10 200 100 nAdc 250 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time (S Figure Fi 14) (See

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1384

MTY55N20E
TYPICAL ELECTRICAL CHARACTERISTICS
120 I D , DRAIN CURRENT (AMPS) 100 80 6V 60 40 5V 20 0 4V 0 0.5 1 1.5 2 2.5 3 3.5 4 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) TJ = 25C 120 7V I D , DRAIN CURRENT (AMPS) 100 80 60 40 20 0 100C TJ = -55C 25C 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

VGS = 10 V

8V 9V

VDS 10 V

Figure 1. OnRegion Characteristics


RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.05 VGS = 10 V 0.04 0.03 0.02 -55C 0.01 0 TJ = 100C 0.027 0.026 0.025 0.024 0.023 0.022

Figure 2. Transfer Characteristics

TJ = 25C

VGS = 10 V

25C

15 V

20

40

60

80

100

120

20

40

60

80

100

120

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature


2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -50 -25 0 25 50 75 100 125 150 1 0 VGS = 10 V ID = 27.5 A

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

10000

VGS = 0 V

TJ = 125C 100C

I DSS , LEAKAGE (nA)

1000

100

10

25C

50

100

150

200

TJ, JUNCTION TEMPERATURE (C)

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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1385

MTY55N20E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP)
24000 20000 C, CAPACITANCE (pF) 16000 12000 8000 Coss 4000 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 Crss Ciss Ciss VDS = 0 V

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

VGS = 0 V

TJ = 25C

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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1386

MTY55N20E
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 10 8 6 4 2 0 Q3 0 50 100 150 VDS 200 Qg, TOTAL GATE CHARGE (nC) Q1 Q2 TJ = 25C ID = 55 A QT VGS 240 200 160 120 80 40 0 250 1000 VDD = 100 V ID = 55 A VGS = 10 V TJ = 25C 100

t, TIME (ns)

tr tf td(off)

td(on) 10

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. Gate Charge versus GatetoSource Voltage

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS


60 50 I S , SOURCE CURRENT (AMPS) 40 30 20 10 0 0.5 VGS = 0 V TJ = 25C

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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1387

MTY55N20E
SAFE OPERATING AREA
1000 I D , DRAIN CURRENT (AMPS) 3000 E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C 10 s 100 s RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 1 ms 10 ms 1000

ID = 55 A

100

2000

10

1000

dc 100

1 0.1

25

50

75

100

125

150

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area


r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 D = 0.5 0.2 0.1 0.1 0.02 0.01 SINGLE PULSE 0.05

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

P(pk)

t2 DUTY CYCLE, D = t1/t2 1.0E-04 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01

t1

RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)

0.01 1.0E-05

1.0E+00

1.0E+01

Figure 13. Thermal Response

di/dt IS trr ta tp IS tb TIME 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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1388

VN0300L
Preferred Device

Small Signal MOSFET 200 mAmps, 60 Volts


NChannel TO92
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 s) Continuous Drain Current Pulsed Drain Current Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg Value 60 60 20 40 200 500 350 2.8 Unit V V Vdc Vpk mA mA mW mW/C C S Max 312.5 300 Unit C/W C TO92 CASE 29 Style 22 12 G

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200 mAMPS 60 VOLTS RDS(on) = 1.2


NChannel D

THERMAL CHARACTERISTICS
Characteristics Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds Symbol RJA TL

MARKING DIAGRAM & PIN ASSIGNMENT


VN0300L YWW

1 Source 2 Gate Y WW

3 Drain

= Year = Work Week

ORDERING INFORMATION
Device VN0300L VN0300LRLRA VN0300LRLRE Package TO92 TO92 TO92 Shipping 1000 Units/Box 2000 Tape & Reel 2000 Tape & Reel

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1389

November, 2000 Rev. 2

Publication Order Number: VN0300L/D

VN0300L
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Max Unit

STATIC CHARACTERISTICS
DrainSource Breakdown Voltage (VDS = 0, ID = 10 A) Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0) (VDS = 48 Vdc, VGS = 0, TA = 125C) GateBody Leakage (VDS = 0, VGS = 30 V) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) OnState Drain Current (Note 1.) (VDS = VGS, ID = 1.0 mA) DrainSource On Resistance (Note 1.) (VGS = 5.0 V, ID = 0.3 A) (VGS = 10 V, ID = 1.0 A) Forward Transconductance (Note 1.) (VDS = 10 V, ID = 0.5 A) V(BR)DSS IDSS IGSS VGS(th) ID(on) rDS(on) gfs 200 3.3 1.2 mS 0.8 1.0 10 500 100 2.5 nA V A 30 V A

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 15 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 100 95 25 pF pF pF

SWITCHING CHARACTERISTICS
TurnOn Time TurnOff Time (VDD = 25 Vdc, ID = 1.0 A, RL = 24 , RG = 25 ) ton toff 30 30 ns ns

1. Pulse Test; Pulse Width < 300 ms, Duty Cycle v 2.0%.

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1390

VN2222LL
Preferred Device

Small Signal MOSFET 150 mAmps, 60 Volts


NChannel TO92
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Nonrepetitive (tp 50 s) Drain Current Continuous Pulsed Total Power Dissipation @ TA = 25C Derate above 25C Operating and Storage Temperature Range Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg Value 60 60 20 40 150 1000 400 3.2 55 to +150 mW mW/C C G S Unit Vdc Vdc Vdc Vpk mAdc

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150 mAMPS 60 VOLTS RDS(on) = 7.5


NChannel D

THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds Symbol RJA TL Max 312.5 300 Unit C/W C 12 3 TO92 CASE 29 Style 22

MARKING DIAGRAM & PIN ASSIGNMENT


VN2222LL YWW

1 Source 2 Gate Y WW

3 Drain

= Year = Work Week

ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 1393 of this data sheet. Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1391

November, 2000 Rev. 2

Publication Order Number: VN2222LL/D

VN2222LL
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 100 Adc) Zero Gate Voltage Drain Current (VDS = 48 Vdc, VGS = 0) (VDS = 48 Vdc, VGS = 0, TJ = 125C) GateBody Leakage Current, Forward (VGSF = 30 Vdc, VDS = 0) V(BR)DSS IDSS IGSSF 10 500 100 nAdc 60 Vdc Adc

ON CHARACTERISTICS (Note 1.)


Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 0.5 Adc) (VGS = 10 Vdc, ID = 0.5 Vdc, TC = 125C) DrainSource OnVoltage (VGS = 5.0 Vdc, ID = 200 mAdc) (VGS = 10 Vdc, ID = 500 mAdc) OnState Drain Current (VGS = 10 Vdc, VDS 2.0 VDS(on)) Forward Transconductance (VDS = 10 Vdc, ID = 500 mAdc) VGS(th) rDS(on) VDS(on) 750 100 7.5 13.5 Vdc 1.5 3.75 mA mhos 0.6 2.5 Vdc

ID(on) gfs

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 60 25 5.0 pF

SWITCHING CHARACTERISTICS (Note 1.)


TurnOn Delay Time TurnOff Delay Time (VDD = 15 Vdc, ID = 600 mA, Rgen = 25 , RL = 23 ) ton toff 10 10 ns

1. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%.

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1392

VN2222LL
2 1.8 I D, DRAIN CURRENT (AMPS) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1 2 3 4 5 6 7 8 9 TA = 25C I D, DRAIN CURRENT (AMPS) VGS = 10 V 9V 8V 7V 6V 5V 4V 3V 10 0 1 2 3 4 5 6 7 8 9 10 VDS, DRAIN-SOURCE VOLTAGE (VOLTS) VGS, GATE-SOURCE VOLTAGE (VOLTS) 0.8 0.6 0.4 0.2 VDS = 10 V -55C 125C 1 25C

Figure 1. Ohmic Region


r DS(on) , STATIC DRAIN-SOURCE ON-RESISTANCE (NORMALIZED) VGS(th) , THRESHOLD VOLTAGE (NORMALIZED)

Figure 2. Transfer Characteristics

2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 -60 -20 +20 +60 T, TEMPERATURE (C) +100 +140 VGS = 10 V ID = 200 mA

1.2 1.15 1.1 1.05 1 0.95 0.9 0.85 0.8 0.75 0.7 -60 -20 0 +20 +60 T, TEMPERATURE (C) +100 +140 VDS = VGS ID = 1 mA

Figure 3. Temperature versus Static DrainSource OnResistance

Figure 4. Temperature versus Gate Threshold Voltage

ORDERING INFORMATION
Device
VN2222LL VN2222LLRL VN2222RLRA VN2222RLRM

Package
TO92 TO92 TO92 TO92

Shipping
1000 Unit/Box 2000 Tape & Reel 2000 Tape & Reel 1000 Unit/Box

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1393

VN2406L
Preferred Device

Small Signal MOSFET 200 mAmps, 240 Volts


NChannel TO92
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 s) Continuous Drain Current Pulsed Drain Current Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg Value 240 60 20 40 200 500 350 2.8 Unit Vdc Vdc Vdc Vpk mAdc mAdc mW mW/C C S Max 312.5 300 Unit C/W C TO92 CASE 29 Style 22 12 G

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200 mAMPS 240 VOLTS RDS(on) = 6


NChannel D

THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds Symbol RJA TL

MARKING DIAGRAM & PIN ASSIGNMENT


VN2406L YWW

1 Source 2 Gate Y WW

3 Drain

= Year = Work Week

ORDERING INFORMATION
Device VN2406L VN2406LZL1 Package TO92 TO92 Shipping 1000 Units/Box 2000 Ammo Pack

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1394

November, 2000 Rev. 2

Publication Order Number: VN2406L/D

VN2406L
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Max Unit

STATIC CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 100 A) Zero Gate Voltage Drain Current (VDS = 120 Vdc, VGS = 0) (VDS = 120 Vdc, VGS = 0, TA = 125C) Gate Body Leakage (VDS = 0, VGS = 15 V) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) OnState Drain Current (Note 1.) (VGS = 10 V, VDS 2.0 VDS(on)) DrainSource On Resistance (Note 1.) (VGS = 2.5 V, ID = 0.1 A) (VGS = 10 V, ID = 0.5 A) Forward Transconductance (Note 1.) (VDS = 10 V, ID = 0.5 A) V(BR)DSS IDSS IGSS VGS(th) ID(on) rDS(on) gfs 300 10 6.0 mS 0.8 1.0 10 500 100 2.0 nAdc Vdc Adc 240 Vdc Adc

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 125 50 20 pF pF pF

SWITCHING CHARACTERISTICS
TurnOn Time (VDD = 60 Vd Vdc, ID = 0.4 0 4 A, A RL = 150 , RG = 25 ) TurnOff Time 1. Pulse Test; Pulse Width < 300 s, Duty Cycle v 2.0%. t(on) t(r) t(off) t(f) 8.0 8.0 23 34 ns ns ns ns

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1395

VN2410L
Preferred Device

Small Signal MOSFET 200 mAmps, 240 Volts


NChannel TO92
MAXIMUM RATINGS
Rating DrainSource Voltage DrainGate Voltage GateSource Voltage Continuous Nonrepetitive (tp 50 s) Continuous Drain Current Pulsed Drain Current Power Dissipation @ TC = 25C Derate above 25C Operating and Storage Temperature Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg Value 240 60 20 40 200 500 350 2.8 Unit Vdc Vdc Vdc Vpk mAdc mAdc mW mW/C C S Max 312.5 300 Unit C/W C TO92 CASE 29 Style 22 12 G

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200 mAMPS 60 VOLTS RDS(on) = 10


NChannel D

THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/16 from case for 10 seconds Symbol RJA TL

MARKING DIAGRAM & PIN ASSIGNMENT


VN2410L YWW

1 Source 2 Gate Y WW

3 Drain

= Year = Work Week

ORDERING INFORMATION
Device VN2410L VN2410LZL1 Package TO92 TO92 Shipping 1000 Units/Box 2000 Ammo Pack

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

1396

November, 2000 Rev. 2

Publication Order Number: VN2410L/D

VN2410L
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristic Symbol Min Max Unit

STATIC CHARACTERISTICS
DrainSource Breakdown Voltage (VGS = 0, ID = 100 A) Zero Gate Voltage Drain Current (VDS = 120 Vdc, VGS = 0) (VDS = 120 Vdc, VGS = 0, TA = 125C) Gate Body Leakage (VDS = 0, VGS = 15 V) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) OnState Drain Current (Note 1.) (VGS = 10 V, VDS 2.0 VDS(on)) DrainSource On Resistance (Note 1.) (VGS = 2.5 V, ID = 0.1 A) (VGS = 10 V, ID = 0.5 A) Forward Transconductance (Note 1.) (VDS = 10 V, ID = 0.5 A) V(BR)DSS IDSS IGSS VGS(th) ID(on) rDS(on) gfs 300 10 10 mS 0.8 1.0 10 500 100 2.0 nAdc Vdc Adc 240 Vdc Adc

DYNAMIC CHARACTERISTICS
Input Capacitance Output Capacitance Reverse Transfer Capacitance (VDS = 25 Vd Vdc, VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 125 50 20 pF pF pF

SWITCHING CHARACTERISTICS
TurnOn Time (VDD = 60 Vd Vdc, ID = 0.4 0 4 A, A RL = 150 , RG = 25 ) TurnOff Time 1. Pulse Test; Pulse Width < 300 s, Duty Cycle v 2.0%. t(on) t(r) t(off) t(f) 8.0 8.0 23 34 ns ns ns ns

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1397

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1398

CHAPTER 2 MOSFET Application Note Abstracts

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1400

AN1040 Mounting Considerations for Power Semiconductors The operating environment is a vital factor in setting current and power ratings of a semiconductor device. Reliability is increased considerably for relatively small reductions in junction temperature. Faulty mounting not only increases the thermal gradient between the device and its heat sink, but can also cause mechanical damage. This comprehensive note shows correct and incorrect methods of mounting all types of discrete packages, and discusses methods of thermal system evaluation. AN1083 Basic Thermal Management of Power Semiconductors Switching audio amplifiers were impractical before the availability of complementary Power MOSFETs. Now, gate drive circuitry is simpler than for bipolar transistors, and the MOS devices operate more efficiently at higher frequencies. This detailed discussion of switching amplifier design is supported by a 72W Class D circuit. AN1090 Understanding and Predicting Power MOSFET Switching Behavior SPICE is a userfriendly, generalpurpose circuit simulation program for nonlinear DC, nonlinear transient and linear AC analysis. It is now available in various commmercial versions for use on personnel computers. ON and LAASCNRS Research Laboratory have bult a TMOS Power MOSFET library to simplify power dissipation simulation using SPICE. This note describes how to use the library; the physics of the Power MOSFET; the implementation of the model within SPICE; the method of extracting the parameters for the library; and a comparison of practical and simulated characteristics. AN1102 Interfacing Power MOSFETs to Logic Devices Most popular power MOSFETs need 10 volts of gate drive to support their maximum drain current. This creates problems when attempting to drive from 5V logic. The new logic level power MOSFETs solve some but not all of the problems. This note discusses easy methods of directly interfacing both types of MOSFET to TTL and CMOS logic, and to microprocessors such as the M68HC11. Discusses a method of calculating switching times, to minimize switching losses, and stresses the significance of logic power supply variations. AN1317 HighCurrent DC Motor Drive Uses Low OnResistance Surface Mount MOSFETs Surface mount technology have often been used in controllers for small disk drive motors with peak currents of 1 or 2 amps. Now the availability of low ONresistance, surface mount power MOSFETs has increased the current handling capability of surface mount technology. This application note presents a 5 amp DC motor drive board (DEVB148) using all surface mount components apart from the filter capacitor. It features a cyclebycycle current limit and is intended for direct control from a microcontroller. AN1319 Design Considerations for a Low Voltage NChannel HBridge Motor Drive Complementary MOSFET halfbridges are commonly used in low voltage motor drives to simplify gate drive design. However, the Pchannel FET in the halfbridge usually has higher ONresistance or is larger and more expensive then the Nchannel halfbridge, which uses silicon more efficiently and minimizes cost and conduction losses. The tradeoff is usually a more complex gate drive; this note looks at ways of minimizing gate drive complexity, and also discusses diode snap, shootthrough current and general design considerations. A design is implemented in the dEVB151 development board. AN1520 HDTMOS POWER MOSFETs Excel in Synchronous Rectifier Applications The new HDTMOS technology combines VLSI techniques with the ruggedness of vertical power structures to obtain increased cell density and to provide devices with lower overall onresistance. The reverse recovery characteristic of the parasitic body diode is also faster than in MOSFETs that use conventional technologies. This note examines the advantages of using HDTMOS transistors as synchronous rectifiers in a high power buck converter, and in a 5V DC to 3.3V DC buck converter, in order to increase circuit performance and efficiency while minimizing parts count. AN1541/D Introduction to insulated Gate Bipolar Transistors The ideal switch for use in power conversion applications would have zero voltage drop in the ON state, infinite resistance in the OFF state, would switch with infinite speed and not need any power to make it operate. IN practice, the designer must make a compromise and choose a device that suits the application with minimal loss of efficiency. Combining the low conduction losses of a BJT with the switching speed of a power MOSFET would create an optimal solid state switch. The insulated Gate Bipolar Transistor (IGBT) offers a combination of these attributes. This note explains how it is made, how it works, and how it compares with BJTs and power MOSFETs.

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1401

AN1570 Basic Semiconductor Thermal Measurement This application note provides basic information about power semiconductor thermal parameters, how they are measured, and how they are used. The intention is to enable the reader to better describe power semiconductors and to answer many common questions relating to their power handling capability. Four key topics are covered: Understanding basic semiconductor thermal parameters; Semiconductor thermal test equipment; Thermal parameter test procedures; Using thermal parameters to solve frequently asked thermal questions. AN211A Field Effect Transistors in Theory and Practice There are two types of fieldeffect transistor: the Junction FieldEffect Transistor (JFET) and the Metal Oxide Semiconductor FieldEffect Transistor (MOSFET). The principles on which these devices operate are very similar, the main difference being in the method by which the control element is made. This difference, however, results in a considerable difference in device characteristics and necessitates different approaches in circuit design. AN220 FETs in Chopper and Analog Switching Circuits The authors discussion begins with elementary chopper and analog switch characteristics, explores fully the considerations required for conventional and FET chopper and anlog switch design, and finishes with specific FET circuit examples. AN861 Power Transistor Safe Operating Area: Special Considerations for Motor Drives Motor drives present a unique set of safe operating area conditions for power output transistors. Starting with the basics of forward and reverse safe operating area, considerations unique to motor drives are discussed. The industrial motor drive application is sufficiently different from the electronics uses of power transistors that a new safe operating area specification has been developed. It is called overload safe operating area (OSLOA). The concept and that data sheet curves that go with it are presented. AN873 Understanding Power Transistor Dynamic Behavior: dv/dt Effects on Switching RBSOA Power transistor dynamic behavior can be affected to a large extent by dv/dt limitations. A look at the internal workings of the transistor readily shows how these limitations arise. A simple circuit model is developed which reproduces the behavior of power transistors in dv/dtlimited modes of operation. Experience with the model gives some guidelines for minimizing dv/dt limitations in practical circuits. AN875 Power Transistor Safe Operating Area: Special Considerations for Switching Power Supplies The purpose of this application note is to take a look at some of the more subtle aspects of how stress imposed by the power supply relates to transistor safe operating area, and to differentiate those stresses that the transistor can handle from those it cannot. In order to provide a proper foundation, special considerations are preceded by a review of forward bias safe operating area. AN876 Using Power MOSFETs in Stepping Motor Control Stepping Motor control techniques and circuits utilizing Power MOSFETs driven from CMOS Integrated Circuits are discussed. The techniques described are shift register phase generation, comparator switched current limiting, utilization of synchronous rectification, transient current suppression by use of the Power FET transfer characteristic, and the transient voltage protection requirements of the Power FET. The techniques are presented as components for an 88% efficient stepping motor drive circuit; however they are also applicable to other power control tasks. AN913 Designing with TMOS Power MOSFETs Clearly, the advantages and disadvantages that the power MOSFET gives technology are its specific realm of usefulness. Some designers also favor the power MMOSFET because of its extended FBSOA or its other more subtle advantages. The most common considerations that designers should be aware of when designing with TMOS power MOSFETs are outlined and explained here. AN918 Paralleling Power MOSFETs in Switching Applications The present TDT series of application notes are updated in this note with a more detailed analysis and design guide for TMOS power MOSFET parallel applications to account for devicetodevice parameter

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1402

AN929 Insuring Reliable Performance from Power MOSFETs Due to their many unique advantages, power MOSFETs are being used in an increasing number of applications. To aid the circuit designer in developing reliable power MOSFET circuits, this application note examines six potential problem areas and offers suggestions for eliminating or minimizing problems in each area. In addition, as an aid to the many designers who are using power MOSFETs in switchedmode power supplies, this note includes a section on improving switching power supply circuits. EB125 Testing Power MOSFET Gate Charge Most power MOSFET manufacturers now specify Gate Charge, as well as Input Capacitance, as an indication of the drive current required to turn on the device. The data can be useful in predicting switching speeds and drive losses. Commercially available gate charge test equipment is not yet widely used, and this simple tester for both N and Pchannel devices is a practical alternative for smaller users. EB131 Curve Tracer Measurement Techniques for Power MOSFETs Most curve tracers are designed to measure the parameters of bipolar transistors, but because of similarities in their characteristics, the same techniques can also be used to measure the parameters of power MOSFETs. This bulletin explains how, with particular reference to the Tektronix 370A Curve Tracer. EB201 High Cell Density MOSFETs HDTMOS technology brings high cell density with additional advantages such as greatly improved body diode performance. The technological advances are sufficiently great that they are fundamentally changing low voltage power transistor technology. This bulletin discusses high cell density technology and its benefits for the end user.

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1403

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1404

CHAPTER 3 MOSFET Case Outlines and Package Dimensions

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1406

CASE OUTLINE AND PACKAGE DIMENSIONS

CHIPFET CASE 1206A01 ISSUE A


NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A B C D G J K L M S MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.15 0.30 0.45 0.55 BSC 5 NOM --1.80 INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.012 0.018 0.022 BSC 5 NOM --0.071

A
8 7 6 5

M K
5 6 3 7 2 8 1

S
1 2 3 4

B
4

L G

C 0.05 (0.002)

SO8 CASE 75107 ISSUE W


X A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244

B
1 4

0.25 (0.010)

Y G C Z H D 0.25 (0.010)
M SEATING PLANE

X 45 _

0.10 (0.004)

Z Y

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1407

CASE OUTLINE AND PACKAGE DIMENSIONS

Micro8 CASE 846A02 ISSUE E


NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 --1.10 0.25 0.40 0.65 BSC 0.05 0.15 0.13 0.23 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 --0.043 0.010 0.016 0.026 BSC 0.002 0.006 0.005 0.009 0.187 0.199 0.016 0.028

PIN 1 ID

G D 8 PL 0.08 (0.003)
M

T B

SEATING PLANE

0.038 (0.0015) H

C J L

SOT223 (TO261) CASE 318E04 ISSUE K


A F

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3

S
1 2

D L G J C 0.08 (0003) H M K

INCHES DIM MIN MAX A 0.249 0.263 B 0.130 0.145 C 0.060 0.068 D 0.024 0.035 F 0.115 0.126 G 0.087 0.094 H 0.0008 0.0040 J 0.009 0.014 K 0.060 0.078 L 0.033 0.041 M 0_ 10 _ S 0.264 0.287

MILLIMETERS MIN MAX 6.30 6.70 3.30 3.70 1.50 1.75 0.60 0.89 2.90 3.20 2.20 2.40 0.020 0.100 0.24 0.35 1.50 2.00 0.85 1.05 0_ 10 _ 6.70 7.30

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1408

CASE OUTLINE AND PACKAGE DIMENSIONS

TSOP6 CASE 318G02 ISSUE G


A L
6 5 1 2 4 3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181

D G M 0.05 (0.002) H C K J

TSSOP8 CASE 948S01 ISSUE O


K REF 0.10 (0.004) L/2
8 5 M

8x

0.20 (0.008) T U

T U

2X

L
1 PIN 1 IDENT 4

B U

J J1


K1 K SECTION NN W

0.20 (0.008) T U

A V C

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ --2.20 --3.20 INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ --0.087 --0.126

0.076 (0.003) T
SEATING PLANE

DETAIL E

P N P1

0.25 (0.010) M

DIM A B C D F G J J1 K K1 L M P P1

F DETAIL E

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1409

CASE OUTLINE AND PACKAGE DIMENSIONS

SOT23 (TO236) CASE 31808 ISSUE AF


NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

A L
3 1 2

B S

G C D H K J

DIM A B C D G H J K L S V

INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0140 0.0285 0.0350 0.0401 0.0830 0.1039 0.0177 0.0236

MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.35 0.69 0.89 1.02 2.10 2.64 0.45 0.60

SC70/SOT323 CASE 41904 ISSUE L


A L
3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D G H J K L N S INCHES MIN MAX 0.071 0.087 0.045 0.053 0.032 0.040 0.012 0.016 0.047 0.055 0.000 0.004 0.004 0.010 0.017 REF 0.026 BSC 0.028 REF 0.079 0.095 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.00 0.30 0.40 1.20 1.40 0.00 0.10 0.10 0.25 0.425 REF 0.650 BSC 0.700 REF 2.00 2.40

S
1 2

D G

C 0.05 (0.002)

N K

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1410

CASE OUTLINE AND PACKAGE DIMENSIONS

SC88 (SOT363) CASE 419B01 ISSUE G


A G V
DIM A B C D G H J K N S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 0.012 0.016 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 0.30 0.40

S
1 2 3

D 6 PL

0.2 (0.008) N

J C

DPAK CASE 369A13 ISSUE AA


SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 --0.030 0.050 0.138 --MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 --0.77 1.27 3.51 ---

T B V R
4

C E

A S
1 2 3

Z U

K F L D G
2 PL

J H 0.13 (0.005)
M

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1411

CASE OUTLINE AND PACKAGE DIMENSIONS


D2PAK CASE 418B03 ISSUE D
C E B
4

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E G H J K S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40

A
1 2 3

T
SEATING PLANE

K G D 3 PL 0.13 (0.005) H
M

T B

TO220 THREELEAD TO220AB CASE 221A09 ISSUE AA


NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04

T B
4

SEATING PLANE

F T S

Q
1 2 3

A U K

H Z L V G D N R J

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1412

CASE OUTLINE AND PACKAGE DIMENSIONS

TO247 CASE 340K01 ISSUE C

0.25 (0.010)

Q T B M U A
1

T E B L R
2 3 DIM A B C D E F G H J K L P Q R U V

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 19.7 20.3 15.3 15.9 4.7 5.3 1.0 1.4 1.27 REF 2.0 2.4 5.5 BSC 2.2 2.6 0.4 0.8 14.2 14.8 5.5 NOM 3.7 4.3 3.55 3.65 5.0 NOM 5.5 BSC 3.0 3.4 INCHES MIN MAX 0.776 0.799 0.602 0.626 0.185 0.209 0.039 0.055 0.050 REF 0.079 0.094 0.216 BSC 0.087 0.102 0.016 0.031 0.559 0.583 0.217 NOM 0.146 0.169 0.140 0.144 0.197 NOM 0.217 BSC 0.118 0.134

V F D 0.25 (0.010)
M

H J

Y Q

TO264 CASE 340G02 ISSUE H

0.25 (0.010) B Q

T B

T C

U N A R Y P K
1 2 3

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. DIM A B C D E F G H J K L N P Q R U W MILLIMETERS MIN MAX 28.0 29.0 19.3 20.3 4.7 5.3 0.93 1.48 1.9 2.1 2.2 2.4 5.45 BSC 2.6 3.0 0.43 0.78 17.6 18.8 11.0 11.4 3.95 4.75 2.2 2.6 3.1 3.5 2.15 2.35 6.1 6.5 2.8 3.2 INCHES MIN MAX 1.102 1.142 0.760 0.800 0.185 0.209 0.037 0.058 0.075 0.083 0.087 0.102 0.215 BSC 0.102 0.118 0.017 0.031 0.693 0.740 0.433 0.449 0.156 0.187 0.087 0.102 0.122 0.137 0.085 0.093 0.240 0.256 0.110 0.125

F 2 PL G

W D 3 PL 0.25 (0.010)
M

J H Y Q
S

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1413

CASE OUTLINE AND PACKAGE DIMENSIONS

DPAK CASE 936D03 ISSUE B


NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. DIM A B C D E G H J K L M N P R S U V INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.125 MAX 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 3.175 MAX 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN

T A K B
1 2 3 4 5 OPTIONAL CHAMFER

TERMINAL 6

U V

S H M L

J D 0.010 (0.254)
M

N G R

TO92 CASE 2911 ISSUE AL

A R P L
SEATING PLANE

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 --0.250 --0.080 0.105 --0.100 0.115 --0.135 --MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 --6.35 --2.04 2.66 --2.54 2.93 --3.43 ---

X X G H V
1

D J C SECTION XX N N

DIM A B C D G H J K L N P R V

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1414

CHAPTER 4 Index

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1415

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1416

Index

Device Number 2N7000 2N7002LT1 BS107 BS107A BS108 BS170 BSS123LT1 BSS138LT1 BSS84LT1 MGB15N35CL MGB15N40CL MGB19N35CL MGP15N35CL MGP15N40CL MGP19N35CL MGSF1N02ELT1 MGSF1N02LT1 MGSF1N03LT1 MGSF1P02ELT1 MGSF1P02LT1 MGSF2P02HD MGSF3442VT1 MGSF3454VT1 MLD1N06CL MLP1N06CL MLP2N06CL MMBF0201NLT1 MMBF0202PLT1 MMBF1374T1 MMBF170LT1 MMBF2201NT1 MMBF2202PT1 MMDF1300 MMDF1N05E MMDF2C01HD MMDF2C02E MMDF2C02HD MMDF2C03HD

Page 264 267 271 271 275 277 280 284 289 293 301 309 293 301 309 316 320 324 328 332 336 344 349 354 360 366 372 377 382 384 388 392 396 399 404 416 427 439

Device Number MMDF2N02E MMDF2N05ZR2 MMDF2P01HD MMDF2P02E MMDF2P02HD MMDF2P03HD MMDF3N02HD MMDF3N03HD MMDF3N04HD MMDF3N06HD MMDF3N06VL MMDF4N01HD MMDF5N02Z MMDF6N03HD MMDF7N02Z MMDFS2P102 MMDFS6N303 MMFT107T1 MMFT2406T1 MMFT2955E MMFT2N02EL MMFT3055V MMFT3055VL MMFT5P03HD MMFT960T1 MMSF10N02Z MMSF10N03Z MMSF1308 MMSF1310 MMSF2P02E MMSF3300 MMSF3P02HD MMSF5N02HD MMSF5N03HD MMSF7N03HD MMSF7N03Z MPF930 MPF960

Page 451 459 468 477 485 494 503 512 521 531 540 542 551 560 569 579 589 599 605 610 619 628 637 646 656 662 671 681 689 697 705 715 724 733 742 751 761 761

Device Number MPF990 MTB1306 MTB20N20E MTB23P06V MTB29N15E MTB30N06VL MTB30P06V MTB36N06V MTB40N10E MTB50N06V MTB50N06VL MTB50P03HDL MTB52N06V MTB52N06VL MTB55N06Z MTB60N05HDL MTB60N06HD MTB75N03HDL MTB75N05HD MTB75N06HD MTD1302 MTD15N06V MTD15N06VL MTD20N03HDL MTD20N06HD MTD20N06HDL MTD20P03HDL MTD20P06HDL MTD2955V MTD3055V MTD3055VL MTD3302 MTD4N20E MTD5P06V MTD6N20E MTD6P10E MTD9N10E MTDF1N02HD

Page 761 765 772 781 790 798 807 816 825 834 843 852 862 871 880 885 895 905 915 922 932 942 951 960 970 980 990 1000 1010 1019 1028 1037 1048 1057 1066 1075 1084 1093

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1417

Index (continued)

Device Number MTDF1N03HD MTDF2N06HD MTP10N10E MTP10N10EL MTP12P10 MTP1302 MTP1306 MTP15N06V MTP15N06VL MTP20N06V MTP20N15E MTP20N20E MTP23P06V MTP27N10E MTP2955V MTP29N15E MTP2P50E MTP3055V MTP3055VL MTP30N06VL MTP30P06V MTP36N06V MTP40N10E MTP50N06V MTP50N06VL MTP50P03HDL MTP52N06V MTP52N06VL MTP5P06V MTP60N06HD MTP6P20E MTP75N03HDL MTP75N05HD

Page 1104 1115 1123 1130 1136 1141 1148 1155 1161 1167 1173 1175 1181 1187 1193 1199 1207 1213 1219 1225 1231 1237 1243 1249 1255 1261 1268 1274 1280 1286 1293 1299 1306

Device Number MTP75N06HD MTP7N20E MTSF1P02HD MTSF3N02HD MTSF3N03HD MTW32N20E MTW32N25E MTW35N15E MTW45N10E MTY55N20E NGD15N41CL NIB64045L NIMD6302R2 NTB45N06 NTB45N06L NTB75N0306 NTB75N03L09 NTD20N03L27 NTD20N06 NTD3055094 NTD3055L104 NTD32N06 NTD32N06L NTD4302 NTGS3433T1 NTGS3441T1 NTGS3443T1 NTGS3446T1 NTGS3455T1 NTHD5902T1 NTHD5903T1 NTHD5904T1 NTHD5905T1

Page 1313 1320 1326 1337 1348 1359 1365 1371 1377 1383 21 23 27 210 215 220 225 29 33 35 37 39 44 49 57 61 67 73 76 80 85 90 95

Device Number NTHS5402T1 NTHS5404T1 NTHS5441T1 NTHS5443T1 NTHS5445T1 NTMD3P03R2 NTMD6N02R2 NTMD6P02R2 NTMD7C02 NTMS10P02R2 NTMS3P03R2 NTMS4N01R2 NTMS4P01R2 NTMS5P02R2 NTMSD2P102LR2 NTMSD3P102R2 NTMSD3P303R2 NTP27N06 NTP45N06 NTP45N06L NTP75N0306 NTP75N03L09 NTQD6866 NTQS6463 NTTD1P02R2 NTTD2P02R2 NTTS2P02R2 NTTS2P03R2 NTUD01N02 VN0300L VN2222LL VN2406L VN2410L

Page 100 106 109 112 114 120 127 134 141 143 150 157 164 171 178 188 198 208 210 215 220 225 230 232 234 241 248 255 262 1389 1391 1394 1396

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1418

ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICES


UNITED STATES ALABAMA
Huntsville . . . . . . . . . . . 2567741000

CANADA ONTARIO
Ottawa . . . . . . . . . . . . . 6132263491

INTERNATIONAL (continued) ITALY


Milan . . . . . . . . . . . . . . . . 390282201

CALIFORNIA
Irvine . . . . . . . . . . . . . . . 9496238485 San Jose . . . . . . . . . . . 4083504800 Encino . . . . . . . . . . . . . . 8186549040

QUEBEC
St. Laurent . . . . . . . . . . 5143332125

JAPAN
Tokyo . . . . . . . . . . . . 83357402700

KOREA
Seoul . . . . . . . . . . . . . . 8225282700

COLORADO
Littleton . . . . . . . . . . . . . 3032565884

MALAYSIA
Penang . . . . . . . . . . . . 6042269368

FLORIDA
Tampa . . . . . . . . . . . . . . 8132866181

INTERNATIONAL BRAZIL
Sao Paulo . . . . . . 5501130305244

MEXICO
Guadalajara . . . . . . . . . 5236699100

GEORGIA
Atlanta . . . . . . . . . . . . . 8887933435

PHILIPPINES
Manila . . . . . . . . . . . . . 6328083801

ILLINOIS
Chicago . . . . . . . . . . . . 8474132500

CHINA
Beijing . . . . . . . . . . . 861065642288 Shenzhen . . . . . . . . 867552091128 Shanghai . . . . . . . . 862163907468

PUERTO RICO
San Juan . . . . . . . . . . . 7876414100

INDIANA
Carmel . . . . . . . . . . . . . 3178489958

SINGAPORE
Singapore . . . . . . . . . . . . 652981768

MASSACHUSETTS
Boston . . . . . . . . . . . . . 7813764223

CZECH REPUBLIC
Roznov . . . . . . . . . . 420651667141

SPAIN
Madrid . . . . . . . . . . . . 34917456817

MICHIGAN
Detroit . . . . . . . . . . . . . . 7349536704

FINLAND
Vantaa . . . . . . . . 358985666460

SWEDEN
Stockholm . . . . . . . . 46850904680

MINNESOTA
Plymouth . . . . . . . . . . . 6122492360

FRANCE
Paris . . . . . . . . . . 33139264100

TAIWAN
Taipei . . . . . . . . . . . 886227189961

NORTH CAROLINA
Raleigh . . . . . . . . . . . . . 9197855025

GERMANY
Munich . . . . . . . . . . . . 4989921030

THAILAND
Bangkok . . . . . . . . . . . 6626535031

PENNSYLVANIA
Philadelphia/Horsham 2159974340

HONG KONG
Hong Kong . . . . . . . . . 85226890088

UNITED KINGDOM
Aylesbury . . . . . . . . 441296610400

TEXAS
Dallas . . . . . . . . . . . . . . 9726330881

INDIA
Bangalore . . . . . . . . . . 91805598615

UTAH
Draper . . . . . . . . . . . . . . 8015724010

ISRAEL
Herzelia . . . . . . . . . . 97299609111

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ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS


DATA SHEET CLASSIFICATIONS A Data Sheet is the fundamental publication for each individual product/device, or series of products/devices, containing detailed parametric information and any other key information needed in using, designingin or purchasing of the product(s)/device(s) it describes. Below are the three classifications of Data Sheet: Product Preview; Advance Information; and Fully Released Technical Data PRODUCT PREVIEW A Product Preview is a summary document for a product/device under consideration or in the early stages of development. The Product Preview exists only until an Advance Information document is published that replaces it. The Product Preview is often used as the first section or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer at the bottom of the first page: This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. ADVANCE INFORMATION The Advance Information document is for a device that is NOT fully qualified, but is in the final stages of the release process, and for which production is eminent. While the commitment has been made to produce the device, final characterization and qualification may not be complete. The Advance Information document is replaced with the Fully Released Technical Data document once the device/part becomes fully qualified. The Advance Information document displays the following disclaimer at the bottom of the first page: This document contains information on a new product. Specifications and information herein are subject to change without notice. FULLY RELEASED TECHNICAL DATA The Fully Released Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces the Advance Information document and represents a part that is fully qualified. The Fully Released Technical Data document is virtually the same document as the Product Preview and the Advance Information document with the exception that it provides information that is unavailable for a product in the early phases of development, such as complete parametric characterization data. The Fully Released Technical Data document is also a more comprehensive document than either of its earlier incarnations. This document displays no disclaimer, and while it may be informally referred to as a data sheet, it is not labeled as such. DATA BOOK A Data Book is a publication that contains primarily a collection of Data Sheets, general family and/or parametric information, Application Notes and any other information needed as reference or support material for the Data Sheets. It may also contain cross reference or selector guide information, detailed quality and reliability information, packaging and case outline information, etc. APPLICATION NOTE An Application Note is a document that contains realworld application information about how a specific ON Semiconductor device/product is used, or information that is pertinent to its use. It is designed to address a particular technical issue. Parts and/or software must already exist and be available. SELECTOR GUIDE A Selector Guide is a document published, generally at set intervals, that contains key lineitem, devicespecific information for particular products or families. The Selector Guide is designed to be a quick reference tool that will assist a customer in determining the availability of a particular device, along with its key parameters and available packaging options. In essence, it allows a customer to quickly select a device. For detailed design and parametric information, the customer would then refer to the devices Data Sheet. The Master Components Selector Guide (SG388/D) is a listing of ALL currently available ON Semiconductor devices. REFERENCE MANUAL A Reference Manual is a publication that contains a comprehensive system or devicespecific descriptions of the structure and function (operation) of a particular part/system; used overwhelmingly to describe the functionality or application of a device, series of devices or device category. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less). HANDBOOK A Handbook is a publication that contains a collection of information on almost any give subject which does not fall into the Reference Manual definition. The subject matter can consist of information ranging from a device specific design information, to system design, to quality and reliability information. ADDENDUM A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in the primary publication it supports. Individual addendum items are published cumulatively. The Addendum is destroyed upon the next revision of the primary document. http://onsemi.com
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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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DL135/D

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