Exploring the Silicon Design Limits of Thin Wafer IGBT Technology: The Controlled Punch Through (CPT) IGBT

J. Vobeck, M. Rahimo, A. Kopta, S. Linder ISPSD, May 2008, Orlando, USA Copyright [2008] IEEE. Reprinted from the International Symposium on Power Semiconductor Devices & IC's.

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Exploring the Silicon Design Limits of Thin Wafer IGBT Technology: The Controlled Punch Through (CPT) IGBT
J. Vobeck, M. Rahimo, A. Kopta, S. Linder
ABB Switzerland Ltd, Semiconductors, Fabrikstrasse 3, CH - 5600 Lenzburg, Switzerland
Abstract - The paper introduces a new Controlled Punch Through (CPT) IGBT buffer for next generation devices, which utilise thin wafers technology. The new concept is based on very shallow buffers with optimized doping profiles enabling minimum silicon design thicknesses close to the theoretical limit for a given voltage class. The advanced shaping of the buffer doping profile brings additional degree of freedom in IGBT design. The work was carried out for 1200V IGBTs, but the CPT buffer can be applied with advantages to any voltage class. While this approach is targeting mainly reduced ON-State losses, the IGBT maintains good blocking, soft turn-off, wide SOA and good short circuit capability.

I. INTRODUCTION Thin wafer technology processing for the IGBT has seen continuous developments in the past ten years especially for power devices rated below 2000V. The introduction of Soft/Light Punch Through/Field Stop buffer concepts has enabled modern IGBTs to achieve very low losses due to the very thin silicon specifications for a given voltage class [1][2][3]. However, current SPT/FS type buffer designs are more and more approaching the silicon design limits and time comes to consider a new and more efficient buffer concept for further loss reductions while retaining good overall performance. Todays 1200V IGBT are designed with a total thickness ranging between 120 m up to 140 m. A large portion (25%-30%) of this thickness consists of the buffer region. The main purpose for such a thick buffer is to ensure good and controllable switching behaviour (softness) and stable reverse blocking. The buffer is relatively low doped and does not effectively utilize silicon thus giving a potential for further improvement of total IGBT losses. In addition, other performance parameters such as leakage current at higher operating temperatures and the ruggedness under short circuit conditions are heavily influenced by the bipolar transistor gain, which is largely dependent on the shape of the buffer design and the anode strength [4]. Last but not least, thin wafer processing requires that the majority of the backside processing is done after the front side cathode is completed, including metallisation. This limits the temperature treatments after thinning to below 500C and so the means for forming both the buffer and anode regions are very limited. In spite of such obstacles, the new concept of a very thin Controlled-Punch-Through (CPT) buffer keeping all common requirements laid on the state-of-the-art SPT-IGBT is proposed in Fig.1 and described below.

Fig.1: SPT IGBT (top) and the new CPT-IGBT (bottom).

II. THIN BUFFER OPTIMIZATION Using the existing SPT buffer for the 1200V IGBT, the rate of reduction the ON-State voltage VCEsat with decreasing thickness is 5 mV/m at 25oC and 9 mV/m at 125oC. However, by doing so, the breakdown voltage VBR is reduced by about 7 V/m at 25oC. Hence, the reduction from the current thickness down to 100 m decreases VCEsat by approximately 300 mV, while VBR drops well below 1200 V. In order to recover VBR back to above 1200 V, the point of stopping the electric field must be moved closer to the anode by about 15 20 m. The simplest way consists of replacing the SPT buffer by a narrow Gaussian profile as shown for a 100 m thick device in Fig.2a. This "Single buffer" can be obtained by ion implantation and subsequent annealing. While the positioning of this peak relatively to anode does not change VCEsat, it affects mainly the VBR and especially the leakage current. To obtain low leakage and high VBR, the buffer must be positioned away from the anode and its concentration well above 1x1016 cm-3. To rely on precise and reproducible processing of the single peak with concentrations above 1x1016 cm-3 using post implantation annealing below 500oC at aggressively thinned wafers is impractical. Moreover, there is an insufficient degree of freedom for setting all relevant parameters which are usually acting in trade-offs. Such drawbacks may be eliminated by the introduction of a second buffer peak as shown below.

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Fig.2b shows a "double buffer" that consists of two Gaussian peaks. The first one (N1) is placed at a certain distance from the anode and its role is to fully stop the electric field and keep the base width of PNP transistor independent of applied anode voltage. The second buffer (N2) is adjacent to the anode with the purpose of adjusting an optimal bipolar transistor gain even when utilizing high anode strengths. While the influence of buffers' parameters on the VCEsat is quantitatively similar, the leakage current is suppressed already from a peak concentration of N1 = 5x1015 cm-3 and VBR is increased as well. A suitable choice of various buffer peak concentrations N1 and N2 already brings a sufficient degree of freedom to the overall device design. The degree of freedom can be extended by modifying the donor concentration between N1 and N2 by incomplete annealing of implantation defects below 500oC.

The incomplete annealing modifies carrier lifetime within the buffer. As this controls the recombination rate in the base of the PNP transistor, it also modifies the bipolar gain and hereby relevant device parameters. All this results in what we refer to as the Controlled-Punch-Through (CPT) Buffer that is illustrated in Fig.2b) (hollow circles, top). The overall concept of the ON-state loss reduction is schematically summarized in Fig.1. The vertical arrow shows the point of stopping the electric field. It is actually the much steeper and higher doping profile of the CPT buffer N1 at the point of stopping the electric field that allows for reduction of the overall buffer thickness. The missing part of the SPT buffer is then more efficiently compensated for by the buffer peak N2.
Doping Concentration (a. u.) 10 10 10 10 10
4 3 2 1 0

SPT Buffer Anode Single Buffer

Depth Buffer Peak Concentration

N

SPT Buffer Anode Double Buffer CPT Buffer

P
N1 N2

0.5

0.6

1.75 1.70 1.65 1.60 15 1x10 Breakdown Voltage (V) 1200 1100 1000 900 800 700 600 500 15 1x10 Single Buffer: depth1 Single Buffer: depth2 Single Buffer: depth3

0.7 0.8 Depth (a. u.)

15 -3

0.9

1.0

(V)

1.75

1.70 1.65 1.60

VCESAT

Double Buffer N1=2.10 cm 15 -3 Double Buffer N1=5.10 cm 16 -3 Double Buffer N1=1.10 cm

1x10 -3 Buffer Peak Concentration (cm )

16

1x10

17

VCESAT

(V)

1x10

15

1x10 -3 Buffer N2 Peak Concentration (cm )

16

1x10

17

Breakdown Voltage (V)

Single Buffer: depth1 Single Buffer: depth2 Single Buffer: depth3 1x10 -3 Buffer Peak Concentration (cm )
16

1x10

17

1200 1100 1000 900 800 700 600 500 1x10

15

Double Buffer N1=2.10 cm 15 -3 Double Buffer N1=5.10 cm 16 -3 Double Buffer N1=1.10 cm

15

-3

1x10 -3 Buffer N2 Peak Concentration (cm )

15

16

1x10

17

Leakage Current (a. u.)

Leakage Current (a. u.)

60 50 40 30 20 10 0 15 1x10

Single Buffer: depth1 Single Buffer: depth2 Single Buffer: depth3

60 50 40 30 20 10 0 1x10

Double Buffer N1=2.10 cm 15 -3 Double Buffer N1=5.10 cm 16 -3 Double Buffer N1=1.10 cm

-3

1x10 -3 Buffer Peak Concentration (cm )

16

1x10

17

15

1x10 -3 Buffer N2 Peak Concentration (cm )

16

1x10

17

Fig. 2a: Simulated static parameters of the IGBT with a single peak N-buffer and total thickness of 100 m. Vcesat is simulated at T = 400K, the breakdown voltage and leakage current at T = 300K. The buffer depth from the anode is varied in the order of m: depth3>depth2 >depth1. Depth1 represents a buffer connected to the anode. Anode doping is identical for all simulated points.

Fig. 2b Simulated static parameters of the IGBT with a double peak N-buffer and total thickness of 100 m. Vcesat is simulated at T = 400K, the breakdown voltage and leakage current at T = 300K. The CPT buffer is shown without any electrical data for illustration (top). The arrows show the area of practical importance. Anode doping is identical for all simulated points.

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III. EXPERIMENTAL RESULTS The new buffer design was implemented on 100A/1200V IGBT devices with an active area of 1cm2. This device also incorporates additional enhancement of the planar cell design for further loss reduction schematically shown in Fig.3 [5].
Eoff (mJ) (600V, 100A, 125C)

18 16 14 12 10 8 6 4 2 0

A B

Optimized EP SPT-IGBT C

EP SPT-IGBT

Optimized EP CPT IGBT

1.5

1.6

1.7 1.8 1.9 2.0 Vce (V) (100A, 125C)

2.1

2.2

Fig. 5 Technology Performance Chart for 100A/1200V IGBTs.

300 250
Fig. 3 The concept of Enhanced Planar (EP) IGBT.

Optimized EP CPT B 25C Optimized EP CPT B 125C Optimized EP SPT 25C Optimized EP SPT 125C

200

Ic (A)

The positive effect of the second buffer peak N2 on the reduction of leakage current simulated in Fig.2b) is experimentally acknowledged in Fig.4 for devices thinned to ~100um. The smaller rise of leakage with increasing voltage and reduced spread in the leakage current values between individual samples with the double buffer is obvious.
0.40

150 100 50 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Vce (V)
Fig. 6 Output characteristics for the 100A/1200V SPT-IGBT (dashed) and new CPT-IGBT (solid) measured at 25 and 125oC.

Leakage Current at 125C (mA)

0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 200 300 400 500 600 700 800 900

Single Buffer

This reduction of VCEsa at a rated current of 100 A between the Optimized EP and Optimized CPT technologies is evident from Fig.6 including the ON-state thermal coefficients of VCEsat. The turn-off waveforms of the different design versions are also shown in Fig.7. A higher anode strength is clearly needed to enhance softness of the thinner CPT design as indicated by the turn-off charts.
Turn-off waveforms (600V, 100A, 125C) 160 140 120 Ic (A) 100 80 60 40 20 0 Ic 800 700 600 500 400 300 200 100 0 Vce (V)

Double Buffer

Blocking Voltage (V)

Fig. 4 Leakage current for 100A/1200V IGBTs with Single N1 and Double Buffer peaks N1 and N2.

Fig.5 shows the technology points (VCE vs. Eoff) of the standard Enhanced Planar (EP) 1200V SPT-IGBT, and the Optimized EP 1200V SPT-IGBT. Fig.5 also includes the latest cathode technology implemented on the CPT-IGBT having a 25% thinner silicon substrate (thickness ~ 100um) with different anode strengths (A, B & C). During this work, the doping concentration of the silicon base regions was unaltered to evaluate the effect of the thickness alone on device softness. The total VCEsat reduction for the same Eoff was around 100mV for the Optimized EP technology with a further reduction of 300mV for the CPT-IGBT.

Vce

Optimized EP CPT IGBT: A B C Optimized EP SPT IGBT

Time (100nsec/div)

Fig. 7: Turn-off softness waveforms under nominal conditions.

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The SOA waveforms at 1000V and 3x nominal current for the CPT-IGBT design B are shown in Fig.8 under dynamic avalanche and Switching-Self-Clamping-Mode SSCM [6]. The maximal voltage during clamping gives evidence of good avalanche capability of so aggressively thinned device.
Turn off RBSOA waveforms (1000V, 300A, 125C) 350 300 250 Ic (A) 200 150 100 50 0 Time (100nsec/div)
Fig. 8: Turn-off waveforms under SOA and switching self-clamp conditions for the CPT-IGBT.

Ic Vce Optimized EP CPT-IGBT Split B

1400 1200 1000 Vce (V) 800 600 400 200 0

We have observed that the state-of-the-art SPT-IGBT inherits a clear trade-off between the short circuit, SSCM and the leakage current. Hence, the optimisation of the CPT-IGBT internal PNP bipolar transistor gain plays the key role in the design process. Investigations show that high PNP gain designs will always improve the short circuit and SSCM capability while having the drawback of increased leakage currents especially at high temperatures, which is very critical for the device blocking stability. The CPT-IGBT buffer concept provided a better degree of freedom for optimising the device performance specifically with regard to the short circuit ruggedness vs. leakage current trade-off. IV. CONCLUSIONS A new IGBT design concept referred to as the ControlledPunch-Through (CPT) IGBT has been introduced in order to maximize the effect of using thin wafer technology for the reduction of the device overall losses. The device comprises a very shallow N-buffer with an optimized doping distribution to maintain good blocking, soft turn-off, wide safe operation area, and very good short circuit capability. With an estimated 400mV potential reduction in VCEsat, the new CPT-IGBT offers a very significant advantage over state-of-the-art devices targeting power electronics applications striving on minimising losses while maintaining good overall behaviour. Although presented only for 1200 V IGBT, the concept of the CPT buffer can be employed for any voltage platform with an increased degree of freedom in the optimization of device parameters closely related to anode and buffer design properties. V. ACKNOWLEDGMENT The initial phase of development was carried out in cooperation with the Research Centre LC06041 at the Czech Technical University in Prague supported by the Ministry of Education, Youth and Sports of the Czech Republic. Wolfgang Janisch and Frank Ritchie are acknowledged for advanced processing of thin wafers. REFERENCES

Finally, Fig.9 presents the nominal turn-on waveforms and Fig.10 short circuit performance at 900V for the same CPTIGBT split B. The devices show a reasonable controlled behaviour despite of the thinner silicon design. However, further optimisation will be required in this area.
Turn on waveforms (600V, 100A, 125C)
700 600 500 Vce (V) 400 300 200 100 0 Time (100nsec/div) 350 300

Vce Optimized EP CPT-IGBT Split B

250 200 Ic (A)

Ic

150 100 50 0

Fig. 9: Turn-on waveforms for the CPT-IGBT.

Short Circuit waveforms (900V, 125C) 1200 1000 800 Vce (V) 600 400 200 0 Time (2usec/div)
Fig. 10: Short Circuit waveforms for the CPT-IGBT.

1200 Vce Optimized EP CPT-IGBT Split B 1000 800 Ic (A) 600 400 200 0

Ic

[1] T. Laska et al Short circuit properties of Trench/Field Stop IGBTs design aspects for a superior robustness, Proc. ISPSD2003, p. 152. [2] M. Rahimo et al Extending the boundary limits of high voltage IGBTs and diodes to above 8kV, Proc. ISPSD'2002, p. 41. [3] H K. Nakamura et al Advanced wide cell pitch IGBT having Light Punch Through (LPT) structures, Proc. ISPSD2002, p. 277. [4] A. Nakagawa et al MOSFET-mode Ultra Thin Wafer PTIGBTs for Soft Switching Application Theory and Experiments, Proc. ISPSD2004, p. 103. [5] M. Rahimo et al "Novel EnhancedPlanar IGBT Technology Rated up to 6.5kV for lower Losses and Higher SOA Capability", Proc. ISPSD2006, p. 33. [6] M. Rahimo et al " Switching-Self-Clamping-Mode SSCM, a breakthrough in SOA performance for high voltage IGBTs and Diodes ", Proc. ISPSD2004, p. 437.

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