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Digital Design Chapter 1 Introduction and Methodology

17 February 2010

VHDL

Digital Design
Digital Design: An Embedded Systems Approach Using VHDL
Chapter 1 Introduction and Methodology

Digital: circuits that use two voltage levels to represent information

Logic: use truth values and logic to analyze circuits

requirements while satisfying constraints

Design: meeting functional

Constraints: performance, size, power, cost, etc.


Digital Design Chapter 1 Introduction and Methodology 2

Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.

VHDL

VHDL

Design using Abstraction

Circuits contain millions of transistors

Billions

How can we manage this complexity? Focus on aspects relevant aspects, ignoring other aspects Dont break assumptions that allow aspect to be ignored! Transistors are on or off Voltages are low or high
Digital Design Chapter 1 Introduction and Methodology 3 Digital Design Chapter 1 Introduction and Methodology 4

Abstraction

Examples:

VHDL

VHDL

More Trends..

Xilinx XC6VSX475T 2,016 DSP48E1 Slices 25 18 bit Multipliers 48 bit Accumulators (600 MHz) Digital Design Chapter 1 Introduction and Methodology 5 Digital Design Chapter 1 Introduction and Methodology 6

Digital Design Chapter 1 Introduction and Methodology

17 February 2010

VHDL

VHDL

Digital Systems

Electronic circuits that use discrete representations of information

FPGAs now give the best GFLOPs/Watt performance. In a National Science Foundation benchmark, a Stratix IV FPGA delivered 171 GFLOPs and was the clear overall leader in highest GFLOPs/Watt [1].
[1] Alteras floating-point solutions for military applications. April 2009, SS-01058-1.1 http://www.altera.co.uk/literature/po/ss-military-floating-point.pdf

Discrete in space and time

Digital Design Chapter 1 Introduction and Methodology

Digital Design Chapter 1 Introduction and Methodology

VHDL

VHDL

Embedded Systems

Binary Representation

Most real-world digital systems include embedded computers

Basic representation for simplest form of information, with only two states

Processor cores, memory, I/O

Different functional requirements can q be implemented


by the embedded software by special-purpose attached circuits

a switch: open or closed a light: on or off a microphone: active or muted a logical proposition: false or true a binary (base 2) digit, or bit: 0 or 1

Trade-off among cost, performance, power, etc.


Digital Design Chapter 1 Introduction and Methodology 9 Digital Design Chapter 1 Introduction and Methodology 10

VHDL

VHDL

Binary Representation: Example


+V

Binary Representation: Example


+V

switch_pressed

lamp_enabled

lamp_lit

sensor

dark

Signal represents the state of the switch

high-voltage => pressed, low-voltage => not pressed lamp_lit = switch_pressed


Digital Design Chapter 1 Introduction and Methodology 11

Equally, it represents state of the lamp

dark: its night time lamp_enabled: turn on lamp at night lamp_lit: lamp_enabled AND dark Logically: day time => NOT lamp_lit
Digital Design Chapter 1 Introduction and Methodology 12

Digital Design Chapter 1 Introduction and Methodology

17 February 2010

VHDL

VHDL

Basic Gate Components

Combinational Circuits

Primitive components for logic design

Circuit whose output values depend purely on current input values


>30C

vat 0

>25C

AND gate

OR gate
low level

0 1
>30C

0 1

buzzer

+V

inverter

multiplexer

vat 1

>25C

select vat 1 select vat 0

low level

Digital Design Chapter 1 Introduction and Methodology

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Digital Design Chapter 1 Introduction and Methodology

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VHDL

VHDL

Sequential Circuits

Flipflops and Clocks

Circuit whose output values depend on current and previous input values

Edge-triggered D-flipflop

stores one bit of information at a time


rising edge falling edge

Include some form of storage of values


clk

Nearly systems are sequential y all digital g y q


Mixture of gates and storage components Combinational parts transform inputs and stored values

D clk

Q
D Q

1 0 1 0 1 0

Timing diagram

Graph of signal values versus time


Digital Design Chapter 1 Introduction and Methodology 16

Digital Design Chapter 1 Introduction and Methodology

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VHDL

VHDL

Real-World Circuits

Integrated Circuits (ICs)

Assumptions behind digital abstraction

Circuits formed on surface of silicon wafer

ideal circuits, only two voltages, instantaneous transitions, no delay

Greatly simplify functional design Constraints arise from real components and real-world physics Meeting constraints ensures circuits are ideal enough to support abstractions
Digital Design Chapter 1 Introduction and Methodology 17

Minimum feature size reduced in each technology generation Currently 90nm, 65nm 45 nm, 32 nm (Intel Westmere) Moores Law: increasing transistor count CMOS: complementary MOSFET circuits
+V

input

output

Digital Design Chapter 1 Introduction and Methodology

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Digital Design Chapter 1 Introduction and Methodology

17 February 2010

VHDL

VHDL

Logic Levels

Actual voltages for low and high

Example: 1.4V threshold for inputs


receiver threshold nominal 1.4V threshold

1.5V 1 0V 1.0V 0.5V

2.5V 2.0V 1.5V 1.0V 0.5V

signal with added noise logic high threshold driven signal logic low threshold

Digital Design Chapter 1 Introduction and Methodology

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Digital Design Chapter 1 Introduction and Methodology

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VHDL

VHDL

Logic Levels

Static Load and Fanout

TTL logic levels with noise margins


signal with added noise
2.5V 2.0V 1.5V 1.0V 0.5V VOH VIH

Current flowing into or out of an output

+V

High: SW1 closed, SW0 open

noise margin

R1 SW1

Voltage drop across R1 Too much current: VO < VOH Voltage drop across R0 Too much current: VO > VOL

driven signal
VIL VOL

Low: SW0 closed, SW1 open


output

noise margin

SW0 R0

VOL: output low voltage VOH: output high voltage

VIL: input low voltage VIH: input high voltage


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Fanout: number of inputs connected to an output

determines static load


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Digital Design Chapter 1 Introduction and Methodology

Digital Design Chapter 1 Introduction and Methodology

VHDL

VHDL

Capacitive Load and Prop Delay

Other Constraints

Inputs and wires act as capacitors


output

+V

3.0V
R1 S 1 SW1 SW0 R0 input

tr

tf VOH VOL

Wire delay: delay for transition to traverse interconnecting wire Flipflop timing

2.0V 1 0V 1.0V

delay y from clk edge g to Q output p D stable before and after clk edge current through resistance => heat must be dissipated, or circuit cooks!
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Cin

tr: rise time tf: fall time tpd: propagation delay

Power

delay from input transition to output transition


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Digital Design Chapter 1 Introduction and Methodology

Digital Design Chapter 1 Introduction and Methodology

17 February 2010

VHDL

VHDL

Area and Packaging

Models

Circuits implemented on silicon chips

Larger circuit area => greater cost More wires => g greater cost Package dissipates heat

Abstract representations of aspects of a system being designed

Chips in packages with connecting wires


Allow us to analyze the system before building it V=IR Represents electrical aspects of a resistor Expressed as a mathematical equation Ignores thermal, mechanical, materials aspects
Digital Design Chapter 1 Introduction and Methodology 26

Example: Ohms Ohm s Law


Packages interconnected on a printed circuit board (PCB)

Size, shape, cooling, etc, constrained by final product


Digital Design Chapter 1 Introduction and Methodology 25

VHDL

VHDL

VHDL

VHSIC = very-high speed integrated circuits The defense department launched the VHSIC program in the 1980s, which created VHDL.

Entity Declarations

VHSIC Hardware Description Language


A computer language for modeling behavior and structure of digital systems

Describes input and outputs of a circuit


above_30_0 temp_bad_0 inv_0 or_0a or_0b wake_up_0 select_mux
0

>30C

Electronic Design Automation (EDA) using VHDL


>25C

above_25_0

low level

b l below_25_0 25 0 low_level_0

Design entry: alternative to schematics Verification: simulation, proof of properties Synthesis: automatic generation of circuits

buzzer

>30C

above_30_1

buzzer

temp_bad_1 inv_1 or_1a or_1b wake_up_1 select_vat_1 +V

>25C

above_25_1

below_25_1

low level

low_level_1

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Digital Design Chapter 1 Introduction and Methodology

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VHDL

VHDL

Entity Declarations
library ieee; use ieee.std_logic_1164.all; entity vat_buzzer is port ( above_25_0, above_30_0, _ _ : in std_logic; _ g ; low_level_0 above_25_1, above_30_1, low_level_1 : in std_logic; select_vat_1 : in std_logic; buzzer : out std_logic ); end entity vat_buzzer;

Structural Architectures
library dld; use dld.gates.all; architecture struct of vat_buzzer is signal below_25_0, temp_bad_0, wake_up_0 : std_logic; signal below_25_1, temp_bad_1, wake_up_1 : std_logic; begin -- components for vat 0 inv_0 : inv (above_25_0, below_25_0); or_0a : or2 (above_30_0, below_25_0, temp_bad_0); or_0b : or2 (temp_bad_0, low_level_0, wake_up_0); -- components for vat 1 inv_1 : inv (above_25_1, below_25_1); or_1a : or2 (above_30_1, below_25_1, temp_bad_1); or_1b : or2 (temp_bad_1, low_level_1, wake_up_1); select_mux : mux2 (wake_up_0, wake_up_1, select_vat_1, buzzer); end architecture struct;

Digital Design Chapter 1 Introduction and Methodology

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Digital Design Chapter 1 Introduction and Methodology

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Digital Design Chapter 1 Introduction and Methodology

17 February 2010

VHDL

VHDL

Behavioral Architectures
architecture behavior of vat_buzzer is begin buzzer <= low_level_1 or (above 30 1 or not above_25_1) (above_30_1 above 25 1) when select_vat_1 = '1' else low_level_0 or (above_30_0 or not above_25_0); end architecture behavior;

Design Methodology

Simple systems can be design by one person using ad hoc methods Real-world systems are design by teams

Require a systematic design methodology Tasks to be undertaken Information needed and produced Relationships between tasks

S ifi Specifies

dependencies, sequences

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EDA tools used


Digital Design Chapter 1 Introduction and Methodology 32

VHDL

VHDL

A Simple Design Methodology


Requirements and Constraints (VHDL) Design Converts VHDL to the physical implementation of the circuit Synthesize For FPGAs there is a place and route step, i.e. which physical circuits to use.
Physical Implementation

Hierarchical Design

Manufacture

Circuits are too complex for us to design all the detail at once Design subsystems for simple functions Compose subsystems to form the t system

Functional Verification OK? N Y

Post-synthesis Verification OK? N Y

Physical Verification OK? N Y

Test

Treating subcircuits as black box components Verify independently, then verify the composition

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Top-down/bottom-up design
Digital Design Chapter 1 Introduction and Methodology 34

Digital Design Chapter 1 Introduction and Methodology

VHDL

VHDL

Hierarchical Design
Architecture Design Unit Design Unit Verification N OK? Y Integration Verification N OK? Y
Digital Design Chapter 1 Introduction and Methodology 35

Synthesis

We usually design using register-transferlevel (RTL) VHDL

Design

Higher level of abstraction than gates

Functional Verification OK? N Y

Synthesis tool translates to a circuit of gates that performs the same function Specify to the tool

the target implementation fabric constraints on timing, area, etc. synthesized circuit meets constraints
Digital Design Chapter 1 Introduction and Methodology 36

Post-synthesis verification

Digital Design Chapter 1 Introduction and Methodology

17 February 2010

VHDL

VHDL

Physical Implementation

Codesign Methodology
Requirements and Constraints

Implementation fabrics

Application-specific ICs (ASICs) Field-programmable gate arrays (FPGAs)


Hardware Requirements and Constraints

Partitioning Software Requirements and Constraints

Floor-planning: arranging the subsystems Pl t arranging i th t within ithi Placement: the gates subsystems Routing: joining the gates with wires Physical verification

Hardware Design and Verification N OK? Manufacture and Test 37

Software Design and Verification OK? N

physical circuit still meets constraints use better estimates of delays


Digital Design Chapter 1 Introduction and Methodology

Digital Design Chapter 1 Introduction and Methodology

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VHDL

Summary

Digital systems use discrete (binary) representations of information Basic components: gates and flipflops Combinational and sequential circuits Real-world constraints

logic levels, loads, timing, area, etc

VHDL models: structural, behavioral Design methodology


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