Beruflich Dokumente
Kultur Dokumente
MC68HC908JK8
MC68HC908KL8
MC68HC08JL8
MC68HC08JK8
Data Sheet
M68HC08
Microcontrollers
MC68HC908JL8
Rev. 3.1
3/2005
freescale.com
MC68HC908JL8
MC68HC908JK8
MC68HC908KL8
MC68HC08JL8
MC68HC08JK8
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Semiconductor 3
Revision History
Revision Page
Date Description
Level Number(s)
Added IRQ timing to Table 17-5 . Control Timing (5V) and Table 17-8 .
Mar 2005 3.1 188, 190
Control Timing (3V)
4 Freescale Semiconductor
List of Chapters
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Freescale Semiconductor 5
List of Chapters
6 Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 2
Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.8 FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.9 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.10 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.11 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.12 FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 3
Configuration and Mask Option Registers (CONFIG & MOR)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4 Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.5 Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 4
Central Processor Unit (CPU)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Freescale Semiconductor 7
Table of Contents
Chapter 5
System Integration Module (SIM)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.7.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.7.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.7.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8 Freescale Semiconductor
Chapter 6
Oscillator (OSC)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.1 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.2 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.4 XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.6 Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.4.7 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.4.8 Internal Oscillator Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.6 Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 7
Monitor ROM (MON)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.3.1 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.3.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.3.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.3.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.3.5 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.3.6 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.5 ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.5.1 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.5.2 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.5.3 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.5.4 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.5.5 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.5.6 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.5.7 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.5.8 EE_READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Freescale Semiconductor 9
Table of Contents
Chapter 8
Timer Interface Module (TIM)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
8.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.8.1 TIM Clock Pin (ADC12/T2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.8.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1) . . . . . 113
8.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Chapter 9
Serial Communications Interface (SCI)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10 Freescale Semiconductor
9.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.7.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
9.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9.8.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.8.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.8.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 10
Analog-to-Digital Converter (ADC)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.3.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.6.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.7.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10.7.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Freescale Semiconductor 11
Table of Contents
Chapter 11
Input/Output (I/O) Ports
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.2.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
11.2.3 Port A Input Pull-Up Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.3.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.4.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.4.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.4.3 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.5 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.5.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.5.2 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Chapter 12
External Interrupt (IRQ)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.3.1 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.4 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.5 IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Chapter 13
Keyboard Interrupt Module (KBI)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.3 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.5 Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.5.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.5.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
13.7 Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Chapter 14
Computer Operating Properly (COP)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
14.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12 Freescale Semiconductor
14.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.3.1 ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.3.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.3.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.3.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.3.5 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
14.3.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
14.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Chapter 15
Low Voltage Inhibit (LVI)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
15.4 LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Chapter 16
Break Module (BREAK)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
16.3.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16.3.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16.3.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16.3.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
16.4 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.4.1 Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.4.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
16.4.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
16.4.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Freescale Semiconductor 13
Table of Contents
Chapter 17
Electrical Specifications
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
17.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
17.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
17.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
17.5 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
17.6 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
17.7 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
17.8 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
17.9 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
17.10 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
17.11 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
17.12 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
17.13 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
17.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Chapter 18
Mechanical Specifications
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
18.2 20-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
18.3 20-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
18.4 28-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
18.5 28-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
18.6 32-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
18.7 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Chapter 19
Ordering Information
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
19.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Appendix A
MC68HC08JL8
A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
A.4 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
A.5 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
A.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
A.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
A.7.1 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
A.8 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
A.9 MC68HC08JL8 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
14 Freescale Semiconductor
Appendix B
MC68HC908KL8
B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
B.2 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
B.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
B.4 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
B.5 Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
B.6 MC68HC908KL8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Freescale Semiconductor 15
Table of Contents
16 Freescale Semiconductor
Chapter 1
General Description
1.1 Introduction
The MC68HC908JL8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
Table 1-1. Summary of Devices
Generic Part Description Pin Count
1.2 Features
Features of the MC68HC908JL8 include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• Low-power design; fully static with stop and wait modes
• Maximum internal bus frequency:
– 8-MHz at 5V operating voltage
– 4-MHz at 3V operating voltage
• Oscillator options:
– Crystal or resonator
– RC oscillator
• 8,192 bytes user program FLASH memory with security(1) feature
• 256 bytes of on-chip RAM
• Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture,
output compare, and PWM capability on each channel; external clock input option on TIM2
• 13-channel, 8-bit analog-to-digital converter (ADC)
• Serial communications interface module (SCI)
• 26 general-purpose input/output (I/O) ports:
– 8 keyboard interrupt with internal pull-up
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
Freescale Semiconductor 17
General Description
18 Freescale Semiconductor
MCU Block Diagram
INTERNAL BUS
M68HC08 CPU
KEYBOARD INTERRUPT PTA7/KBI7**‡ #
CPU ARITHMETIC/LOGIC PTA6/KBI6**¥
REGISTERS UNIT (ALU) MODULE
PTA5/KBI5**‡
PORTA
PTA4/KBI4**‡
DDRA
8-BIT ANALOG-TO-DIGITAL PTA3/KBI3**‡
CONTROL AND STATUS REGISTERS — 64 BYTES CONVERTER MODULE ##
PTA2/KBI2**‡
PTA1/KBI1**‡
USER FLASH — 8,192 BYTES PTA0/KBI0**‡
2-CHANNEL TIMER INTERFACE
MODULE 1
PTB7/ADC7
USER RAM — 256 BYTES
PTB6/ADC6
2-CHANNEL TIMER INTERFACE PTB5/ADC5
PORTB
MODULE 2
DDRB
MONITOR ROM — 959 BYTES PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
USER FLASH VECTORS — 36 BYTES BREAK
PTB1/ADC1
MODULE
PTB0/ADC0
ADC12/T2CLK #
CRYSTAL OSCILLATOR
OSC1 SERIAL COMMUNICATIONS
PTD7/RxD**†‡
INTERFACE MODULE
¥
OSC2/RCCLK RC OSCILLATOR PTD6/TxD**†‡
PTD5/T1CH1
PORTD
DDRD
POWER-ON RESET PTD4/T1CH0
INTERNAL OSCILLATOR
MODULE PTD3/ADC8‡
PTD2/ADC9‡
PTD1/ADC10
##
SYSTEM INTEGRATION LOW-VOLTAGE INHIBIT PTD0/ADC11
* RST MODULE MODULE
PTE1/T2CH1
DDRE
PTE
EXTERNAL INTERRUPT #
* IRQ MODULE COMPUTER OPERATING
PROPERLY MODULE PTE0/T2CH0
Freescale Semiconductor 19
General Description
ADC12/T2CLK
25 PTD4/T1CH0
PTA0/KBI0
PTA7/KBI7
PTA5/KBI5
32 VSS
RST
IRQ
27
26
31
30
29
28
OSC1 1 24 PTD5/T1CH1
OSC2/RCCLK/PTA6/KBI6 2 23 PTD2/ADC9
PTA1/KBI1 3 22 PTA4/KBI4
VDD 4 21 PTD3/ADC8
PTA2/KBI2 5 20 PTB0/ADC0
PTA3/KBI3 6 19 PTB1/ADC1
PTB7/ADC7 7 18 PTD1/ADC10
PTB6/ADC6 8 17 PTB2/ADC2
10
11
12
13
14
15
PTB3/ADC3 16
PTB5/ADC5 9
PTD7/RxD
PTD6/TxD
PTE0/T2CH0
PTE1/T2CH1
PTB4/ADC4
IRQ 1 32 ADC12/T2CLK
PTA0/KBI0 2 31 PTA7/KBI7
VSS 3 30 RST
OSC1 4 29 PTA5/KBI5
OSC2/RCCLK/PTA6/KBI6 5 28 PTD4/T1CH0
PTA1/KBI1 6 27 PTD5/T1CH1
VDD 7 26 PTD2/ADC9
PTA2/KBI2 8 25 PTA4/KBI4
PTA3/KBI3 9 24 PTD3/ADC8
PTB7/ADC7 10 23 PTB0/ADC0
PTB6/ADC6 11 22 PTB1/ADC1
PTB5/ADC5 12 21 PTD1/ADC10
PTD7/RxD 13 20 PTB2/ADC2
PTD6/TxD 14 19 PTB3/ADC3
PTE0/T2CH0 15 18 PTD0/ADC11
PTE1/T2CH1 16 17 PTB4/ADC4
20 Freescale Semiconductor
Pin Functions
IRQ 1 28 RST
PTA0/KBI0 2 27 PTA5/KBI5
VSS 3 26 PTD4/T1CH0
OSC1 4 25 PTD5/T1CH1
OSC2/RCCLK/PTA6/KBI6 5 24 PTD2/ADC9
PTA1/KBI1 6 23 PTA4/KBI4
VDD 7 22 PTD3/ADC8
PTA2/KBI2 8 21 PTB0/ADC0
PTA3/KBI3 9 20 PTB1/ADC1
Pins not available on 28-pin packages
PTB7/ADC7 10 19 PTD1/ADC10
PTE0/T2CH0
PTB6/ADC6 11 18 PTB2/ADC2
PTE1/T2CH1
PTB5/ADC5 12 17 PTB3/ADC3
PTD7/RxD 13 16 PTD0/ADC11 ADC12/T2CLK
PTD6/TxD 14 15 PTB4/ADC4 PTA7/KBI7
Internal pads are unconnected.
Set these unused port I/Os to output low.
IRQ 1 20 RST
VSS 2 19 PTD4/T1CH0
Pins not available on 20-pin packages
OSC1 3 18 PTD5/T1CH1
PTA0/KBI0 PTD0/ADC11
OSC2/RCCLK/PTA6/KBI6 4 17 PTD2/ADC9
PTA1/KBI1 PTD1/ADC10
VDD 5 16 PTD3/ADC8
PTA2/KBI2
PTB7/ADC7 6 15 PTB0/ADC0
PTA3/KBI3 PTE0/T2CH0
PTB6/ADC6 7 14 PTB1/ADC1 PTA4/KBI4 PTE1/T2CH1
PTB5/ADC5 8 13 PTB2/ADC2 PTA5/KBI5
PTD7/RxD 9 12 PTB3/ADC3 ADC12/T2CLK
PTD6/TxD 10 11 PTB4/ADC4 PTA7/KBI7
Internal pads are unconnected.
Set these unused port I/Os to output low.
The 20-pin MC68HC908JL8 is designated MC68HC908JK8.
Freescale Semiconductor 21
General Description
PTA0–PTA5 and PTA7 have LED direct sink capability. Out VSS
PTD2–PTD3 and PTD6–PTD7 have LED direct sink capability Out VSS
22 Freescale Semiconductor
Pin Functions
NOTE
Devices in 28-pin packages, the following pins are not available:
PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.
Devices in 20-pin packages, the following pins are not available:
PTA0/KBI0–PTA5/KBI5, PTD0/ADC11, PTD1/ADC10,
PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.
Freescale Semiconductor 23
General Description
24 Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
The CPU08 can address 64-kbytes of memory space. The memory map, shown in Figure 2-1, includes:
• 8,192 bytes of user FLASH memory
• 36 bytes of user-defined vectors
• 959 bytes of monitor ROM
Freescale Semiconductor 25
Memory
$0000
I/O REGISTERS
↓
64 BYTES
$003F
$0040
RESERVED
↓
32 BYTES
$005F
$0060
RAM
↓
256 BYTES
$015F
$0160
UNIMPLEMENTED
↓
55,968 BYTES
$DBFF
$DC00
FLASH MEMORY
↓
8,192 BYTES
$FBFF
$FC00
MONITOR ROM
↓
512 BYTES
$FDFF
$FE00 BREAK STATUS REGISTER (BSR)
$FE01 RESET STATUS REGISTER (RSR)
$FE02 RESERVED
$FE03 BREAK FLAG CONTROL REGISTER (BFCR)
$FE04 INTERRUPT STATUS REGISTER 1 (INT1)
$FE05 INTERRUPT STATUS REGISTER 2 (INT2)
$FE06 INTERRUPT STATUS REGISTER 3 (INT3)
$FE07 RESERVED
$FE08 FLASH CONTROL REGISTER (FLCR)
$FE09
↓ RESERVED
$FF0B
$FE0C BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0D BREAK ADDRESS LOW REGISTER (BRKL)
$FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0F RESERVED
$FE10
MONITOR ROM
↓
447 BYTES
$FFCE
$FFCF FLASH BLOCK PROTECT REGISTER (FLBPR)
$FFD0 MASK OPTION REGISTER (MOR)
$FFD1
RESERVED
↓
11 BYTES
$FFDB
$FFDC
USER FLASH VECTORS
↓
36 BYTES
$FFFF
26 Freescale Semiconductor
Monitor ROM
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003 Port D Data Register (PTD) Write:
Reset: Unaffected by reset
Read:
Data Direction Register A DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
$0004 Write:
(DDRA)
Reset: 0 0 0 0 0 0 0 0
Read:
Data Direction Register B DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
$0005 Write:
(DDRB)
Reset: 0 0 0 0 0 0 0 0
Read:
$0006 Unimplemented Write:
Read:
Data Direction Register D DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
$0007 Write:
(DDRD)
Reset: 0 0 0 0 0 0 0 0
Read:
Port E Data Register PTE1 PTE0
$0008 Write:
(PTE)
Reset: Unaffected by reset
Read:
$0009 Unimplemented Write:
Read: 0 0 0 0
Port D Control Register SLOWD7 SLOWD6 PTDPU7 PTDPU6
$000A Write:
(PDCR)
Reset: 0 0 0 0 0 0 0 0
Read:
$000B Unimplemented Write:
Read:
Data Direction Register E DDRE1 DDRE0
$000C Write:
(DDRE)
Reset: 0 0 0 0 0 0 0 0
Port A Input Pull-up Read:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000D Enable Register Write:
(PTAPUE) Reset: 0 0 0 0 0 0 0 0
PTA7 Input Pull-up Read:
PTAPUE7
$000E Enable Register Write:
(PTA7PUE) Reset: 0 0 0 0 0 0 0 0
$000F Read:
↓ Unimplemented Write:
$0012
U = Unaffected X = Indeterminate = Unimplemented R = Reserved
Freescale Semiconductor 27
Memory
28 Freescale Semiconductor
Monitor ROM
Freescale Semiconductor 29
Memory
Read: SBSW
R R R R R R R
$FE00 Break Status Register (BSR) Write: See note
Reset: 0
Note: Writing a logic 0 clears SBSW.
Read: POR PIN COP ILOP ILAD MODRST LVI 0
$FE01 Reset Status Register (RSR) Write:
POR: 1 0 0 0 0 0 0 0
Read:
R R R R R R R R
$FE02 Reserved Write:
30 Freescale Semiconductor
Monitor ROM
Read: 0 0 0 0
FLASH Control Register HVEN MASS ERASE PGM
$FE08 Write:
(FLCR)
Reset: 0 0 0 0 0 0 0 0
$FE09 Read:
R R R R R R R R
↓ Reserved Write:
$FE0B
Break Address High Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
$FE0C Register Write:
(BRKH) Reset: 0 0 0 0 0 0 0 0
Break Address low Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$FE0D Register Write:
(BRKL) Reset: 0 0 0 0 0 0 0 0
Break Status and Control Read: 0 0 0 0 0 0
BRKE BRKA
$FE0E Register Write:
(BRKSCR) Reset: 0 0 0 0 0 0 0 0
Freescale Semiconductor 31
Memory
—
$FFFF Reset Vector (Low)
Highest
32 Freescale Semiconductor
Random-Access Memory (RAM)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
Freescale Semiconductor 33
Memory
34 Freescale Semiconductor
FLASH Mass Erase Operation
Freescale Semiconductor 35
Memory
36 Freescale Semiconductor
FLASH Program Operation
1
Set PGM bit
Algorithm for programming
a row (32 bytes) of FLASH memory
2
Read the FLASH block protect register
4
Wait for a time, tnvs
5
Set HVEN bit
6
Wait for a time, tpgs
7
Write data to the FLASH address
to be programmed
8
Wait for a time, tprog
Completed Y
programming
this row?
10
NOTE: Clear PGM bit
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed 11
to clearing PGM bit (step 7 to step 10) Wait for a time, tnvh
must not exceed the maximum programming
time, tprog max.
12
Clear HVEN bit
This row program algorithm assumes the row/s
to be programmed are initially erased.
13
Wait for a time, trcv
End of programming
Freescale Semiconductor 37
Memory
Address: $FFCF
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset: Unaffected by reset; $FF when blank
Non-volatile FLASH register; write by programming.
BPR[7:0]
38 Freescale Semiconductor
FLASH Block Protect Register
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page
boundaries — 64 bytes) within the FLASH memory.
Examples of protect start address:
$71
$DC40 (1101 1100 0100 0000)
(0111 0001)
$72
$DC80 (1101 1100 1000 0000)
(0111 0010)
$73
$DCC0 (1101 1100 1100 0000)
(0111 0011)
and so on...
$FD
$FF40 (1111 1111 0100 0000)
(1111 1101)
$FE
$FF80 (1111 1111 1000 0000)
(1111 1110)
Freescale Semiconductor 39
Memory
40 Freescale Semiconductor
Chapter 3
Configuration and Mask Option Registers (CONFIG & MOR)
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register
(MOR).
The configuration registers enable or disable these options:
• Computer operating properly module (COP)
• COP timeout period (213 –24 or 218 –24 ICLK cycles)
• Internal oscillator during stop mode
• Low voltage inhibit (LVI) module
• LVI module voltage trip point selection
• STOP instruction
• Stop mode recovery time (32 or 4096 ICLK cycles)
• Pull-up on IRQ pin
The mask option register selects the oscillator option:
• Crystal or RC
Freescale Semiconductor 41
Configuration and Mask Option Registers (CONFIG & MOR)
42 Freescale Semiconductor
Configuration Register 2 (CONFIG2)
Address: $FFD0
Bit 7 6 5 4 3 2 1 Bit 0
Read:
OSCSEL R R R R R R R
Write:
Erased: 1 1 1 1 1 1 1 1
Reset: Unaffected by reset
Non-volatile FLASH register; write by programming.
R = Reserved
Freescale Semiconductor 43
Configuration and Mask Option Registers (CONFIG & MOR)
44 Freescale Semiconductor
Chapter 4
Central Processor Unit (CPU)
4.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes, and architecture.
4.2 Features
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-Bit Index Register with X-Register Manipulation Instructions
• 8-MHz CPU Internal Bus Frequency
• 64-Kbyte Program/Data Memory Space
• 16 Addressing Modes
• Memory-to-Memory Data Moves without Using Accumulator
• Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions
• Enhanced Binary-Coded Decimal (BCD) Data Handling
• Modular Architecture with Expandable Internal Bus Definition for Extension of Addressing Range
beyond 64 Kbytes
• Low-Power Stop and Wait Modes
Freescale Semiconductor 45
Central Processor Unit (CPU)
7 0
ACCUMULATOR (A)
15 0
H X INDEX REGISTER (H:X)
15 0
STACK POINTER (SP)
15 0
PROGRAM COUNTER (PC)
7 0
V 1 1 H I N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 4-1. CPU Registers
4.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: Unaffected by reset
46 Freescale Semiconductor
CPU Registers
Bit
14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
15
Read:
Write:
Reset: 0 0 0 0 0 0 0 0 X X X X X X X X
X = Indeterminate
Bit
14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
15
Read:
Write:
Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address
(page 0) space. For correct operation, the stack pointer must point only to
RAM locations.
Freescale Semiconductor 47
Central Processor Unit (CPU)
Bit
14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
15
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Bit 7 6 5 4 3 2 1 Bit 0
Read:
V 1 1 H I N Z C
Write:
Reset: X 1 1 X 1 X X X
X = Indeterminate
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
48 Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
Freescale Semiconductor 49
Central Processor Unit (CPU)
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) – – – – – – IMM AF ii 2
50 Freescale Semiconductor
Opcode Map
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3
DIR (b0) 11 dd 4
DIR (b1) 13 dd 4
DIR (b2) 15 dd 4
DIR (b3) 17 dd 4
BCLR n, opr Clear Bit n in M Mn ← 0 – – – – – –
DIR (b4) 19 dd 4
DIR (b5) 1B dd 4
DIR (b6) 1D dd 4
DIR (b7) 1F dd 4
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 – – – – – – REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 – – – – – – REL 29 rr 3
BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 – – – – – – REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 – – – – – – REL 2E rr 3
Freescale Semiconductor 51
Central Processor Unit (CPU)
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 – – – – – – REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 1 – – – – – – REL 91 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 – – – – – – REL 2C rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 – – – – – – REL 2D rr 3
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
DIR (b3) 07 dd rr 5
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 – – – – – R
DIR (b4) 09 dd rr 5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
DIR (b3) 06 dd rr 5
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + rel ? (Mn) = 1 – – – – – R
DIR (b4) 08 dd rr 5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
DIR (b0) 10 dd 4
DIR (b1) 12 dd 4
DIR (b2) 14 dd 4
DIR (b3) 16 dd 4
BSET n,opr Set Bit n in M Mn ← 1 – – – – – –
DIR (b4) 18 dd 4
DIR (b5) 1A dd 4
DIR (b6) 1C dd 4
DIR (b7) 1E dd 4
52 Freescale Semiconductor
Opcode Map
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
Freescale Semiconductor 53
Central Processor Unit (CPU)
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
A ← (H:A)/(X)
DIV Divide – – – – R R INH 52 7
H ← Remainder
54 Freescale Semiconductor
Opcode Map
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
MOV opr,opr DD 4E dd dd 5
(M)Destination ← (M)Source
MOV opr,X+ DIX+ 5E dd 4
Move 0 – – R R –
MOV #opr,opr IMD 6E ii dd 4
H:X ← (H:X) + 1 (IX+D, DIX+)
MOV X+,opr IX+D 7E dd 4
Freescale Semiconductor 55
Central Processor Unit (CPU)
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
SP ← SP + 1; Pull (PCH)
RTS Return from Subroutine – – – – – – INH 81 4
SP ← SP + 1; Pull (PCL)
56 Freescale Semiconductor
Opcode Map
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
Freescale Semiconductor 57
Central Processor Unit (CPU)
Effect on
Operand
Address
Opcode
Cycles
Mode
Source CCR
Operation Description
Form
V H I N Z C
58 Freescale Semiconductor
Freescale Semiconductor
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2
DIR 3 EXT 3 IX2 4 SP2 2
IX1 3 SP1 1
IX
5 4 3 5 4 4 5 6 4 4 3 2 3 4 4 5 3 4 2
1 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP CMP CMP
3 DIR 2 DIR 2 REL 3 DIR 3 IMM 3 IMM 3 IX1+ 4 SP1 2 IX+ 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 5 7 3 2 3 2 3 4 4 5 3 4 2
2 BRSET1 BSET1 BHI MUL DIV NSA DAA BGT SBC SBC SBC SBC SBC SBC SBC SBC
3 DIR 2 DIR 2 REL 1 INH 1 INH 1 INH 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 9 3 2 3 4 4 5 3 4 2
3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI BLE CPX CPX CPX CPX CPX CPX CPX CPX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2
4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR LSR TAP TXS AND AND AND AND AND AND AND AND
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 3 4 3 4 1 2 2 3 4 4 5 3 4 2
5 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT BIT BIT
3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 IMM 2 DIR 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 2 3 4 4 5 3 4 2
6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA LDA LDA LDA LDA LDA LDA LDA LDA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX AIS STA STA STA STA STA STA STA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
8 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR EOR EOR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2
9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC ADC ADC
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2
A BRSET5 BSET5 BPL DEC DECA DECX DEC DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA ORA ORA
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 5 3 3 5 6 4 2 2 2 3 4 4 5 3 4 2
B BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD ADD ADD
3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 INH 3 IX1 4 SP1 2 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 4 1 1 4 5 3 1 1 2 3 4 3 2
C BRSET6 BSET6 BMC INC INCA INCX INC INC INC CLRH RSP JMP JMP JMP JMP JMP
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 4 3 3 1 1 3 4 2 1 4 4 5 6 5 4
D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST TST NOP BSR JSR JSR JSR JSR JSR
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 4 3 5 4 4 4 1 2 3 4 4 5 3 4 2
E BRSET7 BSET7 BIL MOV MOV MOV MOV STOP LDX LDX LDX LDX LDX LDX LDX LDX
3 DIR 2 DIR 2 REL 3 DD 2 DIX+ 3 IMD 2 IX+D 1 INH * 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
5 4 3 3 1 1 3 4 2 1 1 2 3 4 4 5 3 4 2
F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR CLR WAIT TXA AIX STX STX STX STX STX STX STX
3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 3 SP1 1 IX 1 INH 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 4 SP2 2 IX1 3 SP1 1 IX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset MSB
Opcode Map
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset 0 High Byte of Opcode in Hexadecimal
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with LSB
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment 5 Cycles
DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with Low Byte of Opcode in Hexadecimal 0 BRSET0 Opcode Mnemonic
IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment 3 DIR Number of Bytes / Addressing Mode
*Pre-byte for stack pointer indexed instructions
59
Central Processor Unit (CPU)
60 Freescale Semiconductor
Chapter 5
System Integration Module (SIM)
5.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM
is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state
controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 5-1 shows the internal signal names used in this section.
Table 5-1. Signal Name Conventions
Signal Name Description
ICLK Internal oscillator clock
The XTAL or RC frequency divided by two. This signal is again divided by two in the SIM
OSCOUT
to generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W Read/write signal
Freescale Semiconductor 61
System Integration Module (SIM)
MODULE STOP
MODULE WAIT
STOP/WAIT CPU STOP (FROM CPU)
CONTROL CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
÷2
VDD
CLOCK
CONTROL CLOCK GENERATORS INTERNAL CLOCKS
INTERNAL
PULL-UP
RESET
62 Freescale Semiconductor
SIM Bus Clock Control and Generation
From ICLK
OSCILLATOR SIM COUNTER
Freescale Semiconductor 63
System Integration Module (SIM)
ICLK
RST
64 Freescale Semiconductor
Reset and System Initialization
IRST
32 CYCLES 32 CYCLES
ICLK
Freescale Semiconductor 65
System Integration Module (SIM)
OSC1
PORRST
4096 32 32
CYCLES CYCLES CYCLES
ICLK
OSCOUT
RST
66 Freescale Semiconductor
SIM Counter
held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls
down the RST pin for all internal reset sources.
5.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 5-8 flow charts the handling of system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
Freescale Semiconductor 67
System Integration Module (SIM)
FROM RESET
YES
BREAK INTERRUPT?
I BIT SET?
NO
YES
I BIT SET?
NO
IRQ YES
INTERRUPT?
NO
TIMER 1 YES
INTERRUPT?
FETCH NEXT
INSTRUCTION
SWI YES
INSTRUCTION?
NO
RTI YES
INSTRUCTION? UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
68 Freescale Semiconductor
Exception Control
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 5-9 shows
interrupt entry timing.
Figure 5-10 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
R/W
MODULE
INTERRUPT
I BIT
IAB SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1
R/W
Freescale Semiconductor 69
System Integration Module (SIM)
CLI
INT1 PSHH
INT2 PSHH
70 Freescale Semiconductor
Exception Control
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
Address: $FE04
Bit 7 6 5 4 3 2 1 Bit 0
Read: IF6 IF5 IF4 IF3 0 IF1 0 0
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Freescale Semiconductor 71
System Integration Module (SIM)
Address: $FE05
Bit 7 6 5 4 3 2 1 Bit 0
Read: IF14 IF13 IF12 IF11 0 0 IF8 IF7
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Address: $FE06
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0 0 IF15
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
R = Reserved
5.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
72 Freescale Semiconductor
Low-Power Modes
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 5-15. Wait Mode Entry Timing
Figure 5-16 and Figure 5-17 show the timing for WAIT recovery.
Freescale Semiconductor 73
System Integration Module (SIM)
EXITSTOPWAIT
32 32
Cycles Cycles
RST
ICLK
74 Freescale Semiconductor
SIM Registers
CPUSTOP
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 5-18. Stop Mode Entry Timing
ICLK
INT/BREAK
Address: $FE00
Bit 7 6 5 4 3 2 1 Bit 0
Read: SBSW
R R R R R R R
Write: Note(1)
Reset: 0 0 0 0 0 0 0 0
R = Reserved 1. Writing a logic zero clears SBSW.
Freescale Semiconductor 75
System Integration Module (SIM)
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU 5
LOBYTE EQU 6
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
Address: $FE01
Bit 7 6 5 4 3 2 1 Bit 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR: 1 0 0 0 0 0 0 0
= Unimplemented
76 Freescale Semiconductor
SIM Registers
Address: $FE03
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BCFE R R R R R R R
Write:
Reset: 0
R = Reserved
Freescale Semiconductor 77
System Integration Module (SIM)
78 Freescale Semiconductor
Chapter 6
Oscillator (OSC)
6.1 Introduction
The oscillator module provides the reference clocks for the MCU system and bus. Two oscillators are
running on the device:
Address: $FFD0
Bit 7 6 5 4 3 2 1 Bit 0
Read:
OSCSEL R R R R R R R
Write:
Erased: 1 1 1 1 1 1 1 1
Reset: Unaffected by reset
Non-volatile FLASH register; write by programming.
R = Reserved
Freescale Semiconductor 79
Oscillator (OSC)
2OSCOUT OSCOUT
XTALCLK
÷2
SIMOSCEN
MCU
OSC1 OSC2
RB
RS*
X1
*RS can be zero (shorted) when used with higher-frequency crystals.
Refer to manufacturer’s data.
See Chapter 17 for component value requirements.
C1 C2
80 Freescale Semiconductor
Internal Oscillator
6.2.2 RC Oscillator
The RC oscillator circuit is designed for use with external resistor and capacitor to provide a clock source
with tolerance less than 10%.
In its typical configuration, the RC oscillator requires two external components, one R and one C.
Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10%
tolerance. The oscillator configuration uses two components:
• CEXT
• REXT
From SIM To SIM To SIM
2OSCOUT OSCOUT
PTA6
1 PTA6
I/O
MCU PTA6EN
SIMOSCEN ICLK
CONFIG2
EN
STOP_ICLKDIS INTERNAL
OSCILLATOR
Freescale Semiconductor 81
Oscillator (OSC)
NOTE
The internal oscillator is a free running oscillator and is available after each
POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS
bit in CONFIG2 (see 3.4 Configuration Register 2 (CONFIG2)).
82 Freescale Semiconductor
Low Power Modes
Freescale Semiconductor 83
Oscillator (OSC)
84 Freescale Semiconductor
Chapter 7
Monitor ROM (MON)
7.1 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM
allows complete testing of the MCU through a single-wire interface with a host computer. This mode is
also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be
achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are
blank, thus reducing the hardware requirements for in-circuit programming.
7.2 Features
Features of the monitor ROM include the following:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor ROM and host computer
• Standard mark/space non-return-to-zero (NRZ) communication with host computer
• Execution of code in RAM or FLASH
• FLASH memory security feature(1)
• FLASH memory programming interface
• 959 bytes monitor ROM code size
• Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
• Standard monitor mode entry if high voltage, VTST, is applied to IRQ
• Resident routines for FLASH programming and EEPROM emulation
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
Freescale Semiconductor 85
Monitor ROM (MON)
RST
0.1 µF
HC908JL8
VDD
VDD
EXT OSC (50% DUTY) VDD
0.1 µF
OSC1 VSS
9.8304MHz
OSC1
10M
20 pF
OSC2
20 pF
MAX232 VDD
1 16
C1+ VCC
+ + XTAL CIRCUIT
1 µF 1 µF
3 15 1 µF
C1– GND
+
4 2 VTST A SW1
C2+ V+ (SEE NOTE 1)
+ VDD 1k IRQ
1 µF 6 8.5 V
V– B VDD
5 C2–
1 µF 10 k
+ 10 k
DB9 74HC125
2 7 10 6 5
PTB0
74HC125
3 8 9 2 3 4 VDD
VDD
1
5
10 k 10 k
C SW2 PTB1
(SEE NOTE 2) PTB3
NOTES: D PTB2
1. Monitor mode entry method:
SW1: Position A — High voltage entry (VTST) 10 k 10 k
Bus clock depends on SW2.
SW1: Position B — Reset vector must be blank ($FFFE = $FFFF = $FF)
Bus clock = OSC1 ÷ 4.
2. Affects high voltage entry to monitor mode only (SW1 at position A):
SW2: Position C — Bus clock = OSC1 ÷ 4
SW2: Position D — Bus clock = OSC1 ÷ 2
5. See Table 17-4 for VTST voltage level requirements.
86 Freescale Semiconductor
Functional Description
PTB2
PTB1
PTB0
NOT
VDD X X X X X OSC1 ÷ 4 Enters User mode.
BLANK
1. RC oscillator cannot be used for monitor mode; must use either external oscillator or XTAL oscillator circuit.
2. See Table 17-4 for VTST voltage level requirements.
If VTST is applied to IRQ and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus
frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with VTST applied to IRQ upon
monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to
OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if VTST is applied to IRQ. In this event, the OSCOUT frequency is equal to the
2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
Entering monitor mode with VTST on IRQ, the COP is disabled as long as VTST is applied to either IRQ or
RST. (See Chapter 5 System Integration Module (SIM) for more information on modes of operation.)
If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF)
(Table 7-1 condition set 3, where applied voltage is VDD), then all port B pin requirements and conditions,
Freescale Semiconductor 87
Monitor ROM (MON)
including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements
when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the
state of IRQ or the RST.
Figure 7-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ
= VDD. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.
POR RESET
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
POR NO
TRIGGERED?
YES
88 Freescale Semiconductor
Functional Description
Notes:
1. If the high voltage (VTST) is removed from the IRQ pin or the RST pin, the SIM asserts
its COP enable output. The COP is a mask option enabled or disabled by the COPD bit
in the configuration register.
When the host computer has completed downloading code into the MCU RAM, the host then sends a
RUN command, which executes an RTI, which sends control to the address on the stack pointer.
NEXT
START START
BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
Figure 7-3. Monitor Data Format
NEXT
START START
$A5 BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT
BIT
START STOP
BREAK BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT NEXT
START
BIT
Figure 7-4. Sample Monitor Waveforms
Freescale Semiconductor 89
Monitor ROM (MON)
The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive
baud rates must be identical.
7.3.4 Echoing
As shown in Figure 7-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin
for error checking.
SENT TO
MONITOR
READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Figure 7-5. Read Transaction
Any result of a command appears after the echo of the last byte of the command.
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
7.3.6 Commands
The monitor ROM uses the following commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
90 Freescale Semiconductor
Functional Description
Opcode $4A
Command Sequence
SENT TO
MONITOR
READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Operand Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Opcode $49
Command Sequence
SENT TO
MONITOR
WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA
ECHO
Freescale Semiconductor 91
Monitor ROM (MON)
Opcode $1A
Command Sequence
SENT TO
MONITOR
ECHO RESULT
Opcode $19
Command Sequence
SENT TO
MONITOR
ECHO
NOTE
A sequence of IREAD or IWRITE commands can sequentially access a
block of memory over the full 64-Kbyte memory map.
92 Freescale Semiconductor
Security
Operand None
Opcode $0C
Command Sequence
SENT TO
MONITOR
ECHO RESULT
Operand None
Opcode $28
Command Sequence
SENT TO
MONITOR
RUN RUN
ECHO
7.4 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTB0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code from FLASH. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. (See Figure 7-7.)
Freescale Semiconductor 93
Monitor ROM (MON)
VDD
RST
24 BUS CYCLES
COMMAND
BYTE 1
BYTE 2
BYTE 8
FROM HOST
PTB0
1 4 1 1 2 4 1
FROM MCU
COMMAND ECHO
BYTE 1 ECHO
BYTE 8 ECHO
BYTE 2 ECHO
BREAK
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 7-7. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
94 Freescale Semiconductor
ROM-Resident Routines
1. The listed stack size excludes the 2 bytes used by the calling instruction, JSR.
The routines are designed to be called as stand-alone subroutines in the user program or monitor mode.
The parameters that are passed to a routine are in the form of a contiguous data block, stored in RAM.
The index register (H:X) is loaded with the address of the first byte of the data block (acting as a pointer),
and the subroutine is called (JSR). Using the start address as a pointer, multiple data blocks can be used,
any area of RAM be used. A data block has the control and data bytes in a defined order, as shown in
Figure 7-8.
During the software execution, it does not consume any dedicated RAM location, the run-time heap will
extend the system stack, all other RAM location will not be affected.
FILE_PTR R A M
DATA
ARRAY
DATA N
Freescale Semiconductor 95
Monitor ROM (MON)
7.5.1 PRGRNGE
PRGRNGE is used to program a range of FLASH locations with data loaded into the data array.
The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the
number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be
programmed in one routine call is 128 bytes (max. DATASIZE is 128).
ADDRH:ADDRL do not need to be at a page boundary, the routine handles any boundary misalignment
during programming. A check to see that all bytes in the specified range are erased is not performed by
this routine prior programming. Nor does this routine do a verification after programming, so there is no
return confirmation that programming was successful. User must assure that the range specified is first
erased.
The coding example below is to program 32 bytes of data starting at FLASH location $EF00, with a bus
speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address
pointer, FILE_PTR, pointing to the first byte of the data block.
96 Freescale Semiconductor
ROM-Resident Routines
ORG RAM
:
FILE_PTR:
BUS_SPD DS.B 1; Indicates 4x bus frequency
DATASIZE DS.B 1; Data size to be programmed
START_ADDR DS.W 1; FLASH start address
DATAARRAY DS.B 32; Reserved data array
ORG FLASH
INITIALISATION:
MOV #20, BUS_SPD
MOV #32, DATASIZE
LDHX #FLASH_START
STHX START_ADDR
RTS
MAIN:
BSR INITIALISATION
:
:
LDHX #FILE_PTR
JSR PRGRNGE
7.5.2 ERARNGE
ERARNGE is used to erase a range of locations in FLASH.
There are two sizes of erase ranges: a page or the entire array. The ERARNGE will erase the page (64
consecutive bytes) in FLASH specified by the address ADDRH:ADDRL. This address can be any address
within the page. Calling ERARNGE with ADDRH:ADDRL equal to $FFFF will erase the entire FLASH
array (mass erase). Therefore, care must be taken when calling this routine to prevent an accidental mass
erase. To avoid undesirable routine return addresses after a mass erase, the ERARNGE routine should
not be called from code executed from FLASH memory. Load the code into an area of RAM before calling
the ERARNGE routine.
The ERARNGE routine do not use a data array. The DATASIZE byte is a dummy byte that is also not
used.
Freescale Semiconductor 97
Monitor ROM (MON)
The coding example below is to perform a page erase, from $EF00–$EF3F. The Initialization subroutine
is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).
ERARNGE EQU $FCBE
MAIN:
BSR INITIALISATION
:
:
LDHX #FILE_PTR
JSR ERARNGE
:
7.5.3 LDRNGE
LDRNGE is used to load the data array in RAM with data from a range of FLASH locations.
The start location of FLASH from where data is retrieved is specified by the address ADDRH:ADDRL and
the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can
be retrieved in one routine call is 128 bytes. The data retrieved from FLASH is loaded into the data array
in RAM. Previous data in the data array will be overwritten. User can use this routine to retrieve data from
FLASH that was previously programmed.
The coding example below is to retrieve 32 bytes of data starting from $EF00 in FLASH. The Initialization
subroutine is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).
LDRNGE EQU $FF30
MAIN:
BSR INITIALIZATION
:
:
LDHX #FILE_PTR
JSR LDRNGE
:
98 Freescale Semiconductor
ROM-Resident Routines
7.5.4 MON_PRGRNGE
In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into
the data array.
The MON_PRGRNGE routine is designed to be used in monitor mode. It performs the same function as
the PRGRNGE routine (see 7.5.1 PRGRNGE), except that MON_PRGRNGE returns to the main program
via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to
the monitor code.
7.5.5 MON_ERARNGE
In monitor mode, ERARNGE is used to erase a range of locations in FLASH.
The MON_ERARNGE routine is designed to be used in monitor mode. It performs the same function as
the ERARNGE routine (see 7.5.2 ERARNGE), except that MON_ERARNGE returns to the main program
via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the
monitor code.
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Monitor ROM (MON)
7.5.6 MON_LDRNGE
In monitor mode, LDRNGE is used to load the data array in RAM with data from a range of FLASH
locations.
The MON_LDRNGE routine is designed to be used in monitor mode. It performs the same function as the
LDRNGE routine (see 7.5.3 LDRNGE), except that MON_LDRNGE returns to the main program via an
SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor
code.
7.5.7 EE_WRITE
EE_WRITE is used to write a set of data from the data array to FLASH.
1. The minimum data size is 2 bytes. The maximum data size is 15 bytes.
2. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0.
The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the
number of bytes in the data array is specified by DATASIZE. The minimum number of bytes that can be
programmed in one routine call is 2 bytes, the maximum is 15 bytes. ADDRH:ADDRL must always be the
start of boundary address (the page start address: $XX00, $XX40, $XX80, or $00C0) and DATASIZE
must be the same size when accessing the same page.
In some applications, the user may want to repeatedly store and read a set of data from an area of
non-volatile memory. This is easily possible when using an EEPROM array. As the write and erase
operations can be executed on a byte basis. For FLASH memory, the minimum erase size is the page —
64 bytes per page for MC68HC908JL8. If the data array size is less than the page size, writing and erasing
to the same page cannot fully utilize the page. Unused locations in the page will be wasted. The
EE_WRITE routine is designed to emulate the properties similar to the EEPROM. Allowing a more
efficient use of the FLASH page for data storage.
When the user dedicates a page of FLASH for data storage, and the size of the data array defined, each
call of the EE_WRTIE routine will automatically transfer the data in the data array (in RAM) to the next
blank block of locations in the FLASH page. Once a page is filled up, the EE_WRITE routine automatically
erases the page, and starts to reuse the page again. In the 64-byte page, an 4-byte control block is used
by the routine to monitor the utilization of the page. In effect, only 60 bytes are used for data storage. (see
Figure 7-9). The page control operations are transparent to the user.
F L A S H
PAGE BOUNDARY
CONTROL: 8 BYTES $XX00, $XX40, $XX80, OR $XXC0
DATA ARRAY
DATA ARRAY
DATA ARRAY
ONE PAGE = 64 BYTES
PAGE BOUNDARY
ORG RAM
:
FILE_PTR:
BUS_SPD DS.B 1; Indicates 4x bus frequency
DATASIZE DS.B 1; Data size to be programmed
START_ADDR DS.W 1; FLASH starting address
DATAARRAY DS.B 15; Reserved data array
ORG FLASH
INITIALISATION:
MOV #20, BUS_SPD
MOV #15, DATASIZE
LDHX #FLASH_START
STHX START_ADDR
RTS
MAIN:
BSR INITIALISATION
:
:
LHDX #FILE_PTR
JSR EE_WRITE
NOTE
The EE_WRITE routine is unable to check for incorrect data blocks, such
as the FLASH page boundary address and data size. It is the responsibility
of the user to ensure the starting address indicated in the data block is at
the FLASH page boundary and the data size is 2 to 15. If the FLASH page
is already programmed with a data array with a different size, the
EE_WRITE call will be ignored.
7.5.8 EE_READ
EE_READ is used to load the data array in RAM with a set of data from FLASH.
1. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0.
The EE_READ routine reads data stored by the EE_WRITE routine. An EE_READ call will retrieve the
last data written to a FLASH page and loaded into the data array in RAM. Same as EE_WRITE, the data
size indicated by DATASIZE is 2 to 15, and the start address ADDRH:ADDRL must the FLASH page
boundary address.
The coding example below uses the data stored by the EE_WRITE coding example (see 7.5.7
EE_WRITE). It loads the 15-byte data set stored in the $EF00–$EE7F page to the data array in RAM. The
initialization subroutine is the same as the coding example for EE_WRITE (see 7.5.7 EE_WRITE).
EE_READ EQU $FDD0
MAIN:
BSR INITIALIZATION
:
:
LDHX FILE_PTR
JSR EE_READ
:
NOTE
The EE_READ routine is unable to check for incorrect data blocks, such as
the FLASH page boundary address and data size. It is the responsibility of
the user to ensure the starting address indicated in the data block is at the
FLASH page boundary and the data size is 2 to 15. If the FLASH page is
programmed with a data array with a different size, the EE_READ call will
be ignored.
8.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a
timing reference with Input capture, output compare, and pulse-width-modulation functions. Figure 8-1 is
a block diagram of the TIM.
This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
8.2 Features
Features of the TIM include:
• Two input capture/output compare channels:
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse-width-modulation (PWM) signal generation
• Programmable TIM clock input
– 7-frequency internal bus clock prescaler selection
– External clock input on timer 2 (bus frequency ÷2 maximum)
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TCH0 may refer generically to
T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
T2CLK
(FOR TIM2 ONLY)
PRESCALER SELECT
INTERNAL
BUS CLOCK PRESCALER
TSTOP
PS2 PS1 PS0
TRST
TOV0
CHANNEL 0 ELS0B ELS0A PORT
CH0MAX T[1,2]CH0
LOGIC
16-BIT COMPARATOR
TCH0H:TCH0L CH0F
16-BIT LATCH INTERRUPT
LOGIC
MS0A CH0IE
MS0B
TOV1
CHANNEL 1 ELS0B ELS0A PORT
CH1MAX T[1,2]CH1
INTERNAL BUS
LOGIC
16-BIT COMPARATOR
TCH1H:TCH1L CH1F
16-BIT LATCH CH01IE INTERRUPT
LOGIC
MS0A CH1IE
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to
set the pin if the state of the PWM pulse is logic 0.
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000. See 8.9.1 TIM Status and Control Register.
PERIOD
PULSE
WIDTH
TCHx
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. (See 8.9.4 TIM Channel Status and Control Registers.)
8.5 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.
CHxF and CHxIE are in the TIM channel x status and control register.
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See Table 8-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See
Table 8-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin. Table 8-3 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
Table 8-3. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA Mode Configuration
Pin under port control;
X0 00
initial output level high
Output preset
Pin under port control;
X1 00
initial output level low
00 01 Capture on rising edge only
00 10 Capture on falling edge only
Input capture
Capture on rising or
00 11
falling edge
01 01 Toggle output on compare
Output compare
01 10 Clear output on compare
or PWM
01 11 Set output on compare
1X 01 Toggle output on compare
Buffered output
1X 10 compare or Clear output on compare
buffered PWM
1X 11 Set output on compare
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As Figure 8-11 shows, the CHxMAX bit takes effect in the cycle
after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
PERIOD
TCHx
9.1 Introduction
This section describes the serial communications interface (SCI) module, which allows high-speed
asynchronous communications with peripheral devices and other MCUs.
9.2 Features
Features of the SCI module include the following:
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Separate receiver and transmitter CPU interrupt requests
• Programmable transmitter output polarity
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
• Interrupt-driven operation with eight interrupt flags:
– Transmitter empty
– Transmission complete
– Receiver full
– Idle receiver input
– Receiver overrun
– Noise error
– Framing error
– Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
• Bus clock as baud rate clock source
INTERNAL BUS
TRANSMITTER
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
RECEIVER
CONTROL
CONTROL
CONTROL
CONTROL
ERROR
DMA
RECEIVE TRANSMIT
RxD TxD
SHIFT REGISTER SHIFT REGISTER
TXINV
SCTIE
R8
TCIE
T8
SCRIE
ILIE
DMARE
TE
SCTE DMATE
RE
TC
RWU
SCRF OR ORIE
SBK
IDLE NF NEIE
FE FEIE
PE PEIE
LOOPS
LOOPS ENSCI
BKF M
ENSCI WAKE
RPF
ILTY
÷ 16 DATA SELECTION
CONTROL
9.4.2 Transmitter
Figure 9-4 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI is the bus clock.
INTERNAL BUS
PRE- BAUD
BUS CLOCK ÷4 SCALER DIVIDER ÷ 16 SCI DATA REGISTER
SCP1 11-BIT
START
STOP
SCP0 TRANSMIT
SHIFT REGISTER
SCR1
H 8 7 6 5 4 3 2 1 0 L TxD
SCR2
SCR0
MSB
TRANSMITTER CPU INTERRUPT REQUEST
TXINV
M
LOAD FROM SCDR
PEN PARITY
GENERATION SHIFT ENABLE
PREAMBLE
PTY
BREAK
ALL 0s
T8 ALL 1s
DMATE TRANSMITTER
DMATE CONTROL LOGIC
SCTIE
SCTE
SCTE SBK
DMATE
SCTE
LOOPS
SCTIE
SCTIE ENSCI
TC
TC TE
TCIE
TCIE
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register
2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing
to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic
1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port pin.
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current character shifts out to the TxD pin. Setting TE after the stop
bit appears on TxD causes data previously written to the SCDR to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit becomes
set and just before writing the next byte to the SCDR.
9.4.3 Receiver
Figure 9-5 shows the structure of the SCI receiver.
INTERNAL BUS
SCR1
SCP1 SCR2 SCI DATA REGISTER
SCP0 SCR0
PRE- BAUD
BUS CLOCK ÷4 ÷ 16
START
SCALER DIVIDER
STOP
11-BIT
RECEIVE SHIFT REGISTER
DATA
RxD H 8 7 6 5 4 3 2 1 0 L
RECOVERY
ALL 0s
BKF
ALL 1s
MSB
RPF
ERROR CPU INTERRUPT REQUEST
M
CPU INTERRUPT REQUEST
SCRF RWU
DMA SERVICE REQUEST
WAKE WAKEUP
IDLE
ILTY LOGIC
PEN PARITY R8
PTY CHECKING
IDLE
ILIE
ILIE
DMARE
SCRF
SCRIE
SCRIE
DMARE
SCRF
SCRIE
DMARE
DMARE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
RxD
RT
CLOCK
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT CLOCK
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT1
RT2
RT3
RT4
STATE
RT CLOCK
RESET
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 9-3 summarizes the results of the data bit samples.
Table 9-3. Data Bit Recovery
RT8, RT9, and RT10 Data Bit
Noise Flag
Samples Determination
000 0 0
001 0 1
010 0 1
011 1 1
100 0 1
101 1 1
110 1 1
111 1 0
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 9-4
summarizes the results of the stop bit samples.
Table 9-4. Stop Bit Recovery
RT8, RT9, and RT10 Framing
Noise Flag
Samples Error Flag
000 1 0
001 1 1
010 1 1
011 0 1
100 1 1
101 0 1
110 0 1
111 0 0
MSB STOP
RECEIVER
RT CLOCK
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
DATA
SAMPLES
Figure 9-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 9-7, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 9-7, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is
RECEIVER
RT CLOCK
RT10
RT11
RT12
RT13
RT14
RT15
RT16
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
DATA
SAMPLES
Figure 9-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 9-8, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is
154 – 160 × 100 = 3.90% ·
--------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 9-8, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is
11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is
• Address mark — An address mark is a logic 1 in the most significant bit position of a received
character. When the WAKE bit is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can
then compare the character containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and processes the characters that
follow. If they are not the same, software can set the RWU bit and put the receiver back into the
standby state.
• Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start
bit or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
Address: $0014
Bit 7 6 5 4 3 2 1 Bit 0
Read:
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
Write:
Reset: 0 0 0 0 0 0 0 0
Address: $0015
Bit 7 6 5 4 3 2 1 Bit 0
Read: R8
T8 DMARE DMATE ORIE NEIE FEIE PEIE
Write:
Reset: U U 0 0 0 0 0 0
= Unimplemented U = Unaffected
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character.
R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on
the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE — DMA Receive Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
DMATE — DMA Transfer Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
Address: $016
Bit 7 6 5 4 3 2 1 Bit 0
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset: 1 1 0 0 0 0 0 0
= Unimplemented
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
BYTE 1 BYTE 2 BYTE 3 BYTE 4
SCRF = 0
SCRF = 0
SCRF = 1
SCRF = 1
OR = 1
OR = 1
OR = 0
OR = 1
BYTE 1 BYTE 2 BYTE 3 BYTE 4
Address: $0017
Bit 7 6 5 4 3 2 1 Bit 0
Read: BKF RPF
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Address: $0018
Bit 7 6 5 4 3 2 1 Bit 0
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Address: $0019
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0
SCP1 SCP0 R SCR2 SCR1 SCR0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented R = Reserved
10.1 Introduction
This section describes the 13-channel, 8-bit linear successive approximation analog-to-digital converter
(ADC).
10.2 Features
Features of the ADC module include:
• 13 channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
INTERNAL
DATA BUS
READ DDRB/DDRD
DDRBx/DDRDx
RESET
WRITE PTB/PTD
PTBx/PTDx ADCx
READ PTB/PTD
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC0–ADC11 ADC12
CLOCK
BUS CLOCK GENERATOR
ADIV[2:0]
Figure 10-2. ADC Block Diagram
10.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
Address: $003C
Bit 7 6 5 4 3 2 1 Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset: 0 0 0 1 1 1 1 1
= Unimplemented
Address: $003D
Bit 7 6 5 4 3 2 1 Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Indeterminate after reset
= Unimplemented
Address: $003E
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
0 0 0 Bus Clock ÷ 1
0 0 1 Bus Clock ÷ 2
0 1 0 Bus Clock ÷ 4
0 1 1 Bus Clock ÷ 8
1 X X Bus Clock ÷ 16
X = don’t care
11.1 Introduction
Twenty six (26) bidirectional input-output (I/O) pins form four parallel ports. All I/O pins are programmable
as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Module Control
Port Bit DDR Pin
Module Register Control Bit
0 DDRA0 KBIE0 PTA0/KBI0
1 DDRA1 KBIE1 PTA1/KBI1
2 DDRA2 KBIE2 PTA2/KBI2
KBI KBIER ($001B)
3 DDRA3 KBIE3 PTA3/KBI3
A 4 DDRA4 KBIE4 PTA4/KBI4
5 DDRA5 KBIE5 PTA5/KBI5
OSC PTAPUE ($000D) PTA6EN
6 DDRA6 RCCLK/PTA6/KBI6(1)
KBI KBIER ($001B) KBIE6
7 DDRA7 KBI KBIER ($001B) KBIE7 PTA7/KBI7
0 DDRB0 PTB0/ADC0
1 DDRB1 PTB1/ADC1
2 DDRB2 PTB2/ADC2
3 DDRB3 PTB3/ADC3
B ADC ADSCR ($003C) ADCH[4:0]
4 DDRB4 PTB4/ADC4
5 DDRB5 PTB5/ADC5
6 DDRB6 PTB6/ADC6
7 DDRB7 PTB7/ADC7
0 DDRD0 PTD0/ADC11
1 DDRD1 PTD1/ADC10
ADC ADSCR ($003C) ADCH[4:0]
2 DDRD2 PTD2/ADC9
3 DDRD3 PTD3/ADC8
D
4 DDRD4 T1SC0 ($0025) ELS0B:ELS0A PTD4/T1CH0
TIM1
5 DDRD5 T1SC1 ($0028) ELS1B:ELS1A PTD5/T1CH1
6 DDRD6 PTD6/TxD
SCI SCC1 ($0013) ENSCI
7 DDRD7 PTD7/RxD
0 DDRE0 T2SC0 ($0035) ELS0B:ELS0A PTE0/T2CH0
E TIM2
1 DDRE1 T2SC1 ($0038) ELS1B:ELS1A PTE1/T2CH1
1. RCCLK/PTA6/KBI6 pin is only available when OSCSEL=0 (RC option);
PTAPUE register has priority control over the port pin.
RCCLK/PTA6/KBI6 is the OSC2 pin when OSCSEL=1 (XTAL option).
11.2 Port A
Port A is an 8-bit special function port that shares all of its pins with the keyboard interrupt (KBI) module
(see Chapter 13 Keyboard Interrupt Module (KBI)). Each port A pin also has software configurable pull-up
device if the corresponding port pin is configured as input port. PTA0–PTA5 and PTA7 has direct LED
drive capability.
NOTE
PTA0–PTA5 pins are available on 28-pin and 32-pin packages only.
PTA7 pin is available on 32-pin packages only.
Address: $0000
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by Reset
LED LED LED LED LED LED LED
Additional Functions:
(Sink) (Sink) (Sink) (Sink) (Sink) (Sink) (Sink)
pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up
Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard Keyboard
Alternative Functions:
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Address: $0004
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset: 0 0 0 0 0 0 0 0
PTAPUEx
WRITE DDRA ($0004)
DDRAx
INTERNAL DATA BUS
RESET
To KBI
Figure 11-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 11-2 summarizes the operation of the port A pins.
Table 11-2. Port A Pin Functions
PTAPUE Accesses to DDRA Accesses to PTA
DDRA Bit PTA Bit I/O Pin Mode
Bit Read/Write Read Write
1 0 X(1) Input, VDD(2) DDRA[7:0] Pin PTA[7:0](3)
0 0 X Input, Hi-Z(4) DDRA[7:0] Pin PTA[7:0](3)
X 1 X Output DDRA[7:0] PTA[7:0] PTA[7:0]
1. X = Don’t care.
2. Pin pulled to VDD by internal pull-up.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance.
Address: $000D
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset: 0 0 0 0 0 0 0 0
Address: $000E
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTAPUE7
Write:
Reset: 0 0 0 0 0 0 0 0
11.3 Port B
Port B is an 8-bit special function port that shares all of its port pins with the analog-to-digital converter
(ADC) module, see Chapter 10
Address: $0001
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
Alternative Functions: ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC2 ADC0
Address: $0005
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset: 0 0 0 0 0 0 0 0
To Analog-To-Digital Converter
Figure 11-9. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 11-3 summarizes the operation of the port B pins.
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
11.4 Port D
Port D is an 8-bit special function port that shares two of its pins with the serial communications interface
module (see Chapter 9), two of its pins with the timer 1 interface module, (see Chapter 8), and four of its
pins with the analog-to-digital converter module (see Chapter 10). PTD6 and PTD7 each has high current
sink (25mA) and programmable pull-up. PTD2, PTD3, PTD6 and PTD7 each has LED sink capability.
NOTE
PTD0–PTD1 are available on 28-pin and 32-pin packages only.
Address: $0003
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
LED LED LED LED
Additional Functions
(Sink) (Sink) (Sink) (Sink)
25mA sink 25mA sink
(Slow Edge) (Slow Edge)
pull-up pull-up
Alternative Functions: RxD TxD T1CH1 T1CH0 ADC8 ADC9 ADC10 ADC11
Address: $0007
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset: 0 0 0 0 0 0 0 0
PTDPU[6:7]
WRITE DDRD ($0007)
DDRDx
INTERNAL DATA BUS
RESET
Address: $000A
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Write:
Reset: 0 0 0 0 0 0 0 0
11.5 Port E
Port E is a 2-bit special function port that shares its pins with the timer 2 interface module (see Chapter 8).
NOTE
PTE0–PTE1 are available on 32-pin packages only.
Address: $0008
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTE1 PTE0
Write:
Reset: Unaffected by reset
Alternative Functions: T2CH1 T2CH0
Address: $000C
Bit 7 6 5 4 3 2 1 Bit 0
Read:
DDRE1 DDRE0
Write:
Reset: 0 0 0 0 0 0 0 0
RESET
To TIM2
Figure 11-16. Port E I/O Circuit
When DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When DDREx is a logic 0,
reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 11-5 summarizes the operation of the port E pins.
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
12.1 Introduction
The external interrupt (IRQ) module provides a maskable interrupt input.
12.2 Features
Features of the IRQ module include the following:
• A dedicated external interrupt pin (IRQ)
• IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Selectable internal pullup resistor
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long
as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See 5.5 Exception
Control.)
RESET
ACK
TO CPU FOR
VECTOR BIL/BIH
INTERNAL ADDRESS BUS
FETCH INSTRUCTIONS
DECODER
VDD
IRQPUD
INTERNAL VDD
IRQF
PULLUP
DEVICE CLR
D Q IRQ
SYNCHRONIZER
CK INTERRUPT
IRQ REQUEST
IMASK
MODE
HIGH TO MODE
VOLTAGE SELECT
DETECT LOGIC
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK
bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that
poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK
bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ pin to logic one — As long as the IRQ pin is at logic zero, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
NOTE
An internal pull-up resistor to VDD is connected to the IRQ pin; this can be
disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
Address: $001D
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 IRQF
IMASK MODE
Write: ACK
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Address: $001E
Bit 7 6 5 4 3 2 1 Bit 0
Read:
IRQPUD R R LVIT1 LVIT0 R R R
Write:
Reset: 0 0 0 Not affected Not affected 0 0 0
POR: 0 0 0 0 0 0 0 0
R = Reserved
13.1 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are
accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pull-up
device is also enabled on the pin.
13.2 Features
Features of the keyboard interrupt module include the following:
• Eight keyboard interrupt pins with pull-up devices
• Separate keyboard interrupt enable bits and one keyboard interrupt mask
• Programmable edge-only or edge- and level- interrupt sensitivity
• Exit from low-power modes
1. PTA6/KBI6 is only available when OSCSEL=0 at $FFD0 (RC option), and PTA6EN=1 at $000D.
MODEK
KBIE7
TO PULLUP ENABLE
Figure 13-2. Keyboard Interrupt Block Diagram
Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or
disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also
enables its internal pull-up device regardless of PTAPUEx bits in the port A input pull-up enable register
(see 11.2.3 Port A Input Pull-Up Enable Registers). A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK
bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an
interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on
one pin because another pin is still low, software can disable the latter pin while it is low.
• If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as
long as any keyboard pin is low.
If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both
of the following actions must occur to clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1
to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in
applications that poll the keyboard interrupt pins and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the vector address at locations $FFE0 and $FFE1.
• Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, disable the pull-up device, use the data direction
register to configure the pin as an input and then read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a logic 0 for software to
read the pin.
Address: $001A
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 KEYF 0
IMASKK MODEK
Write: ACKK
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Address: $001B
Bit 7 6 5 4 3 2 1 Bit 0
Read:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset: 0 0 0 0 0 0 0 0
14.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
CONFIG1 register.
SIM
COP TIMEOUT
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET CLEAR
COPCTL WRITE COP COUNTER
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
218 – 24 or 213 – 24 ICLK cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. Writing any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 × ICLK cycles and sets the COP bit in the reset status register
(RSR). (See 5.7.2 Reset Status Register (RSR).).
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
14.3.1 ICLK
ICLK is the internal oscillator output signal, typically 50-kHz. The ICLK frequency varies depending on the
supply voltage. See Chapter 17 Electrical Specifications for ICLK parameters.
Address: $001F
Bit 7 6 5 4 3 2 1 Bit 0
Read:
COPRS R R LVID R SSREC STOP COPD
Write:
Reset: 0 0 0 0 0 0 0 0
R = Reserved
Address: $FFFF
Bit 7 6 5 4 3 2 1 Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
14.5 Interrupts
The COP does not generate CPU interrupt requests.
15.1 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin
and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage.
15.2 Features
Features of the LVI module include the following:
• Selectable LVI trip voltage
• Selectable LVI circuit disable
VDD
LVID
LVIT1 LVIT0
Address: $001E
Bit 7 6 5 4 3 2 1 Bit 0
Read: STOP_
IRQPUD R R LVIT1 LVIT0 R R
Write: ICLKDIS
Reset: 0 0 0 Cleared by POR only 0 0 0
Address: $001F
Bit 7 6 5 4 3 2 1 Bit 0
Read:
COPRS R R LVID R SSREC STOP COPD
Write:
Reset: 0 0 0 0 0 0 0 0
1 1 Reserved
16.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
16.2 Features
Features of the break module include the following:
• Accessible I/O registers during the break Interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
8-BIT COMPARATOR
IAB[15:0]
CONTROL BKPT
(TO SIM)
8-BIT COMPARATOR
IAB[7:0]
Figure 16-1. Break Module Block Diagram
Address: $FE0E
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0
BRKE BRKA
Write:
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Address: $FE0C
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
Address: $FE0D
Bit 7 6 5 4 3 2 1 Bit 0
Read:
Bit 7 6 5 4 3 2 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
Address: $FE00
Bit 7 6 5 4 3 2 1 Bit 0
Read: SBSW
R R R R R R R
Write: Note(1)
Reset: 0
R = Reserved 1. Writing a logic zero clears SBSW.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU 5
LOBYTE EQU 6
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode was exited
; by break.
Address: $FE03
Bit 7 6 5 4 3 2 1 Bit 0
Read:
BCFE R R R R R R R
Write:
Reset: 0
R = Reserved
17.1 Introduction
This section contains electrical and timing specifications.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
3. Values are based on characterization results, not tested in production.
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
tRL
RST
tILIL
tILIH
IRQ
14
12
RC frequency, fRCCLK (MHz)
CEXT = 10 pF MCU
10
5V @ 25°C
8 OSC1
6
VDD
4 REXT CEXT
0
0 10 20 30 40 50
Resistor, REXT (kΩ)
Figure 17-2. RC vs. Frequency (5V @25°C)
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
3. Values are based on characterization results, not tested in production.
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
tRL
RST
tILIL
tILIH
IRQ
14
12
RC frequency, fRCCLK (MHz)
CEXT = 10 pF MCU
10
3V @ 25°C
OSC1
8
6
VDD
4 REXT CEXT
0
0 10 20 30 40 50
Resistor, REXT (kΩ)
Figure 17-4. RC vs. Frequency (3V @25°C)
60 –40°C
+25°C
50
+85°C
40 +125°C
30
20
2 3 4 5 6
Supply Voltage, VDD (V)
Figure 17-5. Internal Oscillator Frequency
10
6 5.5 V
3.3 V
4
0
0 1 2 3 4 5 6 7 8 9
fOP or fBUS (MHz)
5.5 V
3
IDD (mA)
3.3 V
2
0
0 1 2 3 4 5 6 7 8 9
fOP or fBUS (MHz)
18.1 Introduction
This section gives the dimensions for:
• 20-pin plastic dual in-line package (case #738)
• 20-pin small outline integrated circuit package (case #751D)
• 28-pin plastic dual in-line package (case #710)
• 28-pin small outline integrated circuit package (case #751F)
• 32-pin shrink dual in-line package (case #1376)
• 32-pin low-profile quad flat pack (case #873A)
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
20 11 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEAD WHEN
1 10 FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C L
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
–T– C 0.150 0.180 3.81 4.57
K D 0.015 0.022 0.39 0.55
SEATING
PLANE M E 0.050 BSC 1.27 BSC
F 0.050 0.070 1.27 1.77
E N G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
G F K 0.110 0.140 2.80 3.55
J 20 PL
L 0.300 BSC 7.62 BSC
D 20 PL 0.25 (0.010) M T B M M 0_ 15 _ 0_ 15_
0.25 (0.010) M T A M N 0.020 0.040 0.51 1.01
–A– NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
20 11 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
–B– 10X P (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.010 (0.25) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
1 10 (0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–T– SEATING
PLANE
18X G M
K
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
28 15
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
MILLIMETERS INCHES
1 14 DIM MIN MAX MIN MAX
A 36.45 37.21 1.435 1.465
L B 13.72 14.22 0.540 0.560
A C C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
N F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
H 1.65 2.16 0.065 0.085
J 0.20 0.38 0.008 0.015
H G F J K 2.92 3.43 0.115 0.135
K M L 15.24 BSC 0.600 BSC
D
SEATING M 0° 15° 0° 15°
PLANE N 0.51 1.02 0.020 0.040
NOTES:
-A- 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
28 15 2. CONTROLLING DIMENSION: MILLIMETER.
14X P 3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
-B- 0.010 (0.25) M B M 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 14 PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
28X D AT MAXIMUM MATERIAL CONDITION.
M MILLIMETERS INCHES
0.010 (0.25) M T A S B S
DIM MIN MAX MIN MAX
R X 45 A 17.80 18.05 0.701 0.711
B 7.40 7.60 0.292 0.299
C C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
-T- F 0.41 0.90 0.016 0.035
26X G SEATING G 1.27 BSC 0.050 BSC
PLANE
J 0.23 0.32 0.009 0.013
K K 0.13 0.29 0.005 0.011
F
M 0° 8° 0° 8°
P 10.01 10.55 0.395 0.415
J R 0.25 0.75 0.010 0.029
3
27.9 B
A 27.8
32 17
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
10.46 8.9 PER ASME Y14.5, 1994.
9.86 8.8 3 3. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS.
4. DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION.
1 16
2.49
2.39
C T 10 ° 0.34
0.5 SEATING 0° 0.22
32X 0.4 4 PLANE
–T– –U–
B V AE
P
B1 DETAIL Y
8 17
V1
AE
9 DETAIL Y
4X
–Z–
9 S1 0.20 (0.008) AC T–U Z NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
S Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
DETAIL AD 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
G AT DATUM PLANE –AB–.
–AB– 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
SEATING 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PLANE
–AC– PROTRUSION. ALLOWABLE PROTRUSION IS
0.10 (0.004) AC 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
AC T–U Z
BASE DO INCLUDE MOLD MISMATCH AND ARE
METAL
ÉÉ
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
N
ÉÉ
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
ÉÉ
M
F D 0.0076 (0.0003).
ÉÉ
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
8X M_
R J MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 7.000 BSC 0.276 BSC
A1 3.500 BSC 0.138 BSC
SECTION AE–AE B 7.000 BSC 0.276 BSC
C E B1 3.500 BSC 0.138 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
W Q_ G 0.800 BSC 0.031 BSC
H K H 0.050 0.150 0.002 0.006
0.250 (0.010)
GAUGE PLANE
19.1 Introduction
This section contains ordering numbers for the MC68HC908JL8.
A.1 Introduction
This section introduces the MC68HC08JL8, the ROM part equivalent to the MC68HC908JL8/JK8. The
entire data book applies to this ROM device, with exceptions outlined in this appendix.
Table A-1. Summary of MC68HC08JL8 and MC68HC908JL8 Differences
MC68HC08JL8 MC68HC908JL8
Mask option register ($FFD0) Defined by mask; read only. Read/write FLASH register.
M68HC08 CPU
KEYBOARD INTERRUPT PTA7/KBI7**‡ #
CPU ARITHMETIC/LOGIC PTA6/KBI6**¥
REGISTERS UNIT (ALU) MODULE
PTA5/KBI5**‡
PORTA
PTA4/KBI4**‡
DDRA
8-BIT ANALOG-TO-DIGITAL PTA3/KBI3**‡
CONTROL AND STATUS REGISTERS — 64 BYTES CONVERTER MODULE ##
PTA2/KBI2**‡
PTA1/KBI1**‡
USER ROM — 8,192 BYTES PTA0/KBI0**‡
2-CHANNEL TIMER INTERFACE
MODULE 1
PTB7/ADC7
USER RAM — 256 BYTES
PTB6/ADC6
2-CHANNEL TIMER INTERFACE PTB5/ADC5
PORTB
MODULE 2
DDRB
MONITOR ROM — 447 BYTES PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
USER ROM VECTORS — 36 BYTES BREAK
PTB1/ADC1
MODULE
PTB0/ADC0
ADC12/T2CLK #
CRYSTAL OSCILLATOR
OSC1 SERIAL COMMUNICATIONS †‡
PTD7/RxD**
INTERFACE MODULE
¥ OSC2/RCCLK
RC OSCILLATOR PTD6/TxD**†‡
PTD5/T1CH1
PORTD
DDRD
POWER-ON RESET PTD4/T1CH0
INTERNAL OSCILLATOR
MODULE PTD3/ADC8‡
PTD2/ADC9‡
PTD1/ADC10
##
SYSTEM INTEGRATION LOW-VOLTAGE INHIBIT PTD0/ADC11
* RST MODULE MODULE
PTE1/T2CH1
DDRE
PTE
EXTERNAL INTERRUPT #
* IRQ MODULE COMPUTER OPERATING
PROPERLY MODULE PTE0/T2CH0
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. The numbers in parenthesis are MC68HC908JL8 values.
12
RC frequency, fRCCLK (MHz)
CEXT = 10 pF MCU
10
5V @ 25°C
8 OSC1
6
VDD
4 REXT CEXT
MC68HC908JL8
2 MC68HC08JL8
0
0 10 20 30 40 50
Resistor, REXT (kΩ)
Figure A-3. RC vs. Frequency (5V @25°C)
14
12
RC frequency, fRCCLK (MHz)
CEXT = 10 pF MCU
10
3V @ 25°C
OSC1
8
6
VDD
4 REXT CEXT
MC68HC908JL8
2 MC68HC08JL8
0
0 10 20 30 40 50
Resistor, REXT (kΩ)
Figure A-4. RC vs. Frequency (3V @25°C)
B.1 Introduction
This appendix introduces the MC68HC908KL8, an ADC-less device of the MC68HC908JL8. The entire
data book applies to this device, with exceptions outlined in this appendix.
MC68HC908KL8 MC68HC908JL8
M68HC08 CPU
KEYBOARD INTERRUPT PTA7/KBI7**‡ #
CPU ARITHMETIC/LOGIC PTA6/KBI6**¥
REGISTERS UNIT (ALU) MODULE
PTA5/KBI5**‡
PORTA
PTA4/KBI4**‡
DDRA
PTA3/KBI3**‡
CONTROL AND STATUS REGISTERS — 64 BYTES
PTA2/KBI2**‡
PTA1/KBI1**‡
USER FLASH — 8,192 BYTES PTA0/KBI0**‡
2-CHANNEL TIMER INTERFACE
MODULE 1
PTB7
USER RAM — 256 BYTES
PTB6
2-CHANNEL TIMER INTERFACE PTB5
PORTB
MODULE 2
DDRB
MONITOR ROM — 959 BYTES PTB4
PTB3
PTB2
USER FLASH VECTORS — 36 BYTES BREAK
PTB1
MODULE
PTB0
T2CLK #
CRYSTAL OSCILLATOR
OSC1 SERIAL COMMUNICATIONS †‡
PTD7/RxD**
INTERFACE MODULE
¥ OSC2/RCCLK
RC OSCILLATOR PTD6/TxD**†‡
PTD5/T1CH1
PORTD
DDRD
POWER-ON RESET PTD4/T1CH0
INTERNAL OSCILLATOR
MODULE PTD3‡
PTD2‡
PTD1
SYSTEM INTEGRATION LOW-VOLTAGE INHIBIT PTD0
* RST MODULE MODULE
PTE1/T2CH1
DDRE
PTE
EXTERNAL INTERRUPT #
* IRQ MODULE COMPUTER OPERATING
PROPERLY MODULE PTE0/T2CH0
IRQ 1 28 RST
PTA0/KBI0 2 27 PTA5/KBI5
VSS 3 26 PTD4/T1CH0
OSC1 4 25 PTD5/T1CH1
OSC2/RCCLK/PTA6/KBI6 5 24 PTD2
PTA1/KBI1 6 23 PTA4/KBI4
VDD 7 22 PTD3
PTA2/KBI2 8 21 PTB0
Pins not available on 28-pin packages
PTA3/KBI3 9 20 PTB1
PTE0/T2CH0
PTB7 10 19 PTD1 PTE1/T2CH1
PTB6 11 18 PTB2
PTB5 12 17 PTB3 T2CLK
PTD7/RxD 13 16 PTD0 PTA7/KBI7
PTD6/TxD 14 15 PTB4 Internal pads are unconnected.
Set these unused port I/Os to output low.
$FFDE Reserved
— IF15
$FFDF Reserved
MC68HC908JL8
Rev. 3.1, 3/2005