IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO.

1, JANUARY 2013

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Glitch-Free NAND-Based Digitally Controlled Delay-Lines

Davide De Caro, Senior Member, IEEE
AbstractThe recently proposed NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum delay of previously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm CMOS technology and compared, in this technology, to the state-of-the-art. Simulation results show that novel circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest delay. Simulations also conrm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is used to realize an All-digital spread-spectrum clock generator (SSCG). The employ of proposed DCDL in this circuit allows to reduce the peak-to-peak absolute output jitter of more than the 40% with respect to a SSCG using three-state inverter based DCDLs. Index TermsAll-digital delay-locked loop (ADDLL), all-digital phase-locked loop (ADPLL), delay-line, digitally controlled oscillator (DCO), ip-ops, sense amplier, spread-spectrum clock generator (SSCG).

I. INTRODUCTION N RECENT deep-submicrometer CMOS processes, time-domain resolution of a digital signal is becoming higher than voltage resolution of analog signals [1]. This claim is nowadays pushing toward a new circuit design paradigm in which the traditional analog signal processing is expected to be progressively substituted by the processing of times in the digital domain. Within this novel paradigm, digitally controlled delay lines (DCDL) should play the role of digital-to-analog converters in traditional, analog-intensive, circuits. From a more practical point of view, nowadays, DCDLs are a key block in a number of applications, like all-digital PLL (ADPLL) [2][8], all-digital DLL (ADDLL) [9][16], all-digital spread-spectrum clock generators (SSCGs) [17], [18], and ultra-wide band (UWB) receivers with ranging feature [19], [20].
Manuscript received August 04, 2011; accepted December 07, 2011. Date of publication January 23, 2012; date of current version December 19, 2012. The author is with the Department of Electronic Engineering, University of Napoli Federico II, 80125 Napoli, Italy (e-mail: dadecaro@unina.it). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TVLSI.2011.2181547

The classical approach [3][6], [9], [17] to design a DCDL is using a delay-cells chain and a MUX to select the desired cell output. In these mux-based DCDLs, the MUX delay increases with the increase of the number of cells. This results in a of tradeoff between the delay range and minimum delay is a critical design paramthe DCDL. It is worth to note that eter in many application. As an example in ADPLL/ADDLL, determines the maximum output frequency of the circuit. This property remains true also for the All-digital SSCG of [18], where a correct DCDL synchronization is obtained only by imposing that is lower than one half input clock period. The large of MUX-based DCDLs can be reduced by using a tree-based multiplexer topology [3]. This however results in an irregular structure which complicates layout design and, consequently, also increases the nonlinearity of the DCDL. The DCDL topology employed in [10] and [11] uses again a delay cells chain. Differently from the above approaches, in this technique each cell is constructed by using NAND gates. This apparently solves the tradeoff related to the MUX of previous structures. A deepen analysis of the structure, however, reveals that the input capacitance of the DCDL increases linearly with the number of cells. This, clearly, reintroduces a tradeoff between the number of cells and the minimum delay, similarly to MUX-based DCDLs. A similar reasoning applies also to the MUX-based DCDL proposed in [16]. In [12][15], the DCDL is constructed by using a regular cascade of equal delay elements (DE). In this circuit, the multiplexer of previous DCDL is conceptually spread among all cells. is very low and becomes inIn this way the minimum delay dependent of the number of cells. In addition the highly regular topology allows a simple layout organization [18] which provides very low nonlinearity layout effects. Each DE in [12][15] is constructed by using only NAND gates, obtaining a very good linearity and resolution. An analysis of the circuit reveals that is given by ( being the DCDL resolution the delay of a NAND gate). The DCDL proposed in [8] uses again a structure of cascaded delay elements. Differently from [12][15], each element is constructed by using three-state inverters (TINV), obtaining a res. Since the pull-up network of a TINV olution requires two series devices whereas a NAND gate uses a single device in the pull-up, we can expect that the resolution of this solution is higher than the resolution of NAND-based DCDLs [12][15]. The DCDL proposed in [18] is also based on a cascade of equal delay elements, which allows a simple layout organization. In this case each delay element is constructed by using an inverter and an inverting multiplexer. This

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Fig. 1. Glitching problem of NAND-based DCDL [12][15] (a) glitching when the delay control-code increases by one; (b) glitching when the delay control-code increases by two.

topology, however, presents two drawbacks. A rst weakness is due to the different delays of the inverter and the multiplexer which results in a mismatch between odd and even control-codes. This mismatch results in an increased INL. A second drawback is due to the large multiplexer delay, which provides a resolution higher than the resolution of both NANDbased DCDLs and TINV-based DCDLs. Glitching is a common design problem in systems employing DCDLs. In the most common applications, DCDLs are employed to process clock signals, therefore a glitch-free operation is required. A necessary condition to avoid glitching is designing a DCDL which have no-glitch in presence of a delay control-code switching. This is an issue at the DCDL-design level. Many approaches are known to avoid glitching in mux-based DCDLs [21][23]. It is interesting to observe that the DCDL topologies of [8] and [18], from a logical point of view, correspond to distributed MUX-based structure. Glitching in these topologies can be avoided by using a thermometer code for the control-bits, or using the approach of [23]. On the other hand the NAND-based DCDL topology of [12][15] presents a glitching problem that, to the best of our knowledge, is still not known in Literature. It is worth to note that in the ADDLL topologies of [12][15] the DCDL glitching is ltered by the phase detector and harmonic locking circuitry during locking phase. In other applications, however, the presence of this glitching phenomenon can substantially limit the employ of NAND-based DCDLs. This represents a substantial drawback of this topology in comparison to the solutions of [8] and [18]. The errors that in some applications can originate from DCDL glitching will be also discussed within this paper. This paper gives two contributions to the design of NAND-based DCDLs. First it is shown and analyzed the glitching problem of the NAND-based DCDL of [12][15]. Afterwards a novel glitch-free NAND-based DCDL is presented. The proposed NAND-based DCDL allows to achieve a resolution , similarly to the NAND-based DCDL of [12][15]. The paper is organized as follows. The NAND-based DCDL of [12][15] is recalled in Section II. In the same section the glitching problem of this DCDL is analyzed. The structure of proposed, glitch-free, NAND-based DCDL is presented in Section III. Section IV analyzes theoretically the novel DCDL structure by deriving the conditions (timing constraints) needed to avoid glitching in proposed circuit. These results are used to propose three different driving circuits for the delay control-bits of proposed DCDL. Section V presents the obtained simulation results for a 90-nm CMOS technology. The results presented

in this section, in addition to verify the correctness of the analysis of Section IV, demonstrate the performances of proposed DCDLs in comparison to previously proposed structures. Finally, Section VI describes the employ of proposed DCDL to implement an All-digital SSCG designed with the approach described in [18]. II. PREVIOUSLY PROPOSED NAND-BASED DCDL AND GLITCHING Fig. 1(a) shows the NAND-based DCDL of [12][15]. The circuit is composed by a series of equal delay-elements (DE), each composed by four NAND gates. In the gure A denotes the fast input of each NAND gate. Gates marked with D are dummy cells added for load balancing. The delay of the circuit is controlled through control-bits , which encode the delay control-code with a thermometric code: for and for . By using this encoding, each DE in Fig. 1(a) can be either in pass-state or in turn-state . In Fig. 1(a) all NAND gates present the same load (two NAND gates) and, therefore, in a rst order approximation, present the same delay. This consideration allows to write the delay , from In to Out, as follows: (1) where while and represent the delay of each NAND gate for a low-to-high and high-to-low output commutation, respectively. It is interesting to observe that (1) holds both for low-to-high and high-to-low Out commutations. Equations (1) suggests that and . In DCDL applications, to avoid DCDL output glitching, the switching of delay control-bits is synchronized with the switching of In input signal. Glitching is avoided if the control-bits arrival time is lower than the arrival time of the input signal of the rst DE which switches from or to the turn-state. Unfortunately in the DCDL of Fig. 1(a) this condition is not sufcient to avoid glitching. In this circuit, in fact, it is possible to have output glitches also considering only the control-bits switching, with a stable input signal. Some examples of glitching problems of this DCDL are highlighting in Fig. 1. Let us name the vector of the control-bits of the DCDL. In Fig. 1(a) it is assumed that and that the control-code of the DCDL is switched from to . Please note that, within the structure, the switching of and results in two different paths that generate an output glitch. It can be

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Fig. 2. Transient simulations highlighting glitching problems of the NAND-based DCDL of [12][15] and the glitch-free operation of proposed DCDL.

Fig. 3. Transient simulation of two ring-oscillator-based DCO designed by using proposed and NAND-based DCDLs of [12][15].

easily veried that the same glitching behavior exists when input In is 1, and the delay control-code is increased by 1 starting from an even value. Fig. 1(b) shows that the structure exhibits a more severe glitching problem when the delay control-code is increased by more than 1. In particular the Fig. 1(b) considers the case in which control-code of the DCDL is switched from to . The analysis of the gure, in this case, reveals that, in the worst case, four paths propagate within the DCDL structure and may create a multiple-glitch at the delay-line output. More in general the glitching problem of NAND-based DCDL grows up because, for a control-code equal to , all and signals in Fig. 1, with , are stuck-at 1, while for , the logic state of and signals depends on the input In. When the control-code is increased, the logic state of the output becomes dependant on a portion of the DCDL for which and switch from 1 to a logic state dependant on In. This switching may determine output glitches. This consideration also demonstrates that no glitching can occur when the control-code is decreased. Please note that, when the control-code is increased by one, the glitching problem could be avoided by delaying signals with respect to signals (see in Fig. 1(a). This solution, however, does not solve the glitching problem when the control-code is increased by more than one [see Fig. 1(b)]. The Fig. 2 shows a transistor-level simulation of a NANDbased DCDL composed by 64 elements. In this simulation, rst, . The control-code of the DCDL is rstly changed from 9 to 62 and, afterwards, changed back from 62 to 9. The DCDL output is reported in the third curve of the gure (Out (NANDbased [12][15])). When the code word is increased , it can be observed the presence of three glitches on the DCDL output. As observed before, when the code word is decreased , no output glitching occurs. The second portion of the simulation shows that the same behavior can be observed for .

The glitching problem in still more severe when the DCDL is closed in a ring-oscillator topology to build a DCO. As an example Fig. 3 shows the simulation of a ring-oscillator based DCO designed by using the NAND-based DCDL of [12][15]. It can be observed that the delay control-code is initially equal to 20, this corresponds to an oscillation frequency of about 500 MHz. When delay control-code is switched from 20 to 30 a glitch is produced by the DCDL. Because of the feedback topology of the DCO, this glitch remains entrapped in the ring-oscillator, providing a strong modication also of the steady-state response of the circuit. Substantially the ring-oscillator enter in an oscillation state with more than one output rising-edge for oscillation period. The output frequency of the DCO, in these conditions, should be of about 333 MHz, while the circuit provides an output with a frequency which varies between 800 MHz and 1.2 GHz, with a mean value which corresponds to three times the desired frequency GHz . Afterwards the delay-control code is switched back to 20. Note that this switching does not result in DCDL glitching, however the ring-oscillator state remains compromised by the presence of the glitch in previous control-code switching. The DCO output frequency, in fact, should return to 500 MHz, while the output frequency of the circuit varies between 1.3 and 2.0 GHz with a mean value of 1.5 GHz. III. PROPOSED NAND-BASED DCDL The structure of proposed DCDL is shown in Fig. 4. In this gure A denotes the fast input of each NAND gate. Gates marked with D, represents dummy cells added for load balancing. Two sets of control-bits, and , control the DCDL. The bits encode the control-code by using a thermometric code: for and for . The bits encode again by using a one-cold code: , for . The Fig. 4 shows the state of all signals in the case , . According to the chosen control-bits encoding, each delay-element (DE) can be in one of three possible states.

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Fig. 4. Proposed glitch-free NAND-based DCDL (inverting topology).

Fig. 5. Proposed glitch-free NAND-based DCDL (non-inverting topology).

TABLE I LOGIC-STATES OF EACH DE IN PROPOSED DCDLS

The DEs with are in pass-state . In this state the NAND 3 output is equal to 1 and the NAND 4 allows the signal propagation in the lower NAND gates chain. The DE with is in turn-state . In this state the upper input of the DE is passed to the output of NAND 3. The next DE is in post-turn-state . In this DE the output of the NAND 4 is stuck-at 1, by allowing the propagation, in the previous DE (which is in turn-state), of the output of NAND 3 through NAND 4. All remaining DEs (for ) are again in turn-state . The three possible DE states of proposed DCDL and the corresponding and values are summarized in Table I. In the proposed DCDL the state of all and signals depends on the input ( and ) with the only exception of , which is stuck-at 1. The glitch-free switching property of the proposed DCDL is conceptually simple to demonstrate. Let us assume a switching of the delay control-code from to . In the initial state of the line, and , with the exception of , which is stuck-at 1. Let us suppose to rst switch the th DE from the post-turn-state to the turn-state. By looking to Fig. 4 it can be observed that, in these conditions, switches from 1 to . The signal is the input of the NAND 4 gate of th DE. The switching of is glitch-free since the other input of this gate is stuck-at , therefore the NAND 4 output remains equal to . After the th DE switching, all cells are either in pass-state or in turn-state. In these conditions it is possible to freely change the state of DEs from pass-state to turn-state, since this change does not affect the logic state of signals and . After this phase the th DE can be switched from turn-state to post-turn-state. This switching is again glitchfree, since only signal switches from to 1. This procedure has the drawback to require a three-step switching of the DCDL. The following section provides a more detailed analysis of the glitching of proposed circuit in order to show that a glitch-free operation can also be achieved by using a properly designed two-step switching mechanism. The last signal plotted in Fig. 2 is the output of proposed DCDL of Fig. 4, simulated by using the above described threestep switching mechanism, and in the same conditions of the

Fig. 6. Control-bits waveforms of proposed DCDL for a control-code switch to : (a) case; (b) case. from

NAND-based DCDL [12][15]. This simulation conrms that no glitching is obtained at the output of proposed DCDL. Please note also that, in Fig. 4, by increasing the controlcode by one, two NAND gates are inserted in the signal propagation path between In and Out. Therefore, similarly to the NAND-based DCDL of Fig. 1, the resolution can be written as . The minimum delay of proposed inverting solution is higher than the of the NAND-based DCDL of [12][15] . The circuit of Fig. 4 is an inverting DCDL. In this circuit it is interesting to observe that the rst DE is never in post-turn state, therefore is always 1 (see Table I). This observation allows to construct a non-inverting DCDL by modifying only the rst DE, as shown in Fig. 5. In this circuit the NAND gates 1 and 2 of the rst DE have been deleted, together with signal . The signal of the second DE is now equal to In, therefore the whole behavior of the DCDL is non-inverting. This topology maintains the same of previous solution, while it can easily veried that the minimum delay is now . The non-inverting DCDL of Fig. 5, therefore, maintains the same performances of the NAND-based DCDL of [12][15], while avoiding its glitching problem. The last signal plotted in Fig. 3 is the output of DCO designed by using proposed DCDL of Fig. 5. This simulation conrms that no glitching is obtained at the output and this results in a correct DCO operation. In fact the simulation shows that the DCO output switches correctly from 500 to 333 MHz and back to 500 MHz, without any glitch or any problem.

IV. GLITCH-FREE SWITCHING OF PROPOSED DCDL CONTROL-BITS DRIVING CIRCUITS

AND

In the previous section we have seen that the glitch-free operation of the proposed DCDL can be obtained with a three-step switching mechanism: for a switching from a delay control code to a delay control code , rst, the th DE is switched from post-turn-state to the turn-state; next all DE are

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Fig. 7. Possible driving circuits for the control-bits of proposed DCDL: (a) signals delayed with different LH/HL delays by using a NAND-based circuit; (b) signals delayed using clock-tree delay ( ; (c) Si delayed with different LH/HL delays by using clock-tree delay and double-clock ip-ops (see Fig. 8).

switched from pass to turn-state (or vice versa) and nally the th DE is switched to post-turn-state. This switching mechanism presents the drawback of being slow and can result in a not simple driving circuit for the DCDL control-bits. Actually, a more detailed analysis of proposed DCDL (see Appendix I), shows that a sufcient condition to achieve a glitch-free operation in proposed DCDL is imposing the following two timing constraints: (2) (3) , , and represents the arrival times where of HL and LH switching of and signals, respectively. In order to show how this timing constraints can be, in practice, realized let us dene two times, and , as follows: (4) By using the above denitions, the two timing constraints (2),(3) becomes (5) (6) By using the above denitions, the Fig. 6 shows the waveforms of the DCDL control-bits for a switching of the DCDL delay, from a control-code to a control-code . The Fig. 6(a) considers the case in which the delay control-code needs to be increased . In this case the relevant timing constraint is (2). This constraint corresponds to imposing that, in Fig. 6(a), the delay is greater than [see (5)]. The Fig. 6(b), on the other hand, considers the case in which the delay control-code needs to be decreased . In this case the relevant timing constrain is (3). This constraint corresponds to imposing that, in Fig. 6(b), the delay is lower than [see (6)]. Please note that, formally, the choice veries this constraint. However, from a practical point of view, realizing a may be not obvious (see Fig. 6). The Fig. 7 shows three possible driving circuits that can be used to generate the control-bits of the proposed DCDL, following the waveforms shown in Fig. 6. By analyzing Fig. 6 it can be noted that signals have to be delayed with respect to signals and that it could be useful to have a different delay for LH and HL transitions. It is also worth to note that, to avoid

glitching of the DCDL, and signals must themselves be glitch-free. By following this reasoning, in all presented driving circuits, it is assumed that signals are generated as output of ip-ops, which, at the same time, both properly time the DCDL considering system-level aspects, and act as deglitching elements. The Fig. 7(a) shows the rst driving technique. In this solution each signal is obtained by using a ip-op followed by a NAND-based circuit which presents different LH and HL propagation delays . In this solution, as shown in the gure, while . By using the denitions (4), we have (7) The two constrains (5) and (6) are therefore veried, both with . A drawback of this solution is the a timing-margin of relatively large complexity, since, for each signal, a driving circuit composed of three NAND gates is needed (in addition to the ip-op). The driving circuit of Fig. 7(b) results simpler than the circuit of Fig. 7(a). In this second solution signals are delayed by delaying the clock signal of the ip-ops. The clock signal delay can be easily obtained by properly designing the clock-tree. As an example, in a standard-cells design ow based on automatic place and route, a different clock-tree delay can be obtained on a ip-op by ip-op bases by using the useful-skew feature of the tools. As shown in Fig. 7(b), we will name the delay difference between the clock signals of ip-ops and ipops. Therefore, by recalling the denitions (4), in this case, we have (8) The two constraints (5) and (6), therefore, becomes (9) According to this equation, the best solution is choosing (10) with respect to This choice results in a timing-margin of both constraints (5) and (6). We can therefore conclude that the driving circuit of Fig. 7(b) is simpler than the circuit of Fig. 7(a), but presents the drawback of a reduced timing-margin.

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Fig. 8. Double-clock ip-op realized by using a sense-amplier-based topology.

The third solution of Fig. 7(c) joins the advantages of the two previous solutions. The circuit of Fig. 7(c) is based on the employ of a special ip-op that we will name double-clock ip-op in the following. This ip-op employs two different clock signals: one clock signal is used to capture the high logic-state of the D input while another clock signal captures the low logic-state of the D input. In the driving circuit of Fig. 7(c), this special ip-op allows to control separately the LH and HL instants of switch of the signals through the delays of the two clock signals and . As in the case of Fig. 7(b), the clock signals delays can be implemented by properly designing the clock-tree. This solution therefore promises a low circuit complexity. In addition, having the possibility to change independently from it is possible to achieve a timing margin as high as desired. As an example, a timing-margin of can be obtained by choosing and . The Fig. 8 shows a possible implementation of a double-clock ip-op. The proposed circuit is a modication of sense-amplier-based ip-op topology [24], [25]. This topology includes a sense-amplier-based rst stage, which is in charge of capturing the input signal state on the clock rising-edge, and a latch stage which provides the two ip-ops outputs ( and ). This last stage is not detailed in Fig. 8 and can be realized by using either a simple NAND-based SR latch (see [24], [25]), or more advanced structures [26][28]. Let us briey illustrate the operation of the novel sense-amplier stage, which provides the double-clock functionality to the circuit of Fig. 8. When the two clock signals and are low, both and nodes are pre-charged to Vdd by means of P3-P6 pMOS. In these conditions the Latch stage maintains the ip-op state. Please note that it is sufcient that one of the two clock signals goes high to disable these two pre-charge pull-up networks. Let us analyze what happens when one of the two clock signals goes high. We will rst assume . In this case, as you can see from Fig. 8, the relevant clock signal is . In fact, only when goes high the pulldown network composed by N1,N2,N6 is activated and node goes to zero, instructing the latch stage to switch to the state . Please note that, once node is gone to zero, N5 device is turned-off, disabling the acquisition of the ip-op state through clock signal. This shows that the LH switching

of the ip-op output is driven by signal. The behavior of the sense-amplier stage is similar in the case in which . In these conditions the discharge path activated within the sense-amplier stage is through devices N3,N4,N5. Since device N4 is controlled by , the relevant clock signal for the HL switching of node is . Please note that when , it could be happen that nodes and are both in a dynamic high state. This condition is generally not a problem since the two clock signals are delayed of few picoseconds, and, therefore, this dynamic state exists only in a limited timing window. However, in applications in which it is expected a strong crosstalk noise in this timing window, a fully static operation can easily be obtained by using two weak keepers on and , similarly to other sense-amplier-based ip-ops [29]. The Fig. 9 shows a transistor-level simulation of the ip-op of Fig. 8. The simulated circuit uses a simple NAND-based SR latch as latch stage. In this simulation the initial ip-op state is . As you can see from the gure, the input D is initially high. On the rising-edge of clock the signal goes low and the ip-op output switch to . The LH switching of the ip-op output is therefore effectively triggered by the rising-edge of signal. Subsequently the input D goes low. Correctly this switching does not change the ip-op state. The input is read by the ip-op on the rising-edge of signal . Only on this rising-edge, in fact, signal switches to zero, by forcing . Please note that, in the simulation of Fig. 9, when goes high with nodes and are both in a dynamic high condition. In this case no particular problem can be observed on the ip-op, also without keepers on and nodes. V. SIZING AND SIMULATION RESULTS In order to verify the effectiveness of proposed solution, the circuits of Figs. 15 and the DCDL of [8] have been designed for a 90-nm CMOS technology, with 1.0 V supply voltage and using standard-Vt devices. The considered length, for all DCDLs, is 64 elements. All NAND-based DCDLs have been sized in order to optimize . All NAND gates present a ratio , where and represent the widths of pMOS and nMOS, respectively. In proposed DCDL the INL is improved by slightly changing the ration of NAND 3 in each DE. This NAND gate, in fact, presents opposite switching for odd and even delay control-codes and is, therefore, responsible for an asymmetry in the minimum delay between these two conditions. This asymmetry is the major contribution to the INL of NAND-based DCDL. Before to evaluate the performances of the DCDLs, a series of simulations to verify the glitching behavior have been performed. To that purpose a simulation testbench has been considered in which the delay control-code is changed by using a test vector of 10 000 random delay control-codes. In these conditions, the circuit of Fig. 1 [12][15] exhibited 5208 glitches.1 The glitching behavior of proposed DCDL has been veried by
1Please note that the glitching probability of NAND-based DCDL [12][15] can be much smaller within DLL circuits since, in this case, during the tracking phase, the coarse delay control-code is generally constant and can vary only for second-order effects like input clock jitter or under temperature variations.

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Fig. 9. Transient simulation of the ip-op of Fig. 8.

TABLE II DCDL PERFORMANCES FOR A 90-nm CMOS TECHNOLOGY (TYPICAL CORNER, 1.0 V, 27 C)

and Fig. 10. Results of glitching simulations of proposed DCDL by varying . The DCDL has been simulated with 10 000 random delay control-codes.

Fig. 11. Simulated INL of the proposed non-inverting DCDL in typical process corner.

considering the waveforms of Fig. 6, and by varying the two delays and . The Fig. 10 shows the obtained simulation results and compares these results with the two timing constraints (5),(6). The graph presents on the two axis the delays and , normalized to the NAND gate propagation delay .A circle and a cross are used to represent simulations in which either no glitching or a glitching behavior is observed, respectively. The analysis of Fig. 10 conrms the correctness of the model developed in Section IV, highlighting that effectively the two constraints (5),(6) represent a worst-case condition. The Table II compares the performances of proposed DCDLs with previously proposed structures for the typical process corner. From the table it can be noted that, as expected, the proposed solutions achieve the same resolution of NAND-based DCDL [12][15], by avoiding its glitching problem. The minimum delay of proposed non-inverting DCDL is very close to of NAND-based DCDL [12][15]. The lowest is achieved by TINV-based DCDL [8]. This solution, however, pays a 58% higher with respect to NAND-based DCDL and a higher power dissipation. Please note that proposed

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TABLE III DCDL PERFORMANCES FOR A 90-nm CMOS TECHNOLOGY (SLOW AND FAST CORNERS)

Fig. 13. Transistor-level simulation of two SSCG (using the architecture of Fig. 12). One SSCG employs the NAND-based DCDLs of [12][15], a second SSCG uses proposed DCDLs. Input clock and output clock frequencies are 500 and 385 MHz, respectively.

Fig. 12. All-digital SSCG proposed in [18].

DCDLs result in a lower power dissipation with respect to TINV-based DCDL [8] since transistor sizing can be much more efcient in proposed circuit with respect to TINV-based DCDL, where the PMOS sizing has to be about 2.5 times larger than nMOS. The analysis of the INL data reported in Table II reveals that proposed sizing approach results very effecting, allowing to achieve a maximum INL as low as 0.3 ps. The Fig. 11 shows the simulated INL of the proposed non-inverting DCDL. Table III reports the performances of proposed DCDL in slow and fast corners. The most interesting data in this table is the maximum INL, which remains very low, in spite of the large delay variability due to PVT variations. This is a conrmation of the validity of proposed sizing strategy. VI. APPLICATION TO AN ALL-DIGITAL SPREAD SPECTRUM CLOCK GENERATOR In order to verify the effectiveness of proposed solutions in a real application the All-digital spread-spectrum clock generator (SSCG) proposed in [18] has been redesigned by using proposed DCDL in UMC 90-nm CMOS technology. For comparison other SSCGs have also been designed by using the TINVbased DCDL of [8] and the NAND-based DCDL of [12][15]. Fig. 12 shows the top-level architecture of the all-digital SSCG following the approach of [18]. The circuit employs a couple of DCDLs ( and ) and an XOR gate to generate a frequency modulated output clock signal with an

instantaneous frequency lower than the frequency of the input clock CLK. The two DCDL and are in charge of generating output clock edges in a timing window of one half clock period length starting from the input clock rising and falling edges respectively (see Fig. 12). A third DCDL , closed in a ring-oscillator topology, and a measurement unit are used to continuously monitor the ratio between the input clock period and the DCDL resolution in order to compensate process, voltage and temperature variations. In the architecture of Fig. 12 each of the two DCDL and is used for one half input clock period. The remaining half clock period is used as a timing margin for DCDL control-bits switching. Consequently the circuit is correctly timed if (11) represent the time needed to settle the DCDL controlwhere bits. In the SSCG architecture of Fig. 12 the DCDL glitching produces output clock glitches also when (11) is veried. As an example the Fig. 13 shows a transistor-level simulation of the outputs of two SSCG circuits. One SSCG uses NAND-based DCDLs designed by using the approach of [12][15], while another SSCG uses the proposed DCDL. The simulation conrms the correct (glitch-free) operation of proposed DCDLs while highlights the problems which arise when a glitching DCDL is used in this application. By comparing the proposed DCDL solution with the TINV-based DCDL, the most relevant drawback of TINV-based DCDL is the increased resolution which

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TABLE IV PERFORMANCES
OF SSCG DESIGNED BY NAND-BASED DCDLS

USING PROPOSED

VALID LOGIC-STATES OF Fig. 14. Simulated absolute jitter histogram of two SSCG designed by using proposed a TINV-based DCDLs. Input clock and output clock frequencies are 500 MHz and 385 MHz, respectively. Modulation is turned-off.

TABLE V th DE GIVEN THE STATE OF th DE

VII. CONCLUSION A NAND-based DCDL which avoids the glitching problem of previous circuit [12][15] has been presented. A timing model of the novel DCDL structure has been developed to demonstrate the glitch-free property of the proposed circuit. As an additional result, the developed model provides also the timing constraints that need to be imposed on the DCDL control-bits in order to guarantee a glitch-free operation. Three different driving circuit for the DCDL control-bits, which verify the given timing constraints, have been also proposed in the paper. The simulation results conrm the correctness of developed model and show that proposed solutions improve the resolution with respect to previous approaches. As example application proposed DCDL is used to realize an all-digital SSCG. The employ of proposed DCDL in this circuit allowed to reduce the peak-to-peak absolute output jitter of more than the 40% with respect to an SSCG using three-state inverter-based DCDLs. APPENDIX DETAILED GLITCHING ANALYSIS OF PROPOSED DCDL This section performs a detailed switching analysis of proposed DCDL. Without loss of generality let us focus on the inverting topology of Fig. 4, and let us consider a switching from a delay control-code to a delay control-code . Please note that the presented analysis remains valid also for the other topology of Fig. 5. A general study of the switching of a delay-line would require the analysis of the commutations of whole circuit. However, in the case of proposed DCDL, in steady-state conditions, the switching, at the DE boundary, will change the state of two signals only: the signal switches from 1 to and the signal switches from to 1. In order to demonstrate the glitch-free operation of the line, therefore, it is sufcient to show that the

Fig. 15. Layout of SSCG designed by using proposed 90-nm CMOS.

NAND-based

DCDL in

translates in increased output clock jitter. Fig. 14, as an example, shows the simulated histogram of the absolute output clock jitter of two SSCG, one designed by using proposed NAND-based DCDL and another using the TINV-based DCDL of [8]. To correctly measure the output jitter component due to only the noise added by the circuit, in both simulations the output frequency modulation is turned-off and the circuits are driven with a 500 MHz clock signal to generate a 385 MHz output signal. From the data reported in Fig. 14 it can be observed that proposed solution results in a peak-to-peak jitter of about 62ps, while the SSCG using TINV-based DCDLs, due to higher delay-line resolution and higher difference between and , presents a more than 60% larger peak-to-peak jitter. Fig. 15 shows the layout of the SSCG designed by using proposed NAND-based DCDL. The circuit performances are summarized in Table IV. The total silicon area occupation of the developed SSCG is only 0.032 mm . By looking to Fig. 15 it can be observed that about the 65% of the area is due to the Modulator, while the three DCDL occupies the 17% of the total silicon area. The SSCG is able to work up to 1.0 GHz clock frequency with a power dissipation of only 28.2 mW. The power dissipation of the three DCDL is as low as 3.3 mW.

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TABLE VI POSSIBLE SWITCHING OF A COUPLE OF SUCCESSIVE DE, BY CONSIDERING THE CONSTRAINTS OFTABLE II

Fig. 16. Timing analysis of a couple of DEs of the proposed DCDL of Fig. 4 in three different cases: (a) case #11 in Table VI; (b) case #14 in Table VI; (c) case #6 in Table VI.

switching of every couple of successive DE is glitch-free in all possible conditions. Each DE can be in one of three possible logic-states (pass, turn, post-turn). In principle, therefore, the analysis of all possible commutations of a couple of DEs will require the study of about cases. In our DCDL, however, there is a relationship between the logic-states of successive DEs. As an example a DE in post-turn-state is always followed by a DE in turn-state. The Table V lists all possible logic-states of th DE, given the logic-state of th DE. By considering the constraints of Table V, only the 20 cases reported in Table VI are possible and need to be analyzed. Each row of this table corresponds to a possible switching condition, by considering the initial state (before the switching) of the th and th DEs and the nal state (after the switching) the th and th DEs. The last column of the table reports comments about the constraints needed to avoid glitching in each case.

Clearly, presenting the analysis of all 20 cases shown in Table VI is out of the scope of this paper. We will limit our attention to three cases that represents a signicant set to understand the behavior and discover the limitations of the proposed circuit. As you can see in the last column of Table VI, some switching result intrinsically in a glitch-free operation, since no constraint is required to avoid glitching. On the other hand, in some other cases, a timing constraint on control-bits is required to avoid glitching. This timing constraints are not surprising since, in Section III, it has been shown that a sufcient condition to avoid glitching is using a three-step switching process. From Table VI it can be observed that, by considering all cases, two different constraints have to be imposed to avoid glitching. In the following we will analyze in more detail a case where no constraint is required and two cases in which the two different constraints are needed, respectively.

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The rst case considered is case #11. In this case a couple of DEs is switched from turn-state to pass-state. This switching is required when the control-code is increased by more than one. The Fig. 16(b) shows the switching analysis of the DEs couple in these conditions. In this gure the logic-state of the th DE input has been named . The state will depend on the input In ( In for even , and for odd ). From the gure it can be observed that no switching is obtained at the output of the NAND 4 of the th DE. In fact one input of this NAND gate switches from to 1, while the other is xed at . Since the output of this NAND gate remains at . The same reasoning applies to the NAND 4 of th DE. The second considered case is #13. In this case the th and th DEs start from turn-state and post-turn-state, respectively, and, both DEs are required to switch to pass-state. Similarly to previous case, again, this switching is required when the control-code is increased by more than one. The Fig. 16(b) shows the switching analysis of the DEs couple, again assuming a generic logic-state at the input of th DE. The gure shows that, in these conditions, in the th DE, both inputs of the NAND 4 switch. The A input of this gate switches from 1 to , and this switching is driven by the low-to-high (LH) switching of . The other input (B input) of the NAND gate switches from to 1, because of the high-to-low (HL) switching of . A glitch can occur at the output of this gate if the B input switches much before the A input. We will assume that no glitch is produced when the difference between the arrival time of A input and the arrival time of B input is lower than the propagation delay of the gate . The timing constraint to impose, therefore, can be written as (12) and represent the arrival time of LH where switching of signals and the arrival time of HL switching of signals, respectively. By simplifying (12), the constraint (2) is found. It is worth to note that, as indicated in Table VI, exactly the same constraint is needed in case #14, where, differently from the considered case #13 [see Fig. 16(b)], the th DE is switched in turn-state. This switching is required when the control-code is increased by one. The nal considered case is case #6 in Table VI, where the th DE is switched from pass-state to turn-state, while the th DE is switched from turn-state to post-turn-state. This switching is required when the delay control-code is decreased by one. The Fig. 16(c) shows the timing analysis of this case. As you case see, similarly to previous considered case, also in these conditions, in th DE, both inputs of the NAND 4 switch. In this case, however, the input B has a switching from 1 to , while the input A switches from to 1. Therefore, to avoid glitching, now B inputs needs to be sufciently faster than A input. By following the same reasoning of previous case, the timing constraint to impose can be written as (13) and represent the arrival time of LH where switching of signals and the arrival time of HL switching of

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[28] A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, A novel high speed sense amplier based ip-op, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 11, pp. 12661274, Nov. 2005. [29] B. S. Kong, S. S. Kim, and Y. H. Jun, Conditional-capture ip-op for statistical power reduction, IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 12631271, Aug. 2001. Davide De Caro (M05SM09) was born in Naples, Italy, on February 9, 1973. He received the M.S. degree in electronic engineering with honors and the Ph.D. degree in electronic engineering and computer science from the University of Naples Federico II, Naples, Italy, in 1999 and 2003, respectively. He has worked in the area of digital integrated VLSI circuit design for the last eight years. Since March 2003, he has been a Researcher with the Department of Electronics and Telecommunication Engineering, University of Naples, where he is working on high performance ip-ops (including both low-power and high-speed structures), VLSI implementation of arithmetic circuits (squarers, xed-width multipliers, Reed-Solomon decoders, Galois-eld multipliers), direct digital frequency synthesizers and digital mixers. He is the author or co-author of over 40 technical papers in international journals and refereed international conferences. Dr. De Caro acted as a reviewer for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I AND II, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, and IEEE TRANSACTIONS ON COMPUTERS.