VLSI PROJECT LIST (VHDL/Verilog)

S.No.
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PROJECT TITLES
A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix-2 Modified Booth Algorithm. An Efficient Architecture for 3-D Discrete Wavelet Transform. The Design of FIR Filter Base on Improved DA Algorithm and its FPGA Implementation. Design of On-Chip Bus with OCP Interface. Design of a Self-Motivated Arbitration Scheme for the Multilayer AHB Busmatrix. Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance Single chip encryptor/ decryptor core implementation using AES algoritham Implementation of IEEE 802.11 a WLAN Baseband Processor Design of Simple Spectrum Analyzer A Dual-Purpose Real/Complex Logarithmic Number System ALU An Efficient Architecture for 2-D Lifting-based Discrete Wavelet Transform. Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers A Spurious-Power Suppression Technique for Multimedia/DSP Applications Design of AES (Advanced Encryption Standard) Encryption and Decryption Algorithm with 128-bits Key Length DDR3 based lookup circuit for high-performance network processing. Multiplication Acceleration Through Twin Precision 32-bit RISC CPU Based on MIPS High Speed Hardware Implementation of 1D DCT/IDCT Efficient FPGA implementation of convolution High Speed VLSI Architecture for General Linear Feedback Shift Register (LFSR) Structures Implementation of a visible Watermarking in a secure still digital Camera using VLSI design Implementation of FFT/IFFT Blocks for OFDM Design and Synthesis of High speed CAM using Xilinx Spartan3E

www.mycollegeproject.com Ph: +91 9490219339, 04023731030 Ameerpet: A-8, 2nd floor, Eureka court, beside Image hospital, Ameerpet, HYDERABAD 73. Dilsukhnagar: 203, Sreemaan Rama Towers, Opp: Kalanikethan , Chaitanyapuri, Dilsukhnagar, Hyderabad-62. Santoshnagar: Opp: Big Bazaar, Santoshnagar X-Roads, HYDERABAD 59.

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Embedded a low area 32 bit AES for image encryption and decryption application Implementation of a visible water marking in a secure still digital camera using VLSI design Design and Implementation of a 64-bit RISC Processor using VHDL Design and Implementation of Wi-Fi MAC Transmit Protocol using VHDL High speed parallel architecture for cyclic convolution based on FNT A ParalleYPipelined Algorithm for the Computation of MDCT and IMDCT Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter A Memory-efficient Huffman Decoding Algorithm Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers A New High-Speed Architecture for Reed-Solomon Decoder Design and Implementation of Efficient Systolic Array Architecture for DWT (Discrete Wavelet Transform) Design and Implementation of 10/100 Mbps (Mega bits per second) Ethernet Switch for Network applications (Verilog) Design and Implementation of USB 2.0 Transceiver Macro-cell Interface (UTMI) (VHDL) Advanced Design Verification methods using VHDL code modification Design and Implementation of Bloom filter using Xilinx ISE A Reusable Distributed Arithmetic Architecture for FIR Filtering Effective Uses of FPGAs for Brute-ForceAttack on RC4 Ciphers USING VHDL Design and synthesis of vhdl Based Cost-Efficient SHA Hardware Accelerators AMBA AHB Bus Protocol Checker with Efficient Debugging Mechanism Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic FPGA implementation of Extended Tiny Encryption Algorithm (XTEA) for Pervasive Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA IMPLEMENTATION OF A FFT/IFFT MODULE ON FPGA: COMPARISON OF

www.mycollegeproject.com Ph: +91 9490219339, 04023731030 Ameerpet: A-8, 2nd floor, Eureka court, beside Image hospital, Ameerpet, HYDERABAD 73. Dilsukhnagar: 203, Sreemaan Rama Towers, Opp: Kalanikethan , Chaitanyapuri, Dilsukhnagar, Hyderabad-62. Santoshnagar: Opp: Big Bazaar, Santoshnagar X-Roads, HYDERABAD 59.

METHODOLOGIES 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique (Verilog) Design and Implementation of Digital low power base band processor for RFID Tags (Verilog) Design and Implementation of Reversible Watermarking for JPEG2000 Standard FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging Design and Implementation of High Speed DDR SDRAM (Dual Data Rate Synchronously Dynamic RAM) Controller (VHDL) Design and Implementation of Lossless DWT/IDWT for Medical Images High Performance Complex Number Multiplier Using Booth-Wallace Algorithm High Speed Parallel CRC Implementation Based On Unfolding, Pipelining and Retiming A HIGH PERFORMANCE VLSI FFT ARCHITECTURE Design of an Bus Bridge between OCP and AHB Protocol (VHDL) Design of Gigabit Ethernet MAC (Medium Access Control) Transmitter Design of an AMBA-Advanced High performance Bus (AHB) Protocol IP Block Design of Data Encryption Standard (DES) Design of Distributed Arithmetic FIR Filter Design of Universal Asynchronous Receiver Transmitter (UART) Design of Triple Data Encryption Standard (DES) Design of 16 Point Radix-4 FFT (Fast Fourier Transform) Algorithm Design of Dual Elevator Controller Design of an ATM (Automated Teller Machine) Controller Design of 8-Bit Pico Processor

www.mycollegeproject.com Ph: +91 9490219339, 04023731030 Ameerpet: A-8, 2nd floor, Eureka court, beside Image hospital, Ameerpet, HYDERABAD 73. Dilsukhnagar: 203, Sreemaan Rama Towers, Opp: Kalanikethan , Chaitanyapuri, Dilsukhnagar, Hyderabad-62. Santoshnagar: Opp: Big Bazaar, Santoshnagar X-Roads, HYDERABAD 59.

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Design of JPEG Image compression standard

Design of Digital FM Receiver using PLL (Phase Locked Loop) Design of 16-bit QPSK (Quadrature Phase Shift Keying) Design of 16-bit QAM (Quadrature Amplitude Modulation) Modulator Design of AES (Advanced Encryption Standard) Encryption Algorithm with 128-bits Key Length Design of RS-232 System Controller Design of Floating-Point Multiplier using IEEE-754 Standard Design of CRC (Cyclic Redundancy Check) Generator

Design and Implementation of OFDM Transmitter Design of 8-bit Microcontroller Design and synthesis of ALU, Verification using Advanced design Verification Technique Design Synthesis and Verification of Simple All Digital FM Receiver using Xilinx FPGA Design, simulation and Synthesis of CPU 8086 using Xilinx FPGA Design and Verification of PCI-Express Bus Design of UART Simulation and Synthesis using Xilinx FPGA Design and Verification of 8 bit Hamming Encoder and Decoder. Design and Verification of Modified Booths Algorithm-Synthesis using Xilinx ISE 5x4Gbps 0.35 Micron CMOS CRC Generator Designed With Standard Cells Design and Verification of CACHE COHERENCE MEMORY. Design and Synthesis of MICRO UART using Xilinx spartan3E IMPLEMENTATION OF ETHERNET TRIMODE MAC
Design Synthesis and Verification of PCI EXPRESS using Xilinx FPGA

www.mycollegeproject.com Ph: +91 9490219339, 04023731030 Ameerpet: A-8, 2nd floor, Eureka court, beside Image hospital, Ameerpet, HYDERABAD 73. Dilsukhnagar: 203, Sreemaan Rama Towers, Opp: Kalanikethan , Chaitanyapuri, Dilsukhnagar, Hyderabad-62. Santoshnagar: Opp: Big Bazaar, Santoshnagar X-Roads, HYDERABAD 59.

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Design and Verification of ADAPTIVE FILTER Design and Synthesis of DIGITAL INSTANTANEOUS FREQUENCY MEASUREMENT PROCESSOR Low Power Register Exchange Viterbi Decoder For Wireless Applications PPI - Programmable Peripheral Interface Triple DES Encryption and Decryption core using Design and Verification of Bluetooth Base Band Controller. Implementation of frame synchronizer using verilog . Design and Synthesis of DIGITAL INSTANTANEOUS FREQUENCY MEASUREMENT PROCESSOR Design and Verification of IMPROVING MULTIPLIER DESIGN BY USING

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IMPROVED COLUMN COMPRESSION TREE AND OPTIMIZED FINAL ADDER IN CMOS TECHNOLOGY

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Double Precision Floating Point Core

www.mycollegeproject.com Ph: +91 9490219339, 04023731030 Ameerpet: A-8, 2nd floor, Eureka court, beside Image hospital, Ameerpet, HYDERABAD 73. Dilsukhnagar: 203, Sreemaan Rama Towers, Opp: Kalanikethan , Chaitanyapuri, Dilsukhnagar, Hyderabad-62. Santoshnagar: Opp: Big Bazaar, Santoshnagar X-Roads, HYDERABAD 59.