Beruflich Dokumente
Kultur Dokumente
October 1998
Features
s High performance CMOS 70 ns access time s Fast turn-off for microprocessor compatibility s Simplified upgrade path VPP and PGM are Dont Care during normal read operation s Manufacturers identification code s Fast programming s JEDEC standard pin configurations 32-pin PDIP package 32-pin PLCC package 32-pin CERDIP package
Block Diagram
VCC GND VPP OE CE PGM Output Enable, Chip Enable, and Program Logic
Data Outputs O0 - O7
Output Buffers
Y Decoder
..
1,048,576-Bit Cell Matrix
.......
X Decoder
DS010798-1
Connection Diagrams
DIP PIN CONFIGURATIONS
27C080 27C040 27C020 27C512 27C256
DIP NM27C010
XX/VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
27C256
27C512
27C020
27C040
27C080
XX/VPP XX/VPP A16 A16 A15 A15 A15 A12 A12 A12 A7 A7 A7 A6 A6 A6 A5 A5 A5 A4 A4 A4 A3 A3 A3 A2 A2 A2 A1 A1 A1 A0 A0 A0 O0 O0 O0 O1 O1 O1 O2 O2 O2 GND GND GND
VCC VCC VCC VCC XX/PGM A18 A18 XX/PGM A V V A A17 XX CC CC 17 17 A14 A14 A14 A14 A14 A14 A13 A13 A13 A13 A13 A13 A8 A8 A8 A8 A8 A8 A9 A9 A9 A9 A9 A9 A11 A11 A11 A11 A11 A11 OE OE/VPP OE OE/VPP OE OE A10 A10 A10 A10 A10 A10 CE/PGM CE/PGM CE CE/PGM CE/PGM CE O7 O7 O7 O7 O7 O7 O6 O6 O6 O6 O6 O6 O5 O5 O5 O5 O5 O5 O4 O4 O4 O4 O4 O4 O O O O3 O O3 3 3 3 3
DS010798-10 Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C010 pins.
Pin Names
A0A16 CE OE O0O7 PGM XX Addresses Chip Enable Output Enable Outputs Program Dont Care (During Read)
A7 A6 A5 A4 A3 A2 A1 A0 O0
5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20
29 28 27 26 25 24 23 22 21
O1 O2 GND O3 O4 O5 O6
Top View
DS010798-3
www.fairchildsemi.com
Operating Range
Range
Commercial Extended
Temperature
0C to +70C -40C to +85C
VCC
+5V +5V
Tolerance
10% 10%
Parameter
Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Standby Current (CMOS) VCC Standby Current (TTL) VCC Active Current VPP Supply Current VPP Read Voltage Input Load Current Output Leakage Current
Test Conditions
Min
-0.5 2.0
Max
0.8 VCC +1 0.4
Units
V V V V
IOL = 2.1 mA IOH = -2.5 mA CE = VCC 0.3V CE = VIH CE = OE = VIL I/O = 0 mA VPP = VCC VCC - 0.7 VIN = 5.5 or GND VOUT = 5.5V or GND -1 -10 f = 5 MHz 3.5
100 1 30 10 VCC 1 10
A mA mA A V A A
Parameter Min
Address to Output Delay CE to Output Delay OE to Output Delay Output Disable to Output Float Output Hold from Addresses, CE or OE , Whichever Occurred First 0
70 Max
70 70 35 30
90 Min Max
90 90 40 35
Min
150 Max
150 150 50 45
Units
ns
Parameter
Input Capacitance Output Capacitance
Conditions
VIN = 0V VOUT = 0V
Typ
6 10
Max
15 15
Units
pF pF
www.fairchildsemi.com
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8) 5 ns 0.45V to 2.4V 0.8V and 2V 0.8V and 2V Input Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level Inputs Outputs
Address Valid
CE
2V 0.8V
tCF
(Note 4, 5)
OE 0.8V tOE
(Note 3) 2V 0.8V
2V
tCE tDF
(Note 4, 5)
Valid Output
OUTPUT
Hi-Z tACC
(Note 3)
Hi-Z tOH
DS010798-4
Note 1: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 A. CL: 100 pF includes fixture capacitance. Note 9: VPP may be connected to VCC except during programming. Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14)
Symbol
tAS tOES tCES tDS tVPS tVCS tAH tDH tDF tPW
Parameter
Address Setup Time OE Setup Time CE Setup Time Data Setup Time VPP Setup Time VCC Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay Program Pulse Width
Conditions
Min
1 1
Typ
Max
Units
s s s s s s s s
OE = VIH
1 1 1 1 0 1
CE = VIL
0 45 50
60 105
ns s
www.fairchildsemi.com
Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14) (Continued)
Symbol
tOE IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT
Parameter
Data Valid from OE VPP Supply Current during Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions
CE = VIL CE = VIL PGM = VIL
Min
Typ
Max
100 15 20
Units
ns mA mA C V V ns
20 6.2 12.5 5
25 6.5 12.75
30 6.75 13.0
0.45
V V
2.0 2.0
V V
Program ADDRESS
2V 0.8V
Program Verify
Address N
t AS DATA
2V 0.8V
Data In Stable ADD N
t AH Hi-Z
Data Out Valid ADD N
t DS
6.25V
t DH
t DF
VCC
12.75V
t VCS
VPP CE
t VPS
0.8V
t CES PGM 2V
0.8V
t PW OE 2V
0.8V
t OES
t OE
DS010798-5
Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 F capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 14: During power up the PGM pin must be brought high (VIH) either coincident with or before power is applied to VPP.
www.fairchildsemi.com
NO
DEVICE FAILED
YES
n = 10?
FAIL
VERIFY BYTE
PASS
LAST ADDRESS ?
YES
NO
FAIL
LAST ADDRESS ?
YES
CHECK ALL BYTES 1ST: VCC = VPP = 6.0V 2ND: VCC = VPP = 4.3V
Note: The standard National Semiconductor Algorithm may also be used but it will have longer programming time. DS010798-6
FIGURE 1.
www.fairchildsemi.com
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 5V in the other three modes.
The EPROM is in the programming mode when the VPP power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 F capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 s pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 s pulse. The EPROM must not be programmed with a DC signal applied to the PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled EPROM.
Read Mode
The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE , assuming that CE has been low and addresses have been stable for at least tACC tOE.
Standby Mode
The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 165 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.
Program Inhibit
Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE all like inputs (including OE and PGM) of the parallel EPROM may be common. A TTL low level program pulse applied to an EPROMs PGM input with CE at VIL and VPP at 12.75V will program that EPROM. A TTL high level CE input inhibits the other EPROMs from being programmed.
Output Disable
The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE).
Program Verify
A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 12.75V. VPP must be at VCC, except during programming and program verify.
Output OR-Tying
Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.
Programming
CAUTION: Exceeding 14V on the VPP or A9 pin will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the 1s state. Data is introduced by selectively programming 0s into the desired bit locations. Although only 0s will be programmed, both 1s and 0s can be presented in the data word. The only way to change a 0 to a 1 is by ultraviolet light erasure.
www.fairchildsemi.com
be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components and even system designs have been erroneously suspected when incomplete erasure was the problem.
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 F bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.
MODE SELECTION
The modes of operation of the NM27C010 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature.
CE
VIL X VIH VIL VIL VIH
OE
VIL VIH X VIH VIL X
PGM
X (Note 15) X X VIL VIH X
VPP
X X X 12.75V 12.75V 12.75V
VCC
5.0V 5.0V 5.0V 6.25V 6.25V 6.25V
Outputs
DOUT High Z High Z DIN DOUT High Z
A0 (12)
VIL VIH
A9 (26)
12V 12V
O7 (21)
1 1
O6 (20)
0 0
O5 (19)
0 0
O4 (18)
0 0
O3 (17)
1 0
O2 (15)
1 1
O1 (14)
1 1
O0 (13)
1 0
Hex Data
8F 86
www.fairchildsemi.com
R 0.025 (0.64)
0.585 (14.86) MAX
0.005 MIN (0.127) TYP 0.225 MAX TYP (5.72) 0.125 MIN (3.18) TYP
Glass Sealant
0.175 (4.45) MAX
86-94 TYP 0.060-0.100 (1.52 - 2.54) TYP 0.090-0.110 (2.29 - 2.79) TYP 0.015-0.021 (0.38 - 0.53) TYP
90 - 100 TYP
0.685 (17.40)
32-Lead EPROM Ceramic Dual-In-Line Package (Q) Order Number NM27C010QXXX Package Number J32AQ
1.64 1.66 (41.66 42.164) 32 17
16
32-Lead Molded Dual-In-Line Package (N) Order Number NM27C010NXXX Package Number
www.fairchildsemi.com
60
( [10.16] )
0.400
-G-
-F-
A F-G S
, ,
0.025 [0.64] Min 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64]
0.050
0.123-0.140 [3.12-3.56]
0.030-0.040 [0.76-1.02]
0.065-0.071 [1.65-1.80]
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
www.fairchildsemi.com