Lahore University of Management Sciences

EE 421 Digital System Design Fall 2012 - 13

Instructor Room No. Office Hours Email Telephone Secretary/TA TA Office Hours Course URL (if any) Course Basics Credit Hours Lecture(s) Lab (per week) Tutorial (per week)

Dr. Shahid Masud 9-323A Friday 0930 to 1030 smasud 8199 8355 LMS page

4 Nbr of Lec(s) Per Week Nbr of Lab(s) Per Week Nbr of Lec(s) Per Week

2 1

Duration 75 mins Duration 3 hours Duration

Course Distribution Core Elective Open for Student Category Close for Student Category COURSE DESCRIPTION

EE Junior / Senior / MS Freshman / Sophomore

This course explains how to go about designing complex, high-speed digital circuits and systems. The use of modern EDA tools in the design, simulation, synthesis and implementation is explored. Application of a hardware description language such as Verilog or VHDL to model digital systems at Behavior and RTL level is studied. Field programmable gate arrays (FPGA) are used in the laboratory exercises as a vehicle to understand complete design-flow of an integrated circuit. Advanced methods of logic minimization and state-machine design are discussed. Design and implementation of digital system building blocks such as arithmetic circuits, datapaths, microprocessors, I/O modules, UARTs, frequency generators, memories etc. is included. BIST and Scan techniques for testing of digital systems are also covered. Laboratories and projects are an integral part of this course that culminates in a comprehensive design exercise.

COURSE PREREQUISITE(S) Microprocessors and Interfacing OR Computer Organization and Assembly Language
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COURSE OBJECTIVES To teach modern techniques of complex hardware design using hardware description language and field programmable gate array devices.

Learning Outcomes Upon completion of the course, students should be able to: i. Understand issues in designing high-speed complex digital systems ii. Understand hardware architectures of basic building blocks of digital systems iii. Undertake design and optimization complex combinational and sequential logic iv. Describe a complex digital system using VHDL v. Simulate and Debug digital systems using EDA tools vi. Implement digital systems on FPGA platforms vii. Analyze and specify timing in high-speed design

Grading Breakup and Policy Lab Exercises(s): 15% (Attendance during lab=4%, Completion of lab tasks=6%, Lab Midterm=5%) Project: 15% (Specifications=2%, Coding and Simulation=5%, FPGA Implementation=4%, Report=4%) Quiz(s): 15% (Around 6) Midterm Examination: 25% Final Examination:30%

Examination Detail Yes/No: Yes Combine Separate: Combine Duration: 75 minutes Preferred Date: Exam Specifications: Calculators allowed Yes/No: Yes Combine Separate: Combine Duration: 120 mins Exam Specifications: Calculators allowed

Midterm Exam

Final Exam

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Lecture / Week 1 / Wk 1 2 / Wk 1 Lab 1 3 / Wk 2 4 / Wk 2 Lab 2 5 / Wk 3 6 / Wk 3 Lab 3 7 / Wk 4 8 / Wk 4 Lab 4 9 / Wk 5 10 / Wk 5 Lab 5 11 / Wk 6 12 / Wk 6 13 / Wk 7 Wk 7 14 / Wk 7 14 / Wk 7 15 / Wk 8 16 / Wk 8 Lab 7 17 / Wk 9 18 / Wk 9 Lab 8 19 / Wk 10 20 / Wk 10 Lab 9 21 / Wk 11 22 / Wk 11 Lab 10 22 / Wk 11 23 / Wk 12 Lab 11 24 / Wk 13 25 / Wk 13 Labs 12 to 14 26 / Wk 14 Course Topics Introduction to digital systems and their design flow Review of combinational logic, logic minimization Introductory VHDL 1 Timing in Combinational Circuits, Hazards and Glitches, Review of sequential logic Lecture - Introductory VHDL - 2 VHDL Coding and Simulation on Modelsim Design using flip-flop and latches, State machines State reduction, timing issues VHDL Behavioural Coding and Simulation Design of Adders and Subtractors, Carry Lookahead Adders Serial Adders, Array Multipliers, Critical Paths VHDL Sequential Coding and Simulation Booth and Radix-4 Encoded Signed Multipliers Further VHDL modeling, parameterization VHDL Design of State Machines Design of dividers and other arithmetic circuits Circuits for Floating Point Implementation Serial Multipliers, Keyboard Scanner, Signed Multiplication of Fractions Due Specifications (up to 2 pages) of Design Exercise Midterm Exam Midterm Exam Programmable logic, PAL, PLA, CPLD Construction and operation of FPGA Midterm Lab Exam Controller design using ASM charts Controller Design for Sequential Multipliers and Dividers FPGA Implementation 1 LFSR, BRM, Function Generators, Design Examples Faults and Testability BIST and SCAN techniques FPGA Implementation 2 Design for test JTAG Advanced VHDL Memories and Register Files Design Example 1 VHDL Synthesis Issues Advanced VHDL / Examples of Digital Systems Design Example 2 Asynchronous Sequential Design Processor Design 1 Design Exercise (Simulation, FPGA Implementation, Demonstration) Processor Design - 2 Readings Roth Roth Lab 1 Roth Lab / Quiz

Lab 2 Roth Roth Lab 3 Roth Roth Lab 4 Notes Lab 6 Roth Roth Roth

Roth Roth Lab Exam Roth Roth Lab 8 Notes Roth Lab 9 Roth Lab 10 Zwolinski Notes Lab 11 Zwolinski Roth Design Exercise Roth
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27 / Wk 14 Digital Design Case Study Due Final Report and Submission of Design Exercise Final Exam Week 15 Notes

Lab Exercises: Lab / Week 1. / Wk 1 2. / Wk 2 3. / Wk 3 4. / Wk 4 5. / Wk 5 6. / Wk 6 Wk 7 7. / Wk 8 8. / Wk 9 9. / Wk 10 10. / Wk 11 11. / Wk 12 Wk 13 - 14

Lab Topics Structural and Modular VHDL coding Simulation and testing of VHDL code Behavior Design Examples, coding and simulation RTL Design, coding and simulation FSM in VHDL, coding and simulation VHDL Design Examples Lab Exam VHDL Simulation Xilinx Synthesis - FPGA implementation of design 1 Xilinx Synthesis - FPGA implementation of design 2 Optimize logic design (speed, area), placement and routing Design Exercise and further FPGA experiments Advanced VHDL Concepts, simulation and synthesis Design Exercise including FPGA Implementation

Readings

Textbook(s)/Supplementary Readings Text book: 1. Principles of Digital Systems Design using VHDL, Charles H. Roth, Lizy K. John, CEngage Learning, 1998, Indian Reprint 2008 Supplementary Reading: 1. Digital Electronics and Design with VHDL, Volnei A. Pedroni, Elsevier Publishers, 2008 2. Digital System Design with VHDL, Second edition, Mark Zwolinski, Pearson Education, 2004

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