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Outputs
1 0 1 0
S
1 0 0 0 1
R (reset)
Q
(a) Logic Diagram
S (set)
R
0 0 1 0 1
2
Q
0 0 1 1 0
Q
1 1 0 0 0
1 0
S (set)
Q
(a) Logic Diagram
1 0
S
1 1 0 1 0
R (reset)
R
0 1 1 1 0
Q
0 0 1 1 1
Q
1 1 0 0 1 (after S=0, R=1) (after S=1, R=0)
R CP S
Q S
1
R Q(t+1)
0 1 0 1 0 1 0 1 0 0 1 Indeterminate 1 0 1 indeterminate
0 0 0 0 1
0 0 1 1 0 0 1 1
1 1 1
Q R
Q S
Q 0 1
SR 00
X 1
R
1 1
Q(t+1) = S+RQ SR = 0
CP
(b) Graphical Symbol
Clocked RS flip-flop
D CP
5
S
3 1
Q D Q(t+1)
0 0 1 1 0 1 0 1 0 1 0 1
Q 0 1
1 1
Q(t+1) = D
CP
(b) Graphical Symbol
Clocked D flip-flop
K CP J
(a) Logic diagram Q K Q J
Clocked JK flip-flop
Q J K Q(t+1)
0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0
Q 0 1
JK 00
J 01 11 10
1 1
K
1 1
CP
1 1 1 1
Q(t+1) = JQ+KQ
T CP
Clocked T flip-flop
Q
(a) Logic diagram Q Q T
Q T Q(t+1)
0 0 1 1 0 1 0 1 0 1 1 0
Q
0 1
T 0
1 1
Q(t+1) = TQ+TQ
CP
Positive Pulse
Negative Pulse
Positiveedge
Negativeedge
Negativeedge
Positiveedge
S Master
S Slave
CP MASTER-SLAVE FLIP-FLOP
Y Q
Y
5 7
K CP
S R Q Q
1 0 1 1 1 0 0 1 0 1 1 0 1 0 1 1
1 0 1 0
(NC) (NC)
Q Q
S=R=1 for steady state values When S=1 & R=0 : Q=0 When S=0 & R=1 : Q=1
CP
3
0 1 S CP=0
1 1 S
CP=0
3
R D=1
D=0
(a) With CP = 0
0 1 S CP=1
1 0 S
CP=1
3
R D=1
D=0
So Q = 0 & Q = 1
So Q = 1 & Q = 0
(b) With CP = 1
Direct Inputs Asynchronous Function Table Inputs Outputs Clear Clock J K Q Q 0 1 1 1 1 x x 0 0 1 1 x 0 1 0 1 0 1 No Change 0 1 1 0 Toggle
Clear
Q K
Q J
CP
x A B
x A x A x B x B
CP
R Q
B B
A A
State table for circuit Present State AB 00 01 10 11 Next State x=0 x=1 AB AB 00 01 11 01 10 00 10 11 Output x=0 x=1 y y 0 0 0 0 0 1 0 0
Q(t+1) = S+ RQ SR=0
Bx A 0 A 1 00 01 11
B 10 A 0 A 1
Bx 00 01 11
B 10
1 1
x A(t+1) = Bx+(B+x)A (a) A(t+1) = Bx + (Bx) A A(t+1) = S+ RA
1 1
x
x A B
x A x A x B x B
CP
R Q
B B
A A
B y B C x B C x
CP
A A
The problem of statereduction is to find ways of reducing the number of states in a sequential circuit without altering the inputoutput relationships. 0/0
0/0
0/0
minimizes the cost of circuit by reducing flipflops & gates. Consider the input sequence 01010110100 starting from present state a.
a
1/0
c
0/0
d g
0/0 1/1 1/1
f
1/1
1/1
State diagram
d 0 0 e 1 1 f 1 1 f 0 0 g 1 1 f 0 0 g 0 0 a
a 0 0
a 1 0
b 0 0
c 1 0
State Table Present State a b c d e f g Next State x=0 x=1 a b c d a d e a g a f f f f Output x=0 x=1 0 0 0 0 0 0 0 0 0 0 1 1 1 1
d d
0 0 0 0
f f
a 0 0
a 1 0
b 0 0
c 1 0
d 0 0
e 1 1
d 1 1
d 0 0
e 1 1
d 0 0
e 0 0
Reduced State Table Present State a b c d e Next State x=0 x=1 a b c d a d e d a d Output x=0 x=1 0 0 0 0 0 0 0 1 0 1
0/0 0/0
101 e
001 a
1/0
010 b
m flip-flops can represent up to 2m distinct states (i.e. if m=3, 8 states => 000111) For five states, 3 flipflops are required. Fewer states do not guarantee a saving in the number of flip-flops or number of gates.
1/1
1/0 0/0
100 d
1/1
Three possible binary state assignments State a b c d e Assignment 1 001 010 011 100 101 Assignment2 000 010 011 101 111 Assignment3 000 100 010 101 011
Reduced State Table with binary assignment 1 Next State Output Present State x=0 x=1 x=0 x=1 001 001 010 0 0 010 011 100 0 0 011 001 100 0 0 100 101 100 0 1 101 001 100 0 1
(a) RS
Q(t) 0 0 1 1 Q(t+1) 0 1 0 1 D 0 1 0 1 Q(t) 0 0 1 1
(b) JK
Q(t+1) 0 1 0 1 T 0 1 1 0
(c) D
(d) T
Design the clocked sequential circuit using JK flip-flops from the given state diagram.
0 00 1 1 10 0 1 11 0
01
State diagram
Next State Present State A 0 0 1 1 B 0 1 0 1 A 0 1 1 1 x=0
State Table
Output x=1 B 0 0 0 1 A 0 0 1 0 B 1 1 1 0
Q(t) 0 0 1 1
Q(t+1) 0 1 0 1
J 0 1 X X
K X X 1 0
Excitation table
Inputs of Combinational Circuit Present state A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Input x 0 1 0 1 0 1 0 1 A 0 0 1 0 1 1 1 0 B 0 1 0 1 0 1 1 0 JA 0 0 1 0 X X X X Next state KA X X X X 0 0 0 1
A Q K
A Q J Q K
B Q J CP
KA A A B B
JA
KB
Combinational Circuit
x External Inputs
Bx A 0 A 1 00 01 11
B 10
Bx
B 01 11 10
1 X X
x
A 0 1
00
X 1
JA = Bx
Bx A 0 1 00 01 11 B 10 Bx A 0 1 00
KA = Bx
B 01 11 10
1 1 JB = x
X X
X X
X X
X X 1
KB = A . X = Ax + Ax
A B
Q K JA = Bx KA = Bx JB = x KB = A Q J Q K Q J
CP
x
Q: Design a sequential circuit using state table with assignment 1 employing RS flip-flops.
Excitation table
Present state
A 0 0 0 0 0 0 1 1 1 1 B 0 0 1 1 1 1 0 0 0 0 C 1 1 0 0 1 1 0 0 1 1
Input
x 0 1 0 1 0 1 0 1 0 1
Next State
A 0 0 0 1 0 1 1 1 0 1 B 0 1 1 0 0 0 0 0 0 0 C 1 0 1 0 1 0 1 0 1 0 SA 0 0 0 1 0 1 X X 0 X
Flip-flop Inputs
RA X X X 0 X 0 0 0 1 0 SB 0 1 X 0 0 0 0 0 0 0 RB X 0 0 1 1 1 X X X X SC X 0 1 0 X 0 1 0 X 0 RC 0 1 0 X 0 1 0 X 0 1
Output
y 0 0 0 0 0 0 0 1 0 1
Q(t) 0 0 1 1
Q(t+1) 0 1 0 1
S 0 1 0 X
R X 0 1 0
Cx AB 00 00 x 01 A 11 10 01 11
C 10
Cx AB 00 00 x 01 01 11
x 1 1 x x x x x
x x
x x
Cx 10 AB 00 x 00 x
01
11
10
x x
1 x x
x x
x x
01 11
x x
x x
11 10
1 10
RA=Cx Cx 10 AB 00 SB=ABx Cx 10 AB 00 01 11 10
SA=Bx
Cx AB 00 01 11 10 AB 00 01 11 00 x x x x x 01 1 1 1 1 11 x 10 x
01 11
x x x x
x x
x x x x
1 1 x 1 x
x x
x x 1
y=Ax
x x
x x
x x
x 1
x
SC=x
x 1
RB=BC+Bx
RC=x
Logic diagram
y S x Q A A
R Q
Q B
R Q
Example: Analyse the sequential circuit and determine the effect of unused states.
Unused states
A B C X
000 110 111 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1
0/0
001
0/0 1/1
0/0
011
1/0
101
The circuit is self-starting and self-correcting since it eventually goes to a valid state from which it continues to operate as required.
1/0 0/0
100
110
0/0
111
010
110
011 100
101
A0 0 1 0 1 0 1 0 1 A1 10
01
1 1
11
1 1
10
01
1 1
11
1 1
10
1 1
TA1 = A0
TA0 = 1
A1
Q T
A0
Q T
CP
1
Q: Design a counter that counts a repeated sequence as shown below using JK flip-flop
Counting Sequence : 0, 1, 2, 4, 5 and 6
Q(t+1)
0 1 0 1
J
0 1 X X
K
X X 1 0
x x
BC 00
1 x
JA = B 10
x x
x 1
KA = B 10
x
01
x
11
A 0 1
1 1
BC 00 01
x x
11
x x
JB = C 10
A 0 1
BC 00
01
11
x x
BC 00
x x
01
x x
11
1 1
KB = 1 10
A 0 1
1 1
x x
x x
JC = B
A 0 1
x x
1 1
x x
x x
KC = 1
A B Q K Count Pulses Q J Q K
Q J
Q K
Q J
000
111
001
110
Using K-maps JA = B KA = B JB = C KB = 1 JC = B KC = 1
010
101
100
Input x
0 1 0 1 0 1 0 1
Next State A
0 0 1 0 1 1 1 0
B
0 0 1 1 0 0 1 1
B
0 1 0 1 0 1 1 0
DA = AB + Bx DB = Ax + Bx +ABx
Bx 00 0 1
1
01
1
11
10
1 1
A 0 1
Bx 00
01
1 1
11
1
10
1
Q 0 0 1 1
Qt 0 1 0 1
D 0 1 0 1
DA = AB + Bx
DB = Ax + Bx +ABx
D x
A A
B B
DA = AB + Bx DB = Ax + Bx +ABx
CP
Logic diagram
Example # 2 : Design a sequential Circuit as per given conditions using D flip flops:A(t+1) = C + D B(t+1) = A C(t+1) = B D(t+1) = C So DA = C + D DB = A DC = B DD = C
Q D
Q D
Q D
Q D
CP
Example # 3:- Design a Sequential Circuit with JK flip-flops to satisfy the given equations:State Equations [Characteristic equation of JK flip-flops = Q(t+1) = (J) Q + (k) Q ]
A(t+1) = ABCD + ABC + ACD + ACD B(t+1) = AC + CD + ABC C(t+1) = B D(t+1) = D Algebraic manipulations for matching characteristic equation of JK flipflops: A(t+1) = (BCD + BC) A + (CD + CD)A = (J)A + (K) A J = BCD + BC = BC ------------(i) (K) = (CD +CD) = CD + CD------(ii) B(t+1) = (AC +CD) + (AC)B B(t+1) = (AC + CD)(B+B) + (AC)B = (AC + CD) B + (AC + CD + AC) B = (J)B + (K) B J = AC + CD -------------(iii) (K) = (AC + CD + AC) = AC + AD ---------- (iv)
C(t+1) = B = B(C + C) = BC + BC = (J) C + (K) C J = B ----------(v) (K) = B -------(vi) D(t+1) = D = 1.D + 0.D = (J) D + (K) D J = K = 1 J = 1----------(vii) (K) = (O) = (K) = 1-----------(viii) JA = BC ----------(i) KA = CD + CD-----------(ii) JB = AC + CD --------(iii) KB = AC + AD -------(iv) JC = B ---------(v) KC = B ----------(vi) JD = 1 ----------(vii) KD = 1 ------------(viii)