An Integrated Automatic Test Generation and Executing System

Huxun Chen#1, DeQing Chen*2, Jinlin Ye#3, Weizhou Cao#4, Lei Gao#5
Beijing, HeroTec Test & Control Ltd. 1 Huayuan Rd., Haidian, Beijing 100191, China 1 huxunchen@yahoo.com.cn 3 jye@mtcs.com.cn 4 cao.mail@gmail.com 5 lukegao@gmail.com * Microsoft Corp. 1 Microsoft Way, Redmond, WA 98052, USA 2 lukechen@microsoft.com
Abstract This paper presents an integrated Automatic Test Generation (ATG) and Automatic Test Executing/Equipment (ATE) system for complex boards. We developed an ATG technique called Behavior-Based Automatic Test Generation technique (namely BBATG). BBATG uses the device behavior fault model and represents a circuit board as interconnection of devices. A behavior of a device is a set of functions with timing relations on its in/out pins. When used for a digital circuit board test generation, BBATG utilizes device behavior libraries to drive behavior error signals and sensitize paths along one or multiple vectors so that a heavy and complicated iterating process can be avoided for sequential circuit test deductions. We have developed a complete set of test executing software and test supporting hardware for the ATE which can use the BBATG generated test data directly to detect behavior faults and diagnose faults at the device level for complex circuit boards. In addition, we have proposed and implemented useful technique, especially Design For Testability (DFT) [1][2] application technique on the integrated system, so the test generating/executing for complex boards with VLSI can be further simplified and optimized. Keywords Behavior Fault Model, Detect Test, Diagnosis Test, Automatic Test Generation (ATG), Automatic Test Executing/Equipment (ATE), Design for Testability (DFT) application, JTAG Device (Device with JTAG circuit).
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Random ATG is less complex than deterministic ATG. Random ATG may be able to quickly generate tests initially, but it would be very inefficient to generate more tests to achieve higher coverage [4]. Furthermore, in sequential circuits, random vectors may fail to initialize a circuit when specific initialization sequences are required. Control inputs such as clock and reset lines have much more influence on circuit behavior than other inputs. It is also possible that random vectors may create race conditions and oscillations, and thus such vectors have to be discarded. 2) Deterministic ATG Deterministic ATG can be applied to both combinational circuits and sequential circuits. Earliest digital circuit test generation systems are almost exclusively for combinational circuits, such as D-algorithm [5], PODEM algorithm [6], and FAN algorithm [7]. They use stuck-at fault model and are gate-based. In theory, sequential ATG can be treated as an extension of combinational ATG [4] by adding a dimension of time to the testing vector. In practice sequential ATG is in orders of magnitude more complex than combinational ATG. There are some algorithms and products for sequential ATG. Timeframe expansion algorithms convert time domain into space domain so that combinational ATG can be used. Examples include Extended BackTrace (EBT) Algorithm [8], Back Algorithm [9], ESSENTIAL Algorithm [10], HITEC Algorithm [11], and etc. Their test deductions are iteratively performed. Sequential circuits are transformed to iterative logic arrays by unrolling the Huffman model and applying D-algorithm or PODEM, path sensitizer, etc. Stuck-at fault model is defined at the level of simple gates' pins. An ATG that uses stuck-at fault model requires gate-based circuit descriptions for devices. With rapid developing of IC, the number of gates inside a device is growing exponentially and circuit logic structures have become more and more complex. Especially, their sequences have been increasing. Consequently, most ATG using stuck-

I.

INTRODUCTION

A. Background Circuit boards test is crucial to digital system design, manufacture, maintenance, and repair. There are many researches on Automatic Test Generating (ATG) theory and techniques in the last century [3]. Two types of ATG random ATG and deterministic ATG have been researched for circuit boards. 1) Random ATG

978-1-4244-9363-0/11/$26.00 2011 IEEE

at fault model cant deduce tests for complex circuit boards with LSI/VLSI. And consequently, there are two following techniques have been researched and applied. 3) Test Simulation Test simulation programs can deduce circuit output response from a circuit input stimulus and can calculate which faults would be detected by this stimulus. The successful example of test simulation is LASAR simulation software made by Teradyne [12]. The insufficiency of test simulation programs is that they cant select or generate required input stimulus, this work would need users to try a long time tediously. 4) Design for Testability (DFT) Design for Testability (DFT) [13][14] requires formulating test strategy at the time of design has become increasingly important. DFT during the design phase can considerably mitigate the test generation problem. Built-In Self Test (BIST) [1] and Boundary Scan (JTAG/IEEE1149.1) [2] are two typically DFT techniques. Boundary Scan has provided the possibility of rapidly testing the connectivity of a circuit board. Unfortunately, most SSI/ MSI devices and some LSI/VLSI devices have no boundary scan circuits so that completely tests of connectivity couldnt be implemented for most circuit boards. Additionally connectivity testing cant test device inner functions completely and many devices have no BIST. B. Our Contributions This paper presents an integrated Automatic Test Generation (ATG) and Automatic Test Executing/Equipment (ATE) system. The system has the following distinct features: 1) We developed an ATG technique called BehaviorBased Automatic Test Generation technique (BBATG). Unlike most other deterministic ATG using the stuck-at fault model, BBATG use the device behavior fault model which can completely describe functions and timing relations for a combination or sequence device, and then neednt decompose devices to gate-level descriptions. 2) BBATG treats a device as a black box and studies its behavior through the relationship between its inputs and outputs. A devices behavior model is implemented correspondingly as functional representation with the associated timing relations between its inputs and outputs. At the same time, we use the structural model to describe circuit board as an interconnection of devices. Thus, we can study and apply a deterministic algorithm to deduction tests for complex circuit boards. 3) BBATG Test deductions are supported by reusable device behavior libraries. The libraries are implemented using a proprietary BBATG Test Description Language. Currently, we have

implemented libraries for most TTL devices and for some common LSI/VLSI. Users can add their own device test groups with the help of BBTDL and device manuals. We must emphasis that the creation of device test groups is a one-time effort for each device and the device test groups can be reused in test deductions in different boards/systems. In addition, BBATG can apply DFT technique. In that case, test deductions neednt be sustained by JTAG device (device with JTAG circuit) test groups (see below). 4) We have developed techniques to simplify and optimize test generating/executing. With the DFT application technique, BBATG treats JTAG device I/O pins as board/system initial I/O pins without creating JTAG device test groups. BBATG with DFT application would become more useful for generating tests for complex digital boards as more VLSI integrating with JTAG circuit. 5) Our system has integrated an intelligent ATE which can directly use the BBTAG generated test data to test boards. Especially, its JTAG test interface (and native testing software) allows the use of test data generated by BBATG with DFT application to test complex VLSI boards. In this paper, Section II discusses the main principles of BBATG technique. Section III summarizes BBATG optimization techniques. Section IV describes the Automatic Test Executing/Equipment (ATE) system. We conclude with a discussion in Section V. II. BBATG TECHNOLOGY

In this section, we described the three main components behind the BBATG technique: 1) a behavior-based device model; 2) a set of reusable device test libraries; 3) an automatic test deduction algorithm. A. Behavior-Based Device Model In this paper, we use a device model and a circuit board model similar to the one described by Rooster [15]. 1) Circuit board model: A circuit board is defined as a system of an interconnection of components. In such a structural model, devices are at the lowest level and consequently are considered as primitive components. In the following discussions, we will dont distinguish system and circuit board. 2) Device model: A device is defined as a black box whose behaviors can be represented by the relationship between its inputs and outputs. Accordingly a devices behavior model is described as its functional representation with the associated timing relations between the inputs and outputs. Input pins of a device may take 0, 1, x and its output pins may take 0, 1, x ,u, where x represents

arbitrary value (may be 0 or 1) and u represents unknown value. 3) Device Behavior fault model: A device has a behavior fault when its behavior fails. In system test deductions, we only review device behavior faults. Wire faults between individual devices in a system are attributed as faults at the connecting devices. In order to detect and diagnose fan-in/fan-out faults at system initial input/output pins, users can treat each system connector interface as one device so that wire faults are converted to device faults. 4) Behavior Error Signal: In BBATG, a behavior error signal is presented as an H or L. H represents 1 when the signal is normal and 0 when fault; L implies 0 when the signal is normal and 1 when fault. 5) Single Behavior Fault Assumption: During the course of an error deduction in system we assume that the behavior fault in consideration is only generated by the H/L error of the original device. The devices other behaviors and behaviors of other devices are normal. The single behavior fault assumption can greatly simplify the test deduction process and it is suitable for most circuit board instances. If ATE uses probe-guided fault locating technique and one-by-one fault repairing method in testing procedure, this assumption can still hold for most diagnosis of multiple faults. 6) Detection Test and Diagnostic Test We consider two kinds of test tasks: detection test and diagnostic test. A detection test is to find if a circuit has a behavior fault. A diagnostic test is to locate the behavior fault inside the circuit. Since devices are primitive components, we discuss only their detection tests. For circuit boards, we will discuss both detection test and diagnostic test. A circuit test is the set of its input stimulus and its expected output response, as described in the following formula: T={X, Z} (1)

set with length s, for example, (X1, Z1), (X2, Z2) (Xs, Zs). B. Device Behavior Libraries For deducing tests of a circuit board on device behavior level, we have designed "Device Test Description Language (BBTDL) and created Device Behavior Libraries. Currently, we have implemented libraries for most TTL devices and for some common LSI/VLSI. Users can add their own device test groups with the help of BBTDL and device manuals. Device Behavior Libraries consist of the Device Error Library and the Device Transfer Library. 1) A Device Error Library consists of various device error groups that provide H/L error sources for circuit board test deductions. Each error group contains behavior error patterns (namely ERR) for a single device and is obtained by traversing all detection tests of the devices behaviors. Each group maintains the following data set: (1) a pin array to represent the relationships of the pin reference names, their device pin numbers, their positions in test vectors, and its I/O type ; (2) initialization vector arrays for the device behavior tests if necessary; (3) one or more test vector sequence for each testable device behavior. A simple error group example is shown in Example1. Example 1: The error group for TTL 7400A is as the following:
ERR_7400A (){ PIN[]={IN1-1-0-I, IN2-2-1-I, OU-3-2-O}; NO0[]={0xH}; NO1[]={x0H}; NO2[]={11L;} }%

TTL 7400A is a NAND combination gate. Its behavior faults are the same as its stuck-at faults. 2) A Device Transfer Library contains various device transfer groups that contain transfer functions (namely TRN) of each device. These TRN support H/L behavior err signals and sensitizing paths driving in circuit board test deductions. Similar to the device error group, each transfer group is described with a pseudo-C function. It starts with a PIN array like that of the error group, followed by initialization arrays if necessary, and individual TRN (transfer function). Each TRN contains a PROC (process) description and FUNC (function) descriptions. A PROC uses one or multi-vectors to describe the input/output variable timing relations and a FUNC uses equations or conditional sentences to describe the input/output variable functionality. An example is shown in Example2. Example 2: The transfer group for IDT-72V293 data write/read is:

T is a test, X is the test stimulus applied on the inputs, and Z is the expected output response on the outputs. If there is a fault in the circuit, the output response would change from Z to W, and ZW (2)

In another word, if we find there are differences between the actual output and the expected output, we say T can detect the fault in the circuit. For a combinational circuit, T is a one-dimensional vector. For a sequential circuit, T might be a sequence vector

TRN_IDT72V293(){ PIN[]={ MRC-78-0-I, WCLK-80-1-I, OE-59-2-I, RCLK-62-3-I, D0-29-5-I, Q0-31-8-O; }; DQTR(){ PROC[]={ 1[#010_111](WCLK)XX[DSR_0S](D0)U, 1X(OE)[#010_111](RCLK)X[DSR_0S](Q0) ; } FUNC{ (Q0_0-R)=(WCLK_1)(D0_0)(RCLK_1)(OE_0), (Q0_1-R)=(WCLK_1)(D0_1)(RCLK_1)(OE_0); } }}% //DBUS [0:17] //QBUS[0:17]

current device specified by system wire table. Depending on FUNC representations, PROC vector-bit variables are substituted and H/L will be propagated to the output of the current device. During the process of err H/L signal driving, whenever BBATG finds that at least one of the fan-outs arrives at the system initial output, it will conclude that forward driving has succeeded.

In the example, for simplifying test deduction we use bus patterns replacing and vector expressing formats (Section III), hence the bus vector bits (D and Q) have a [busname_type] prefix, and the WR and RD vector bits has [# 1/0 sequence] prefix. IDT72V293 in the above example is a FIFO memory device with clocked read and write controls and a flexible bus-matching x18/x9 data flow. In the TRN (DQTR), PROC presents the test vector sequence as a data transfer from the D input pin to the output pin Q. The first expressed vector of its 3 vectors writes the input D into IDT72V293, and the second expressed vector reads the saved data to the Q output. In the FUNC, 2 expressions describe required input variable values for Q getting 1 or 0. C. System Test Deduction Figure 1. shows the flow chart of the BBATG's system test deduction process. When started, BBATG first read system input file, and accordingly pick up device ERR groups and device TRN groups from the device test libraries. The system input file contains system wire table, system interface table, initial data, selected ERR listing, preset data, and etc. After accomplishing pre-process, BBATG will perform ERR test deductions one by one. As same as most deterministic ATG, the system test deduction by BBATG is heuristic. It includes forward err H/L driving stage and backtrack driving stage. When inconsistent justification results happen, a backdating process would be performed. 1) Forward H/L driving Forward H/L driving starts with reading a devices H/L ERR from a device error group. BBATG then applies device transfer groups to drive forward the H/L err signal to the system initial outputs. The H/L output from previous stage device must be driven to the corresponding inputs of the

Figure 1. BBATG Test Deduction Flow

2) Backtrack driving When forward H/L driving finishes, BBATG would start backtrack the values for every input pins of the ERR device and the H/L sensitizing path except arriving at the system initial inputs. BBATG reuse the device transfer groups in backtrack driving process. Selecting a TRN of the previous stage device, BBATG conversely compute the required input variable values according to the FUNC representation, and then justify it with their previous specified values. After variable values substituting and justifying, the PROC would get some 0 or 1 vector-bit values which must backtrack further. The process will continue until every 0 / 1 values arriving at the system initial inputs. 3) Backdating On the process of forward H/L driving and backtrack driving, when inconsistent justification results happen, BBATG should select another TRN or backdate to the past device, then it can select different sensitive value or an alternative path. This backdating process would continue until it has backdated at the H/L error device. If all trials

fail, then the device behavior error cannot be tested in the system. III. BBATG OPTIMIZATION TECHNIQUES We have developed techniques to simplify and optimize BBATG test deductions as following: A. Eliminating System Feedback Wires We call the feedback wires among devices system feedback wires. To simplify system test deductions, we assume there is no system feedback wire in the system. In the preprocess phase, system feedback wires are identified and removed by some methods. First we can absorb system feedback wires into suppositional devices. This is feasible because BBATG permit inner circuits of a device may have complex sequence relation. Secondly we have developed a program that can deduce the initial vector sequence for a complex sequence system having system feedback wires. Due to the limit of space, we will leave the details to be addressed elsewhere. B. Bus Test Pattern Replacing Buses are frequently used to transfer data and perform functional operations. The large number of messages and multifarious behaviors on bus make it very difficult for system test deduction. However, since every pin in a parallel bus has the same dependent relation with other device pins in the system, we can treat an entire parallel bus as a none-bus type pin or wire in the system test deduction process. In postprocess stage, BBATG will automatically replace it back with the actual bus test patterns (such as using scan 0 and scan 1 patterns for a data bus). Therefore we have designed the description format of bus test pattern library in BBTDL. C. Test Vector Expressing Technique BBATG maintains two test vector sequence formats: test vector sequence spread format and test vector sequence express format. Every vector ranges in order for first format and more vectors are expressed on one row for second format. In the previous Example 2, we adopted the second format. The first format can be immediately applied by ATE for testing. The second format can highly simplify BBATG test deductions. D. Circuit Initializing In LSI/VLSI application, users would have to first set LSI/VLSI into an initial condition by creating modes of control or operation (or both). When generating tests for these devices, creating modes of control/operation requires us to analysis LSI/VLSI inner circuit structure that would be impossible for users. To resolve the trouble, we have designed INI behavior sentence in device ERR/TRN groups. Users can describe device initial conditions in INI sentence according to device manuals. In addition, we also have designed the system-level initial module SINI in the system input file. Similar with

LSI/VLSI, initial conditions would be required in complex systems. When the instance appears, we first apply BBATG to generate tests for initial conditions according to the system circuit structure, and then add the resulting tests into SINI module for later system test deduction calling. E. DFT (JTAG and BIST) Application As depiction in Section I, only relying on JTAG and BIST is difficult to completely test most circuit boards. But using our technique with JTAG and BIST, the difficulty could be resolved, and the test deductions of system with VLSI devices can be greatly simplified.

Figure 2. JTAG and BIST Applying

A practical scheme is shown in Figure 2. where the VLSI device has JTAG and other devices have no JTAG. We use BBATG for the system consisting by SSI, MSI, LSI, system connectors and I/O pins of VLSI to generate tests first. Here I/O pins of VLSI are treated as system initial O/I pins, and ATE will use JTAG interface sending test stimulus to output pins of VLSI and receiving system responses from input pins of VLSI. After that, we can use JTAG or other pins/bus of VLSI to start the BIST of VLSI to perform the VLSI kernel self testing. Especially, in the scheme we neednt develop ERR/TRN groups for JTAG VLSI. In addition, if the VLSI hasnt BIST, users can adopt absent judge method at repairing system course. Namely, ATE first performs other tests for the system besides the VLSI kernel, and then according to the test result to judge the VLSI kernel if or not has faults. Example 3: Test Deductions for a Demo System Here we discuss a test generation example shown in Figure 3. The functionality of the demo system is to compare values on two data buses. The system uses 7 devices an Intel 8255 LSI bus controller (4U5), a data transceiver 74245 (3U4), a bus comparator 74688 (5U6), a decoder 74138 (3U3), two logical gates (1U1A and 2U2A), and a system connector (0J26).

COMP(){ PROC[]={(G)[8TR_0S](P)[8TR_0S](Q)(PQ);} FUNC{ (PQ_0-T)=(G_0)(P_1)(Q_1), (PQ_0-T)=(G_0)(P_0)(Q_0), (PQ_1-T)=(G_0)(P_1)(Q_0), (PQ_1-T)=(G_0)(P_0)(Q_1), (PQ_1-T)=(G_1)(P_X)(Q_X) ; }} }%

BBATG selects the first FUNC expression and drives the H to 5U6-19 (PQ) at L. After variable values substituting, the PROC vector becomes:
PROC[1]={0 [8TR_0S]H[8TR_0S]1L;} // (2) After arriving at the system initial output, the forward driving terminates. Now BBATG will start backtrack driving for every 1 or 0 in (1) and (2). Especially for 5U6-18(Q) which connects to 4U5-25(8255 PB OUT), BBATG uses the 8255-PB TRN to drive the value 1 to input pins of the 8255. The 8255-PB TRN is as below (PIN array is ignored) MODE0_B_OUT(){ PROC[]={ Figure 3. Bus Comparator System 0(CS)[#111_101](WR)1(A1)(A0)[8TR_0F](D)uuu, 0011xxxu[8TR_0F](PB)u ;} FUNC{ (PB_1-R)=(A1_0)(A0_0)(WR_0)(CS_0)(D_1), (PB_0-R)=(A1_0)(A0_0)(WR_0)(CS_0)(D_0);} }

This demo system showcases most of BBATG capabilities. We apply the bus test pattern replacing technique to handle data buses and adopt test vector sequence express format. The Intel 8255 is a LSI sequential device. BBATG presets 8255 to 0 out mode by SINI in system input file for both A and B ports, such as below:
8255_MOD0_OUT[RST,WR,RD,D7-D0,A7-A0,PQ]= {0[#101]01[8TR_80]1xxxxxxx00000011u;}

Here, [#101]0 is the express presentation for vector-bit (WR) and [8TR_80] is bus pattern name for intel8255 0 out mode. As an example, we now discuss the test deduction process for 8255 A port out H ERR. The ERR description is as below:
ERR_8255_A_O(){ PIN[]={ RESET-35-0-I, CS-6-1-I, WR-36-2-I,RD-3-3-I, A1-8-4-I, A0-9-5-I, D-27-6-I, PA-37-7-O, PB-25-8-O, PC-10-9-O;} //bus bit MODE0_AH_OUT[]={ 00[#101]0100[8TR_0F]1[8TR_0F]Huu;} // (1) }

BBATG selects the first FUNC expression, after variable values substituting, the PROC vectors becomes:
PROC[]={ 00[#111_101]0110[8TR_0F]1uuu, 0011xxxu[8TR_0F]1u; } // (3)

According (3), BBATG will continue backtrack driving. And then on every backtrack step (back to abut device) we would got one or more vectors on which there are some 1 or 0 vector-bit to be backtrack driving. Backtrack driving continues on, until all 1/0 vector-bits have been backtracked at system initial inputs. In the HL forward driving and backtrack driving, if an incompatible value found, the deduction will backdate. The system test for Intel 8255A port out HERR is generated as the following:
4U5-37H [RST,WR,RD,D7-D0,A7-A0,PQ] ={ 0[#101]01[8TR_80]1xxxxxxx00000011u, 0[#010]01[8TR_0F]1xxxxxxx00000001u,

BBATG drives the ERR H to 5U6 which is a bus comparer. The TRN group is as below:
TRN_74LS688J(){ PIN[]={G-1-0-I, P-17-1-I, Q-18-2-I, PQ-19-3-O;}

[#101]01[8TR_0F]1xxxxxxx00000000u, xxxxxxxxxxxx000001xxL;}

In post-process stage, BBATG will automatically replace the bus vector-bit back with actual bus test patterns. In the example, [8TR_80] is replaced by mode pattern (10000000) and [8TR-0F] is replaced by scan 0 and scan 1patterns. The later will spread one test to multi-tests. A typical system test pattern on spread format is as below:
SYSTST31 [RST, WR, RD, D7-D0, A7-A0, PQ] ={ 0011000000000000011u, 0111000000000000011u, 0011000000000000011u, 0010000100000000001u, 0110000100000000001u, 0010000100000000001u, 0010000100000000000u, 0110000100000000000u, 0010000100000000000u, 001xxxxxxxx000001xxL;}

As depicted above, BBATG treats I/O pins of JTAG devices as board/system initial I/O pins. Each BBATG generated system/board test vector contains I/O pin values of system connectors (besides TDI, TDO, TMS, TCK and TRST) and I/O pin values of JTAG devices (if the board has JTAG devices). When testing the board, ATE transmits/receives the first through digital test interface and/or AD/DA test interface by only one step, and the later through JTAG interface by many steps which requires a JTAG test vector sequence to be implemented.

The system test will be performed by ATE as following: first to write mode word for 8255A device, secondly to write data to PB, and finally write data to PA and the bus comparing result appearing on PQ. Additionally, BBATG also generates fault dictionary and probe paths. IV. ATE INTELLIGENT TESTING

We have developed a complete set of test executing software and test supporting hardware for the ATE that can use the BBATG generated test data to detect behavior faults and diagnose faults at the device level further for complex circuit boards. As shown in Figure 4. , the ATE test supporting hardware is based on PXI bus. In addition to parallel digital stimulus/response test interfaces, it also has an AD/DA test interface, a JTAG test interface, a guidedprobe test interface, and etc. All the interfaces use FIFO queues to store stimulus/response data. The AD/DA test interface can transmit/receive stimulus/response on both step and burst mode in phase with parallel digital stimulus/response test interfaces. AD/DA test interface is useful for analog circuit testing digitization. The guidedprobe test interface uses 1 bit path from the parallel digital response FIFO to store probed data. The fault diagnosis program compares the probed data with the expected data generated by BBATG to locate a fault at the device where a behavior fails. The device that operates in IEEE 1149.1 BST mode uses four required pins, TCK (test clock input), TMS (test mode select), TDI (test data input), TDO (test data output), and one optional pin TRST (test reset input). The ATE can transmit stimulus to TCK, TMS, TDI and TRST; and receives responses from TDO through the JTAG interface on step or burst mode independently. To identify TDO response, the JTAG interface returns TCK, TMS, and TDI to response FIFO queues.

Note: Inf, Interface abbreviation; Ctl, Control circuit abbreviation; FF, FIFO abbreviation; P, Probe path abbreviation. Figure 4. ATE Hardware Block Diagram

The ATE mainly uses EXTEST and PRELOAD (optional) JTAG instructions for transmitting/receiving stimulus/response to/from I/O pins of JTAG devices. According to IEEE Std. 1149.1 [2] and BSDL [16] descriptions of JTAG devices supplied by device vendors, we can prepare JTAG test vector format sequences for each JTAG device and save them to a library (namely JTAG test vector format library) for later uses. As a post process task, BBATG will draw JTAG devices I/O pin values (if exist) from generated test vectors into the JTAG test vector format sequence, and then get the actual JTAG test vector sequence. V. CONCLUSIONS

As described above, the integrated ATG and ATE system has the following important features:

1) BBATG uses device behavior fault model which can describe functions and timing relations for a combination or sequential device to avoid decomposing devices into gatelevel descriptions. 2) BBATG utilizes device behavior libraries to drive behavior error signals and sensitize paths along one or multi-vectors without a heavy and complicated iterating process for sequential circuit test deductions. 3) The BBATG with DFT test generation technique and the ATE test executing technique can highly reduce difficulty for testing complex digital boards with VLSI. Now the integrated system has got preliminary application. We expect our future work will optimize the process and apply it on a broader application domain. REFERENCES
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