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Fundamentals of CMOS VLSI

10EC56

Fundamentals of CMOS VLSI Subject Code: 10EC56 Semester: V

PART-A Unit 1: Basic MOS Technology


Integrated circuits era, enhancement and depletion mode MOS transistors. nMOS fabricat ion. CMOS fabricat ion, Thermal aspects of processing, BiCMOS technology, production of E-beam masks.

MOS transistor theory


Introduction, MOS device design equations, the complementary CMOS inverter -DC characterist ics, static load MOS inverters, the different ial inverter, the transmissio n gate, tristate inverter.

Unit-2: Circuit Design Processes


MOS layers, stick diagrams, Design rules and layout- lambda-based design and other rules. Examples, layout diagrams, symbo lic diagram, tutorial exercises. Basic physical design of simple logic gates.

Unit 3: CMOS Logic Structures


CMOS complementary logic, BiCMOS logic, Pseudo-nMOS logic, Dynamic CMOS logic, clocked CMOS logic, Pass transistor logic, CMOS domino logic cascaded voltage switch logic (CVSL).

Unit-4: Basic circuit concepts


Sheet resistance, area capacitances, capacitances calculations. The delay unit, inverter delays, driving capacitive loads, propagation delays, wiring capacitances.

Scaling of MOS circuits


Scaling models and factors, limits on scaling, limits due to current density and noise.

Fundamentals of CMOS VLSI

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PART-B Unit-5: CMOS subsystem design


Architectural issues, switch logic, gate logic, design examples-co mbinat ional logic, clocked circuits. Other system considerat ions.

Clocking strategies

Unit-6: CMOS subsystem design processes


General considerat ions, process illustration, ALU subsystem, adders, mult ipliers.

Unit-7: Memory registers and clock


Timing considerations, memory elements, memor y cell arrays.

Unit-8: Testability
Performance parameters, layout issues I/O pads, real estate, system delays, ground rules for design, test and testability.

TEXT BOOKS 1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI 3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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INDEX SHEET

SL.NO 1

TOPIC UNIT 1: Basic MOS technology:

PAGE NO. 7-44

Integrated circuit s era, Enhancement and depletion mode 8-16 MOS transistors 14-16 nMOS fabrication CMOS fabricat ion Thermal aspects of processing, Production of E-beam masks MOS Transistor Theory: BiCMOS techno logy, 17-25 25-27

Introduction, MOS Device Design Equations, The Complementary CMOS Inverter DC Characterist ics, The Differential Inverter, Static Load MOS Inverters, The Transmissio n Gate Tristate Inverter 2 UNIT 2: CIRCUIT DESIGN PROCESSES MOS layers. Stick diagrams. Design rules and layout Lambda-based design and other rules. Examples. Layout diagrams. Symbo lic diagrams Tutorial exercises, Basic Physical Design of Simple logic gates

28-31 31-37 37-40 39-40 41-42 43-44 45-66 45-50 51-54 54-55 55-56 56-57 57-66

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UNIT 3: CMOS LOGIC STRUCTURES CMOS Complementary Logic, Bi CMOS Logic Pseudo-nMOS Logic Dynamic CMOS Logic CMOS Domino Logic Cascaded Vo ltage Switch Logic (CVSL). Clocked CMOS Logic, Pass Transistor Logic

67-78 67 67-68 69-70 71 72-75 76-78 79-118 79-86 86-88 89-92 92-93 93-94 94-95

UNIT 4: BASIC CIRCUIT CONCEPTS Sheet resistance. Area capacitances Capacitance calculat ions. The delay unit Inverter delays. Driving capacit ive loads. Propagation delays Wiring capacitances. Tutorial exercises Scaling of MOS circuits Scaling models and factors Limits on scaling Limits due to current densit y and no ise

96-101 102-117 105-118 119-153 119-122 123-131 132-138 139-142

UNIT 5: CMOS SUBSYSTEM DESIGN Architectural issues. Switch logic Gate logic. Design examples Combinat ional logic. Clocked circuits.

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Other system considerations. Clocking Strategies 6 UNIT 6: CMOS SUBSYSTEM DESIGN PROCESSES General considerat ions Process illustration ALU subsystem Adders Mult ipliers 7 UNIT 7: MEMORY, REGISTERS, AND CLOCK Timing considerat ions Memory elements Memory cell arrays 8 UNIT 8: TESTABILITY Performance parameters. Layout issues I/O pads. Real estate System delays Ground rules for design Test and testabilit y.

143-151 152-153 154-179 154 154-159 160-162 162-171 172-179 180-185 180 180-181 181-185 186-207 186 186 186 187-190 190-207

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PART-A

Unit 1
Basic MOS Technology
Integrated circuits era, enhancement and depletion mode MOS transistors. nMOS fabricat ion. CMOS fabricat ion, Thermal aspects of processing, BiCMOS techno logy, production of E-beam masks.

MOS transistor theory


Introduction, MOS device design equations, the complementary CMOS inverter-DC characterist ics, static load MOS inverters, the different ial inverter, the transmissio n gate, tristate inverter.

Recommended readings:

1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI. 3. CMOS VLSI DESIGNA circuits and systems perpective. 3rd edit ion N.H.Weste and David Harris. Addison-wesley.

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1.1 Integrated circuits era


Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell laboratories. In 1961, first IC was introduced. Levels of Integration:i) SSI: - (10-100) transistors => Example: Logic gates ii) MSI: - (100-1000) => Example: counters iii) LSI: - (1000-20000) => Example: 8-bit chip iv) VLSI: - (20000-1000000) => Example: 16 & 32 bit up v) ULSI: - (1000000-10000000) => Example: Special processors, virtual realit y machines, smart sensors. MooresLaw:The number of transistors embedded on the chip doubles after every one and a half years. The number of transistors is taken on the y-axis and the years in taken on the x-axis. The diagram also shows the speed in MHz. the graph given in figure also shows the variat ion o f speed of the chip in MHz.

Figure 1. Moores law.

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The graph in figure2 compares the various techno logies available in ICs.

Figure 2.Comparison of available technologies.

From the graph we can conclude that GaAs techno logy is better but still it is not used because of growing difficult ies of GaAs crystal. CMOS looks to be a better option compared to nMOS since it consumes a lesser power. BiCMOS techno logy is also used in places where high driving capabilit y is required and from the graph it confirms that, BiCMOS consumes more power compared to CMOS . Levels of Integration:i) Small Scale Integration:- (10-100) transistors => Example: Logic gates ii) Medium Scale Integration:- (100-1000) => Example: counters iii) Large Scale Integration:- (1000-20000) => Example:8-bit chip iv) Very Large Scale Integration:- (20000-1000000) => Example:16 & 32 bit up v) Ultra Large Scale Integration:- (1000000-10000000) => Example: Special processors, virtual realit y machines, smart sensors

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1.2 Basic MOS Transistors:


MOS We should first understand the fact that why the name Metal Oxide Semiconductor transistor, because the structure consists of a layer of Metal (gat e), a layer of oxide (Sio2) and a layer of semiconductor. Figure 3 below clearly tell why the name MOS.

Figure 3.cross section of a MOS structure

We have two types of FETs. They are Enhancement mode and depletion mode transistor. Also we have PMOS and NMOS transistors. In Enhancement mode transistor channel is go ing to form after giving a proper positive gate vo ltage. We have NMOS and PMOS enhancement transistors. In Depletion mode transistor channel will be present by the implant. It can be removed by giving a proper negative gate voltage. We have NMOS and PMOS deplet ion mode transistors.

1.2.1 N-MOS enhancement mode transistor:This transistor is normally o ff. This can be made ON by giving a posit ive gate voltage. By giving a +ve gate voltage a channel of electrons is formed between source drain.

Figure 4. N-MOS enhancement mode transistor.

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1.2.2 P-MOS enhancement mode transistor:This is normally on. A Channel of Holes can be performed by giving a ve gate voltage. In P-Mos current is carried by holes and in N-Mos it s by electrons. Since the mobilit y is o f ho les less than that of electrons P-Mos is slower.

Figure 5. P-MOS enhancement mode transistor.

1.2.3 N-MOS depletion mode transistor:This transistor is normally ON, even wit h Vgs=0. The channel will be implanted while fabricat ing, hence it is normally ON. To cause the channel to cease to exist, a ve voltage must be applied between gate and source.

Figure 6. N-MOS depletion mode transistor.

NOTE: Mobilit y of electrons is 2.5 to 3 times faster than ho les. Hence P -MOS devices will have more resistance compared to NMOS.

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1.2.4 Enhancement mode Transistor action:-

Figure7. (a)(b)(c) Enhancement mode transistor with different Vds values

To establish the channel between the source and the drain a minimum voltage (Vt) must be applied between gate and source. This minimum vo ltage is called as Thresho ld Voltage. The complete working of enhancement mode transistor can be explained wit h the help of diagram a, b and c.

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a) Vgs > Vt Vds = 0 Since Vgs > Vt and Vds = 0 the channel is formed but no current flows between drain and source. b) Vgs > Vt Vds < Vgs - Vt This region is called the non-saturation Regio n or linear region where the drain current increases linearly wit h Vds. When Vds is increased the drain side beco mes more reverse biased (hence more deplet ion region towards the drain end) and the channel starts to pinch. This is called as the pinch off po int.

c) Vgs > Vt Vds > Vgs - Vt This regio n is called Saturation Regio n where the drain current remains almost constant. As the drain voltage is increased further beyo nd (Vgs-Vt) the pinch o ff po int starts to move from the drain end to the source end. Even if the Vds is increased more and more, the increased vo ltage gets dropped in the deplet ion regio n leading to a constant current. The typical thresho ld voltage for an enhancement mode transistor is given by Vt = 0.2 * Vdd.

1.2.5 Depletion mode Transistor action:We can explain the working o f deplet ion mode transistor in the same manner, as that of the enhancement mode transistor only difference is, channel is established due to the implant even when Vgs = 0 and the channel can be cut off by applying a ve voltage between the gate and source. Threshold vo ltage of deplet ion mode transistor is around 0.8*Vdd .

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1.3 NMOS Fabrication:

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Figure8. NMOS Fabrication process steps

The process starts with the oxidat ion of the silicon substrate (Fig. 8(a)), in which a relat ively thick silicon dioxide layer, also called field oxide, is created on the surface (Fig. 8(b)). Then, the field oxide is select ively etched to expose the silicon surface on which the MOS transistor will be created (Fig. 8(c)). Fo llowing this step, the surface is covered with a thin, highqualit y oxide layer, which will eventually form the gate oxide of the MOS transistor (Fig. 8(d)). On top of the thin oxide, a layer of po lysilicon (polycrystalline silicon) is deposited (Fig. 8(e)). Polysilicon is used both as gate electrode material for MOS transistors and also as an interconnect medium in silicon integrated circuits. Undoped polysilicon has relatively high resist ivit y. The resist ivit y o f po lysilicon can be reduced, however, by doping it wit h impurit y atoms.

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After deposit ion, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates (Fig. 8(f)). The thin gate oxide not co vered by po lysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed (Fig. 8(g)). The ent ire silicon surface is then doped with a high concentration o f impurit ies, eit her through diffusio n or ion implantation (in this case with donor atoms to produce n-t ype doping). Figure 8(h) shows that the doping penetrates the exposed areas on the silico n surface, ult imately creating two n-type regions (source and drain junct ions) in the p-t ype substrate. The impurit y doping also penetrates the polysilicon on the surface, reducing it s resist ivit y. Note that the polysilicon gate, which is patterned before doping actually defines the precise location of the channel regio n and, hence, the location o f the source and the drain regions. Since this procedure allows very precise posit ioning of the two regions relat ive to the gate, it is also called the self-aligned process. Once the source and drain regio ns are completed, the ent ire surface is again covered wit h an insulat ing layer of silicon dioxide (Fig. 8 (i)). The insulat ing oxide layer is then patterned in order to provide contact windows for the drain and source junct ions (Fig. 8 (j)). The surface is covered with evaporated aluminum which will form the interconnects (Fig. 8 (k)). Finally, the metal layer is patterned and etched, complet ing the interconnect ion of the MOS transistors on the surface (Fig. 8 (l)). Usually, a second (and third) layer of metallic interconnect can also be added on top of this structure by creating another insulating oxide layer, cutting contact (via) ho les, depositing, and patterning the metal.

1.4 CMOS fabrication: When we need to fabricate both nMOS and pMOS transistors on the same substrate we need to fo llow different processes. The three different processes are, P-well process ,N-well process and Twin tub process.

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1.4.1 P-WELL PROCESS:

. Figure9. CMOS Fabrication (P-WELL) process steps. The p-well process starts with a n t ype substrate. The n type substrate can be used to implement the pMOS transistor, but to implement the nMOS transistor we need to provide a pwell, hence we have provided he place for both n and pMOS transistor on the same n-type substrate. Mask sequence. Mask 1: Mask 1 defines the areas in which the deep p-well diffusio n takes place.

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Mask 2: It defines the thin oxide region (where the thick oxide is to be removed or stripped and thin oxide grown) Mask 3: It s used to pattern the polysilicon layer which is deposited after thin oxide. Mask 4: A p+ mask (anded with mask 2) to define areas where p-diffusio n is to take place. Mask 5: We are using the ve form of mask 4 (p+ mask) It defines where n-diffusio n is to take place. Mask 6: Contact cuts are defined using this mask. Mask 7: The metal layer pattern is defined by this mask. Mask 8: An overall passivat ion (over glass) is now applied and it also defines openings for accessing pads. The cross section below shows the CMOS pwell inverter.

Figure10. CMOS inverter (P-WELL)

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1.4.2 N-WELL PROCESS: In the fo llowing figures, some of the important process steps invo lved in the fabrication of a CMOS inverter will be shown by a top view of the lit hographic masks and a cross-sectional view of the relevant areas. The n-well CMOS process starts with a moderately doped (with impurit y concentration typically less than 1015 cm-3) p-t ype silicon substrate. Then, an init ia l oxide layer is grown on the ent ire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. Once the nwell is created, the active areas of the nMOS and pMOS transistors can be defined. Figures 12.1 through 12.6 illustrate the significant milestones that occur during the fabrication process of a CMOS inverter.

Figure-11.1: Following the creation of the n-well region, a thick field oxide is grown in the areas surrounding the transistor active regions, and a thin gate oxide is grown on top of the active regions. The thickness and the quality of the gate oxide are two of the most critical fabrication parameters, since they strongly affect the operational characteristics of the MOS transistor, as well as its long-ter m reliability.

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Figure-11.2: The polysilicon layer is deposited using chemical vapor deposition (CVD) and patterned by dry (plasma) etching. The created polysilicon lines will funct ion as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step.

Figure-11.3: Using a set of two masks, the n+ and p+ regions are implanted into the substrate and into the n- well, respect ively. Also, the ohmic contacts to the substrate and to the n-well are implanted in this process step.

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Figure-11.4: An insulating silicon dio xide layer is deposited over the ent ire wafer using CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon contact windows. These contact windows are necessary to co mplete the circuit interconnections using the metal layer, which is patterned in the next step.

Figure-11.5: Metal (aluminum) is deposited over the ent ire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the

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qualit y and the integrit y of the metal lines created in this step are very crit ical and are ult imately essent ial for circuit reliabilit y.

Figure-11.6: The co mposite layout and the result ing cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnect ions. The final step is to deposit the passivation layer (for protection) over the chip, except for wirebonding pad areas.

1.4.3Twin-tub process: Here we will be using both p-well and n-well approach. The starting po int is a n-type material and then we create both n-well and p-well region. To create the both well we first go for the epitaxial process and then we will create both wells on the same substrat e.

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Figure 12 CMOS twin-tub inverter.

NOTE: Twin tub process is one of the solut ions for latch-up problem.

1.5 Bi-CMOS technology: - (Bipolar CMOS)


The driving capabilit y o f MOS transistors is less because of limited current sourcing and sinking capabilit ies of the transistors. To drive large capacit ive loads we can think of Bi-Cmos techno logy. This technology co mbines Bipo lar and CMOS transistors in a single integrated circuit, by retaining benefit s of bipo lar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-densit y performance previously unattainable wit h either techno logy individually. Characteristics of CMOS Technology Lower static power dissipat ion Higher no ise margins Higher packing densit y lower manufacturing cost per device High yield wit h large integrated complex functions High input impedance (low drive current) Scaleable threshold voltage High delay sensit ivit y to load (fan-out limitat ions) Low output drive current (issue when driving large capacit ive loads) Low transconductance, where transconductance, gm a Vin Bi-direct ional capabilit y (drain & source are interchangeable) A near ideal switching device

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Characteristics of Bipolar Technology Higher switching speed Higher current drive per unit area, higher gain Generally better noise performance and better high frequency characterist ics Better analogue capabilit y Improved I/O speed (particularly significant with the growing importance of package limitat ions in high speed systems). High power dissipat ion Lower input impedance (high drive current) Low voltage swing logic Low packing densit y Low delay sensit ivit y to load High gm (gm a Vin) High unit y gain band width (ft) at low currents Essentially unidirectional fro m the two previous paragraphs we can get a comparison between bipo lar and CMOS techno logy. The diagram given below shows the cross section of the BiCMOS process which uses an npn transistor.

Figure 13 Cross section of BiCMOS process

The figure below shows the layout view o f the BiCMOS process.

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Fig.14. Layout view of BiCMOS process. The graph below shows the relative cost vs. gate delay.

Fig.16. cost versus delay graph.

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1.6 Production of e-beam masks:


In this topic we will understand how we are preparing the masks using e-beam technology. The fo llowing are the steps in production of e-beam masks. Starting materials is chromium coated glass plates which are coated with e-beam sensit ive resist. E-beam machine is loaded with the mask descriptio n data. Plates are loaded into e-beam machine, where they are exposed with the patterns specified by mask descript ion data. After exposure to e-beam, plates are introduced into developer to bring out patterns. The cycle is fo llowed by a bake cycle which removes resist residue. The chrome is then etched and plate is stripped of the remaining e-beam resist. We use two types o f scanning, Raster scanning and vector scanning to map the pattern on to the mask. In raster type, e-beam scans all possible locat ions and a bit map is used to turn the ebeam on and off, depending on whether the particular location being scanned is to be exposed or not. In vector type, beam is directed only to those locatio ns which are to be exposed.

1.6.1 Advantages e-beam masks: - Tighter layer to layer registration; - Small feature sizes

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MOS transistor theory


1.7 Introduction: A MOS transistor is a majorit y-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the gate. Symbo ls

Figure 17: symbols of various types of transistors.

NMOS (n-type MOS transistor) (1) Majorit y carrier = electrons (2) A posit ive voltage applied on the gate with respect to the substrate enhances the number of electrons in the channel and hence increases the conduct ivit y of the channel. (3) If gate voltage is less than a thresho ld vo ltage Vt , the channel is cut -off (very low current between source & drain). PMOS (p-type MOS transistor) (1) Majorit y carrier = holes (2) Applied vo ltage is negat ive with respect to substrate.

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Relationship between Vgs and Ids, for a fixed Vds:

Figure 18: graph of Vgs vs Ids

Devices that are normally cut-off wit h zero gate bias are classified as "enhancementmode devices. Devices that conduct with zero gate bias are called "depletion-mode devices. Enhancement-mode devices are more popular in practical use. Threshold voltage (Vt): The vo ltage at which an MOS device begins to conduct ("turn on"). The threshold voltage is a function of (1) Gate conductor material (2) Gate insulator material (3) Gate insulator thickness (4) Impurit y at the silicon-insulator interface (5) Voltage between the source and the substrate Vsb (6) Temperature

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1.8 MOS equations (Basic DC equations): Three MOS operating regions are: Cutoff or subthresho ld region, linear region and saturation region. The fo llowing equation describes all these three regions:

Where is MOS transistor gain and it is given by = /tox (W/L) again is the mobilit y of the charge carrier is the permittivit y of the oxide layer. tox is the thickness of the oxide layer. W is the width of the transistor.( shown in diagram) L is the channel length of the transistor.(shown in diagram)

Diagram just to show the length and width of a MOSFET. The graph of Id and Vds for a given Vgs is given below:

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Figure 19: VI Characterist ics of MOSFET Second Order Effects: Fo llowing are the list of second order effects of MOSFET. Threshold vo ltage Body effect Subthreshold regio n Channel length modulat ion Mobilit y variat ion Fowler_Nordheim Tunneling Drain Punchthrough Impact Ionization Hot Electrons Threshold voltage Body effect The change in the thresho ld vo ltage of a MOSFET, because of the vo ltage difference between body and source is called body effect. The expressio n for the thresho ld vo ltage is given by the fo llowing expressio n.

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If Vsb is zero, then Vt = Vt(0) that means the value of the thresho ld vo ltage will not be changed. Therefore, we short circuit the source and substrate so that, Vsb will be zero. Subthreshold region: For Vgs<Vt also we will get some value of Drain current this is called as Subthres ho ld current and the region is called as Subthresho ld region. Channel length modulation: The channel length of the MOSFET is changed due to the change in the drain to source voltage. This effect is called as the channel length modulation. The effective channel length & the value of the drain current considering channel length modulat ion into effect is given by,

Where is the channel length modulat ion factor. Mobility: Mobilit y is the defined as the ease wit h which the charge carriers drift in the substrate material. Mobilit y decreases wit h increase in doping concentration and increase in temperature. Mobilit y is the ratio of average carrier drift velocit y and electric field. Mobilit y is represented by the symbo l . Fowler Nordhiem tunneling: When the gate oxide is very thin there can be a current between gate and source or drain by electron tunneling through the gate oxide. This current is proportional to the area of the gate of the transistor.

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Drain punchthough: When the drain is a high vo ltage, the deplet ion regio n around the drain may extend to the source, causing the current to flow even it gate voltage is zero. This is known as Punchthrough condit ion. Impact Ionization-hot electrons: When the length of the transistor is reduced, the electric field at the drain increases. The field ca n beco me so high that electrons are imparted with enough energy we can term them as hot. These hot electrons impact the drain, dislodging ho les that are then swept toward the negat ively charged substrate and appear as a substrate current. This effect is known as Impact Ionizat ion.

1.9 MOS Models


MOS model includes the Ideal Equations, Second-order Effects plus the addit ional Curve-fitt ing parameters. Many semiconductor vendors expend a lot of effects to model the devices the y manufacture. (Standard: Level 3 SPICE) . Main SPICE DC parameters in level 1,2,3 in 1n-well CMOS process.

1.10 CMOS INVETER CHARACTERISTICS

Figure 20: CMOS Inverter

CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and adaptable MOSFET inverters used in chip design. They operate with very litt le power loss

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and at relatively high speed. Furthermore, the CMOS inverter has good logic buffer characterist ics, in that, its no ise margins in both low and high states are large. A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply vo ltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.( given in diagram). It is important to notice that the CMOS does not contain any resistors, which makes it more power efficient that a regular resistor -MOSFET inverter. As the voltage at the input of the CMOS device varies between 0 and VDD, the state of the NMOS and PMOS varies accordingly. If we model each transistor as a simple switch activated by VIN, the inverters operations can be seen very easily:

The table given, explains when the each transistor is turning on and off. When VIN is low, the NMOS is "o ff", while the PMOS stays "on": instant ly charging VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "off": taking the vo ltage at VOUT to logic low. 1.10.1 Inverter DC Characteristics: Before we study the DC characterist ics of the inverter we should examine the ideal characterist ics of inverter which is shown below. The characterist ic shows that when input is zero output will high and vice versa.

Figure 21: Ideal Characteristics of an Inverter.

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The actual characterist ic is also given here for the reference. Here we have shown the status of both NMOS and PMOS transistor in all the regions of the characterist ics.

Figure 22: Actual Characteristics of an Inverter.

Graphical Derivation of Inverter DC Characteristics: The actual characterist ics are drawn by plotting the values o f output voltage for different values of the input voltage. We can also draw the characterist ics, starting wit h the VI characterist ics o f PMOS and NMOS characterist ics.

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Figure 23-a,b,c: Graphical Derivation of DC Characteristics.

The characteristics given in figure 23a is the vi characterist ics of the NMOS and PMOS characterist ics (plot of Id vs. Vds). The figure 23b shows the values of drain current of PMOS transistor is taken to the positive side the current axis. This is done by taking the abso lute value of the current. By superimposing both characterist ics it leads to figure 23c. the actual characterist ics may be now determined by the points of co mmo n Vgs intersect ion as s hown in figure 23d.

Figure 23d: CMOS Inverter Dc Characteristics.

Figure 23d shows five regions namely region A, B, C, D & E. also we have shown a dotted curve which is the current that is drawn by the inverter.

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Region A: The output in this regio n is high because the P device is OFF and n device is ON. In regio n A, NMOS is cutoff regio n and PMOS is on, therefore output is logic high. We can analyze the inverter when it is in region B. the analysis is given below: Region B: The equivalent circuit of the inverter when it is regio n B is given below.

Figure 24: Equivalent circuit in Region B.

In this region PMOS will be in linear region and NMOS is in saturation region. The expression for the NMOS current is

The expression for the PMOS current is

The expressio n for the vo ltage Vo can be written as

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Region C: The equivalent circuit of CMOS inverter when it is in regio n C is given here. Both n and p transistors are in saturation region, we can equate both the currents and we can obtain the expressio n for the midpo int voltage or switching point vo ltage of a inverter. The corresponding equations are as fo llows:

Figure 25: Equivalent circuit in Region C.

The corresponding equations are as fo llows:

By equating both the currents, we can obtain the expressio n for the switching point vo ltage as,

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Region D: The equivalent circuit for region D is given in the figure below.

Figure 26: equivalent circuit in region D.

We can apply the same analysis what we did for region B and C and we can obtain the expression for output voltage. Region E: The output in this region is zero because the P device is OFF and n device is ON . Influence of n / p on the VTC characteristics:

Figure 27: Effect of n/p ratio change on the DC characteristics of CMOS inverter.

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The characterist ics shifts left if the ratio of n/p is greater than 1(say 10). The curve shifts right if the rat io of n/p is lesser than 1(say 0.1). This is decided by the switching point equation o f region C. the equation is repeated here the reference again.

Noise Margin: Noise margin is a parameter related to input output characterist ics. It determines the allowable no ise voltage on the input so that the output is not affected. We will specify it in terms of two things: LOW no ise margin HIGH noise margin LOW noise margin: is defined as the difference in magnitude between the maximum Low output voltage of the driving gate and the maximum input Low voltage recognized by the driven gate.

NML=|VILmax VOLmax|
HIGH noise margin: is defined difference in magnitude between minimum High output voltage of the driving gate and minimum input High vo ltage recognized by the receiving gate.

NMH=|Vohmin VIHmin|

Figure 28: noise margin definitions.

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Figure shows how exact ly we can find the no ise margin for the input and output. We can also find the no ise margin of a CMOS inverter. The following figure gives the idea of calculat ing the no ise margin.

Figure 29: CMOS inverter noise margins. 1.11 Static Load MOS inverters: In the figure given below we have shown a resist ive load and current source load inverter. Usually resist ive load inverters are not preferred because o f the power consumpt ion and area issues.

Figure 30: static load inverter.

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1.12 Pseudo-NMOS inverter: This circuit uses the load device which is p device and is made to turn on always by connect ing the gate terminal to the ground.

Figure 31: Pseudo-NMOS inverter.

Power consumpt ion is High co mpared to CMOS inverter particularly when NMOS device is ON because the p load device is always ON. 1.13 Saturated load inverter: The load device is an nMOS transistor in the saturated load inverter. This type of inverter was used in nMOS techno logies prior to the availabilit y o f nMOS deplet ion loads.

Figure 32: Saturated load inverter

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1.14 Transmission gates: It s a parallel co mbination o f pmos and nmo s transistor with the gates connected to a complementary input. After looking into various issues of pass transistors we will co me back to the TGs again.

Figure 33: Transmission gate

1.15 Pass transistors: We have n and p pass transistors.

Figure 18: n and p pass transistors.

The disadvantage with the pass transistors is that, they will not be able to transfer the logic levels properly. The fo llowing table gives that explanat ion in detail.

If Vdd (5 volts) is to be transferred using nMOS the output will be (Vdd-Vtn). POOR 1 or Weak Logic 1

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If Gnd(0 vo lts) is to be transferred using nMOS the output will be Gnd. GOOD 0 or Strong Logic 0 If Vdd (5 volts) is to be transferred using pMOS the output will be Vdd. GOOD 1 or Strong Logic 1 If Gnd(0 vo lts) is to be transferred using pMOS the output will be Vtp. POOR 0 or Weak Logic 0.

1.16 Transmission gates (TGs): It s a parallel co mbination o f pmos and nmo s transistor with the gates connected to a complementary input. The disadvantages weak 0 and weak 1 can be overcome by using a TG instead of pass transistors. Working of transmissio n gate can be explained better with the fo llowing equation. When _=0 n and p device off, Vin=0 or 1, Vo= Z When _=1 n and p device on, Vin=0 or 1, Vo=0 or 1 , where Z is high impedance. One more important advantage of TGs is that the reduction in the resistance because two transistors will co me in parallel and it is shown in the graph. The graph shows the resistance of n and p pass transistors, and resistance of TG which is lesser than the other two.

Figure 19: Graph of resistance vs. input for pass transistors and TG.

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1.17 Tristate Inverter: By cascading a transmissio n gate with an inverter the tristate inverter circuit can be obtained. The working can be explained wit h the help of the circuit.

Figure 20: Tristate Inverter

The two circuits are the same only difference is the way they are written. When CL is zero the output of the inverter is in tristate condit ion. When CL is high the output is Z is the inversion o f the input A

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Recommended questions:
1. Write a note on integration era. 2. What do you mean MOS. 3. Bring out the difference between enhancement mode and depletion mode MOS transistors. 4. Explain the types of MOS transistors. 5. What do you mean by fabricat ion. 6. Explain nMOS fabrication process. 7. Explain CMOS fabricat ion process. 8. Explain BiCMOS techno logy. 9. What is the different between CMOS and BiCMOS techno logy. 10. Write a short note on production of E-beam. 11. Write MOS device design equation for all the region of operations. 12. List the region of operations of MOS transistors. 13. Explain CMOS inverter with all the region of operations. 14. Write a note on static load MOS inverter and different ial inverter with neat diagram. 15. Explain transmissio n gate. 16. Write a note on tristate inverter.

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Unit-2
Circuit Design Processes
MOS layers, stick diagrams, Design rules and layo ut - lambda-based design and other rules. Examples, layout diagrams, symbo lic diagram, tutorial exercises.

Basic physical design of simple logic gates.

Recommended readings:

1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI 3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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2.1 Introduction:
In this chapter we are going to study how to get the schematic into stick diagrams or layouts. MOS circuits are formed on four basic layers: > N-diffusion > P-diffusion > Polysilicon > Metal These layers are isolated by one another by thick or thin silicon dioxide insulating layers. Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel. 2.2 Stick diagrams: Stick diagrams may be used to convey layer infor mation through the use of a color code. For example: ndiffusion--green poly--red blue-- metal yellow--implant black--contact areas. Encodings for NMOS process:

Figure 1: NMOS encodings.

Figure shows the way of representing different layers in stick diagram notation and mask layout using nmos style.

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Figure l shows when a n-transistor is for med: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure also shows how a depletion mode transistor is represented in the stick for mat. 2.2.1 Encodings for CMOS process:

Figure 2: CMOS encodings.

Figure 2 shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. Figure 2 also shows when a p-transistor is formed: a transistor is formed when a yellow line (p+ diffusion) crosses a red line (poly) completely. 2.2.2 Encoding for BJT and MOSFETs:

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Figure 3: Bi CMOS encodings.


There are several layers in an nMOS chip: _ a p-type substrate _ paths of n-type diffusion _ a thin layer of silicon dioxide _ paths of polycrystalline silicon _ a thick layer of silicon dioxide _ paths of metal (usually aluminum) _ a further thick layer of silicon dioxide With contact cuts through the silicon dioxide wher e connections are required. The three layers carrying paths can be considered as independent conductors that only interact where polysilicon crosses diffusion to form a transistor. These tracks can be drawn as stick diagrams with _ diffusion in gr een _ polysilicon in red _ metal in blue using black to indicate contacts between layers and yellow to mark regions of implant in the channels of depletion mode transistors. With CMOS there are two types of diffusion: n-type is drawn in green and p-type in brown. These are on the same layers in the chip and must not meet. In fact, the method of fabrication required that they be kept relatively far apart. Modern CMOS processes usually support mor e than one layer of metal. Two are common and three or more are often available. Actually, these conventions for colors are not universal; in particular, industrial (rather than academic) systems tend to use red for diffusion and green for polysilicon. Moreover, a shortage of

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colored pens nor mally means that both t ypes of diffusion in CMOS are colored green and the polarity indicated by drawing a circle round p-type transistors or simply inferred from the context. Colorings for multiple layers of metal are even less standard. There are three ways that an nMOS inverter might be drawn:

Figure 4: nMOS depletion load inverter.

Figure4 shows schematic, stick diagram and corresponding layout of nMOS depletion load inverter

Figure 5: CMOS inverter

Figure 5 shows the schematic, stick diagram and corresponding layout of CMOS inverter.

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Figure 6 shows the stick diagrams for nMOS NOR and NAND.

Figure 7: stick diagram of a given function f.

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Figure 7 shows the stick diagram nMOS implementation of the function f= [(xy) +z]'.Figure 8 shows the stick diagram CMOS NOR and NAND, where we can see that the p diffusion line never touched the n diffusion directly, it is always joined using a blue color metal line. 2.2.3NMOS and CMOS Design style: In the NMOS style of representing the sticks for the circuit, we use only NMOS tra nsistor, in CMOS we need to differentiate n and p transistor, that is usually by the color or in monochrome diagrams we will have a demarcation line. Above the demarcation line are the p transistors and below the demarcation are the n transistors. Following stick shows CMOS circuit example in monochrome wher e we utilize the demarcation line.

Figure 9: stick diagram of dynamic shift register in CMOS style.

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Figure 9 shows the stick diagram of dynamic shift register using CMOS style. Here the output of the T G is connected as the input to the inverter and the same chain continues depending the number of bits. 2.3 Design Rules: Design rules include width rules and spacing rules. Mead and Conway developed a set of simplified scalable X -based design rules, which are valid for a range of fabrication technologies. In thes e rules, the minimum feature size of a technology is characterized as 2 X. All width and spacing rules are specified in terms of the parameter X. Suppose we have design rules that call for a minimum width of 2

X, and a minimum spacing of 3 X . If we select a 2 um technology (i.e., X = 1 um), the above rules are
translated to a minimum width of 2 um and a minimum spacing of 3 um. On the other hand, if a 1 um technology (i.e., X = 0.5 um) is selected, then the same width and spacing rules are now specified as 1 um and 1.5 um, respectively.

Figure 10: Design rules for the diffusio n layers and metal layers.
Figure 10 shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and p diffusion lines is having a minimum width of 2 and a minimum spacing of 3.Similarly we are showing for other layers.

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Figure 11: Design rules for transistors and gate over hang distance.
Figure shows the design rule for the transistor, and it also shows that the poly should extend for a minimum of 7k beyond the diffusion boundaries. (gate over hang distance)

What is Via? It is used to connect higher level metals from metal connection. The cross section and layout view given figure 13 explain via in a better way.

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Figure 12: cross section showing the contact cut and via
Figure shows the design rules for contact cuts and Vias. The design rule for contact is minimum2x2 and same is applicable for a Via.

Figure 13: Design rules for contact cuts and vias


2.3.1 Buried contact: The contact cut is made down each layer to be joined and it is shown in figure 14.

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Figure 14: Buried contact.


2.3.2 Butting contact: The layers are butted together in such a way the two contact cuts become contiguous. We can better under the butting contact from figure 15.

Figure 15: Butting contact.


2.4 CMOS LAMBDA BASED DESIGN RULES: Till now we have studied the design rules wrt only NMOS, what are the rules to be followed if we have the both p and n transistor on the sa me chip will be made clear with the diagram. Figure 16 shows the rules to be followed in CMOS well processes to accommodate both n and p transistors.

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Figure 16: CMOS design rules. 2.4.1 Orbit process: 2 m CMOS

In this process all the spacing between each layers and dimensions will be in ter ms micrometer. The 2^ m here represents the feature size. All the design rules whatever we have seen will not have lambda instead it will have the actual dimension in micrometer. In one way lambda based design rules are better compared micrometer based design rules, that is lambda based rules are feature size independent. Figure 17 shows the design rule for BiCMOS process using orbit 2um process.

Figure 17: BiCMOS design rules. The fo llowing is the example st ick and layout for 2way selector with enable (2:1 MUX).

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Figure 18: Two way selector stick and layout

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2.5 BASIC PHYSICAL DESIGN AN OVERVIEW

The VLSI design flow for any IC design is as fo llows 1 .Specificat ion 2. Schemat ic (gate level design) 3. Layout 4. Floor Planning 5 .Routing, Placement 6. On to Silicon When the devices are represented using these layers, we call it physical design. The design is carried out using the design tool, which requires to follow certain rules. Physical structure is required to study the impact of moving fro m circuit to layout. When we draw the layout from the schemat ic, we are taking the first step towards the physical de sign. Physical design is an important step towards fabricat ion. Layout is representation o f a schemat ic into layered diagram. This diagram reveals the different layers like ndiff, po lysilicon etc that go into format ion of the device. At every stage of the physical design simulat ions are carried out to verify whether the design is as per requirement. Soon after the layout design the DRC check is used to verify minimum dimensions and spacing of the layers. Once the layout is done, a layout versus schemat ic check carried out before proceeding further. There are different tools available for drawing the layout and simulat ing it. The simplest way to begin a layout representation is to draw the st ick diagram. But as the complexit y increases it is not possible to draw the stick diagrams. For beginners it easy to draw the st ick diagram and then proceed with the layout for the basic digital gates. We will have a look at some of the things we should know before starting the layout. In the schemat ic representation lines drawn between device terminals represent interconnect ions and any no planar situat ion can be handled by crossing over. But in layout designs a litt le more concern about the physical interconnect ion of different layers. By simply drawing one layer above the other it not possible to make interconnect ions, because of the different characters of each layer. Contacts have to be made whenever such interconnect ion is required. The power and the ground (problem definit io n) (equivalence check) (equivalence check)

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connections are made using the metal and the commo n gate connect ion using the polysilicon. The metal and the diffusio n layers are connected using contacts. The substrate contacts are made for same source and substrate voltage. Which are not implied in the schemat ic. These layouts are governed by DRC's and have to be atleast of the minimum size depending on the techno logy used. The crossing over of layers is another aspect which is of concern and is addressed next. 1. Poly crossing diffusio n makes a transistor 2. Metal of the same kind crossing causes a short. 3. Poly crossing a metal causes no interaction unless a contact is made. Different design tricks need to be used to avoid unknown creat ions. Like a combination o f metal1 and metal 2 can be used to avoid short. Usually metal 2 is used for the global vdd and vss lines and metal1 for local connect ions. 2.6 SCHEMATIC AND LAYOUT OF BASIC GATES 1. CMOS INVERTER/NOT GATE SCHEMATIC

Figure 19: Inverter. TOWARDS THE LAYOUT

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Figure 20: Stick diagram of inverter.


The diagram shown here is the stick diagram for the CMOS inverter. It consists of a Pmos and a Nmos connected to get the inverted output. When the input is low, Pmos (yellow) is on and pulls the output to vdd; hence it is called pull up device. When Vin =1, Nmos (green) is on it pulls Vout to Vss, hence Nmos is a pull down device. The red lines are the poly silicon lines connecting the gates and the blue lines are the metal lines for VDD (up) and VSS (down).The layout of the cmos inverter is shown below. La yout also gives the minimum dimensions of different layers, along with the logical connections and main thing about layouts is that can be simulated and checked for errors which cannot be done with only stick diagrams.

Figure 21: Layout of inverter.


The layout shown above is that of a CMOS inverter. It consists of a pdiff (yellow colour) forming the pmos at the junction of the diffusion and the polysilicon (red colour) shown hatched ndiff (green) forming the nmos(area hatched).The different layers drawn are checked for their dimensions using the DRC rule check of the tool used for drawing. Only after the DRC (design rule check) is passed the design can proceed further. Further the design undergoes Layout Vs Schematic checks and finally the parasitic can be extracted.

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Figure 22: Schematic diagrams of nand and nor gate


We can see that the nand gate consists of two pmos in parallel which forms the pull up logic and two nmos in series forming the pull down logic. It is the complementary for the nor gate. We get inverted logic from CMOS structures. The series and parallel connections are for getting the right logic output. The pull up and the pull down devices must be placed to get high and low outputs when required.

Figure 23: Stick diagrams of nand gate.

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Figure 24: Layout of nand gate.

Figure 25: Stick diagram of nor gate.

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Figure 26: Layout of nor gate.

2.7 TRANSMISSION GATE

Figure 27: Symbo l and schemat ic of transmission gate Layout considerations of transmission gate. It consists of drains and the sources of the P&N devices paralleled. Transmission gate can replace the pass transistors and has the advantage of giving both a good one and a good zero.

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Figure 28: layout of transmissio n gate.

Figure 29: TG with nmos switches.


2.8 CMOS STANDARD CELL DESIGN
Geometric regularity is ver y important to maintain some common electrical characteristics between the cells in the library. The common physical limitation is to fix the height and vary the width according to the required function. The Wp and Wn are fixed considering power dissipation, propagation delay, area and noise immunity. The best thing to do is to fix a required objective function and then fix Wn and Wp to obtain the required objective Usually in CMOS Wn is made equal to Wp. In the process of designing these gates techniques may be employed to automatically generate the gates of common size. Later optimization can be carried out to achieve a specific feature. Gate array layout and sea of gate layout are constructed using the above techniques. The gate arrays may be customized by having routing channels in between array of gates. The gate array and the sea of gates have some special layout considerations. The gate arrays use fixed image of the under layers i.e. the diffusion and poly are fixed and metal are programmable. The wiring layers are discretionary and providing the personalization of the array. The rows of transistors are fixed and the routing channels are provided in between them. Hence the design issue involves size of transistors, connectivity of poly and the number of routing channels required. Sea of gates in this style continuous rows of n and

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p diffusion run across the master chip and are arranged without regard to the routing channel. Finally the routing is done across unused transistors saving space.

2.9 GENERAL LAYOUT GUIDELINES


1. The electrical gate design must be completed by checking the following a. Right power and ground supplies b. Noise at the gate input c. Faulty connections and transistors d. Improper ratios c. Incorrect clocking and charge sharing 2. VDD and the VSS lines run at the top and the bottom of the design 3. Vertical poysilicon for each gate input 4. Order polysilicon gate signals for maximal connection between transistors 5. The connectivity requires to place nmos close to VSS and pmos close to VDD 6. Connection to complete the logic must be made using poly, metal and even metal2 The design must always proceeds towards optimization. Here optimization is at transistor level rather then gate level. Since the density of transistors is large, we could obtain smaller and faster layout by designing logic blocks of 1000 transistors instead of considering a single at a time and then putting them together. Density improvement can also be made by considering optimization of the other factors in the layout. The factors are l. Efficient routing space usage. They can be placed over the cells or even in multiple layers. 2. Source drain connections must be merged better. 3. White (blank) spaces must be minimum 4. The devices must be of optimum sizes. 5. Transperent routing can be provided for cell to cell interconnection, this reduces global wiring problems

2.10 LAYOUT OPTIMIZATION FOR PERFORMANCE

l. Vary the size of the transistor according to its posit ion in series. The transistor closest to the output is the smallest. The transistor nearest to the VSS line is the largest. This helps in increasing the performance by 30 %. A three input nand gate with the varying size is shown next.

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Figure 30: Layout optimizat ion with varying diffusio n areas. 2. Less optimized gates could occur even in the case of parallel connected transistors. This is usually seen in parallel inverters, nor & nand. When drains are connected in parallel, we must try and reduce the number of drains in parallel i.e. wherever possible we must try and connect drains in series at least at the output. This arrangement could reduce the capacitance at the output enabling good voltage levels. One example is as shown next.

Figure 30: Layout of nor gate showing series and parallel drains.

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Recommended questions:
1. What do you mean by MOS layers. 2. Define st ick diagram. 3. Explain design rules and layout. 4. Explain lambda-based design rules and layout diagram with an example. 5. Explain physical design flow for a simple logic gates. 6. Explain wit h an example the design flow for basic gates.

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UNIT- 3

CMOS LOGIC STRUCTURES


CMOS complementary logic, BiCMOS logic, Pseudo-nMOS logic, Dynamic

CMOS logic, clocked CMOS logic, Pass transistor logic, CMOS domino logic cascaded voltage switch logic (CVSL).

Recommended readings:

1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI 3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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3.1 Introduction: The various applications that require logic structures have different optimizat ions. Some of the circuit needs fast response, some slow but very precise response; others may need large funct ionalit y in a small space and so on. The CMOS logic structures can be implemented in alternate ways to get specific optimizat ion. These optimizat ions are specific because of the tradeoff between the n numbers of design parameters. 3.2 CMOS COMPLEMENTARY LOGIC CMOS logic structures of nand & nor has been studied in previous unit. They were ratioed logic i.e. they have fixed rat io of sizes for the n and the p gates. It is possible to have rat io less logic by varying the rat io of sizes which is useful in gate arrays and sea of gates. Variable ratios allow us to vary the thresho ld and speed .If all the gates are of the same size the circuit is likely to function more correctly. Apart from this the supply vo ltage can be increased to get better noise immunit y. The increase in vo ltage must be done within a safet y margin of the source -drain break down. Supply vo ltage can be decreased for reduced power dissipat ion and also meet the constraints of the supply vo ltage. Sometimes even power down with low power dissipat ion is required. For all these needs an on chip vo ltage regulator is required which may call for addit ional space requirement. A CMOS requires a nblock and a pblock for complet ion of the logic. That is for a n input logic 2n gates are required. The variat ions to this circuit can include the fo llowing techniques reduction of noise margins and reducing the funct ion determining transistors to one polarit y. 3.3 BICMOS Logic The CMOS logic structures have low output drive capabilit y. If bipo lar transistors are used at the output the capabilit y can be enhanced. Bipolar transistors are current controlled devices and produces larger output current then the CMOS transistors. This combined logic is called BICMOS logic. We can have the bipo lar transistors both for pull up and pull down or only for pull up as shown in the figures below. The figure next shows a CMOS nand gate with NPN transistors at both levels. The Nl & N2 supply current to the base of the NPN2 transistor when the output is high and hence the it can pull it down with larger speed. When the output is low N3 clamps the base current to NPN2, Pl & P2 supply the base current to NPNl

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. Figure 1: Nand wit h two NPN drivers This design shown previously is basically used for speed enhancing in highly automated designs like gate arrays. Since the area occupied by the Bipo lar transistors is more and if the aim in the design is to match the pull up and pull down speeds then we can have a transistor only in the pull up circuit because p devices are slower as shown in the figure next. The usage of BiCMOS must be done only after a trade off is made between the cost, performance etc.

Figure 2: Nand with one NPN in pull up.

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3.4 PSEUDO NMOS LOGIC


This logic structure consists of the pull up circuit being replaced by a single pull up pmos whose gate is permanently grounded. This actually means that pmos is all the time on and that now for a n input logic we have only n+1 gates. This technology is equivalent to the depletion mode type and preceded the CMOS technology and hence the name pseudo. The two sections of the device are now called as load and driver. The Gn/Gp (Gdriver/Gload) has to be selected such that sufficient gain is achieved to get consistent pull up and pull down levels. This involes having ratioed transistor sizes so that correct operation is obtained. However if minimum size drivers are being used then the gain of the load has to be reduced to get adequate noise margin. There are certain drawbacks of the design which is highlighted next 1. The gate capacitance of CMOS logic is two unit gates but for pseudo logic it is only one gate unit. 2. Since number of transistors per input is reduced area is reduced drastically.

The disadvantage is that since the pMOS is always on, static power dissipat ion occurs whenever the nmos is on. Hence the conclusion is that in order to use pseudo logic a tradeoff between size & load or power dissipat ion has to be made.

Figure 3: Pseudo Nmos

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3.4.1 OTHER VARIATIONS OF PSEUDO NMOS 1. Mult i drain logic One way o f implement ing pseudo nmos is to use mult i drain logic. It represents a merged transistor kind of implementation. The gates are combined in an open drain manner, which is useful in some automated circuits. Figure 4.

Figure 4: Mult i drain logic. 3.4.2 GANGED LOGIC

The inputs are separately connected but the output is connected to a commo n terminal. The logic depends on the pull up and pull down ratio. If pmos is able to overcome nmos it behaves as nand else nor.

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3.5 DYNAMIC CMOS LOGIC:

Figure 5: Dynamic CMOS logic This logic looks into enhancing the speed of the pull up device by precharging the output node to vdd. Hence we need to split the working of the device into precharge and evaluate stage for which we need a clock. Hence it is called as dynamic logic. The output node is precharged to vdd by the pmo s and is discharged condit io nally through the nmos. Alternat ively you can also have a p block and precharge the n transistor to vss. When the clock is low the precharge phase occurs. The path to Vss is closed by the nmos i.e. the ground switch. The pull up t ime is improved because of the active pmos which is already precharged. But the pull down time increases because of the ground switch. There are a few problems associated with the design, like 1. Inputs have to change during the precharge stage and must be stable during the evaluate. If this condit io n cannot occur then charge redistribut ion corrupts the output node. 2. A simple single dynamic logic cannot be cascaded. During the evaluate phase the first gate will condit ionally discharge but by the time the second gate evaluates, there is going to be a finite delay. By then the first gate may precharge.

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3.6 CLOCKED CMOS LOGIC (C2MOS)

Figure 6: C2mos logic.

3.7 CMOS DOMINO LOGIC


The disadvantage associated with the dynamic CMOS is over co me in this logic. In this we are able to cascade logic blocks with the help of a single clock. The precharge and the evaluate phases retained as they were. The change required is to add a buffer at t he end of each stage. This logic works in the fo llowing manner. When the clk=0, ie during the precharge stage the output of the dynamic logic is high and the output of the buffer is low. Since the subsequent stages are fed fro m the buffer they are all off in the precharge stage. When the gate is evaluated in the next phase, the output conditionally goes low and the output of the buffer goes high. The subsequent gates make a transit ion fro m high to low.

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Figure 7: Cmos domino logic. Hence in one clock cycle the cascaded logic makes only one transit ion fro m 1 to 0 and buffer makes a transit io n fro m 0 to 1.In effect we can say that the cascaded logic falls like a line of dominos, and hence the name. The advantage is that any number of logic blocks can be cascaded provided the sequence can be evaluated in a single clock cycle. Single clock can be used to precharge and evaluate all the logic in a block. The limitat ion is that each stage must be buffered and only non- inverted structures are possible. A further fine tuning to the domino logic can also be done. Cascaded logic can now consist of alternate p and n blocks and avo id the do mino buffer. When clk=0,ie during the precharge stage, the first stage (with n logic) is precharged high and the second a p logic is precharged low and the third stage is high. Since the second stage is low, the n transistor is o ff. Hence domino connect ions can be made. The advantages are we can use smaller gates, achieve higher speed and get a smooth operation. Care must be taken to ensure design is correct.

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3.7.1 NP DOMINO LOGIC (ZIPPER CMOS)

Figure 8: NP domino logic.

3.8 CASCADED VOLTAGE SWITCH LOGIC


It is a different ial kind o f logic giving both true and co mplementary signal outputs. The switch logic is used to connect a combinational logic block to a high or a low output. There are static and dynamic variants .The dynamic variants use a clock. The st atic versio n (all the figures to shown next) is slower because the pulls up devices have to overcome the pull down devices. Hence the clocked versions with a latching sense amplifier came up. These switch logic are called sample set different ial logic. 3.8.1 STATIC CVSL

Figure 9: Static CVSL

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3.8.2 DYNAMIC CVSL

Figure 10: Dynamic CVSL

3.8.3 DYNAMIC SSDL CVSL

Figure 11: Dynamic SSDLCVSL.

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3.9 PASS TRANSISTOR LOGIC


Switches and switch logic can be formed from simple n or p transistors and from the complementary switch i.e. the transmissio n gate. The co mplex transmission gate came into picture because of the undesirable thresho ld effects of the simple pass transistors. Transmissio n gate gives good non degraded logic levels. But this good package came at the cost of larger area and co mplementary signals required to drive the gates

Figure 12: Some properties of pass transistor. 3.10 CMOS Technology Logic Circuit Structures Many different logic circuits ut ilizing CMOS techno logy have been invented and used in various applicat ions. These can be divided into three types or families of circuits: 1. Complementary Logic Standard CMOS Clocked CMOS (C2MOS) BICMOS (CMOS logic with Bipo lar driver) 2. Ratio Circuit Logic Pseudo-NMOS Saturated NMOS Load Saturated PMOS Load Deplet ion NMOS Load (E/D) Source Follower Pull-up Logic (SFPL)

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3. Dynamic Logic: CMOS Domino Logic NP Domino Logic (also called Zipper CMOS) NOR A Logic Cascade vo ltage Switch Logic (CVSL) Sample-Set Different ial Logic (SSDL) Pass-Transistor Logic

The large number of implementations shown so far may lead to confusio n as to what to use where. Here are some inputs 1. Complementary CMOS The best option, because of the less dc power dissipation, noise immuned and fast. The logic is highly automated. Avoid in large fan outs as it leads to excessive levels of logic. 2. BICMOS It can be used in high speed applicat ions with large fan-out. The economics must be just ified. PSUEDO NMOS Mostly useful in large fan in NOR gates like ROMS, PLA and CLA adders. The DC power can be reduced to 0 in case of power down situations Clocked CMOS Useful in hot electron susceptible processes. CMOS domino logic Used most ly in high speed low power applicat ion. Care must take of charge redistribution. Precharge robs the speed advantage. CVSL This is basically useful in fast cascaded logic .The size; design co mplexit y and reduced no ise immunit y make the design not so popular. Hybrid designs are also being tried for getting the maximum advantage of each of them into one.

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Recommended Questions:
1. Explain difference between BiCMOS and CMOS complementary logic. 2. Write a note on Pseudo-nMOS logic. 3. Write a note on dynamic CMOS logic and Clocked CMOS logic. 4. Explain pass transistor logic. 5. Explain CMOS domino logic wit h neat diagram. 6. Explain cascaded vo ltage switch logic.

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Unit-4
Basic circuit concepts
Sheet resistance, area capacitances, capacitances calculations. The delay unit, inverter delays, driving capacitive loads, propagation delays, wiring capacitances.

Scaling of MOS circuits


Scaling models and factors, limits on scaling, limits due to current density and noise.

Recommended readings:

1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI 3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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4.1 INTRODUCTION
We have already seen that MOS structures are formed by the super imposit ion of a number conducting, insulat ing and transistor forming material. Now each of these layers have their own characterist ics like capacitance and resistances. These fundamental co mponents are required to estimate the performance of the system. These layers also have inductance characterist ics that are important for I/O behavior but are usually neglected for on chip devices. The issues of prominence are 1. Resistance, capacitance and inductance calculations. 2. Delay est imat ions 3. Determinat ion of conductor size for power and clock distribut ion 4. Power consumpt ion 5. Charge sharing 6. Design margin 7. Reliabilit y 8. Effects and extent of scaling 4.2 RESISTANCE ESTIMATION The concept of sheet resistance is being used to know the resist ive behavior of the layers that go into format ion of the MOS device. Let us consider a uniform slab of conduct ing materia l of the fo llowing characterist ics. Resist ivit y- Width - W Thickness - t Length between faces L as shown next

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Figure 1: A slab of semiconductor. We know that the resistance is given by RAB= L/A . The area of the slab considered above is given by A=Wt. Therefore RAB= L/Wt . If the slab is considered as a square then L=W. therefore RAB= /t which is called as sheet resistance represented by Rs. The unit o f sheet resistance is ohm per square. It is to be noted that Rs is independent of the area of the slab. Hence we can conclude that a 1um per side square has the same resistance as that of 1c m per side square of the same material. The resistances of the different materials that go into making of the MOS device depend on the resistivit y and the thickness o f the material. For a diffusio n layer the depth defines the thickness and the impurit y defines the resist ivit y. The table of values for a 5u technology is listed below.5u techno logy means minimu m line width is 5u and = 2.5u.The diffusio n ment ioned in the table is n diffusio n, p diffusion values are 2.5 times o f that of n. The table of standard sheet resistance value fo llows.

SHEET RESISTANCE OF MOS TRANSISTORS

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Figure 2: Min sized inverter.

Figure 3: Nmos depletion inverter. Pull up to pull down ratio = 4.In this case when the nmos is on, both the devices are on simultaneously, Hence there is an on resistance Ron = 40+10 =50k. It is this resistance that leads the static power consumption which is the disadvantage of nmos deplet ion mode devices

Figure 4: CMOS inverter.

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Since both the devices are not on simultaneously there is no static power dissipat ion The resistance of non rectangular shapes is a litt le tedious to est imate. Hence it is easier to convert the irregular shape into regular rectangular or square blocks and then est imate the resistance. For example

Figure 5: Irregular rectangular shapes. CONTACT AND VIA RESISTANCE The contacts and the vias also have resistances that depend on the contacted materials and the area of contact. As the contact sizes are reduced for scaling ,the associated resistance increases. The resistances are reduced by making ohmic contacts which are also called loss less contacts. Currently the values of resistances vary from .25ohms to a few tens of ohms. SILICIDES The connect ing lines that run fro m one circuit to the other have to be optimized. For this reason the width is reduced considerably. With the reduction is width the sheet resistance increases, increasing the RC delay co mponent. With poly silicon the sheet resistance values var y fro m 15 to 100 ohm. This actually effects the extent of scaling down process. Polysilicon is being replaced wit h silicide. Silicide is obtained by deposit ing metal on po lysilicon and then sintering it. Silicides give a sheet resistance of 2 to 4 ohm. The reduced sheet resistance makes silicides a very attractive replacement for poly silicon. But the extra processing steps is an o ffset to the advantage.

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A Problem A particular layer of MOS circuit has a resist ivit y of 1 ohm cm. The sect ion is 55um lo ng, 5um wide and 1 um thick. Calculate the resistance and also find Rs R= RsxL/W, Rs= /t Rs=1x10-2/1x10-6=104ohm R= 104x55x10-6/5x106=110k CAPACITANCE ESTIMATION Parasit ics capacitances are associated with the MOS device due to different layers that go into its format ion. Interconnection capacitance can also be formed by the metal, diffusion and polysilicon (these are often called as runners) in addit ion wit h the t ransistor and conductor resistance. All these capacitances actually define the switching speed o f the MOS device. Understanding the source of parasit ics and their variat ion beco mes a very essent ial part of the design specially when system performance is measured in terms of the speed. The various capacitances that are associated with the CMOS device are 1. Gate capacitance - due to other inputs connected to output of the device 2. Diffusio n capacitance - Drain regions connected to the output 3. Routing capacitance- due to connect ions between output and other inputs The fabricat ion process illustrates that the conducting layers are apparent ly separated from the substrate and other layers by the insulat ing layer leading to the format ion of parallel capacitor s. Since the silicon dioxide is the insulator knowing its thickness we can calculate the capacitance

The gate to channel capacitance formed due to the sio2 separation is the most profound of the ment ioned three types. It is direct ly connected to the input and the output. The other capacitance like the metal, poly can be evaluated against the substrate. The gate capacitance is therefore standardized so as to enable to move from one technology to the other convenient ly. The standard unit is denoted by Cg. It represents the capacitance between gate to channel wit h

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W=L=min feature size. Here is a figure showing the different capacitances that add up to give the total gate capacitance Cgd, Cgs = gate to channel capacitance lumped at the source and drain Csb, Cdb = source and drain diffusio n capacitance to substrate Cgb = gate to bulk capacitance Total gate capacitance Cg = Cgd+Cgs+Cgb Since the standard gate capacitance has been defined, the other capacitances like polysilicon, metal, diffusion can be expressed in terms of the same standard units so that the total capacitance can be obtained by simply adding all the values. In order to express in standard values the fo llowing steps must be fo llowed 1. Calculate the areas of area under consideration relat ive to that of standard gate i.e.42. (standard gate varies according to the technology) 2. Mult iply the obtained area by relat ive capacitance values tabulated. 3. This gives the value of the capacitance in the standard unit of capacitance Cg. Table 1: Relat ive value of Cg

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For a Su technology the area of the minimum .ized tran.ist or is Su Su=-Sum2 ie : .=2.Su. hcnce.area of minimum .izec.l t ran i. tor in lambda is 2:; :. = .2.Th refore for 2u or l._u or any other technology the aren of a minimum sized t ran.i.t r in lambda is "- Let. . olve a few pr blcm. to get to know the things be tter. 4)

Figure 6 :Multilayered structure

TIP figure above h w the dimen ion and the intemction of different layer . for evaluating the total capacitance re. ulling o. Thre capacitance t o b evaluated metalCm.poly ilicon
Area of metal = I00x 3=300:;2 Rel ative area= 300/4=75 Cm=75Xrela tive cap=75X0.075=5.625D Cg Polysilicon capacitance Cp Area of poly=(4x4+Ix 2+2X 2)=22:;2 Rel ative area = 22: 2/4:; 2=5.5 Cp=5.5Xrelative cap=5.5x.1=0.55 D Cg Gate capac itance Cg= ID Cg becau e it is a min size gate Ct=Cm+Cp+Cg=5.625+0.55+I=7.2 D Cg

p and ga te capacitance g

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50

4:.

50

31

2J.

Cin

Figure 7 :Mos structure


The input capacitan ce i s made of three componen t metal capacitance Cm , poly capacita nce Cp, gate capacitance Cg i.e Cin= Cm+Cg+Cp R el ative area of metal =(50x3)X2/4=300/4=75 Cm =75x0.075=5.6251J Cg Rel ative area of pol y = (4x4+2x 1 +2x2)/4 =2214 =5.5 Cp=5.5XO. l =0.55 IJ Cg Cg=l IJ Cg Cin= 7.175 IJ Cg Cout = Cd+Cperi. Assuming Cperi to be negl igible. Cout = Cd. R elative area of d iffu ion=51 x2/4= I 0214=25.5 Cd=25.5x0. 25=6.25 IJ Cg. The relati ve va l ues a re for the Sum technol ogy

DELAY The concept of sh eet resi stance and tandard unit capacitance ca n be used to ca lcul ate the delay. If we consider that a o ne feature ize poly is ch arged by one featu re si ze d iffusion then the delay i s Time consta nt 1 == Rs (n/p cha nn el )x I IJ Cg sees. Thi s can be evaluated for any tech nology. The va lue of IJ Cg w ill vary wi th d ifferent technologie because of the varia tion in the minimum feature size.

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4.3 INVERTER DELAYS


We have seen that the inverter is associated with pull up and pull down resistance values. Specially in nmos inverters. Hence the delay associated with the inverter will depend on whether it is being turned off or on. If we consider two inverters cascaded then the total delay will remain constant irrespective of the transit ions. Nmos and CMOS inverter delays are shown next. NMOS INVERTER

Figure 8: Cascaded nmos inverters.

4.4 CMOS INVERTER:

Figure 9: Cascaded CMOS inverter.

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4.5 FORMAL ESTIMATION OF DELAY


The inverter either charges or discharges the load capacitance CL. We could also estimate the delay by est imat ing the rise time and fall t ime theoretically.

Figure 10: Rise t ime est imation.

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4.6 DRIVING LARGE CAPACITIVE LOAD


The problem of driving large capacit ive loads arises when signals must travel outside the chip. Usually it so happens that the capacitance outside the chip are higher. To reduce the dela y these loads must be driven by low resistance. If we are using a cascade of inverter as drivers the pull and pull down resistances must be reduced. Low rsistance means low L: W ratio. To reduce the ratio, W must be increased. Since L cannot be reduced to lesser than minimum we end up having a device which occupies a larger area. Larger area means the input capacitance increases and slows down the process more. The solut ion to this is to have N cascaded inverters with their sizes increasing, having the largest to drive the load capacitance. Therefore if we have 3 inverters,1st is smallest and third is biggest as shown next.

Figure 11: Cascaded inverters with varying widths.

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4.7 SUPER BUFFER


The asymmetry of the inverters used to solve delay problems is clearly undesirable, this also leads to more delay problems, super buffer are a better solution. We have a inverting and non invert ing variants of the super buffer. Such arrangements when used for 5u techno logy showed that they were capable o f driving 2pf capacitance with 2nsec rise time. The figure shown next is the inverting variant.

Figure 12: Inverting buffer.

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Figure 13: NonInvert ing buffer.

4.8 BICMOS DRIVERS

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By taking certain care during fabricat ion reasonably good bipo lar devices can be produced with large hfe, gm , and small Rc. Therefore bipo lar devices used in buffers and logic circuits give the designers a lot of scpoe and freedom .This is coming wit hout having to do any changes wit h the CMOS circuit.

4.9 PROPAGATION DELAY

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4.10 DESIGN OF LONG POLYSILICONS


The fo llowing points must be considered before going in for long wire. 1. The designer is also discouraged from designing long diffusion lines also because the capacitance is much larger. 2. When it inevitable and long po ly lines have to used the best way to reduce delay is use bu ffers in between. Buffers also reduce the no ise sensit ivit y.

4.11 OTHER SOURCES OF CAPACITANCE


Wiring capacitance 1. Fringing field 2. Interlayer capacitance 3. Peripheral capacitance

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The capacitance are profound when the devices are shrun k in sizes a nd hence must be con idered. Now the total diffusion capacita nce is Ctotal = Carea + Cperi I n order to reduce the ide wall effect , the designer con ider to u e i a lat io n region of alternate impurity.
CHOICE OF LA YEAS

I.Vdd and V s l ines mu t be distri buted on meta l lines except for orne exception 2.Long lengths of poly mu t be avoided becau e they have large R ,it i not uitable for routing Vdd or Vs lines. 3.Since t he re i tance effect of the tran i tor are much l arger, hence wiring effect due to voltage divider are not that profound Capacitance mu t be accuratel y ca lcu lated for fa t igna l l i nes usually tho e u ing h igh R materia l. Diff u ion area must be carefully handl ed because t hey have l arger capacitance to substrate. With all the a bove inputs it is better to model wires as small capacito r give electrica l guidelines for com muni cation ci rcu i ts. which will

PROBLEM S l.A pa rticular section of t he layout incl udes a 3; wide metal pat h which crosse a 211 polysilicon path at right angles. A uming that the layer are eperated by a 0.5 thick sio2,find the capacita nce between the two.
Capacitance = = 0 = in ND Let the technology be Sum,=2.5u m. Area= 7.5umX5um=37.5u m C=4X8.854Xl0-12 x37.5/ 0.5 =2656pF The value of C in tandard units i Rel at i ve area 6 112 /42 =1.5 C = 1.5x0.075=0.1125!J Cg
2 nd part of the problem

The poly ilicon turns across a 4. diffusion layer, f ind the gate to channel capacita nce. Area = 2 :\X 4:\ =82 Relati ve area= 8 :\2 I 4 112 =2 Relati ve capaci tance for 5u = I Tota l ga te capacitance = 2!J Cg Gate to c hannel capacitance>metal CITSTUDENTS.I N
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2. The two nmo tra nsi tors are ca caded to drive a load capacitance of 1 6!J Cg a show n in figure ,Ca1c u late the pair dela y. What are the ratios of each tra nsistors. f stray and wiring capaci ta nce i to be con idered the n each inverter will have an additi ona l capacitance at the output of 4 !J Cg .Find the delay.

v-=-r
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CL

Figure 40 Lpu= I 6. Wpu=2 ;; Zpu=8 Lpd= 2. Wpd =2 ;\ Zpd=1 Ra ti o of inverter 1 = 8: I Lpu = 2. Wpu =2 ;\ Zpu =1 Lpd =2 ;\ Wpd =8. Zpd=114 Ra ti o of inverter 2 = I/1/4=4 Delay without strays 1 = =R xl !J Cg Let the input transiti on from 1 to 0 Delay I= 8R X!J Cg=8 = Delay w i th trays Delay I = 8R X(!J Cg+ 4!J Cg) = 40 = Delay 2= 4R X(!J Cg+ 4!J Cg +I 6 !J Cg)=84 = Total delay = 40+84= I 24 = If = = 0. I ns for 5u i e the del ays are 7.6n a nd 1 2.4n Delay 2=4Rs(!J Cg +1 6 !J Cg)=68 = Total delay= 76 =

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4.12 SCA LING OF MOS DEVICES

The VLSI technology is i n the proces of evol ution lead i ng t o red u ct i on of the feature si ze a nd line width . Thi proces is called cal in g down. The reduction in sizes ha generall y lead to be tter performance of the device . There are ce rta in limits on caling and it becomes i mportant to st ud y the effect of scaling. The effect of scal ing mu t be studied for certain parameter that effect the performance. The parameters a re as tated below J.Minimum feat ure ize 2.Num ber of ga tes on one chip 3.Power eli sipation 4.Maximu m operational frequency 5.Die ize 6.Production cost . These areal o call ed as figures of merit Ma ny of the mentio ned factor ca n be improved by hrinking the ize of tran i tors, interconnects, sepa ration between devices a nd also by adjusti ng the voltage and d oping l evels. Therefore it becomes essent ial for the desi gners to implement caling a nd unde rstand it effect on the performance The re are three types of scaling models u eel J.Con ta nt el ectric field ca l ing model 2.Con ta nt vol tage caling model 3.Co mbined voltage a nd f ield model The three models make u e of two ca ling factor 1/B a nd 1/a . 1/B is chose n a the caling factor for Veld, gate ox ide thickne D. 1/ a i s cho en as the ca l ing factor for a ll the linear dimen ions l i ke l ength, width etc. the figure nex t bows the di rnen ions a nd their cal ing factor The foll owi ng are some simpl e derivation for ca lin g down the device pa rame ter l.Gate area Ag Ag= L x W. Since L & Ware scaled down by 2.Gate capacitance per unit area Co= = o/D, permittivity of si o2 ca nnot be scaled he nce Co ca n be sca led 1/l/B= B CITSTUDENTS.I N
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a. Ag is

ca led dow n by 1/ 6?

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3.Gate capacitance Cg
Cg=CoxA=CoxLxW. Therefore Cg can be ca led by Bx1/ a2

ax 11 a= B/

4.Parasitic capacitance
Cx =Axld, where Ax i the area of t he dep letion arou nd the dra in or ou rce. d i the depletion width .Ax is ca led down by I/a2 and d is cal ed by 1 /a. Hence Cx i caled by l /a2 1lla= 1 1a

S.Carrier de nsity in the channel Qon


Qon =Co.Yg Co is caled by B and V gs i caled by 1 I B,hence Qo i scaled by Bx liB = l.

Channel resistance Ro
Ron = UW x 1 /QoxL,
L

i mobil ity of charge carrier . Ro is caled by I /<ill I ax I= I

Gate delay Td
Tel is propot1iona l to Ro a nd Cg Tel is ca led by l x B!&.? = B/a2

Maximum operating freque ncy fo


fo=1 /td,therefore it is scaled by 1 / B/a2 = a2/B

Saturation curre nt
Ids = Co tW(Ygs-Yt)/2L, Co cale by Band voltages by 1/ B, Id s i calecl by B /82= 1/B =

Current Density
J=Id /A hence J i scaled by l /B/l /a2

a? /B

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1.\\'hat is Scaling?
Proporti ona l adjust ment of the d imen ions of a n el ectron ic dev ice while main ta ining t he e lect ri ca l propertie of the dev i ce, re ult in a dev i ce ei t her larger o r smaller t ha n the u n -sea led devi ce. Then Which way do we scale the devices for V LS I ? BIG and S LOW . .. or SMA LL and FAST ? What do we gain?

2.Wh y Scalin g?...


Sca le the dev ices a nd w i res dow n, Make the chips 'fatter' - f unction a l i ty intel li gen ce, m emory- a nd - faster, Make more chips per wafer - increa ed y ie ld, Make the end use r Happy b y gi v ing more for less a nd therefore, make MORE MONEY!!

3.FoM for Scaling


Impact of ea ting is ch a racterized i n terms of eve ra l indicators: o Min i mum feat u re i ze o Num ber of gates on one chip o Power dissipa tion o Max i mum operatio na l frequency o Die size o Produ ction cost Man y of the FoMs ca n be i mproved by shrinking the dimensions of tra nsi stors a nd interconn ections. Sh rinking the sepa ration between fea tures - tra n sistors and w ires Adjusting doping levels a nd su pply voltages.

3.1 Technology Scaling


Goa ls of sca ling the d imensi ons by 30%: Red u ce gate del ay by 30% (in crease opera ting freq uency by 43%) Doub le t ra nsistor density Red u ce e nergy per transi tion by 65% (50% power sav in g Die size used to in crease by 14% per ge neration Technol ogy gen era ti on spa ns 2-3 yea rs
@

43% increase in f requency)

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Figure I to Figure 5 illustra tes the techno l ogy sca l i ng i n terms of minimum feature size, tra nsistor count, prapogation de lay, power dissipation a nd density a nd techn o logy generation .

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1996

1997

Figu re-2:Tech nology Sca l in g (2)

Fundam entals of CMOS VLSI

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10

r----------r---------- -------- ----------,---------

gate delay (ns)

10-

2 --------

1960

1970

--------

1980

----------

1990

--------

2000

--------

2010

Propagation Delay
Fi gure-3:Technol ogy Sca lin g (3)

.
100 10

I <f

I I

1000

1
100
c
'l:l

/( - - ---

I
IJ

10

f-

_
..E _,

0..

I fIJ

ci:

0.1

f-

ll

IP
IJ D

MPU c DSP
I

I I IJ I I I I

I I

0.01

90 Year (a) Power dissi pation vs. year.

80

85

95

Scali ng Factor K ( normal ized by 4 f.lln design ru le (b) Power densi ty vs. sca l ing factor.

lO

Figure-4:Technol ogy Sca lin g (4 )

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Technology Generations

cs
G 3
1
-1

r:t;.

()6

12

4 2
,!IU

3 1

5 4 II
4 &

n-n

2
-1

3
7t:

Fi gure-5:Technol ogy ge ne rat i on

4.

International Technology Roadmap for Semiconductors (ITRS)


Ta ble I lists the parameters for va tious technol ogies as per ITRS.

Year of lntroduc11on Technology node (nm) SupplyM Wiring levels

1999 180

2000

2001 130

2004
90

2008 60

2011 40

2014 30

1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6


6-7

6-7

9-10

10 14.9
-3.6

Max frequency [GHz],Local-Global Max JLP power (W]

1.2 90 1.4

1.6-1.4 2.1-1.6 106 1.7 130 2.0

3.52 160 2.4

7.1-2.5 171 2.1

11-3 171 2.3

186 2.5

Bat. power (W]

Node years: 2007/65nm, 2010/45nm, 2013133nm. 2016/23nm


Ta ble I: ITR S

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S. Scaling Models
0 Full Scal i ng (Consta n t El ectrica l Fiel d) Idea l model- dimensions and vol tage cal e together by t he sa me ca le factor

0 Fixed Vol tage Scal i ng Most com mon model unti l recentl y - onl y the dimensions sca l e, vol tages remain constant 0 Genera l ScaJing Most real istic for today's si t ua tion- vol tages and dimen ions sca le wit h differen t factor

6. Scaling Factors for Device Parameters


Dev i ce sca lin g m odel ed in terms of generic sca l i n g factors: 1/a a nd liP liP: sca ling factor for suppl y voltage Voo and gate ox ide thickness D 1 /a: li near dimen ion both hori zonta l and vertical dimen ion

Wh y is the sca l ing factor for gate ox ide t h ickness d ifferent f rom other linea r horizonta l and vertica l di me nsions? Consi der t he cross section of t he dev ice as in Figure 6,vari ous para meters deri ved a re as fol l ows.

1
I

I. I a
Si0 2

,:

--------------

N+

P-

Figure-6:Techn ol ogy ge nera t i on

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Gate area A n

"

A g = L*W

Where L: Channel length a nd W: Channel w idth and both are ca led by l la Thu Ag is ca led up by l la2 Gate capaci tance per unit area Co or Cox Cox = EoxiD Whe re ox is permittivit y of gate ox ide(thin-ox)= ins0 a nd D i s the ga te ox ide thickness 1 ca led b liP Thu C0, i caled up by () = fJ

Gate capacitance Cg Thu Cg i

Cg =Co* L *W

caled up by

P* II a?=PI

a2

Para itic capaci t ance Cx

Cx is proportional to Axfd where d i the depletion width a round ource or drai n and caled by I I a Ax i s the a rea of the depletion region aro und ource or drain, sca led by ( I I a2 Thu Cx i ca led up by { l l( l la) }* (II a2 ) = I I a. Canier density in cha nnel Q0n
).

Qon =Co * Ygs where Qon i s the average charge per unit area in the 'on ' sta te. C0 i caled by p a nd Ygs i ca led by I I p Thu Q0n i s caled by I Channel Re ista nce Ron

R =-*--on W Qon * Jl
Where )..1. = chann el ca rrier mobi l ity a nd assumed con tant

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Thu Ran i

caled by I.

Gate delay Td Td i s proportiona l to Ron *Cg

Td i s scaled by Max imum operating frequency fa

fa is i n ver el y pro portio nal to delay Td a nd i scaled by

Satura tion current Idss

dss

= Co f.l * W * (V -V\2
2 L
gs
t

Both Vgs a nd V 1 are caled by ( 1 / ). Therefo re, ldss is sca led by Cu rren t densi ty 1 J I dss CuJTent de nsit =A w here A i s cross sec tional area of the y, Ch annel in the "on" state w hich i scaled by ( I/ a?). So, J is caled by

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Swi tching energy per gate Eg


= - Cg VDD

So Eg is scaled by

Power di ssipation per gate Pg

pg

= pgs + pgd

Pg co mpri ses of two components: sta tic component Pgs a nd dynami c compo ne nt Pgd:

Wh ere, the

ta tic power componen t i given by:

And the d yn amic component by: Since Yoo sca l e by ( I/) and Ron

Pgd

= Eg fo
2 ).

cale by I, Pgs sca l e by ( 1 /

Since Eg ca l e by ( Ita?) and fo by (a2 /), Pgd a l o sca l es by ( 1/


2 ).

ca l e by ( 1 /

2).

Therefore, Pg

Power dissipat ion per unit area Pa

P [;,) a' P= g = =' A, ( 1) {J'


Power- speed product PT

6.1 Scaling Factors ...Su mmary


Ya1iou s dev ice pa ram eters for dif ferent sca l ing mod els are l i sted in Ta b le 2 bel ow.

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Table 2: Device pa rameters for scaling models


NOTE: for Con ta n t E:=a.; for Consta n t V:= I
Para mete rs Description Ge ne ra l Consta nt E (Combined V a nd Dimension) Con tant V

Voo

Su pply vol tage Cha nnel l ength Cha nnel w id th Gate oxid e thi ckness Gate area Gate capacitance per uni t a rea Gate capacitance Par itic capaci tance Carrie r d ensity Channel resistance Satu ration cu rre nt

w
D Ag
Co (or Cox) Cg

liP 1/a 1/a liP 1/ az

1/a 1/a 1/a 1/a l/a2 a 1/a 1/a


11

1 1/a 1/a
1 llaz 1

p
Pla2 1/a

Cx
Qon Ron

l/a2 1/a
1 1

,t
'1 liP

'I
l/a

lds

Parameters

Descri ption Conductor cross section a rea Current d ensity Logic 11evel Switching energy

Consta nt E General (Combined V a nd Dimensi on) 2 l/a2 1/a a2 I 11


2

Consta nt V

l/a2 a2
1

Ac

J
Vg Eg

a 1la 1I a 2 1/a a2 1 1la a 1I a3


3

Pg
N

Pa Td
fo

PT

11a Power dissipation per 1/ 2 ate a2 Gates per unit a rea Power d issipa tion per a2 1 2 unit a rea I a2 Gate dela y Max. ope rating a2 I frequency Power SJ>eed product 11a2

2 1/ a 1 a2 a2 l/a a2 2

2 1/a

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7.Implications of Scaling
0 Im proved Perform a n ce 0 Im proved Cost 0 In terco nnect Woes 0 Power W oe 0 Prod u ctiv ity Chall en ges 0 Ph ysi cal Li n1jts 7.1Cost Improvement
Moore's Law i stiJI going strong as illustra ted in Fi gure 7.
Un s

/
1011

0.1

/
/

MO 1
0.0 I

"'
'-..

/ /
10"

0.000 0.0000 0.000001 0.000000

"-.....
aa '90 '!12 '94 '96 '911 ooo2F

1.-/

,
'68 70 '72 '74 76 '7! '80 '82 '84 '86

"'

Fi g u re-7:Technol ogy ge nerati on

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7.2:Interconnect Woes Sca led transi stors are stead i l y i mproving in delay, but sca led wires are ho ld i ng con tant or getting wor e. SIA mad e a gloomy foreca t in 1 997 Del ay would reach minim um at 250 - 1 80 nm , then get worse because of wires But . . . For short wires, su ch as those inside a l ogi c ga te, the wire RC del ay i s negli gi bl e. However, the lon g w i res present a considerable ch al l enge. Sca led tran i tor a re teadi l y i mprov ing in del ay, but sca led wire a re ho ldi ng constant or getti ng wor e. SIA made a gloomy forecast i n 1 997 Del ay would reach minim u m at 250- 1 80 nm, then get wor e because of wires But . . . For hort wire , u ch a tho e in ide a l ogic ga te, t he wire RC del ay i neg l i gibl e. However, the lon g w i res present a considerable ch al l enge. Figu re 8 illu tta te de l ay V . ge nerati on in nm for d ifferent m ateri al .
45 40

-*" Gat O.loy

:
l Gste

11- Sum of Delays., AI & SI01

,...

Sum of De-l ays. Cu & Low ..:

30

AI & 510,

20

15 10

- "'"
500

/j Jj

//

..... lntorconnoct O.ly.AI & SiO,

-+AI

lnte rco nneet Delay, Cu & low ..-

... ...

_ ---

7l
/

cu

3.0) fl-Gm
... - 4. 0

I w-.: &Lo

w iC. .

J.

S!Oz
AI & CU AI& CuLine

_" ..5"
--,
130 100

.8,,, Thick 43!' Long

k:: -< ..-- v"'


.J..--'r""
p--350 250 180 Generation (nm)

650

Fi g ure-8:Technology generation

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Fundam entals of CMOS VLSI

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7.3 Reachable Radius


We can ' t end a si g na l aero a l arge fast chip in one cycle a n y more

But the microarchitect can plan around this as sh own in Fi gure 9. Just as off-ch i p memory l a ten cies were tolerated
Chip size
Scaling of reachable radius

Figure-9:Technol ogy ge nera tion


7.4 Dynamic Power Intel VP Pat rick Gel sin ge r (ISSCC 2001)
- If sca ling continues a t present pace, by 2005, hi g h speed processors wou ld have powe r densi t y of nuclear reactor, by 20 1 0, a rocket nozzle, a nd by 20 1 5, urface of un. "Bu ine a usual will not work in the future." At tention to power i increa in g(Fi gu re 10)

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100000 10000

f
L

1000 100 10
1

Q)

...

0.1 1971 1974 1978 1985 1992 Year 2000 2004 2008

Figure- I O:Technology genera tion

7.5 Static Power Y oo decreases


Save dynamic pow er Protect thin ga te ox ide a nd short cha nnel No point in h igh va l ue becau e of ve l ocity saturation.
Y 1 mu t decrea e to m a jntain device perform a n ce

But thi ca u ses exponentia l increa e in OFF leakage


A Major future ch a llenge(Fi gure I I)
100 0 -----------------------------.

...
3:
Q)

100

10

0 ==

1 a.. 0. 0. 01 0 . 001 -f-----..,-----,.-----.,------,.-----1 196 0 1970 1980 1990 20 00 2010

Moore(03) Figure- I I :Techn ol ogy ge nera tion

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7.6 Productivity Tra nsi tor count is increa ing f a ter th a n desi gner producti vity (ga tes I week
) Bi gger de ig n tea m Up to 500 for a hi gh-end microprocessor

More ex pensi ve de i gn co t Pressure to raise producti vity Rel y on sy nthesis, IP block

Need for good en gineering ma n agers

7.7 Physical Limits


o Will Moore' Law run o ut of steam ? Can ' t bui ld tran i stors small er than a n ato m .. . o Many rea o n have bee n predi cted for end of cal in g o Dy nami c power Sub-threshold leak age, tunneling Short cha nnel effects Fabri ca ti on costs Electro-mi grati on Interconnect del ay

Rumors of demi e have been exaggerated

8. Limitations of Scaling

Effects, as a resul t of sca l in g down- w hi ch eventua ll y beco m e severe enough to preve nt f urther mini aturi zation. o Sub trate doping o
!

Depl etion width Limit of min i aturiza ti on

' '

Fundamentals of CMOS VLSI

10EC56

o o o o

Lim i ts of inte rconnect and contact resistan ce Lim i ts due to sub threshold currents Lim i t on l ogi c l evel a nd uppl y voltage due to noi e Lim i ts due to curren t densi ty

8.1 Substrate dopi ng o Substrate doping


o Built-i n U un ction ) potenti al VB depends on substra te doping level- ca n be neglected as l on g as V 8 i s sm aJI compared to V oo.

o A s length of a MOS tra n i stor is reduced, the depleti on regi on w idth - ca led d ow n to p revent ource a nd dra i n depletion region f rom m ee tin g. o the depletion region w idth d for the junctions is d

fi ?si ?oV .

Ny

o o

si

rel a ti ve permitti v i ty of il icon permitti v ity of free s pace(8. 85*10- 1 4 F/cm)

o V effecti ve vo ltage across the junction Ya + Vb o q electron ch a rge o o


0

Ns doping l evel of substra te

Ya m ax imum va lue Vdd-ap plied vol tage


v b built i n poten tial a nB

= KT
q

ln[ NB N/)
n; n;

8.2 Depletion width


N 8 is increased to redu ce d , but this increases threshol d voltage Y 1 trends for sca lin g dow n.
19 3

-against

M ax imum val u e of N 8 (1 .3* I 0 cm - , at higher va lues, max imum el ectri c fi eld a pplied to gate is insu fficient a nd no c ha nnel is formed. N s m ain ta ined at sa ti factor y l evel in the cha nnel region to reduce the above problem.

Emax

max imum el ect ri c field i ndu ced i n the junction.

= 2V
d

Fundamentals of CMOS VLSI

max

10EC56

Fundamentals of CMOS VLSI

10EC56

lfN

mrea ed by a Y a =0 Yb 1ncrea ed by In a and d

decreased by

El ectric field acros the depleti on reg10 n 1 increa ed by


1/

{I;W

----;;Reach a criti ca l leve l Ecrit


d

Where

w ith increa ing N B

= ;si

;o ( . )
C fl l

q NB

Figure 1 2 , Fi gure 1 3 a nd Figure 1 4 shows t he rel a tion bet ween ub tra te conce ntration V de pleti on w idth , Electric field a nd tra n sit time. Figure 15 demo n trate the interconnect length V p ropaga ti on del ay a nd Figure 1 6 ox ide thickne s Y . therma l noi e.

d versus N n lor Vlrom 0 lo 50 V

10

10

10

1 1'\

10 '

7 1

10

10'

Substrato concontr !lion /em

Fi gure- 1 2:Tec hno l ogy genera ti on

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c..,.t

e\'8r.WS N 8

lor

v. from

0 /0 5 0

Sub.. tra1 e concentratiOn tcrn3

Fi gure- 1 3:Techn ol og y ge n eration

8.3 Limits of m iniatu rization m i nimum si ze of tra nsistor; p roce

tec h and physi cs of the devi ce

Redu ct i on of geo metry: a lignme nt accuracy a nd re olut ion

Size of tra nsistor measured in term of cha nnel le n gth L L=2d ( to preve nt pu h th rough) L determined by N 8 a nd Veld Minimum tra nsit time for an elect ron to travel f rom ource to dra in is
V d rift

JLE
2d

t=--=vdriji

;.

max imum carrier drift velocity is a pprox. Vsat, rega rd less of uppl y voltage

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5 V ?. V

(a )

Figure- 1 4:Technology generation

8.4 Limits of interconnect and contact resistance


Short di tance interconnect - conduc tor length increa ed by a For constant f eld scaling, 1 is scaled by 1 / a so that IR drop remains constant as a result of scaling.-driving capability/noise margin. caled by 1 /a and re tance i

Figurc-15 :Tcchnology gcnc ta tion

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8.5 Limits due to subthreshold currents


M ajor concern in sca ling dev ices. I sub is d i rectly praportina l exp (Vgs- Yt ) q/KT As vol tages are caled dow n, ratio of V gs-Vt to KT wi ll red uce- o tha t thre hold current increases. Therefore ca ling V g a nd Yt together wi th Vdd . M aximum el ectric field across a depletion region i s

8.6 Limits on supply v oltage due to noise


Decrea eel inter-fea ture paci ng a nd greater witching peed -re ul t in noi e problem

o
a)

0 2

0 ..,.

oa

oe

'o

.2

Ox.UO 1h o cknoa. (1 .,.-") I n'''""

Figure-1 6:Tec hnol ogy generati on

9. Obser vations - Device scaling


o Gate capaci t a n ce per micron i s nearl y ind epend ent of proce o But ON resi ta n ce

* micron

improves with process

o Gates get fa ter with ca ling (good) o Dynam i c power goes down with ca ling (good) o Current den ity goe up with ca ling (bad) o V el ocit y sa turation makes lateral sca l ing unsustainable

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9.1 Observations - Interconnect scaling


o Ca pacitan ce per mi cro n is rema inin g consta nt o Abou t 0.2 tF/ mm o Roughl y l/ lO of gate ca paci ta nce o Local wire are gettin g fa ter o ot qui te trackin g tra nsistor improvement

o But not a m ajor probl em o Gl o ba l w ire a re getting l ower o 10. Sum mar y Scaling a ll ows peopl e to build m ore com pl ex machines - Th at run faster too It doe not to fir
t

o l onger possibl e to cross chip in o ne cycle

order ch a nge the diffi cult y of m odule de ign

-Module wi re w ill get wor e, but onl y lowl y -Yo u d on ' t think to rethink your wires in yo ur ad der, memory Or even your super- calar proce sor core
It doe let you design m ore modules

Con tinued caling of uniproce sor performan ce i getting h ard -Machin e usin g gl oba l re ource run into wire limi tation -Machin es will have to become more ex pli citl y pa rall el

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Recommended questions:
1. Explain sheet resistance with neat diagram. 2. Write a note on area capacitance. 3. With neat diagram explain delay unit. 4. Explain propagation delay and wiring capacitance. 5. Explain scaling models and factors for MOS transistors. 6. What are the limit s due to current densit y and no ise.

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Part-B

U nit-5

CMOS subsystem design


Architectural issues, switch logic, gate logic, design examples-co mbinat ional logic, clocked circuits. Other system considerat ions.

Clocking strategies

Recommended readings:

1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI. 3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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5.1.Wha t i a System"? y ll'm i" a . et of interacting or interdependent cntitiefom1ing ami integrate


whole. Comm n chara teri- tics of a yst em arc o ystem;; ha\'c wruc/llrt' - dctined hy parts and their composition o . ystcm:ha\'c lu llmior - inYolves i nputs. procc.sing and output' (of material. information or energy) o ):-.tem-. ha\'C illft'rcomuctility the \ariou part of the y:-.tem runctional awell as tructural relationships be tween each other

l.lDecom po ition of a Sy rem:

Proc

or

MOOULf

"

.. ...._ _

...._ .....

V L I De ign Flow The electronics indll'\11)' has achieved a phenomennl growth -mainly due to the
mpid advance\ in integration technologic. large !'>Calc -.ystCill!'> design-in short due to L I. Number application' of integrated circuit-. in high-perfonnancc omput ing. telecommunications. and consumer e lectronics ha-. b en rising teadil Current leading-edge technology trend -expected to cominuc with very important implication-. on LSI anc.l :-.yst cm" design. The design pr css.at variom. levels. i C\' lutionary in nature. Y-Chart (lit t i nt roduced bD. Gajski) a ' hown in FigLu 'I illu t ratc'l til' de ign Jlow for mm..t logic chips. u'>ing dc.,ign activities. Three dil"fcrcnt axes (domain) which rc cmolc the lcllcr Y. Three major domains. namely Behavioral domain tructuml domain

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G eometrica l doma in Desi gn fl ow start from the al gorithm that describe t he behav ior of ta rget chip.

Geometric al Layout Domain

Figure I . Typi ca l VLS I de i gn fl ow in three d oma ins( Y-ch a rt)

VLSI design flow, taking in to account the vario u s repre entation , or a b t racti o n of design are Behavioural ,logic,circuit a nd mask l ayout. Verification of de ign pl a ys v ery i mportant role i n every te p du r ing process. Two a pproache fo r de i gn flow a hown i n Fi gure 2 are Top-clow n Bottom-up Top-down de ign flow- exce llent de i gn proce s con trol ln real it y, both top-down a nd bottom-up a pproache have to be co mbined. Figu re 3 expla ins the ty pi ca l full cu tom de ign flow.

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Fundamentals of CMOS VLSI

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Design Flow

0 0

Bottom-up

Figure 2. Typi ca l YLSI de i gn flow

CITSTUDENTS.I N

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.
f:l-' 1r 0!! :ll l

Fi gure 3. Typi ca l ASIC/Custom desi gn fl ow

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5.2 tructured De ign A pproach


o ign me thodologie and tructurl.!d approache de'eloped ' ith complex ha rd''are and softwm'C . R cg:mJJ cs'\ of the actual ,jzc of the project. ha-.ic principl es oft mclllr"'d dcsign impro\'c the prospeco t f '\ucccss. Ciaica l techniquefor reducing the complexity of J C dc ign arc: Hi cru rch y Regularity Modulari t y Loca l it

Hierarchy:

01 I

'"'lr x.l c

1Q U

rt chnl1u kwol'""'<.livl dh

I i'llo uburill th

modulfo 1ndlht-n r cornple)d l y or IIsn

II thoper:1t1 on on I hoe; sub-modult'< lltr art ..cor n g It:! .

Regul arity: Modu l arity: Th Locality: vanou. func tl n. I locks which m k UJ' It 13 well-denned function nd I nterf ace .

r syst

llllt::rnll.lel allreut 4.lb' at th

toe, . 1. The con pt or loc llit


borl

r@ th.1 conn-.dl on" rA tly b...t.v ..-n

avoid i ng lono-dll ance connection l!> lllUCh a!> po:, t

"

..
:=EJ-- ..
!=E)-

Figure 4-S t ruct ured De i gn Approach -Hierarchy

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s.3

Regularity

2-input MUX

OFF

FigureS-.. tru cturcd D sign Anpr ach -Regul ari t y


De.ign of army .t ructures co1u.t mg of ident ica l cell .--uch as parallel multiplication army. Exist al all levels of abstract ion: tran -tior level- uniformlyjzed. logic level- identical g;,a te stn1clurcs 2:I MUX, 0-F/F- in verters and tti sla te buffers Library-well defi ned and well -chamc!erizcd ba ic build ing block. Modularity: enables parallel iz.ation and nllows plug-and-ph1y Locality: [Hemal of each module unimportant to exterior moduleand internal detail remai n a! local level.
Figure 4 and Figure 5 illu tratethese deign approache ' with an example.

5.4 Arch i. tectural i su es


De ign lime increase exponenti ally with increased complexit y Defi ne the req u irements
Partition the overall architec ture into ' Ubsy tcm' .

Con ider the communica tion path Draw the floor plan Aim for regularit y and modularity convert each cell into layout Carry out DRC check and simulate the performan ce
Page- 128

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5.5 .\10 FET a a wi tch

G
(gate)

I
D
(drain)

nMOS transistor: Closed (conduc tinu) when Gate= I (Vdd , 5V

IL

S (source)

Open (non-c onducting) when Gmc 0 (ground, OV)

n
when

We can view MOS t ran i tor a electticall y cont rolled wi tche Voltage at gate control path from source to drain

for nMO witch. ourcc 1 lypicaHy licJ lo gr unJ and i' u cd lo prrfl-dmn ignal :
)ul

'1 .\' . ht!n GaLl! = I, Out = U.10\ :'

when

r:Lll!

= I), Uu = /

high 'i mp.:tl.J n.:..:

or ptvtO

witch, sou rce i

typicJI Iy 4 icd to dd. u cd to pull . igna l. up:

wh n G.at U.
(1

L (

d )

wtJ
Ou t

'"11

fJatc-

u1 - Z l high im('K.xJ.m L:c

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5.5.1 Parallel connection of witche ..


"""r = ( . i ,\.
.-\. +

X
+B

I i f A orB= 0

:r:

5. .2 eri connection of\Vitche - ..

1
-

-4 n -4
y CITSTUDENTS.I N

= I . . I' .an I

-U

I
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5.5.3 erie and parallel connection of witche ..


nMOS: 1 =ON

pMOS: O =ON Ser: both must be ON


Para/let. ei ther can be ON

gl

92
( I)

E
II

0 bf
()Of

by

OFF

ON

01
g2

E
b

0 0 0

bT

b ON

bf

OFF

OFF

O"f

gl

--lQf-tp
b

y
0

o 8
b

1 0

'

'
b

b 0

lei
I

o:f

ON

ON

ON

gl

--l1-1/Z
b

0 o [} 8
I

a
'LJ
b

cfl

CN

ON

CN

5.6 C ircuit Familie : Restor i ng logi c


Cl\10 l1 VERTER

A-(>- y

V DO

GND

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V DO
A y

0
1 0

y
GND

0
I

1
0

Av-Y
GND

5.6.1

ND ga te De ign.. "' a t ,.
p-t)

ign
'auc "I ' value-. f J gi'- funcli
h.lt!lC

t an-.i'l lf tn:c w iJJ pr

n -typc tr ul-.t -.tnr lrcc w ilJ pt >Vide " " value:-. uf


'Truth "I bl" c

funuaon

D:

I
)I
l

I
I

L1
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Pu.... - =A + I:J
N un-;:; A B
., iii... y ---

<=>
A .....----

-t

B
0
1

y 1

0 0
1 1

0
1

D-

B
0
1

y
1 1

0 0
1 1

0
1

A=O --+-------'-----1
8=1 ----'-----------1

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B
0
1

y
1

0 0
1 1

1 1

A=1 +--8=0

--t

0
1

---'------;

5.6.2OR gate De ign..

( R (;at

p-lyp .. l r.m,j,aor lli> . will

rn Vld.

It

I" \ ..tluof
\.JILl.,

lsi. function
of lu "ic un<.tion

11-l.. p l ntn\ i I r lr .. wall pr vic.J .. "0"

IUlh

abJ

-nmp:

CITSTUDENTS.I N

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AB
0

00
(L

o QJ

0
0

10

I1

0
Vllt.l

,_

<=>
4-input CMOS NOR gate

A B

c
D

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5.6.3 CMO Propcrtic Complementary CMOS logic gates nMOS pu/klown network pMOS pull-up netw CMOS Properties ork a.k.a. static CMOS ,steady state is reached to 0 or 1.(no de path from Vdd to gnd)
Pull-u p OFF Pull-down OFF Pull-do ''n 0 Z (float )
0

Pull-up 0
I

X (crowbar)

pMOS pull-up network

output
nMOS pull-down network

Complemen tary C 1 0. g:llcs a l way" produce 0 or I Ex: NA o gate cries n MO : Y=O \\'hen both inpuL-. are I Tim Y= I when either input i 0 Requires paral l el pMO

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Pull-up network is complement of pull-down PJrallc l -> series. sc tics -> parallel Output sign::l ,trcngt h i. i ndependent of input-l evel rcsto1ing Re loring l ogic. Ouput ignal strength i either Va-. (output. high) or Vol (output
low). Ratio le s logic :om pu t i gnal t rength i independent of

pMOS de ice ize to

nMOS size rat i o.

significant curren t only during the transi t ion from one $late lo another and- he nce power is conscr\'cd..

R ise and 1 111 transition limes arc of the same order, V cry high levels of integr;.Hion High performance.

5.6.4 Complex gnte ..


I =- AB +CD . If'-"' w ill prm ide 0\.
Ptrl"c \:

iU pruv1tl J'

0'" of tunclion : is F. F

= AB +

D = AB +

u tO

t mn-.p..cor n ed high tme i nput.... ... u ., le,ir.Jhl for a ll m ptll \ ari1 . ble-.. to
"

be htgh tmc:. JUt

abuvc

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Fundamentals of CMOS VLSI

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Likewi . t, Pa. will prnvicle I \,

Apply DcMnrgan\ Theorem:

F = AB CD=A+ B, (

D)

c-4
...an 11 . o usc K - m p.:
I

l
I

1 1
I I

CITSTUDENTS.I N

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AB
r-"1

u
D
[ (I

tn.:t..: I

= AB

+CD

I)

u]

....n .

\.

'
bt.)

.A.B
I

0./
I

,
C
=(

I
CD

(C + 0)

D +B .
B (C
0)

--

HD D)

+B) ('

l2

..,

"' "'

CITSTUDENTS.I N

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5.6.5 mplex gate

AOI..

Compound gates c an do any Inverti ng unction

Y = ALB + CLD (AND-AND-OR-I VER T. AOI22)

(a)

:e
A

)1-C
)I-

0 -- -- - B
(b)

-101- C -j 1- D 1- D B

--401'--- B C --401'--- 0 1 8 j
(c)

C _ .. A

(d)

B> y
(f)

(e)

unit inverter

AOI21

AOI22

Complex AOI

Y=A

Y = A B+C

Y = A 8+

Y=A'( B + C} + D E
0
E

A{>o- Y

iQ>v

iB>y
gA = 6f3

A B

gA. = 6f3

9A. = 5f3

9e'" 613 9c= 5'3 p 7/3

99 "' 613

9c = 6f3 9b: 6f3


p ..12/3

9a "' 813 9c = 813


9{) 8/3

9"' 813
p = 16f3

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5.6.6 ircui t Familie : Restoring logic " 10 lmerter- tick diagra m

-
n

1:1

. . ,su
_

vdd

bstrate connec tio n

----

-- 1:1

_...,--0 emarcatio n line

Va ut

.. /P-well connection

.....

GND

5.6.7 Re toring logic

10Yarian t :

n 10

Inverter- tick d iagra m

ydd

GND

Schematic
Stick diagram

Basic inverter circu it: load replaced by depl etion mode tran i stor With no current drawn from output, the cunent lets for both transi stor mu t be arne. For the depletion mode tran istor, ga te i connected to the source o it i always on and onl y the characterist ic curve V gs=O i relevan t.

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Depleti on mode i s ca ll ed pull-up a nd the enhan ce ment mode device pull d ow n. Obtain the t ra nsfer cha rac teristics. As Yi n exceeds the p.d. threshold vol tage current begins to flow, Yout thus d ecreases a nd further increase will cause p.d tra nsistor to come o ut of a turati on a nd beco me re i ti ve. p.u transistor is initiall y resisti ve as the p. d i s turned on. Point at w hi ch Yout =Yi n is denoted a Y inv Ca n be shifted by variation of the ratio of pull-up to pull-dow n resi sta nces -Zp.u I Zp.d Z- ratio of cha nnel len gth to width for each tran sistor

For 8:1 nMOS Inverter


Z p.u. = L p.u. I W p.u =8 R p.u = Z p.u. * Rs =80K si mil a rl y R p.d = Z p.d * Rs = I O K Power dissipati on (on) Pd = Y 2 IRp.u + R p.d =0.28mY Input capacita nce= I Cg

For 4:1 nMOS Inverter


Z p.u. = L p.u. I W p.u =4 R p.u = Z p.u. * Rs =40K simil arly R p.d = Z p.d * Rs =5K Power dissipation(on ) Pd = V 2 IRp.u + R p.d =0.56mY Input ca pacita nce= 2Cg

5.6.8Re toring logic

MO

ariant : Bi NIO

Inverter- tick diagram

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A known defi cien cy of MOS technol ogy i it l i mited l oad dri v i n g capa bi liti es (due to limited CUITent sourcing a nd si nking a bilities of pMOS a nd nMOS transi stor . ) Outpu t logic leve l s good-cl ose to rail voltages Hi gh input impeda n ce Low output impeda n ce H i gh d1i ve ca pa bi l i ty but occupie a rel ati vel y sm a l l area. H i gh n oi se m a rgi n Bipol ar tra n istor have h i gher gain bette r noi e ch a racteri stics bette r hi gh f reque ncy cha rac teristics BiCMOS gates ca n be a n effi cient way of s peeding up V LSI circ uits CMOS fa btica tion process ca n be ex tended for BiCMOS Exa mpl e Appli ca ti o ns CMOS- Logic BiCMOS- I/0 a nd dri ver circuit ECL- critical hi gh speed parts of the system
1

5.6.9 Circuit Familie : Re toring looic

10

A D gate

...

-c

- - -

- _ /G ND

Demarcation line

...,

CITSTUDENTS.I N

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5.6.10 Re toring logic

i\11 0'

ariant :_n10

AND gate

Schematic

Stick diagr11m

5.6.11 Re toring logic ClVlO Variant : Bi :\10

A D gate

dd

B
A . Voi.J.

B
vcut

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For nM
bc-U.

and -gate. th"' ratio between pull- up and

llln

or all pul l-down - must

and-gate area requirement nrc considerabl y greater than orTesponding nMO inverter nM and-gme del ay i equa l to num ber or input time - i nverter delay. Hence nM . and-gates arc used very rarely CM and-gate has no ;;uch rC'\Iriction-. BiCMOS gate i more complex and ha larger ran-out
Tra n i t or
.1

5.7.

i rcuit Fa milie : witch logic: P


\\ hy' 1110 d1 op.

"\ 1tch-.:'c tnnJ!I Jl.l''

lngt

I " \\ i thuut a rhrl.!...tmlu \ U h.tgc ( T )

' h n:
\n >

T = 0.7

J.OV (i.e..

Gj
V11> uVuu - V-r
I) \

chn:"'lw l d H,h,g wi ll vary


ucput voltaQl'

= 4.3 , H't'dl \, "1"

to 4.0V.

The 11M

t r-.tn'i"t r will 't p c ndu ting if

< 'I ,l V1 = 0.7 .

1S -+ --+ '"

v
IV---?.'

u --) 5

suun:e gc.,c::frurn 0 h n

-7

V T. ..

g( fro rn 5
"-\'\1jrch

-t UV.

> -t.JV. th n Vu .. <

st p condu t illg.

== 5
Lran i l r

0.7

== 4.JV or

dd - V .

1r

CITSTUDENTS.I N

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..., =- .7 "" = " ' - 5

-5V <

.7V

>

.7V

\lhc.:n I u I< IVT 1;1. mu t.:ontluc.: ting


a ov

V U V-1 '?

.,

So w hen IVGs l < 10.7VI. Yo will go


from 5V0.7V.

5.7.l , witch logic: Pa s Tran istor


g _l_ r ..d
g

=0
d

Input

So-- d

g= 1 o strong 0 g=1
1

Output

g =1

s
g _j_
sd

degraded 1
Output

g=0

Input

s
g=1

9=0 g=0

degraded

5.7.1

w i tch logic: Pa. Tran i tor-n IO


\

in scril'.

.\'

.. v

I
n\ - v

I
u
4.3\'

I
nv
4 1\'

_j

L
0\t 4.3\
U\

Vdt.l \'1 {).7\'

3V
CITSTUDENTS.I N
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Fundamentals of CMOS VLSI

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5.7.2 : witch logic: Tran mi ion gate


J I ' " ..J

h.. t

-.. 1

n 1:-! I ' . n

.:.a' [ " n

( ,.. p..t.-..

-.. l ?

\Vhcu l = J. B = 'rono I

if ;\ = I; . if

B = t on

=0

\Vhcn l== 0. n n c..u[u.luc ting

CITSTUDENTS.I N

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Pass transistors produce degraded outputs Transmiss;on gates pass both 0 and 1 well

lrpl

QJtpJt

g j_

9=0, 9J= 1
<r---

aOb

9=1, 9J=0 str01]0 9=1, 9J=0 1---o------ str01] 1

9J
g
b

T
g

g=1, 9J=0

a--o---.o--- b

9:>

a4-b a-Q-b
9:>

9J

5.8 tructured De ignT ri tate Tristate buffer J)roduce Z when not enabled
EN
0 0

A
0
]

1
1

1
A

-c>-v
Page- 148

EN

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Fundamentals of CMOS VLSI

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Tri tate buffer produces Z when not enabled

E .
0 0
1 1

0
I

z
z
0
1

-t?-v
EN

EN

0
I

5.8.1 truct u red De. ign-Nonre tori ng Tri tate


Transmission gate acts as tristate buffer - Only two transistors
- But nonrestoring

EN _l_

Noise on A is passed on to Y + No V t drop - Requires inverted clock


5.8.3 tructured Design-Tri tate Inverter

0y

T
EN

Trist:;;at:Q invQrt:Qr pr oducs n ;:fs.t:orgd out: put:

VloJates conduction complement rule


- Because we want a Z output

EN EN

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Tristate inverter produces restored output - Violates conduction complement rule - Because we want a Z output

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5.8.4

tructu1ed De ign-l\lultiplexer
2:1 multiplexer choo e between two input

Dl
0 0 1

DO
0
1

0 1
0

s
DO D1

X
0

Ifl
u
0 1 1
X

If
u
1
X

0 1

5.8. 5 Structured De ign-lVIux De ign.. Gate-Level

y = s +SD O (too rmny transistors)


How many tran i tor: are needed? How many tran i tors are needed? 20

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5.8.6 tructured De ign-l\tf ux De ign-Tra n mi

ion Gate

onre taring mux u t wo tran mi ion gate Only 4 tran i tor

s
_L

DO
y
01

Invertingtux I nverti ng multipJex r


e compound AO 22

- Or pa ir f tri.t ate in ve t1ers on i n verting multiplexer add an inver ter

D1 :,J

o-Y

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5.8.7 De ign-4:I lu lti plexe r

4: I mux ch oscs one r 4 input 'i using t w selec ts Two levels I' 2:I muxcs Or four tri talc

Sl
[))

S1

01
y

5.9 tructured De ign-D Latch \ hen CLK = I. lat ch i,tron f )(l r'111 0 llows throu gh Lo Q like a buffer When CLK = 0, the latch i. npaque

- Q holdit.;; old value independent f D a.k.a. tran par('Jll lmch r /ew!l-sensitile latch

CLK

C LK 0

" "e-t rie ":o 'rn----- -/ ei'it cr i cd o :."""e ip-llop i. a hi-. table elcm nt

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a Latch stores data when clock is low

o Register stores data when clock rises

Clk

Clk

D
Q

J
_j
Multiplexer choose. D or old Q

D
Q

5.9.1 D Latch De ign

QJ(

QK

j_

T
aJ<

5.9.. 2 D Latch Operation

CLK = 1

CLK = 0

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tructurcd De ign-Latch De ign


D

cp

In verting buller
o backdriving Fixe either Output noi. e sen.i t i vity Or d i iTu ion input ln \'crtcd Lll put
Rc Iorin e"

T
0

5.9.3

tructurcd D ign-D Flip-flop When CLK rise$, 0 i. copied to Q At all oth r time . Q hold it value a. k.a. positile nlgl'-triggered flip-flop.ma.wer-<tlart' flip-flop

offia

CLK

aJ<

CLK

truct urcd De ign-0 Flip-nop Dc ign

Built from ma tcr and la ve 0 latchc

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5.9.4 D Flip-flop Operation

CLK = 0

D-o

....o----.-----1

GLK"" 1

CLK

D
Q

5.9.- Race ondition Back-t -ba k f1 P a n malfun ti n fr m I k ke\J cc nd flip-fl p lire lat fir.t ll i p-ll p han g and apturc its r ult Ca l l d !t old-timefailurl' r race condition

a.K1
a..K1
QJ<2 QJ<2
Q1

01

_, '-----

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Recommended questions:
1. Explain 4X4 cross bar switch operation. Mention the salient features of subsystem design process. 2. Explain the restoring logic in detail. 3. How to implement the switch logic for 4 way mux? Explain. 4. Describe switch and CMOS logic implementation for 2 input XOR gate. 5. Design a parity generator and draw the stick diagram for one basic cell.

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Unit-6
CMOS subsystem design processes
General considerat ions, process illustration, ALU subsystem, adders, mult ipliers.

Recommended readings:

1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI

3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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6.1 General Considerations Lower unit cost Higher reliabilit y Lower power dissipat ion, lower weight and lower volume Better performance Enhanced repeatabilit y Possibilit y of reduced design/development periods 6.1.1 Some Problems 1. How to design complex systems in a reasonable time & with reasonable effort. 2. The nature of architectures best suited to take full advantage of VLSI and the techno logy 3. The testabilit y of large/co mplex systems once implemented on silicon 6.1.2 Some Solution Problem 1 & 3 are greatly reduced if two aspects of standard practices are accepted. 1. a) Top-down design approach with adequate CAD tools to do the job b) Partitioning the system sensibly c) Aiming for simple interconnections d) High regularit y within subsystem e) Generate and then verify each sect ion of the design 2. Devote significant portion of total chip area to test and diagnostic facilit y 3. Select architectures that allow design object ives and high regularit y in realizat ion 6.2 Illustration of design processes 1. Structured design begins wit h the concept of hierarchy 2. It is possible to divide any complex funct ion into less co mplex sub funct ions that is up to leaf cells 3. Process is known as top-down design 4. As a systems complexit y increases, its organizatio n changes as different factors become relevant to its creation 5. Coupling can be used as a measure of how much submodels interact 6. It is crucial that components interacting wit h high frequency be physically proximate, since one may pay severe penalt ies for long, high-bandwidth interconnects

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7. Concurrency should be explo ited it is desirable that all gates on the chip do useful work most of the time 8. Because technology changes so fast, the adaptation to a new process must occur in a short time. Hence represent ing a design several approaches are possible. They are: Conventional circuit symbo ls Logic symbo ls Stick diagram Any mixture of logic symbo ls and stick diagram that is convenient at a stage Mask layouts Architectural block diagrams and floor plans 6.3 General arrangements of a 4 bit arithmetic processor The basic architecture of digital processor structure is as shown below in figure 6.1. Here the design of data path is only considered.

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Alterna tively, the two data ports may be combined as a single bidirectional port if storage facilities exist in the d atapa th. Control over the functions to be performed is effected by control signals as show n.
Data path

Data in "' Basic ar ithmetic , logical & shift operat ions


Temporary storage of operands

Data out ...


r

Control

Fi gu re 6.2: Communication strategy for the data path Datapath can be decomposed into blocks showing the main subunits as in figu re 3. In doing so it is useful to anticipate a possi ble floor pl an to show the pl anned relative decomposi tion of the subuni ts on the chi p and hence on the mask layo u ts.

Operation Shift Select& Diraction Contro Control Control Control Figure 6.3: Su buni ts and basic interconnection for datapath Nature of the bus architectu re linking the subunits is d jscussed below. Some of the possibilities are:
One b u a rchitecture: 4-bi bus

ALU

Fi gu re 6.4: One bus architecture Sequence: J . J st operand from registers to ALU. Operand is stored there. 2. 2"d operand from register to ALU and added. 3. Result is passed through shi fter and stored in the regi ster

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Two bu arch itecture:

Registers

Figure 6.5: Two bus architecture Sequence: l. Two operands (A & B) are sent from register(s) to ALU & are operated upon, resultS in ALU. 2. Result is passed through the shif ter & stored in registers.

Th ree bu architecture:

Figure 6.6: Three bus a rchitecture Sequence: Two operands (A & B) are sent from registers, operated upon, and shifted result (S) returned to another register, all in same clock period.

In pursuing this design exercise, it was decided to implement the structure with a
2 - bus architecture. A tentative floor plan of the proposed design which includes some fonn of interface to the parent system data bus is shown in figure 6.7.
BUS 1 Input I Output 4 -bit Register ALU 4 - bit Shifter

Bus2
A

,..
System Bus

>"

Figure 6.7: Tentative floor plan for 4- bit datapath

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The proposed processor will be seen to comprise a register array in which 4-bit num bers can be stored, either from an 110 port or from the output of the ALU via a shif ter. Num bers from the register ar ray can be fed in pairs to the ALU to be added (or subtracted) and the resu lt can be sh ifted or not The data coru1ections between the 110 port, ALU, and shi fter must be in the form of 4-bi t buses. Also, each of the blocks must be suitably con nected to control l ines so that its function may be defi ned for an y of a range of possi ble operations. Duri ng the design process, and in particular when defi ning the interconnection strategy and designing the stick diagram s, care must be ta ken in allocating the layers to the various data or control pat hs. Points to be noted: ../ Metal can cross poly or diffusion ../ Poly crossing di ff usion form a transistor ../ W henever lines touch on the same level an in terconnection is formed ../ Simple contacts can be used to join diffusion or poly to metal. ../ B uried contacts or a butting contacts can be used to join diff usion and poly ../ Some processes use 2"d metal ../ 151 and 2"d metal layers may be joined using a via ../ Each laye r has particu lar electrical properti es which must be taken i nto account ../ For CMOS layou ts, p-and n-diffusion wires m ust not directly joi n each other ../ or may they cross ei ther a p-well or ann-well boundary

De ign of a 4-bit hifter

Any general purpose n-bit shi fter should be able to shift incoming data by up to n - 1 place in a right-shi ft or left-shift di rection. Fur1her specifyi ng that a ll shi f ts should be on an end-a round basis, so that an y bit shifted out at one end of a data word will be shif ted in at the other end of the word, the n the problem of right shift or left shift is greatly eased. It can be a nal yzed that for a 4-bit word, that a 1-bit shi ft right i s equivalent to a 3- bit shift left and a 2-bi t shift right is equivalent to a 2-bit left etc. Hence, the design of either shif t right or left can be done. Here the design is of shift right by 0, 1, 2, or 3 places. The shifter must h ave: input from a four l ine pa rallel d ata bu s four ou tput li nes for the s hifted data means of transferring input d ata to outpu t lines with any shift from 0 to 3 bits Consider a direct MOS switch i mplementation of a 4 X 4 crossbar switches show n in figure 6.8. The arrangement is ge neral and may be ex panded to accommodate n- bit inputs/outputs. In this arrangement any input can be connected to any or a ll the outputs. Furthermore, 1 6 control signals (swoo - sw1 s), one for each transistor sw itch, must be provided to drive the crossbar sw itch, a nd such complexi ty is h ighl y undesi rable.

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In 0

In 1

In 2

In 3

Figure 6.8: 4 X 4 crossbar switch An adaptation of this arrangement recognizes the fact that we couple the switch gates together in groups of four and also form four separate groups corresponding to shifts of zero, one, two and three bits. The resulting arrangement is known as a barrel shifter and a 4 X 4 barrel shifter circuit diagram is as shown i n the figure 6.9.

--+--+--+-.......-

-:O..WII'II

Figure 6.9: 4 X 4 barrel shifter The interbus swi tches have their gate inputs connected in a staircase fashi on in groups of four and there are now four shift control inputs which must be mutually exclusive in the active state. CMOS transmission gates may be used in place of the simple pass transistor switches if appropriate. Barrel shifter connects the input lines representing a word to a group of output lines with the required shift d etennined by i ts control inputs (shO, sh I , sh2, sh3). Control inputs also determine the direction of the shi ft. If input word has n - bits and shifts from 0 to n- l bit positions are to be implemented. To ummarie the de ign tep Set out the specifications -i Partition the archi tecture into su bsystems Set a tentative floor plan Determi ne the interconnects Choose layers for the bus & control lines Conceive a regular architecture

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Produce mask layouts for standard cell Ca.cadc & replicate standard cells a. requ i red to complete the de. ign

6.4 De ign of a n A L L" u b y te m H aving de igned Lhc hifter. ' c haJI de ign nether ub ystem of Lhe 4-bit da ta pat h. An appropriate choice i AL a: hown in the figure 6.10 below.

Figure 6.I0: 4-bit data path for proccs or The heart of the AL is a 4-bit adder circ uit. A 4-bit adder must take . u m of'' o _.-bi t numberand there i. a n as. umption t hat a ll +bit quanti tie. arc prescmcd in parallel [! rm and Lhat the hifter circuit is designed to a ccpt and shift a 4-bi t parallel sum from t he A LU. The um is to be tored in paralle l at the ou tput of the adder fr mhere it i fed through t h shift er and back to t h regi ster array. Therefore, a single 4-bi t data bus i needed from the adder to t he .hifter and another 4-bit bu. is required from the . hifted output back to the regi ter array. Hence. for an adder two 4-bit parallel numbers arc fed on two 4-bit buse . The clock ignal i al o required to the adder. during ' hich the input arc given and u rn i genera ted. The hi ftcr is un locked but mu t be connected to four shift con Lrollines. Design of a + bit ndd r: Th c trulIl tabl eofbm ' ary a dd1cr. IS n.s sh own 111 tabl c 6 I Input Output A._

s ..
0
I

c ..
0
0 0 0
I I I I

s ..
0
I I

c ..
0
0 0
I

0 0
I I

0
I

0
I

0 0
I I

0
I

0
I I I

0 0
I

0
I

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A seen from the table any column k there will be three i n put namely A , BL a pre ent inpu t number and CL.J a the previous carry. h can al o be seen that there arc two output urn s.. and carry c... From the table one form of the equation i : um ._ = H LCL.t' + Ht'CL.a Nw carry C1.= A1.. Bl + H.c 1 Where Hal f um H1. = Ao.'BL + A1.. B,.'
Ad der eleme nt req ui rr men t Table 6.1 reveal that the adder requirement may be tated

ns: I f A1.. = 81.. then 1.. = C1..1 Else 1.. = Ct.' And for the carry C1.. If A1.. = 81.. then C1. = A1.. = 81.. Else c.. = c.., . Thu the tandard adder element for 1-bit i a hown i n the figure 6.1 1.
Carry in C 1

Sums.
Cany

Figure 6.1 1 : Adder element


6.4.l lm plemen ti ng .\ Lll functi on "ith a n a dd er:

AnAL must be able to add and : ubtract t\ o bi nary number.. pcrfom1 logical operation: such as And. Or and Equali t y Ex-or) functions. Subtract ion can be performed by taking 2' complement of the negative number and perfonn the f u rther addition. It i. de irable to keep the architecture a imple ns po ible. and aJ o ee that the adder perfonn the logical operation al o. Hence let u examine the po ibi lity. The adder equation arc: um 1: = H :C....t. + H.. c...., Nev. carry C1.. = A1.. B1. + H1. C1..1 Where Hal f um H1. = Ao.'B1. + A1.. 81.' Let u con ider t he um output. i f the previou carry i at logical 0, then S1.. = H . I + H.,'. 0 SL = H, s.. -An Ex-or operation No' . if Ct.J i. logically I. then L = H .;. 0 + HL'. I

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Sk = Hk' - An Ex-Nor operation

Nex t, consider t he carry outp .ut of each eleme nt, first 1 is held at logical 0, then =A ;:B CC ; - An And operati C o ;: n= A;:B ; Now i f Ck.1 is at logical 1, then =A ;:B ;: + Hk . 1 C ; On sol ving C;:= A;: + B;: - An Or operation The adder element implementi ng both the arithmetic a nd logical fu nctions ca n be implemented as shown in the figure 6.12.

ck-t
sk
r"t- BIk I

Bat

ck

Fi gu re 6.1 2: 1 -bi t add er element The a bove can be cascaded to form 4-bit ALU.
A f u rthe r con ideration of add er G eneration:

This princi ple of generation al lows the system to take ad va ntage of the occurrences "a ;=b ;:". In both cases (ak= I or a ;:=O) the carry bit will be know n. Propa gation: If we are able to localize a chain of bits ak ak+J ...at+p and bk bk+J ...bk+p for which ak not equ al to bk fork in [k,k+p], then the outpu t carry bit of this chai n will be equ al to the input carry bit of the chai n. These remarks constitu te the principle of generation and propagatio n used to speed the addi tion of two numbers. All adders which use this p ri nciple calculate i n a fi rst stage. Pk= a k XOR gk = a k b ;:

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6A.2lnn che ter can) -cha in This im plementation can be very pcrformant (20 trnn. istors) depending on the way the XOR fu nction i built. The carry propagation of the carry i controlled by the output of the XO R gate. The generation of the carry is directly made by t he funct ion at the bonom. When both i nput signa ls are I. then the inverse output carry i0.

Fu i re-6.12: An adder with propagation ignal controlling the pas -gate In the schematic of Figure 6.I-the carry pa e through a complelc tran mi ion gate. I f t he carry path i precharged to VOD. the tran. mi.. ion gate i. t hen reduced 1 a simple i lOS tra nsi tor. I n the arne way the PMOS u-ansistors of the carry generation is rcn ved. nc get a Manchester cell.

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p cany I_ _..._c .arry out

g-clock_

Figure-6.1 3: The Ma nchester cell


The Manchester cell is very fast, but a large set of such cascaded cells would be slow. This is due to the distributed RC effect and the body effect making the propagation time grow with the square of the number of cells. Practicall y, an inverter is added every four cells, like in Figure 6. 14.

Figu re-6.14: The Manchester carry cell

Adder Enha ncement techniqu


The operands of additi on are the addend and the augend. The addend is added to the augend to form the sum. In most computers, the augmented operand (the augend) is replaced by the sum, whereas the addend is unchanged. High speed adders are not onJ y for addition but also for subtraction, multiplica tion and division. The speed of a digi tal processor depends heavily on the speed of adders. The adders add vectors of bits and the pri ncipal problem is to speed- up the carry signal. A traditional and non optimized f our bit adder can be made by the use of the generic one-bit adder cell connected one to the other. It is the ripple carry adder. In this case, the sum resulting at each stage need to wait for the incoming carry signal to perform the sum operation. The carry propagation can be speed-u p in two ways. The first -and most obvious- wa y is to use a faster logic ci rcu it technol ogy. The second wa y is to genera te carries by means of forecasting logic that does not rely on the carry signal being rippled from stage to stage of the adder.

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6.4.3 T he 'arl.") - kip Addl'r Depending on lhe po ilion at which a carry ignal ha bee n generated. the pr pagation time can variable. In the be l case. ' hen there i no carry generat ion, the addition time ''ill only take into account the Lime to propagate the carry ignal. Figure 6.15 i. an example illu. trating a carry signal generated twice. with the input carry being equa l to 0. I n thi case t hree imullaneou carry propagation. occur. The Ionge t i the econd, w hich take 7 cell delay (i t tart. at the 4th position and end at the II th po it ion). So Lhe addition time of these two number ''ith thi 16-bit. Ripple Carry Adder is 7.k + k', where k i the delay cell and k' i the time needed to compute the lllh urn bit u. ing the l ith carry-i n. With a Ripple Carry Adder, if the inpu t bi ts Ai and Bi are different for all position i, then the carry signal is propagated at all positions (thus never generated), and the addition is co mpleted when the carry signal has propagated through the whole adder. In this case, the Ripple Carry Adder is as slow as it is large. Actually, Ripple Carry Adders are fast only for some configu rations of the input words, where carry signals are generated at some positions. Carry Skip Adders take advantage both of the generation or the propagation of the carry signal. They are divided i n to blocks, where a special circuit detects quickly if all the bits to be added are different (Pi = 1 i n all the block). The signal produced by this circuit wi ll be called block propagation signa l. If the carry is propagated at all positions i n the block, then the carry signal entering into the block can directly bypass it and so be transmitted through a mu ltiplexer to the next block. As soon as the carry signal is transmitted to a block, it starts to propagate through the block, as if it had been generated at the begiruting of the block. Fi gure 6.16 shows the structure of a 24-bits Carry Skip Adder, divided i nto 4 blocks.
I 0 0 I -] I 0 I 0 0 I O

_ 1_

10

10) Qj

D D DD iilllOO DD D DD IIilJO DD D 0 00 0 0D 0 0 0
Figure 6.15: Ex ample of Carry skip adder

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A. I , 8.I
I1 : 8,...,23

' Bi
la:12 ,...,17

8j

Ai, Bl
j, 0,1,2...,5

i:6,7,...,1 1

, Bi

i:0,1,... ,5

Figure-6. 16: Block diagram of a carry s1dp adder

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Optimization of t he ca rry kip adder


It becomes now obvious that there exist a trade-off between the speed and the size of the blocks. In this part we analyze the division of the adder into blocks of equal size. Let us denote kl the time needed by the carry signal to propagate through an adder cell, and k2 the time it needs to skip over one block. Suppose the N-bit Carry Skip Adder is divided into M blocks, and each block contains P adder cells. The actual addition time of a Ri pple Carry Adder depends on the configuration of the input words. The completion time may be small but it also may reach the worst case, when all adder cells propagate the carry signal. In the same way, we must evaluate the worst carry propagation time for the Carry Skip Adder. The worst case of carry propagation is depicted in Figu re 6. 17.

Figure-6. 17: Worst case carry propagation for Carry Skip adder The confi guration of the input words is such that a carry signal is generated at the beginning of the first block. Then this carry signal is propagated by all the succeeding adder cells bu t the last which generates another carry signal. 111 the first and the last block the block propaga6on signal is equal to 0, so the entering carry signal is not transmitted to the next block. Consequently, in the first block, the last adder cells must walt for the carry signal, whkh comes from the first cell of t1 1e first block. When going out of the first

block, the carry signal is distribu ted to the 2"d, 3rd and last block, where it propagates. In these blocks, the carry signals propagate almost simultaneously (we must account for the m u ltiplexer delays). Any other situation leads to a better case. Suppose for instance that the 2"d block does not propagate the cany signal (its block propagation signal is equal to zero), then it means that a carry signal is generated inside. This carry signal starts to propagate as soon as the inpu t bits are settled. In ot her words, at the begjnning of the addition, there exist two sources for the carry signals. The paths of these carry signals are shorter than the carry path of the worst case. Let us formalize that the total adder is made of N adder cells. It contains M blocks of P adder cells.l11e total of adder cells is then

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_ =M.P
The time T needed by the carry signal to propagate through P adder cells is

The timeT needed by the carry . ignal to kip through M adder block

The problem to ol ve i to minimize the wor t case delay which i :

6.4.4 Th Carry-cll

dd r

This t ype of adder i not a fast as the Carry Look Ahead (CLA ) pre ented in a next section. However, de pite it bigger amount of hard' are needed. it ha. an intere ting de. ign conrepl. The Carry cle t prin iple requ ire. two identical parallel adders that are partitioned into four-bit group . Each group c nsist of t he same dc:ign a. that: hown o n Figure 6. 1 . The group generate. a group carry. In the carry select adder, two um arc generated .imultancou ly. One urn as umes that the carry in i equal to one a!l the ot her a umcs t hat the carry in is equal to zero. o that the predicted group cany i u cd to elect one of the t wo urn .
It can be cen t hat the group carrie logic increase rapidly \ hen more highorder group are added to the total adder length. Thi complexity can be decreased, with a u beq u ent in rea e in the delay, by partition i ng a long adder into sections, wi th four group per se t ion, i milar to the CLA adde r.

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AJ

83

A2

82

SJ

S2

Sl

so

Figure-6.18: The Carry Select adder


Optimization of the ca r r y elect. adder
Computational time

T =K 1 n
Dividing the adder in to blocks with 2 parallel paths

T = K1 n/2 + K2
For a n-bit adder of M-blocks and each block contai ns P adder cells in se ries T = PK 1 + (M- 1) K2 ; n = M.P minimum value forT is when M= ..f(K 1n I K 1 )

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6.-'.5 The 'a rr y Look-.\head Adder

The l imita tion in the eq uential met hod of fonni ng carrie . especia ll y in t h e Ripple Carry adder ari e from pecifying c, a a pecilic function of c,.,. It i po sible to exprc a carry as a function of all t he preceding lo' order carry by using the rccursivity of the carry function. With the following cxprc sion a con iderable i ncrease i n peed can be realized. Ci = G, + Gi-2 PH + Gt-s P1-2 PH + .. .. + Ge Pt P1Pi-t + Ce Pe Pt Pt.P,.J . ually the ize and complexi t y for a big adder using thi equation i not affordable. That i w hy the equat ion i u ed in a modular way by making group of carry (u ually four bit.). Su ch a unit generate then a group carry which give the right predicted infonnation to t he next bl ock gi v i ng time to t he urn unit to perform their calculation.

7t =
1t

PcP tP2P3
+ P3P 2

'Y

Y = g3 + P3
C4 =

g l + P 3P 2P 1 go

Y + J!.CQ

Figurc-6.19: The Carry Generation unit pcrfonning the Carry group computation Such unit can be implemented in various ways, according to the a llowed level of abstraction. In a CMOS process, 17 tra nsis tors are able to guarantee the sta tic function (Figure 6.20). However thi s desig n requires a caref ul sizing of the transistors put in senes. The same design is av ailable with less transistors in a d y namic logic design. The sizi ng is still an important issue, but the number of transistors is reduced (Figure 6.21).

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lt>------93
c 1 ...

go+ po.co

r---- lt>---1 ,---------1

- -y---t-9z

)p---T --+----if--91

o----+-+--+-9o

Po-f --+----lf--...._

-41

C4 = 1:3 + P 3 [ E 2 + P2(1: I + PI {I:O + Po.coJD

Pt -f---f----1......_---41
-f----+- PJ4f -41 -f

t--J

-- -

+------1

Figure-6.20: Stati c implementa tion of the 4-bi t carry lookahead chai n

clod_._- -- --f l

Figure-6.21: Dyn amic im plementation of the 4-- bit carr y lookahead chain Figu re 6.22 shows the implementa tion of 16-bit CLA add er.

Fi gure-6.22: Implementa tion of a 16-bi t CLA add er

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Figure-6.23: Serial-Parallel multiplier 6.5.1Braun Pa ra II<'I l ul tiplicr The implc t parallel multiplier i. the Braun array. All the panial product A.bk are compu ted in paralle l. and then collected through a cascade of Carry Save Adders. At the bottom of the array. the output of the array is noted in Carry Save, so an additional adder convcn it ( by the mean of carry propagation) into the cia ical notation (Figure 6.2-t). The comple tion Lime i limited by the depth of the carry ave array. ru1d by the arry propagation in the adder. Note that this multiplier is only sui ted for positive operands. cgati c operand! may be multiplied usi ng a Baugh-Wooley multiplier.

Figure 6.2-t: A +bit Braun Army

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6.5.2 Baugh-Wool c t\ lultipl icr This technique has been developed i n order to de ign regular nlUit ipliers. uited for 2' -complement numbers.

Let u con idcr 2 numbers A and B:


n-2

A = (3

. 3o) =_ az"-1 +

L ai 2 1
0

B = Cb n.t

b o) =.bn.t 21L J + Lbi 21


0

n.2

The product A.B i given by the folio' ing eq u at ion:


A B = a a. ! b n.l 22Ja-2 +
n-2 n-2
L.J L.J

n-2

i+j - a....l L.J ib i 2


0

zn+i-1 - bn.l L.J.,.2n+ i-L


0

We ec that ubtra tion cell mu t be used. Ln order to use only adder eelb. the negative temlmay be rcriuen as:

- an. t Lbi zi+ = an.t (_z2-2 + z + L bi zi+n-t )


0 0

J\

By thi way. A.B become :

AB

a.l bA-1 22A 2

+L Lai bj zi+j
0 0

n-2 2

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The ft naJ eq u ation is:

+L 0

n.2

L ai.bj. 2i+j +
0

n.2

(an.1 + bn -1). 2n.1

n.2 n.2 +"'bn . -1a-; 2i+n-1 + "'an-1 b, 2i+n-1 1 i


0 0

A and B arc n- bits operand , o their product i a 2n-bit number. Con cqucntly, the mo t ignificam weight i 2n-l, and the fir t tenn -2n.t is taken into account by adding a I in the mo t ignifican t cell of t he multiplier. The implernen ta tion is hown in figure 6.25.

Figurc-6.25: A 4-bit Baugh- Wooley Multiplier


6.5.3 Booth A lgori thm

This algorithm is a powerful direct algorithm for signed-number multiplication. It generates a 2n-bit product and treat both po itive and negative numbers unifonnly. The idea i to redu e the number of add i tion to perform. Booth algori thm allows in the be t case n/2 additions whereru modi lied Booth algori t hm allow. alway. n/2 addition. .

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Let us consider a string of k consecu tive 1s in a multiplier: ..., i +k, i+k-1, i+k-2 , ..., 1, i -1, ... ...' 0 , 1 , 1 ' ..., 1 , 0, ... where there is k consecutive 1 s. By usin g the following property of binary strings:

the k consecuti ve l. s can be replaced b y the following stri ng ..., i+k+l, i+k, i+k-1, i +k-2, ..., i+l, i ' i- 1 ' ... ..., 0 1 0 0 ,..., 0' -1 ' 0 ' ... k-1 co nsecutive Os Addition Subtraction In fact, the modified Booth algorithm con verts a si gned nu mber from the s tand ard 2's-complement radix i nto a number syste m where the digits are in the set { -1,0,1}. In this number system, any number ma y be written in several forms, so the system is called redundant The codi ng table for the modified Booth algorithm is given in Table 1. The a lgorithm scans strings composed of three digits. Depending on the value of the stri ng, a certain operation will be performed. A possi ble implementation of the Booth encoder is given on Figure 6.26. Table-1: Modified Booth codin g table

.-0 0 0 0
1

BIT 21 20 21
yi+l yi Yi.t

OPERATION
add zero (no string) add multipleic (end of string) add multiplic. (a string) add twice the mul. (end of stri ng) sub. twice them (beg. of string) sub. them. (-2X and +X) sub . the m (beg. of string) sub. zero (center of string)

l\1is multiplied

by
+0
+X +X +2X -2X -X -X

0 0
1 1

0
1

0
1

0 0
1 1

0
1

-0

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Figure-6.26: Booth en oder cell To . ummarize t he operat i on: ._ Grouping mu ltiplier bit into pairs Orthogonal idea to the Booth rc oding Reduce the nu m of partial produ t to half If Booth receding not used -+ have to be able to multiply by 3 (hard: hift+add) Applyi ng the grouping Modified Booth Receding (Encoding) We already got rid no mu l tiplication by 3 Ju t negate. hift once or twice 6.5.-' \\'allace Tree For thi purpose, Walla e tree ' ere introduced. The addition t i me gro' l i ke t he logarithm of the bi t number. The simplest Wallace t ree is the adder cell. More general l y, an n-inpu t Wallace tree i an n-input operator and log2(n) outpu ts. . uch that the value of th .. output word i. equal to the number of "I" in the input word. The inpu t hiL and the le. t ignificant bit of the output have the ame weight (Figure 6.27). An important property of Walla " t rees i that Lhey may be con tructed using adder cell. Furthennore. t he number of adder cells needed grows like the logarithm log2(n of the number n of input bit. . Conseque n tly, Wallace tree. arc useful ' hcne er a large number of opera nd s arc to add, like in multipliers. ln a Braun or Baugh-Woolcy multiplier with a Ripple Carry Adder. t h" completion time of the multipl ication i proportiona l to l\ ice Lhe number n of bi t . If the collection of the partial product is made thr ugh WaJiacc tree . the time for getting the result in a carry save notation !.hould be proportional to log2(n). idea of to sequence. Booth of l's

ninputs

,0 ,0 ,.

Log (n) outpuL-.

Figurc-6.27: Wallace cells made of adders

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Figure 6.28 represents a 7-inputs adder. for each weight, W al lace trees are used until there remai n on ly t wo bits of each weight, as to add them using a classical 2-inpu ts adder. When taking int o account t he regu lari ty of the inte rconnecti on , Wa llace trees a re the most i rregul ar.

Fi gu re-6.28: A 7-i nputs Wallace tree To summarize the operation: The Wa llace tree has three steps: r Mu l tiply (that is- AND) each bit of one of the arguments, by each bit of the other, yield i ng n2 results. r Reduce the number of parti a l products to two by l ayers of full a nd half adders. ,. G roup the wi res i n two numbers, and add the m wi th a conventional adder. The second phase works as follows. :,. Take an y three wires with the same weight and i nput them into a full adder. r The re u l t will be a n output w ire of the ame weight and a n output wi re wi th a higher wei ght for each three input wires. :;... lf there are t wo wires of the sarne weight left, input them into a half adder. r If there is just one wire lef t, connect it to the nex t layer.

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Recommended questions:
1. How to implement arithmet ic and logic operation with a standard adder? Explain wit h the help of logic expressio n. 2. Discuss the architectural issues to be followed in the design of VLSI subsystem. 3. Design 4:1 mux using transmission gates. 4. How can 4 bit ALU architecture be used to implement an adder? 5. Explain the design steps for a 4 bit adder. 6. Discuss Baugh Worley method used for 2s complement mult iplicat ion. 7. Discuss timing constraints for both flip-flop and latches. 8. Explain booth mult iplier with example. 9. Explain basic form of 2 phase clock generator.

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Unit-7

Memory registers and clock


Timing considerations, memory elements, memor y cell arrays.

Recommended readings:

1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI. 3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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.l . )' tem t imi ng con idcra tion :


Two phase non-overlapping clock Qt lead 2 Bit to be . torcd are written to rcgi tcr and sub y tcm on 1 Bit. or data written arc a sumed to be settled before 2 2 ignalu.cd to rcfrc h data Delay as.unr-d to be lc than the intervaL between the leading edge of 1 & Bit. or data may be read on th ne x t 1 There must be at leat one clocked toragc clement in scric with every closed

loop signal path 7.2 tornge I ){e mory E lem en t : The clcmcnlS that we will be stud yi ng are: Dy na mic hift register 3T RAM cell
dynamc i IT dynamic memory cell Pseudo tatic RAM I rcgi ter cell ..JT d ynamic & 6T tatic memory cell JK FF circuit D FF circuit

Power di Volatilit)'

i pation static dissipa tion is vety smaU dy namic power is significant d issipation can be reduced by al ternate geometry
data storage time is limited to l msec or less

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7.2.13T dynamic R

I cell:

ircui. t diagta m
Vol)

Bus

GND WR RD

Figure 7.1 : 3T Dyn amic RAM Cell

Working RD = l ow. bit read from bu through Tl, WR =high, logi level on bu sent to Cg ofT2, WR = IO\ again Bit level i torcd in Cg ofT2, RD=WR=Iow Stored bit i read by RD = high. bu will be pulled to ground if a I wa stored else 0 i fT2 non-conducti ng. bus' i ll remain h igh. Di ipation Static d i ipation is nil pend!i on bus pull-up & on duration of RD signal & . wit hing frequency \'ola t ility Celli dynamic, data wi ll be there as long a. charge remain. on Cg of T2 7.2. IT dnamic memory c<'ll:

'ircuit di:-tgram

BL

Figure 7.2: IT Dynamic RAM Cell

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Workin g

Row select (RS) =high, during wri te from RIW line Cm is charged data is read from Cm by detecting the charge on Cm w ith RS =high cell arrangement is bi t com plex. solution: ex tend the diff usion area comprising source of pass transistor, but Cd<<< Cgchannel another sol ution : create signi t1cant capacitor using pol y plate over d iffusion area. Cm is formed as a 3-plate structure wi th all this caref ul design is necessary to achieve consi stent read ability Di ipat ion no static power, but there must be an allowa nce for switching energy during read/write

7.2.3 P eudo tatic RA l / 1 t'gi ter cell:

ircuit di agra m

WR.ct>1 --1
0/P

T
$z
Figure 7.3: nMOS pseudo-static memory Cell

WR, 4>1

R D.

IP t

0/P

Figu re 7.4: CMOS pseudo-static memory Cell

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Working

dyn amic RAM need to be refreshed periodically and hence not convenient static RAM needs to be designed to hold dat a indefi nitely One way is connect 2 inverter stages with a feedback. say t2 to refresh the data every clock cycle bit is written on activati ng the WR line which occurs with <1>1 of the clock bit on Cg of inv erter 1 will produce complemented outpu t at inverter 1 and true at output of in verter 2 at every <P2 , stored bit is refreshed through the ga ted feedback path stored bit is held till <1>2 of clock occu rs at time less than the decay time of stored bit to read RD along with_cp l is activated

Note:

WR and RD rnust be rnutuaJiy exclusive c1>2 is used for refreshing, hence no data to be read.. if so charge sharing effect , leadi ng to destmction of stored bit cells must be stack a ble. both side-by-si de & top to bottom alim for other bus lines to mn through the cell

.2.4 -lT d ynamic & 6T tatic mcnaory cell:


Circuit di nAarn

Figure 7 .4: Dynamic and sialic n1emory cells

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\Vor ki ng uses 2 buses per bit to store bi t and bit' both buses are precharged to logic 1 before read or write operation. write operation read operation \rite opera tion both bit & bit' buses are precharged to VDD with clock <1>1 via transistor T5 & T6 col umn select line is activated along with <1>2 either bit or bit' line is discharged along the 110 li ne when carrying a logic 0 row & column select sign a ls are activated at the same time => bit l ine states are written in via T3 & T4, stored by T L & T2 as charge

Read operatio n bit and bit' lines are again precharged to VDD via T5 & T6 during <j> 1 if J has been stored, T2 ON & Tl OFF bi t' line will be discharged to VSS via T2 each cell of RAM array be of minimum stze & hence will be the transistors implies incapable of sinking large charges quickl y RAM arrays usually employ some form of sense amplifier Tl , T2, T3 & T4 form as flip-flop circuit if sense line to be inactive, state of the bit line reflects the charge presen t on gate capadtance ofT1 & T3 curren t flowing from VDD through an on transistor helps to maintain the state of bit 1i nes

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Recommended questions:
1. Show the funct ioning of single transistor dynamic memory cell. 2. What are the system considerat ions? 3. What is structured design process? 4. Explain CMOS pseudo static D Flip flop. 5. Explain the working of 3TDRAM cell

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Unit-8

Testability
Performance parameters, layout issues I/O pads, real estate, system delays, ground rules for design, test and testability.

Recommended readings:
1. Douglas A. Pucknell & Kamran Eshraghian, Basic VLSI Design PHI 3rd Edit ion (original Edition 1994), 2005. 2. Neil H. E. Weste and K. Eshragian, Principles of CMOS VLSI Design: A System Perspective, 2nd edit ion, Pearson Education (Asia) Pvt. Ltd., 2000. History of VLSI 3. CMOS VLSI DESIGNA circuits and systems perpective. 3 rd edit ion N.H.Weste and David Harris. Addison-wesley.

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8.1Definit ion:

D si. 11 for te rability (Of-T) refers 10 th . de ign n and 1c t application o t-effcctivc.


om t rminologi<.'\:

hnique that make 1c t gcncrnli

I n pu t / out pu t ( VO> pad Protccti n of ircuitl) on hip fr m damage Care to be taken in handling all M Provide for the circuits Provide nc "s.ary buffc.!ring bct\\C"n the cn"ironmcnts n & OFF chip nne Lion ot po'"er . upply
:tr

Pads must be ah :tys pia 'd

und the p.!riphcral

1inimum hl!t of padin lu<k

VDD c nncction pad G D<VS ) nne tion pad


Input pad utput pad Bidirectional V pad natunof cir uitry ratio/ ize of invenerslbuffcrs on "'hich ourput line. arc conne ted how input tine pas. thr ugh the pad circuit (pa.. tran i tor/trnn mi.. ion gate)

Deigncr mu t be aware of:

"tcm d I a) Bu: c nvcnicnt c nccpt in di tributing data c ntrol through a !i.Y tern bidirc ti na t busc arc c tWc.!nicnt in d"'ign of dataparh pr bkm-: capacitive I ad present

l argest capacitance sufficient ti me mu t be al lowed to charge the total bu clock q,, & Q2

Control paths. electors & decoder I . select regi ters and open pa tran i tors to onnccl cell to bu 2. Data propagation d lay bus 3. Carry chain delay

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8.2 f ault and Fa ultlodclin g

A faul t model i a model of how a phy ical or parametric fau lt man.i fe t itself i n the circuit Operation. Fault tc. L"> arc derived based on these models Phy ical Fault are caused due to the folio' ing rca on : , Defect in silicon :ubslratc , Photolithographic defect , Mask contami nation and :cratches , Procc variations and abnormalitie , Ox ide defect. Phy ical fault cause Electrical a11d Logical fault Logical Faull! arc: , Si ngle/multiple tuck-at (most usl'd) , CMOS st uck-open , CMOS tuck-on , A1 D I OR Bridgi ng fault Electrical fauhs arc due to short. open . transi tor tuck on. tuck open, cxce ive tcady stat current:. resi.tive short"> and open. 8.3 De ign for Tetability T' o key concepts Observabi l i ty Con t rollability OFf often is a ociatcd with de ign modifications that provide improved accc s to internal circu i t elmenL"> uch that the local i nternal . tate can be controlled (controllabi lity) ancVor observed (obscrvability) more easily. The de ign modifications can be strict ly phy. ical in na t ure (e.g., adding a physical probe point to a net) and/or add acti c circuit clement to facilitate controllabi lity/ob rvabil ity (e.g., in crting a multiplexer into a net). While controllability and obscrvability improvements for internal circuit clement definitely are importan t for test. they arc not the only t ype of OFf

What oan we do to i noreaee teetability7

inoreaee obeervavillty add more pine (71) add email "probe" bue. eeleotively enable different valuee onto bue uee a haeh funotion to "oompreee" a eequenoe of valuee (e.g., the valuee of a bue over n 1any olook oyolee) into a email numver of bite for later readout oheap readout of all etate Information Page- 195 CITSTUDENTS.I N

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inore6e oontrollbility uee muxee to ieolate eubmodulee and eelect eou rvee of teet data e inpute provide e ey eetup of internztl ette
8.4 Te t i ng com binational logic

The solu t ion to the problem of testing a purely combinational logic block i. a good.ct of pattern. dcte ting "all" the po.. iblc fa ulls. The fir t idea to tc l an N input ci rcuit would be to apply an 7-bi t counter to the inpu t (con trolla bi lit y). then gene rate all the 2 com binations. and ob erve the ou t put for checking (ob crva bil it y). Th i is called "ex ha u li ve te ting". a nd it i very efficient... but onl y for fe, - i nput circui ts. Wh ' n the input nu mber increase. th is technique becomes very tim ' consumi ng.

' I" 'L1

_.

r' o' mr"'no

IJb HillR :

ll L Pl,;

_. 7 \Ill\'\. \0 HOI R..,

.W f't ' l"i _ .

._, l 'L

... !- (.,8 (;l,'lliU

8.5 en itized Path Tc ting

Most of the ti me. in ex hau li ve te ting. many pa ttern , do not occur during the a ppl ication of the circuit So in tead of spendi n g a huge a mount of time searching fo r fault everywhere. the pos i blc fa u l ts are fi rst enu merated and a set of appropriate vectors arc then ge nerated. Thi i called " i ngl e-path se n itization" and it i ba cd on "fault orie nted tc Li ng". The basic idea is to select a path f rom the site of a fa ul t, through a seq uence of gates leading to an ou tput of the combinational logic under test. The process is composed of three steps : Ma nifestatio n : gate in pu ts, at the site of the fau lt, are specified as to generate the opposi te value of the faul ty v al ue (0 for SA J, I for SAO). Propagation : inputs of the other gates are determined so as to propagate the fault signal along the specified path to the primary o u tpu t of the circuit. This is done by setting these inpu ts to "1" for AND/NAND gates and "0" for OR/NOR gates. Con i tency : or justifica tion. This fina l step helps finding the primary i nput pattern that will realize all the necessary in put values. This is do ne by traci ng backward from the gate inpu ts to the primary i nputs of the logic in order to receive the test pa tterns.
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SEN ITIZED PATH

FAULT ORIENTED TESTING :MA IFE TATION PROPAGATIO, CONSISTEN CY

Example!- SAl of l ine I (Ll) : the aim is to tind the vector(s) able to detect this fault .

I'R OPA GATIO{S


.\l\.1> :1.5 = LX = I

OR : Lll o CONSISHN Q'

.A ll. !: .!!
!'iOT : LII O L9 a L7 I OR :L7 = I ll + C+ O = I
\') V2 V3 0 0 0

0
0

0
I

I
0

V4

1\ Ianife tation: Ll = 0 , then i nput A = 0. ln a fault-free si tuati on, the output F cha nges with A if B,C a nd D are fLXed : for B,C and D fixed, Ll is SA I gives F = 0, for instance, even if A= 0 (F = I for fau lt-f ree). Propagation : Throu gh t he AND-gate : L5 = L8 = I, this condition is necessar y for the propagation of the " L1 = 0 ". This leads to Ll 0 = 0. Throu gh the NOR-gate, and si nce Ll0 = 0, then Lll = 0, so the propagated manife tation can reach the primary output F. F is then read and compared with the fault-free value: F= I. Con i tency: From the AND-gate : L5=1, and then L2=B=l. Also L8=1 , and then L7=1. Until now we found the values of A and B. When C and 0 are found, then the test vectors are genera ted, in the same manner, and ready to be a pplied to detect Ll= SAL From the NOT-ga te, Lll=O, so L9=L7=1 (coherency with L8=L7). From the OR-gate L7=J , and since L6=L2=B=l, so B+C+D=L7=l , then C and D can have either 1 or 0.

These three steps have led to four possible vectors detecting L1 =SAL

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Ea mplc 2 - SA I of line SAl

(L8) : The ame combinational logic ha ing one internal line

..
U .l I l . . l.IO O OR : I I . o +1.7 . L8 L9 0 J,JI I,J.IO O Rt CO '\ tR<i "t' 1 I t\:'\.()L I :

Man ifc t a t ion : L

=0

Propagat io n: Through the AND-gate: L5 = Ll = I . then LI O = 0 Through the OR-gate: we '"ru1lto have Ll I = 0, not to ma k LIO = 0. on i tcncy: From the AND-gate 0 leads to L7 0 . From t he OT-gatc Lll 0 means L9 L7 I, L7 could not be set to I a nd 0 at the same t ime. Thi. incompatibility could not be re.ol ved in this case. and the fault "L8 SA I" remain. undetectable.

8.6 0 - AIJ_!orit h m:

G i ven a ircui t cornpri ing combina tional logic. the algorithm ai rn to rind an asignment of input alue that will allow detection of a panicular interna l fault by examining th output condition . ing thi algorithm the y tern can ei ther be aid a. good or fa ult y. The exi te nce of a fault in t he faulty machine ' ill cause a di crcpa ncy between its behavior and that of the good machine for ome particular value of input. The D-algori thm provide a . ystcmatic mea n of as igning i nput va lue. for that particular de. ign . o that the discrepancy is driven to an output where it may be ob. erved a nd thu. detected. The algorithm is time-intensive and computing intensive for large circuit .
Practical d e ign for test guidelines
Practical guidel ines for testa bility should aim to faci litate test processes i n three mai n ways: facilitate test ge neration facilitate test appl jcation avoi d timing problems

These matters are discussed as below:

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8. l m pro'(' on t roll abil it) a nd Ob na bilit y All "de.ign for test" method. en. urc that a de.ign ha enough obscrvabil ity and comrollabiljty to provide for a compl ete and efficien t testing. When a node ha diffi ull access from primary inputs or ou tputs (pads of lhe ci rcu i t ), a very eflicient method is to add internal pad acceding to this kind of node in order. for instance. to con t rol block 82 and observe block B l with a probe.

OlliS

figure .I hnprove Controllability a nd Ob crvabili t y


It is ea.o:;y to ob erve block B I by add i ng a pad just on its ou t put. without break i ng t he link between theto blocks. The cont rol of the block B2 mea ns to .et a 0 or a I to its input. and a l o to be transparent to the link B I-B2. The logic fun Lion of thi purpose are a OR- gate, transpart!nt to a Lcro, and a NA D-gatc, transparent to a one. By this way t he control of 82 is po.sible aero. s the.e two ga te..

Another implementat ion of thi cell i ba ed on pa -gate multiplexers performing the .ame function, but wi t h less tran. istors than with t he A I D and OR gate. ( instead of 1 2).
1l1c imple optimizat i on of observation a nd control is not enough to guaran tee a full testabi lit y of th blocks B I and 82. This technique has to be completed with some other techniques of testing depending on the internal structu res of block. B I and 82.

e Multiplexer
Thjs technique is an extension of the precedent, w hile mu l tiplexers are used in case of limitation of primary inputs and ou tputs. In this case the major penalties are ex tra devices and propagation delays d ue to mu l tiplexers. Demu ltiplexers are also used to i mprove observability. Using multiplexers and dem ultiplexers allows internal access of blocks separately from each other, which is the basis of techniques based on partitioning or bypassing blocks to observe or control separately other blocks.

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SLCn

!lhUt( '2

Figure .2: sc multiplexers 8.8 Pnrtition Lnrge ircuit Panitioning large circuit. into , mal le r . ub-circui ts red uce. the te. t-gcncration cffo n. The test- ge neration effon for a general purpose ci rcuit of n gate L a..umed to be proportiona l to orncw herc betwee n n_ and n3. I f the ci rcuit is panit ioncd into two sub circuits. then the amou nt of test generation cffon i. reduced corresponding l y.

RRDtTT

n "'TST
ln KR

rATHit1\l

Figure 8.3: Parti tion Large Circui t Logical paniti ning of a circui t h uld be based on rc ogni zable u b- function. and can be achieved phy. ically by incorporati ng orne facilitic to i ol atc and conLrOI clock lines, reset Lines a nd power suppl y lines. The multiplexers can be massively used to separate sub-circuits without changing the function of the global circuit Div ide Long Counter Chai n Based on the same principle of par6tioning, the counters are sequential elements that need a large nu mber of vectors to be fully tested. The partitioning of a long counter corresponds to its djvision into sub-cou nters. The full test of a 16-bit counter requires the application of 216 + 1 = 65537 clock pulses. lf tills counter is djvided into two 8-bit cou nters, then each counter can be tested separately, a nd the total test time is reduced 128 times (27). This is also useful if there are subsequent requirements to set the counter to a particular count for tests associated with other parts of the circuit: pre-loadi ng facilities.

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h i ==L =C D =l T = F = .

:t
11
'> < TES'J'I:;R l'ElUOD

TEST TI ME:

'T F.ST' TIT'vffi:2 x 2' x 'T'FSTT'R PE TOD


_, l;.bit COUI'Cf ER ll-bit COUNT Ell

'J'UI' I'

0Uil'L1l'

Figure 8.4: Divide Long Counter Chains

Initial ize equen tiaJ Logic


One of t he most important problems in sequentia l logic testi ng occu rs a t the time of power-on, where the first state is random if there were no initialization. In this case it is i mpossible to start a test sequence correctly, because of memory effects of the sequential elements.
w: =-- .mr: .:w. . m:: w w

IM T IAL IZE SEQUENTIAL LOGIC:

w: w .::w:.:::.:

H.CILJf ,\'T.F. TESTER OVERRT nTT\G AT\1"> T> OW'RR -t.JT> CT.T.A RTN(:

Figure 8.5: Initialize Sequential Logic


The solution is to provide flip-flops or latches with a set or reset i n put, a nd then to use them so t hat the test seq uence would start with a known state. Ideal l y, all memory eleme nts should be able to be set to a known state, but practica lly this could be very surface consuming, also it is not always necessary to initial ize all the sequentia l logi c. For example, a serial-in serial-out counter could have its first flip-flop prov ided with an initialization, then after a few clock pulses the counter is in a !mown state. Overridi ng of the tester is necessary some times, and requires the addition of gates before a Set or a Reset so the tester can override the initialization state of the logi c.

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8.9 A 'oid Anchronou

Logic

Asynchronou logic uses memory element i n which state-tmnslltons arc controlled by the sequence of change on t he primary input . There is thu no way to determine easily ' hen the next state will be established. This i again a problem of timing and memory effect. Asynchronou logic i fa ter than yn hronou logic. sin e the speed in asynchronou logic i only limited by gate propagat ion de l ays and i n terconnects. The design of asy n chronous logic is then more difficult than synchronou (clocked) logic and m u t be carried ou t wit h due regards to the possibi lity of cri tical race (circuit behavior depending on two i n put changing im u l tancously) and hazards occurrence of a momcmary value oppo.itc to the expected value). on-determini tic behavior in a ynchronou l ogic can cause problem. during fa u lt simulation. Ti me dependency of operat ion can make testing very difficult, si nce it i. en. i tive to tester ignal kew. 8.10 'oid Loical Redundancy Logical redundancy exist. either to ma. k a .talic-hazard condition. or unin tent i onally (desi gn bug). I n bot h case. , ' ith a logically redu nda nt node it i. not po.. ible to make a primary outpu t val ue dependen t on the va lue of the red u ndant node. This mean. t hat certai n fau lt conditions on t he node cannot be detected, such as a node SA I of the function F.

F A n + AC:+ nC
= An + AI.

TF.ST VF.CTOR FOR


SA..cJ FA!JI.T: I A

BCJ = l i i O J

c
Figu re 8.6: Avoid Logical Redundancy Another inconvenience of logical redunda ncy is the possibility for a non detectable fa ult on a redundant node to mask the detection of a fa ult normall y-detectable, such a SAO of input C in the second exam ple, masked by a SA1 of a redunda nt node.

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8.11A \'oid DeJ a) DcpNtdent Lo ic Au tomatic tc 1 pauem genera tors ' ork in logic domains. the vie" delay dependent logic a redundant combi national logic. In this case the ATPC will ee a n A I D of a signal ' ith its complement. and will therefore alway. compute a 0 on the output of the AND-gate (in. tcad of a pulse). Adding a n OR -gate after the A D-gatc ou tput pcm1it! to the ATPC to sub t i tute a clock ignal directly.

n; TbRS WOIN I.<)CIC I.I()MAIN KI--.UUI\1>AN"I C:OMUif\(A nONAL LOG IC

Figure 8.7: Avoid Delay Dependent Logic 8.12 c\' oid Clock a tin

When a clock signal i gated wi t h any data signal. for example a load signal com i ng from a tc. lcr. a ske' or any other hazard on t hat sign al can cause an error on the ou tput of logic.

CLOCK

LOAn
Ct.OC" U>AO l: OATA

--:_,r--,..,.

L- r-------.u ----

:""""lG
Figure 8.8: Avoid Clock Gati ng

This is also due to asynchronous type of logic. Clock signals should be distributed in the circuit with respect to sy nchronous logic structure.

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8.13o tingui h B twecn ignal and Clock This is another liming situation to avoid, in which the tester could not be synchro nized if one clock or more arc dependent on asyn chro nous delays (across D-input of nip-tlops, for example).

Figure 8.9: Di tingui h Between Signal and Clock


8.14 . \"oid elf Resetting Logic
The self re!>elling l ogic is more related to a.'>ynchronous logic, since a .rescl input is independent of clock signal.

Before the delayed resel. the t.e_ ter read the et value and continues the nonnal operation. If a reset has occurred before te ter observation, then the :read alue is erroneous. The solution to this problem is to allow the tester to override by adding an OR-gate, for example, with an inhibi lion i nput coming from the lester. By Lhis way the right response is given loth l tcr at the right time.

H li.SliT :\lA Y OCCUR

BE f ORE TilE TEST h H H i\.S OBSER YE O


THE SF.T V A I.lJC

J 'H HJJTJOr- . 1:-1 rn


FOR T ESTING

Figure 8.10: A void Self Resetting Logic U e Bu ed Stru ctu re This approach is related, by structure, to partitioning technique. It is very useful for microprocessor-like circuits. Using this structure allows the external tester the access of three buses, which go to many different modules.

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1'12..\"TJ: C"At\ ACC


OI F FR I V.NT F.l

r:l\m

A..'ID lSOLA'lt: IW:: H:\ 'THE Ul

Figure .I I : sc Bused Structure The te.ter can then disconnect any modu I from the busc. by putting its ou tput into a high- impedance state. Te. t patterns can t hen be applied to each module separately.
8.2 epa rate Ana l oa nd Digit a l ircuit

Testi ng analog circuit requi res a complete l y different strategy than for digital circuit A I o the sharp edge of digital ignals can cau e cross-talk problem to the analog lines, if t hey are cl se to each other.
1 SI::' ARAn : A:'IIAT.OG AND DI<:JTAL cmcu rs
zw ::w: w W- :mr::: .-==::
:m:
_ w::::w;_ m

w :m:

:m: ..

ATl'G

:--

.....
uu;rr AL AALOG

Al\ALOG

i
I
I
'

1:+

r--

Tf.S1Elt

:\lJ C _.. IHU (; O Vl AA LOIJ lNl'trlS 1'0.1( l'h..ST

n,\ CRRI'lG Ol "T DTG TTAL Jl\PUTS FOR 'IEST

Fi gure 8.12: Separate Analog and Digi tal Circuits

If it is necessary to route digi tal signals near an a log lines, then the digi ta l li nes should be properl y bala nced and shield ed. A lso, in the cases of circuits l ike Ana log Digi tal con verters, it is better to bring out analog sign als for observation before conversion. For Digital- Analog converters, digital si gnals are to be brou ght out also for observation before con version.

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8.3 Ad-Hoc OFT lthod

i Good de. ign practice learnt through experience arc u cd a guidcljnc :


A void a ynchronou (un locked) feedback. Make nip-Oop. initializtlble. Avoid redundan t gate . Avoid large fan-in gate . Provide te t control for difficult-to-control Avoid gated clock . Avoid delay dependant logic. Avoid parallel dri er . Avoid mono table and elf-resetting logic. ignals.

De ign Rcvies

:I Manual analy is
Conducted by ex pen

0 Programm d analysi
U.i ng design auditing tool:

0 Programmed enforcement Mu:t usc certain de ign practices and cell t ypes.
bjcctive: Adherence to de ign guideline and tetability improvement technique.ilh little impa t on perfom1ance and area

Disadva ntages of ad-hoc OFT met hods: Experts and tools not always available. Test generation is often manual with no guaran tee of high fa ul t coverage. Design iterations may be necessary. ca n De ign Technique The set of design for testability guideli nes presented a bove is a set of ad hoc methods to design random logic in respect with testability req u irements. The scan design techniques are a set of structured approaches to design (for testability) the sequential circuits. The major difficu l ty in testing seq uential circu its is determining the internal state of the circuit Scan design techniques are directed a t improving the controllability and observabitity of the internal states of a sequential circuit. By this the problem of testing a sequential circuit is red uced to that of testing a combi national circuit, si nce the internal states of the circuit are under control.

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8.4

can Path

The goal of the :can pat h technique is t o recon figu re a sequentia l circuit, for the pu rpose of te. ting. into a combinational circuit. Since a seq uentia l circui t is based on a combinational circuit and .omc tornge element . the technique of can path con i t in connecting together al l the storage elements to form a long erial hift register. Thu the i ntemal slate of the circu i t ca n be ob erved and controlled by hifting (:ca n ning) ou t the conteno t f the storage clement . The hift regi ter i then called a can path.

l\l'l,1

VI
OUT

.._--t--rJ;.Jt--

Figure 8.13: can Pat h The torage el emen t can ei ther be D. J -K. or R-S type of nip-Oop but imple lat he. ca nnot be u.ed in scan path. Ho' ever, t he struc t ure of storage clement. i. :light ly differcnl t ha n cia.! . ical one.. Generally the selection of the input source i. achi eved using a mu l tiplexer on the data input con trol l ed by an ex temaJ mode signal. Thi multiplexer is integra ted into the 0-flip-Oop. in our case: the D-nip-Oop i then called MD-fiip-Oop (mul ti plexed-nip-flop). The sequential circuit containing a scan path has two modes of operation: a normal mode and a test mode which confi gure the storage elements in the scan path. As an alyzed fro m figure 8.13, i n the nonnaJ mode, the storage elements are connected to the co mbina tional circuit, in the J oops of the global sequential circuit, which is considered then as a finite state machine.
In the test mod e, the loops are broken a nd the storage eleme nts are connected together as a serial shlft register (scan path), receiving the same clock signal. The inpu t of the scan pa th is caiJed scan-in and the output scan-ou t Several scan paths can be implemented in one sa me compl ex ci rcuit if it is necessary, though having severa l sca n-in inputs a nd sca n-out outputs.

A large seque ntia l circuit ca n be parti tioned i nto sub-ci rcui ts, contammg combinational sub-circuits, associated with one scan pa th each. Efficiency of the test pattern genera tion for a combi national sub-circuit is greatly improved by partitioning, since its depth is reduced.

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Before applyi ng test patterns, the shift register itself has to be verified by shifting in all ones i.e. ll J...l l , or zeros i.e. 000...00, and comparing. The method of testing a circuit with the scan path is as follows:
I. Set test mode signal, flip-flops accept data from input sca n-in 2. Verify the scan path by shifting in a nd out test data 3. Set the shift register to an ini tial state 4. Apply a test pattern to the primary inputs of the circuit 5. Set normal mode, the circuit settles and can monitor the primary outpulof the circuit 6. Activate the circuit clock for one cycle 7. Return to test mode 8. Scan out the contents of the registers, si multaneously scan in the next pattern 8.5 Len-1 w nsit hity can de iAn t L
'

)))

01 CK1

L1

S1
CK3
CK2 - - - - ..;

L2

Fi gu re 8.1 4: Level sensitivity n . design The levci-M!nsiti vepeel means that the sequen tial net" ork i designed so Lhat ' hen a n input change occu r the re pon c is independent of the component and ' iring delays within Lhe network (Figure .14 ). The scan pa th a pc l is due to lhc u e of shift regi Ler l atchc (SRL) employed as storage clement In Lhe te t mode they are connec ted as a long serial hidt register. Each R L ha. a specific de.ign . imi l ar to a m:u tcr-slave FF. it is driven by 1\ o non over lapping clo k which can bt! controlled readily from Lhc primary input to the circuiL Input OJ i. then m1al data input to the RL: clock CKI and CK2 control the nonmtl opera tion of the SRL whi le cloch CK3 and CK2 control c<m path movements throug h the R L The RL output i derived at L2 in both mode of operation. the mode depending on which clocks arc acti vated. Advantages: Circui t operation i indpendent of dynamic characterist ic of the logic ele ments ATP genera tion i. .implificd El iminate haLard and race Simplifies tc.t generation and fault simula tion

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8.6Bo u nd uy 'canTe t (B 'TI Boundary Scan Test (SST) i. a technique involving can path and .elf-test ing technique. to rc. olve the pr blem of te ting board. carrying VL I integrated circuit and/or urface mounted device (SMD). Printed ci rcuit board ( PCB) arc becoming cry den c and complex. e pecially with SMD cir uit . th.t mo t te t equipment cannot guara ntee good fault coverage. BST {figure 8.1 5) consisin placing a scan path {shi ft register) adjacent to each componen t pin and to intercon nect the cells in order to form a chai n around the border of the circuit. The BST circuit. contained on one board arc then connected together to fom1 a single path lhroug h the board.
The boundary can path i provided wi th erial input and output pad and appropriate clock pads which make it po ible to:

Te. t the interconnections between the various chip Deliver te t data to the chip on board for self-te ting Te t the chip themselve with internal sel f-te.t

ITST

ACCESS
PORT
( 1'\P )

Figure 8.15: Boundary Scan Test ( BST) The advantages of Boundary scan technique. are as follow. : No need for complex te ter in PCB te ting Tc t engineer ' ork is implified and more efficient Time to pend on te t pattern generation and applicat ion i reduced Fau ll coverage i. greatly increa cd. S.

th r ca n teclmictue
Partial Scan Method

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A subset of flip-flops is scanned. Objectives:


o Minimize area overhead and scan sequence length, yet

achieve required fault coverage o Exclude selected flip-flops from scan: Improve performance Allow limited scan design rule violations o Allow automation:
In scan flip-flop selection

In test generation o Shorter scan sequences- reduce application time


Ran dom Acce Sca n .Method

The scan function is implemented like a random


access memory (RAM) All flip-flops form a RAM in scan mode A subset of flip-flops can be included in the RAM if partial scan is desired In scan mode, any flip-flop can be read or written
Procedure: Set test inputs to all test points Apply the master reset signal to initialize all memory elements Set scan-in address & data, then apply the scan clock Repeat the above step u ntil all intemal test inputs are scanned Clock once for normal operation Check states of the output points Read the scan-out states of all memory elements by appl ying the address

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8.8 Built-in-'\elf tl?;,t Objectives:


I. To reduce te t pattcm genenuion co t

2. To reduce volume of test dat a 3. To reduce te t t ime Built-in elf Tc t. or BIST. i the techn ique of de igni ng addition a l hardware and oft ware feat u re into integrated circuit to aJ io\ them to perfom1 self-test ing. i.e.. tc t ing of t heir own operation (functionally. parametrically, or both) using their ow n circuits, thereby red uci n g dependence on a n ex ternal automated tc. t equipmen t {ATE). BIST is a De ign -for-Testabil ity ( OFf) techniq ue. be ause it make t he elect rical teting of a chip ca icr, faMcr, m rc efficient. and Jess co t l y. The concept of B l T is applicable to j ust abou t a ny kind of circuiL .o i t. impl emen!alion can vary a. widely a the product diversity t h at it caters to. A an example. a common BIST approach for
DRAM's includes the incorporation onto the c hip of additionaJ circuits for pattern generation, timi ng, mod e selecti on, a nd go-/ no-go di agnostic tests. Advan tages of im plementing BIST include: 1) Lower cost of test, sin ce the need for ex ternal electrical testing using a n ATE will be reduced, if n ot elim.in ated 2) Better fa ult coverage, since s pecial test stm ctures ca n be incorpora ted onto the chips 3) Shorter test times if the BIST can be designed to test more structures in paraJ lel 4) Easier customer su pport and 5) Ca pabilit y to perform tests outside the production electricaJ testing enviro nmen t The last ad vantage menti oned can actually allow the consumers the mselves to test the chips prior to mounting or even after these are in the appl ication boards. Disad vantages of im plementing BIST include: 1) Addi tional si li con area a nd fab processin g requ iremen ts for the BIST circuits 2) R ed uced access ti mes 3) Additional pin (and possibl y bigger package si ze) requirements, since the BIST circuitry need a way to interface wi th the ou tside world to be effecti ve and 4) Possible issues with the correctness of BIST results, since the on- chi p testing hard ware itself can fai l. Tech niques are: compact test: sig na ture anal ysis linear feedback shift register

BILBO
self checking technique

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Compact Te t: Sign ature a n a l ysi Signature anal ysis perfor ms pol ynomial di v ision that is, di v ision of the data ou t of the device under test (OUT). This data is represen ted as a polynomial P(x) which is di vided by a characteristic pol ynomia l C(x) to give the signature R(x), so that R(x) = P(x)/C(x) This is su mmarized as i n figure 8. 16.

TGP (Di gita l Tester)

OUT

Co mpaction Sig na ture

Analysis

Figu re 8.16: BIST - signature anal ysis


8.9 Li near feedback hift t<cgi
t

r < LF R >:

An LF R i. a hift regi. tcr that. ' hen clocked. advances the . ignal through the register from one bit to the next mo t- ignificant bit. omc of the output arc combined in exclusive-OR onfiguration to form a feedba k mechanism. A l i near fccdba k shift rcgi.ter can be fanned by pcrfonning exclusive-OR (Figure .16) on t he outputs oft' o or more of lhe flip-flop together and feeding those output back into the input of one of the nip-flops. LFSR technique can be applied in a number of ways. in luding random number generation, polynomial division for < ignature analysi . and n-bit counting. LFSR can be eric or parallel. the difference being in the operating peed and in lhc area of silicon occupied:Parallel LFSR being faster but larger than serial LFSR. iO
il

i2

DO

Cl ock

QO

QL

Q2

Figure 8..16: Linear feedback shift register

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8.10 Built-in logic bl ck o b nc r ( BI LBO ):


BI LB i. a bui lt-in le. l generation chcmc wh ich usc. .ig nat u re analy i in conjunctjon with a can path. The major omponen t of a BI LBO i a n LFSR ' ith a few ga les ( Figu re 8.17). A BILB register ( built-in logic:- bl ock obM- nl.'r) combi nes nonnal nipnop w i lh a few addi t ional gates to prov i de four differe nt fu nct ions. The example ci rcuit sho'' n i n the applel realiLc a four-bi t regi ster. However. the gcneraliLat ion to larger bit width . shou ld be obviou . wi th t h XOR gates in t he L FSR feedback pat h cho e n to i rTaplcmcnt a good polynom i al for the given bi t-\ id t h. When the A a nd B co ntrol inputs are both J , the circuit functions as a n onnal paraJiel D-t ype register. When bot h A and B i nputs are 0, the D-i npu ts are ig nored (du e to the AND gate connected to A ), but the tlipfl ops are connected as a shjft-regi ster via the NOR a nd XOR gates. The input to the ftrst fupflop is then selected v ia the multiplexer controlled by the S input. If the S input is J , the multiplexer transmi ts the value of the external SI N shlft-in input to the tirst tli ptlop, so tha t the BILBO register works as a normal shl f t- register. This allows to i nitialize the register contents using a single signal wire, e.g. from an externa l test con troller.

If all of the A , B, and inputs are 0, the tli pflops are configured as a shiftregister, again , but the input bit to the first fli pflop is computed by the XOR gates in the LFSR feedback pa th . This mea ns that the register works as a sta ndard LFSR pse udorandom pa ttern ge nerator, useful to drive the logic connected to the Q ou tputs. Note that the start value of the LFSR sequ ence can be set by shifting it in via the SIN input.
Finall y, if B and are 0 but A is 1, the flipflops are config ured as a shift-register, but the input valu e of each flipflop is the XOR of the D-input and the Q-output of the previ ous flipflop. This is exactly the configuration of a stand ard LFSR si g nature a nalysis register. Beca use a BILBO register can be used as a pattern generator for the block it drives, as well provide sign a ture-anal ysis for the block it is driven by, a whole circuit ca n be made self- testable with very low overhead and with only minimal perionn ance degrad a tion (two ex tra ga tes before the D i nputs of the fupflops).

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lI < I II I II

. . .. ll'lp fD'Jf"'...

"'--''l fl .(l

.. , l..oN I II ._ I I>

,.r..t "NII,fDI

palldmau lpull

Figure 8.17: BIST -BILBO


8.11"If-c heckin g techniqu e': It consists of logic block and checkers should then obey a set of rules in which t he logic block i 'strongly fault secure ' and the checker trongly code disjoint'.The code usc in data encoding dependon the type of errors that may occur at the logic block output. In general three type. arc po ible:
Simple error: one bit only affected at a Lime. Unidirectional error: multiple bits at I in tead of 0 (or 0 in Lead of 1) affected in any order.

Multiple error: multiple bit

elf-checking techniques are applied to circuiin which ccurity ts tmportant :o that fault tolerance is of major interest. Such technique will occupy more area in ilicon than clru ical tcchniques such a: functional te.t ing but prov ide very high test coverage.

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Recommended questions:
1. Define testabilit y. 2. With an example define performance parameters. 3. Briefly explain the layout issues while design a circuit in vlsi. 4. Explain I/O pads. 5. Explain t ypes of I/O pads. 6. What do you mean by real estate in the field of vlsi design. 7. What do you mean by delays. 8. Explain system delays. 9. What is need of providing delays to the system. 10. Write a short note on test and testabilit y.

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