Freescale Semiconductor Application Note

Document Number: AN4603 Rev. 1.0, 12/2012

Power Management Design Guidelines for the i.MX50x Family of Microprocessors

Purpose

Contents
1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 i.MX50 Microprocessor Overview . . . . . . . . 2 4 i.MX50 Power Management Design with MC13892 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 i.MX50 Power Management Design with the MC34709 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 References . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 Revision History . . . . . . . . . . . . . . . . . . . . . 44

The present document is intended to teach the reader how to supply the power management to the i.MX50x family of processors using either the Freescale MC13892 or the MC34709 as the main power management device.

Introduction

The i.MX50x family of microprocessors requires complex power management distribution along with specific sequencing for proper power up. To supply integrated power management to the i.MX50 processors, Freescale provides two highly integrated PMICs solutions for different specific scenarios. The MC13892, provide a highly integrated solution which provides most of the required voltage rails as well as integrated battery charger, 10 bits ADC and backlight LED drivers. Likewise, the MC34709 is a reduced solution providing as well the majority of the required power rails for applications with less system requirements.

Freescale Semiconductor, Inc., 2012. All rights reserved.

i.MX50 Microprocessor Overview

i.MX50 Microprocessor Overview

The i.MX50 Applications Processors (i.MX50) is part of a growing family of multimedia-focused products, offering high performance processing optimized for lowest power consumption. The i.MX50 is optimized for portable multimedia applications and it features Freescale's advanced implementation of the ARM Cortex-A8 core, which operates at speed as high as 800 MHz. The i.MX50 provides a powerful display architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). In addition, i.MX508 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs. The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, and displays. i.MX50 power requirements are summarized in Table 1. Table 1. i.MX50 Power requirements Voltage Domain Name
VDDGP

Voltage TYP
1.05 0.95 0.9 0.85 0.95 1.05 1.225 1.2 0.95 1.2 0.95 3.0 2.5 1.8 1.8 1.875 or 2.775 1.8 1.2

Current Units
V V V V V V V V V V V V V V V V V V 350 mA 10 150 10 10 mA mA mA mA 250 mA 400 mA

Description
400< fARM 800 MHz 167< fARM 400 MHz 24< fARM 167 MHz Stop Mode

Max
1250

Units
mA

VCC

LPM RPM HPM

VDDA

Run Mode Stop Mode

VDDAL1

Run Mode Stop Mode

VDD3P0 VDD2P5 VDD1P2 VDD1P8 NVCC_JTAG NVCC_EMI_DRAM

Bandgap and 480 MHz PLL supply Efuse, 24 MHz oscillator, 32 kHz oscillator mux supply PLL digital supplies PLL analog supplies GPIO digital power supplies DDR2/LPDDR1 LPDDR2

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i.MX50 Microprocessor Overview

Table 1. i.MX50 Power requirements Voltage Domain Name

VREF

Voltage TYP
1/2 NVCC_E MI_DRAM 2.5 HVIO_L=1.875 HVIO_H=3.0

Current Units
V

Description
DRAM Reference Voltage Input

Max
0.004

Units
mA

VDDO25 NVCC_NANDF NVCC_SD1 NVCC_SD2 NVCC_KEYPAD NVCC_EIM NVCC_EPDC NVCC_LCD NVCC_MISC NVCC_SPI NVCC_SSI NVCC_UART NVCC_SRTC NVCC_RESET USB_H1_VDDA25 USB_OTG_VDDA25 USB_DDA33 USB_OTG_VDA33

EMI Pad Predriver supply High voltage I/O (HVIO) supplies

V V

10

mA

SRTC core and I/O supply (LVIO) LVIO USB_PHY analog supply USB PHY I/O analog supply

1.2 1.875 or 2.775 2.5 3.3

V V V V 50 16 mA mA

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i.MX50 Power Management Design with MC13892

3.1

i.MX50 Power-up/down Sequence

NVCC_SRTC

VCC

VDDGP

VDDA VDDAL1

VDD3P0

VDDO2P5

VDD2P5

NVCC_EMI_DRAM

VDD1P8 VDD1P2

VREF

NVCC_EIM NVCC_EPDC NVCC_JTAG NVCC_KEYPAD NVCC_LCD NVCC_MISC NVCC_NANDF NVCC_RESET NVCC_SD1 NVCC_SD2 NVCC_SSI NVCC_UART

USB_OTG_VDDA25 USB_H1_VDDA25 USB_OTG_VDDA33 USB_H1_VDDA33

Figure 1. i.MX50 Power up Sequence

NOTE The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. No power-up sequence dependencies exist between the supplies shown shaded in gray.

3.2

Power-Down Sequence

The power-down sequence is recommended to be the opposite of the power-up sequence. In other words, the same power supply constraints exist while powering off as while powering on.

i.MX50 Power Management Design with MC13892

Battery charger system for wall charging and USB charging 10-bit ADC for monitoring battery and other inputs, plus a coulomb counter support module Four adjustable output buck regulators for direct supply of the processor core and memory 12 adjustable output LDOs with internal and external pass devices Boost regulator for supplying RGB LEDs Serial backlight drivers for displays and keypad, plus RGB LED drivers

The MC13892 is a power management IC that includes the necessary sources to supply the i.MX50. Its main features are:

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i.MX50 Power Management Design with MC13892

Power control logic with processor interface and event detection Real time clock and crystal oscillator circuitry, with coin cell backup and support for external secure real time clock on a companion system processor IC Touch screen interface SPI/I2C bus interface for control and register access

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i.MX50 Power Management Design with MC13892

4.1

MC13892 Voltage supplies

Table 2. MC13892 Voltage Supplies Summary Supply
SW1 SW2 SW3 SW4 SWBST VIOHI VPLL VDIG VSD VUSB2 VVIDEO VAUDIO VCAM

Typical Application
Buck regulators for processor core(s) Buck regulators for processor SOG, etc.

Output Voltage (in V)

0.600-1.375 0.600-1.375; 1.100-1.850

Load Capability (in mA)

1050 800 800

Buck regulators for internal processor memory and 0.600-1.375; 1.100-1.850 peripherals Buck regulators for external memory and peripherals
0.600-1.375; 1.100-1.850

800

Boost regulator for USB OTG, Tri-color LED drivers 5.0 IO and Peripheral supply, eFuse support Quiet Analog supply (PLL, GPS) Low voltage digital (DPLL, GPS) SD Card, external PNP External USB PHY supply TV DAC supply, external PNP Audio supply Camera supply, internal PMOS Camera supply, external PNP 2.775 1.2/1.25/1.5/1.8 1.05/1.25/1.65/1.8 1.8/2.0/2.6/2.7/2.8/2.9/3.0/ 3.15 2.4/2.6/2.7/2.775 2.5/2.6/2.7/2.775 2.3/2.5/2.775/3.0 2.5/2.6/2.75/3.0 2.5/2.6/2.75/3.0 1.2/1.5/2.775/3.15 1.2/1.5/1.6/1.8/2.7/2.8/3.0/ 3.15 1.8/2.9 1.8/2.9 3.3

300 100 50 50 250 50 350 150 65 250 200 350 50 250 100

VGEN1 VGEN2 VGEN3

General peripherals supply #1, external PNP General peripherals supply #2, external PNP General peripherals supply #3, internal PMOS General peripherals supply #3, external PNP

VUSB

USB Transceiver supply

4.2

MC13892 Power-up Sequence

The Power Up mode Select pins (PUMS1 and 2) are used to configure the startup characteristics of the regulators. Supply enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. Tying the PUMSx pins to ground corresponds to 00, open to 01, VCOREDIG to 10, and VCORE to 11. The recommended power up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the bare essentials, to allow processor startup and software to run. With such a strategy, the startup transients are controlled at lower levels, and the rest of the system power tree can be brought up by software. This allows optimization of supply ordering where specific sequences may be required, as well as supply default values. Software code can load up all of the required programmable options to avoid sneak paths, under/over-voltage issues, startup surges, etc., without any change in hardware. For this reason, the Power Gate drivers are limited to activation by software rather than the sequencer, allowing the core(s) to startup before any peripheral loading is introduced.
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i.MX50 Power Management Design with MC13892

The power up defaults Table 3 shows the initial setup for the voltage level of the switching and LDO regulators, and whether they get enabled. Table 3. Power Up Defaults Table PUMS1 PUMS2
SW1 (1) SW2 (1) SW3
(1)

GND Open
0.775 1.025 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 3.150 Off

Open Open
1.050 1.225 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 Off Off

VCOREDIG Open
1.050 1.225 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 3.150 Off

VCORE Open
0.775 1.025 1.200 1.800 Off 3.300 (2) 2.600 1.800 1.250 2.775 Off Off

GND GND
1.200 1.350 1.800 1.800 5.000 3.300 (4) 2.600 1.500 1.250 2.775 3.150 3.150

Open GND
1.200 1.450 1.800 1.800 5.000 3.300 (4) 2.600 1.500 1.250 2.775 3.150 3.150

SW4 (1) SWBST VUSB VUSB2 VPLL VDIG VIOHI VGEN2 VSD

Not initialized during power-up VCAM VGEN1 VGEN3 VVIDEO VAUDIO Notes
1. The SWx regulators are activated in PWM pulse skipping mode, but allowed when enabled by the startup sequencer. 2. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS. 3. The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO 4. SWBST = 5.0 V powers up and does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.

Off Off Off Off Off

Off Off Off Off Off

Off Off Off Off Off

Off Off Off Off Off

Off Off Off Off Off

Off Off Off Off Off

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i.MX50 Power Management Design with MC13892

The power up sequence is shown in Table 4. VCOREDIG, VSRTC, and VCORE are brought up in the pre-sequencer startup. Once VCOREDIG is activated (i.e., at the first-time power application), it will be continuously powered as long as a valid coin cell is present. Table 4. Power Up Sequence Tap x 2ms
0 1 2 3 4 5 6 7 8 9 Notes
5. The following supplies are not included in the matrix since they are not intended for activation by the startup sequencer: VCAM, VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column. 6. USB supply VUSB, is only enabled if 5.0 V is present on UVBUS. 7. SWBST = 5.0 V powers up and so does VUSB regardless of 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.

PUMS2 = Open
SW2 SW4 VIOHI VGEN2 SW1 SW3 VPLL VDIG VUSB (6), VUSB2

PUMS2 = GND
SW2 VGEN2 SW4 VIOHI, VSD SWBST, VUSB (7) SW1 VPLL SW3 VDIG VUSB2

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with MC13892

Power on event

SW2 SW4 VIOHI VGEN2 SW1 SW3 VPLL VDIG

VUSB VUSB2

2ms 2ms 2ms 2ms 2ms

2ms 2ms

4ms

Figure 2. MC13892 Power up Sequence for i.MX50 processors.

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i.MX50 Power Management Design with MC13892

4.3

Interfacing the i.MX50 with the MC13892.

Table 5, shows all the i.MX50 voltage rails, their power requirements and their associated MC13892 regulator. Most of the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending on each application needs Table 5. i,MX50 voltage domain supplies with the MC13892 I.MX50 Power Rail of i.MX50
NVCCSRTC VCC VDDA VDDAL1 VDDGP VDDO2P5 VDD2P5

MC13892 TYP
1.2 1.2 1.2 1.2 1 2.5 2.5

Power Domain
32 kHz osc. power (when chip off) LP Transistor power Peripheral Memory + L2 Cache power L1 Cache power Core and G Transistor power Predriver for EMI pads Power to 24 MHz osc, efuse, xtalok, 32 kHz osc. power mux Power to EMI pins DRAM Reference

Associated Regulator
VSRTC SW2 SW3 SW3 SW1 External LDO External LDO

Voltage Current PUM[4:0]=1110 (mA)

1.2 1.2 1.2 1.2 1 2.5 2.5 0.05 800 800 800 1050 250 250

PUS
0 5 5 4 -

NVCC_EMI_DRAM VREF

1.2 0.9

External Buck Voltage divider 0.5 x NVCC_EMI_DRA M VGEN2

1.2 1.2 * 0.5

250

NVCC EIM NVCC JTAG NVCC SPI NVCC SD NVCC NANDF NVCC SSI NVCC MISC NVCC KEYPAD ALL 3.3V IO NVCC NVCC EPDC NVCC LCD NVCC UART NVCC_SD2 VDD3P0

3.0 V I/Os

3 3 3 3 3

3.0

350

3.0 V I/Os 3.15 3.15 3.15 3.15 VDD2P5 LDO input + power to Bandgap, DCDC predriver, tempsensor, 480 MHz PLL 3

External Buck

3.15

5000

VSD VGEN2

3.15 3.0

250 350

10

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i.MX50 Power Management Design with MC13892

Table 5. i,MX50 voltage domain supplies with the MC13892 I.MX50 Power Rail of i.MX50
USB_OTG_VDDA33 USB_H1_VDDA33 All 1.8 IO NVCC VDD DCDCI VDD DCDCO NVCC_RESET (LVIO)

MC13892 TYP
3.3 3.3 1.8 Not used

Power Domain
Power to USB Host Power to USB OTG 1.8 V I/Os

Associated Regulator
VUSB VUSB SW4

Voltage Current PUM[4:0]=1110 (mA)

3.3 3.3 1.8 100 100 800

PUS
9 9 1

Power to POR_B,RESET_IN_B, TESTMODE, & BOOTMODE[0:1] Power to USB Host Power to USB OTG Power to all PLLs Power to all PLL digital, 32 kHz osc. (when chip on), much of analog, digital

1.875 or 2.775

VPLL

1.8

50

USB_OTG_VDDA25 USB_H1VDDA25 VDD1P8 VDD1P2

2.5 2.5 1.8 1.2

VUSB2 VUSB2 VPLL VDIG

2.5 2.5 1.8 1.2

50 50 50 50

9 9 6 7

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i.MX50 Power Management Design with MC13892

4.3.1

Interfacing Block Diagram

The following block diagrams show all the power connections needed for the interface, as well as how the communication signals must be connected between the i.MX50 and MC13892.

MC13892 SW1 5.0V SW2 SW4B VUSB 4.2V regulator 1.2V Buck VDDGP VCC NVCC_EIM_DRAM i.MX50

USB_VDDA33 USB_VDDA25 VDD1P2 VDD1P8 NVCC_RESET VDDA VDDAL1 VDD3P0 NVCC_MISC NVCC_SPI NVCC_SD1 NVCC_NANDF NVCC_KEYPAD NVCC_SSI NVCC_JTAG

VIN

VUSB2 VDIG

VPLL

VSW3

VGEN2

2.5V LDO 2.5V LDO

VDD2P5

VDDO25 NVCC_UART NVCC_LCD NVCC_EPDC

Peripherals 3.15V Buck regulator 3.15V CODEC HDMI ETHERNET 3G PCIe RS-232

Figure 3. i.MX50 Power Interface with MC13892 Block Diagram

12

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i.MX50 Power Management Design with MC13892

MC13892
RESETBMCU RESETB STANDBY POWERON1

SWx

i.MX50
POR_B RESET_IN_B PMIC_STBY_REQ PMIC_ON_REQ

SWx

WDI INT
SWx

WDOG GPIOX_X

UID CKL MISO/SDA

USB_OTG_ID CSPI_SCLK CSPI_MISO/MOSI

CLK32MCU PUMS1 PUMS2

VCOREDIG NC

CLK

Figure 4. i.MX50 Control Interface with MC34709 Block Diagram

4.3.1.1

3.15 V Buck Regulator

For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current requirements (for example a 3G module or Wi-Fi card). The MC34709 has limited 3.15 V output ability.

4.3.1.2

1.2 V Buck Regulator

A 1.2V Buck regulator is required to provide voltage to the 1.2V LPDDR2 module and the NVCC_EMI_DRAM domain in the i.MX50 processor. Regulator SW4 will supply the input of this regulator at 1.8V and will also be used as the 1.8V supply on the LPDDR2 Module as well.

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i.MX50 Power Management Design with MC13892

4.3.1.3

2.5 V LDO Regulators

Due to the Power-up sequence dependency, two 2.5V LDO regulators are required to power up the VDD2P5 and VDDO25 domains in the i.MX processor. The first one is enabled by the SW2 voltage rail, while the second LDO is enabled with the VGEN2 voltage rail. See Figure 3.

4.3.2

Interface Power-up Sequence

NVCCSRTC VSRTC

The resulting power-up sequence of the interface is shown in the following figure

VCC VDD2P5 2.5V LDO regulator 1.8 NVCC I/O rails VDD DCDCI VDD DCDCO NVCC_EMI _DRAM 1.2V DC-DC regulator

SW2

SW4

N/A

VIOHI

VDD3P0 NVCC EIM NVCC JTAG NVCC SPI NVCC SD NVCC NANDF NVCC SSI NVCC MISC NVCC KEYPAD

VGEN2

VDDO25

2.5V LDO regulator

3.3V NVCC I/O NVCC_EPDC NVCC_LCD NVCC UART

VDDGP

3.15V Buck regulator

SW1

VDDA VDDAL1

SW3

VDD1P8 NVCC_RESET (LVIO)

VPLL

VDD1P2

VDIG

USB_OTG_VDDA33 USB_H1_VDDA33

USB_OTG_VDDA25 USB_H1VDDA25

VUSB

VUSB2

SD2

VSD* Enabled via SPI

Figure 5. Power up Sequence Flow Chart

14

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i.MX50 Power Management Design with MC13892

4.4

Application Example with the MC13892

The following schematic is simplified application example for interfacing the MC13892 with an i.MX50 processor. note that this schematic only includes the block related to the power section as well as power management controlling signals.
U12E PCIMX508DJV1A 3V_VGEN2 SH4 DNP VDD3P0 C66 0.1UF VDD2P5 SH8 DNP GND VDD2P5 C74 0.1UF 1V8_ANA_PLL C89 0.1UF GND VDD1P8 C75 22UF JP3 HDR 1X2 DNP VDDGP 1V_SW1

VDD3P0

AD4

VDD2P5

AD7

VDD1P8

VDDGP_1 VDDGP_2 VDDGP_3 VDDGP_4 VDDGP_5 VDDGP_6 VDDGP_7 VDDGP_8 VDDGP_9 VDDGP_10 VDDGP_11 VDDGP_12 VDDGP_13 VDDGP_14 VDDGP_15 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VDDA_1 VDDA_2

C67 0.22UF GND

C68 0.22UF

C69 0.22UF

C85 0.22UF

C70 0.22UF

C86 0.22UF

C87 0.22UF

C71 0.01UF

C88 0.01UF

C72 10UF

C73 22UF

JP2 HDR 1X2 DNP VCC 1V2_SW2 C76 0.22UF GND C90 0.22UF C77 0.22UF C91 0.22UF C78 0.22UF C92 0.01UF C79 0.01UF C80 10UF C93 22UF

1V2_DIG GND VDD1P2 C81 22UF GND 1V8_SW4 SH6 DNP VDD_DCDCI C84 0.1UF GND DNP TP11 C97 68uFDNP C82 0.1UF

AD6

VDD1P2

H14 H15 H16 H17 J17 K14 K15 K17 L15 P17 VDDA R17

1V2_SW3 C83 0.1UF C94 0.1UF GND SH9 0

Y6

VDD_DCDCI

VDDAL_1 VDDAL_2 Y5 W5
GND

P15 VDDA_L C95 R15

0.1UF

C96 0.1UF GND

SH10 0

2 2.2UH C98 DNP 0.1UF

GND

L8 1 VDD_DCDCO

VDD_DCDCO
VDDO2P5 SH11 0 JP4 HDR 1X2 DNP 1V2_DDR C101 0.22UF GND C102 0.22UF C103 0.22UF C104 0.22UF C105 0.22UF C106 0.22UF C107 0.22UF C108 0.22UF C109 0.01UF C110 0.01UF C111 10UF C112 10UF

GND_DCDC VDDO25

N23
C99 0.1UF GND

3V_VGEN2 SH12 DNP

NVCC_KEYPAD

C100 0.1UF GND 3V_VGEN2 SH14 DNP NVCC_MISC C113 0.1UF GND NVCC_UART C117 0.1UF GND 3V_VGEN2 SH17 DNP

P8

NVCC_MISC

DCDC_3V15 SH15 DNP

T8

NVCC_EMI_DRAM_1 NVCC_EMI_DRAM_2 NVCC_EMI_DRAM_3 NVCC_EMI_DRAM_4 NVCC_EMI_DRAM_5 NVCC_EMI_DRAM_6 NVCC_EMI_DRAM7 NVCC_EMI_DRAM8 NVCC_EMI_DRAM9 NVCC_EMI_DRAM10 NVCC_EMI_DRAM11 NVCC_EMI_DRAM12 NVCC_EMI_DRAM13 NVCC_EMI_DRAM14 NVCC_EMI_DRAM15 NVCC_EMI_DRAM16 NVCC_EIM1 NVCC_EIM2 NVCC_EIM3

NVCC_EIM 3V_VGEN2 C114 0.1UF GND C115 0.1UF C116 0.1UF C118 0.01UF C119 0.01UF C120 10UF NVCC_EPDC C122 0.1UF C123 0.1UF C124 0.1UF C125 0.01UF C126 10UF SH18 DNP SH16 DNP

NVCC_UART

L7 M7 M8

NVCC_SSI C127 0.1UF GND

R8

DCDC_3V15

NVCC_SSI NVCC_EPDC1 NVCC_EPDC2 NVCC_EPDC3 NVCC_EPDC4 NVCC_EPDC5 NVCC_LCD USB_OTG_VDDA33 USB_H1_VDDA33

M10 N10 P10 R10 U10

C121 0.1UF GND

DCDC_3V15 SH19 DNP

NVCC_LCD U11 C128 0.1UF GND

3V3_USB

AD11 AC11
C129

SH20 DNP C130 0.1UF 2V5_VUSB2 SH22 DNP C133 0.1UF C134 0.1UF 1V2_RTC SH24 DNP C136 0.1UF GND 3V_VGEN2 R56 DNP C138 0.1UF SH26 DNP GND GND 1V8_ANA_PLL 3V_VGEN2 0 1V8_SW4 C143 22UF C144 0.01UF

3V_VGEN2 SH21 DNP

0.1UF NVCC_NANDF C131 0.1UF GND C132 0.1UF

V10 V9

NVCC_NANDF2 NVCC_NANDF1 USB_OTG_VDDA25_1 USB_H1_VDDA25_1 AC9 AD9

GND

3V15_VSD SH23 DNP

NVCC_SD2 C135 0.1UF

U8

NVCC_SD2 NVCC_SRTC
GND AA1 NVCC_SRTC

3V_VGEN2 SH25 DNP

GND NVCC_SD1 C137 0.1UF

T7

NVCC_SD1

NVCC_JTAG
GND 3V_VGEN2 SH27 DNP NVCC_SPI C145 0.1UF

U9

NVCC_JTAG

R7

NVCC_SPI

NVCC_RESET
GND

V8

NVCC_RESET

NGND_SRTC

SH28 DNP C146 0.1UF

GND_KEL GND1P2

GND3P0 GND1P8 GND2P5

A1 A18 A24 B18 G20 G21 G23 H12 H13 K12 K13 L12 L13 L14 L17 M11 M14 M15 M17 M18 M20 M21 N11 N14 N15 N17 P11 P12 P13 P14 R11 R12 R13 R14 T17 T18 U12 U13 U14 U15 U16 U17 U18 V17 V18 V20 V21 V23 AA9 AA11 AC18 AD1 AD18 AD24

AA7 AC6

AC3 AC7 AC4

AA2

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54

GND

GND

ICAP Classification: Drawing Title:

FCP: ___

1 2

NVCC_KEYPAD

N8

A21 B21 D21 D23 D24 K21 K23 K24 R21 R23 R24 AA21 AA23 AA24 AC21 AD21

1 2

SH5 0

1 2

AD3

i.MX50 - POWER

G8 G9 G10 H8 H9 H10 H11 J8 K7 K8 K10 K11 L8 L10 L11

SH7 0

SH13 0

FIUO: X

Figure 6. i.MX50 Voltage Domains

i MX50 Reference Des

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

15

i.MX50 Power Management Design with MC13892

VCC_BP R1 C1 C2 0.02 CHRGISNS 5V_APL

C1 C2

C2 C1

B1 B2 A2

A2 B2 B1

10UF 2.2uF VCC_BP

Q1 FDZ193P

Q2 FDZ193P

5V Selection
5V_APL SH88 0 5V_MAIN USB_5V R313 0

1.2V LPDDR2
1V8_SW4 SH85 0

A1

B1 B2 A2
SH83 0 DNP

Q3 FDZ193P

GND

C1 C2

A1

BATTFET

CHRGCTRL CHRGCTRL1 5V_APL

A1

DNP

PCB MOD: Cut Trace

5V_APL R3 DNP 10K

BATTISNS D1 LI-ION_BATTERY R4 0.02

1
LED_ORANGE GND

C6 0.1UF R6 0 DNP

DNP

SH30

CHGR_DET_B_TO_PMIC

VCC_BP C7 10UF

C13

D10

D12

C12

A10

B10

A12 A13 B13

B11

A11

E9 D8 E8

A7 D5 F5 B6 A6

U2 GND GPO1 R8 GND 4,5 BATT_NTC R320 DNP 4,5 0 TP3 BATT_NTC 10K R9 10K GND

GND

B7 E4 B5 E5

R7 47K DNP

C8

C9 GND

C10 GND MC13892 4.7uF

C11 4.7uF

C12 4.7uF

C13 GND 4.7uF

10UF 10UF

CHRGCTRL2_1 CHRGCTRL2_2 CHRGCTRL2_3

CHRGCTRL1

CHRGRAW

CHRGLED CHRGSE1B GNDCHRG

NC LEDMD LEDAD LEDKP GNDSWLED

BATTISNS

CHRGISNS

BATTFET

LEDR LEDG LEDB GNDLED

BP

BPSNS

BATT

PUMS2 PWGTDRV1 PWGTDRV2 SW1IN SW1OUT SW1FB GNDSW1 SW2IN SW2OUT SW2FB GNDSW2 SW3IN SW3OUT SW3FB GNDSW3 SW4IN SW4OUT SW4FB GNDSW4

E7 K4 M7

GND

GND

GND

GND

Put 4.7UF capacitors at pins G13, H13, H1 and J1. (PUS_4) +/- 1%
SW1 C17 10UF GND 1V2_SW2 1V_SW1

Battery Interface & Protection

J6 K9 GND K10 M11 J9 J12 M12 L12 M13 N12 N13

C20 2.2UF GND Note: use 10uF for Coulomb Counting of a battery. DNP if not required. BATTISNS C22 10UF K8 3V_VGEN2 4,8 CSPI_SS0 1,15 CSPI_SCLK 1,15 CSPI_MOSI 1,15 CSPI_MISO 2.775V R15 4.7K 1.5V 1.2V

Charger Interface and Control

Backlight LED Drive

Tri-Color LED Drive

GNDADC ADIN5 ADIN6 ADIN7 TSX1 TSX2 TSY1 TSY2 TSREF_1 TSREF_2 TSREF_3 ADTRIG BATTISNSCC CFP CFM SPIVCC CS CLK MOSI MISO GNDSPI VCORE VCOREDIG Reference Generation REFCORE GNDCORE

SW1 1050mA Buck SW2 800mA Buck Touch Screen interface SW3 800mA Buck

Touch Screen Connector

4,15 TOUCH_X0 4,15 TOUCH_X1 4,15 TOUCH_Y0 4,15 TOUCH_Y1

Sensitive analog lines. X1-X2 and Y1-Y2 make differential pairs.

E11 B12 K7

SW4 800mA Buck

VCC_BP 1.5UH G13 1 2 F13 L2 H10 R10 0 E13 VCC_BP H13 1 2 J13 L3 2.2UH C18 10UF J10 R11 0 GND K13 VCC_BP H1 1 2 G1 L4 2.2UH C19 10UF F4 F1 VCC_BP GND J1 1 2 K1 L5 2.2UH G4 L1 VCC_BP L6 1 D2 2 3.3uH

(PUS_0)
SW2

(PUS_5)
1V2_SW3 SW3 1V8_SW4 SW4 C21 10UF GND SWBST VCC_BP

(PUS_1)

VCC_BP

2 2.2uH is for optional 1

C23 10uF

TO-2.0A
SWBST 350mA Boost SPI/I2C interface VVIDEO 350mA

R14 C25 C27 C28 GND

100K DNP 2.2UF VCORE GND 2.2UF VCOREDIG 0.1UF REFCORE

K2 L2 M2 J2 H2 H4 A9 B9 D7 B8
GND

SWBSTIN SWBSTOUT SWBSTFB GNDSWBST VVIDEODRV VVIDEO VINUSB2 VUSB2_1 VUSB2_2 VUSB2_3 VINAUDIO VAUDIO

A4 B4 D4 A5 K12 L13 A3 A1 A2 B1

MBR120LSFT1G GND VVIDEODRV VCC_BP C24 C26 VCC_BP 2.2UF GND 2.2UF GND 3V_VAUDIO

3
Q6

4
NSS12100XV6T1G 2V775_VVIDEO

1 2 5 6

(PUS_9)

2V5_VUSB2

VUSB2 50mA

N7 N8
VCC_BP C31 C32 VCC_BP 2.2UF

UNUSED
2V775_VIOIH

NOTE: (PUS_X) means the Power Up Sequence index number during turn on.

GND

VAUDIO 150mA VVIOHI 100mA

VINIOHI VIOHI VINPLL VPLL VINDIG VDIG VCAMDRV VCAM

N10 N9
2.2UF GND

(PUS_2)
1V8_ANA_PLL GND (PUS_6) VCC_BP C33 C34 2.2UF 1V2_DIG

UNUSED

C1 E2 M9 M8

5V_APL TP4 SWBST R18 DNP R19 3V3_USB R17 0 TP5 0 0

E6 E1 F2 G2 D1

UID UVBUS VBUSEN VINUSB VUSB

VUSB 100mA

(PUS_7)
2.2UF GND GND C35 2.2UF GND

VDIG 50mA

VPLL 50mA

VCC_BP Q7 NSS12100XV6T1G DNP

UNUSED
VCC_BP 3V_VCAM Q8 NSS12100XV6T1G 3 VCC_BP

VCAM 250mA

C37

2.2UF GND

VSDDRV VSD
VSD 250mA

1 2 5 6

C36

2.2UF GND

(PUS_9)

C2 D2 M10 N11 N4 M3 N3 M1 N1 N2

VSDDRV

M6 K6

1 2 5 6

VCAMDRV

3V15_VSD

Q9 NSS12100XV6T1G DNP VCC_BP

UNUSED
3V_VGEN1 Q10 NSS12100XV6 3

D9
C39 0.1UF GND

LICELL

VGEN1 200mA

VGEN1DRV VGEN1 VGEN2DRV VGEN2

1 2 5 6

C38 VGEN2DRV

2.2UF GND

VGEN1DRV

(PUS_3)
C40 VGEN3DRV VCC_BP Q11 NSS12100UW3 DNP 2.2UF GND

BT1 2994TR

VGEN2 350mA

2 1

Coin cell.
RESETB STANDBYSEC STANDBY INT WDI RESETBMCU CLK32K CLK32KMCU VSRTC
VGEN3 50mA

VINGEN3DRV VGEN3_1 VGEN3_2 VGEN3_3 DVS2 DVS1 GNDREG3 GNDREG2 GNDREG1

XTAL2 GNDRTC GNDCTRL MODE PUMS1 PWRON1 PWRON2 PWRON3

GNDSUB1 GNDSUB2 GNDSUB3 GNDSUB4 GNDSUB5 GNDSUB6 GNDSUB7 GNDSUB8 GNDSUB9

XTAL1

GND

GPO1 GPO2 GPO3 GPO4

C41 2.2UF GND

1 3

UNUSED
1V8_VGEN3

N5 M5 H9 A8 G9 D13 E10 J8

F12 H12

K5 J4 M4

B2 F10 F9 G12

R21

0 R20

10M Y1 1 GND TP59 TP8 R22 0 GPO1 15pF GND ECKIL 0 0 R27 R25 4.7K 0 0 0 0 PWRON2 4,9 C46 1uF GND WDOG_B 4,8 PWR_INT(GP4_18) 4,8 PWRON3 4,15 PWRON1 1V2_RTC U5 VCC GND 1V2_RTC APL_GPIO2 5

1V2_RTC

DNP 1V8_SW4 C42 0.1UF C43 0.1UF GND (active high)

GND C44

32.768KHz

C45

15pF

GND

VCCA

VCCB

J5 E12 G10 F11

VCOREDIG R23 DNP R24 GND VCORE R28 DNP

RESET_IN_B 4,9,15 POR_B 4,9 3V_VGEN2

B3 D6 H5 G5 J7

F6 F7 F8 G6 G7 G8 H6 H7 H8

N6

4,9 PMIC_STBY_REQ

A GND

B NC

4 5

R26

1 2

PMIC_ON_REQ

4,9

VCOREDIG R29 R30 DNP GND

U6 NLSV1T34

Open-drain 4,9

required

GND NC7SP125P5X

GND GND

Figure 7. MC13892 Schematic

16

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

1 2 5 6

3V_VG

+ -

i.MX50 Power Management Design with MC13892

VSOURCE SH1 0 C47 100UF + C48 100UF + C49 100UF + C50 4.7uF C51 VDDI 0.1UF R31 9.31K GND U7

18

19

20

22

23 VIN2 BOOT VOUT 21 11 15 16 17 9

C55 R38 20PF C56 C53 0.1UF

Vout = 0.7 * [ R(sw-inv) / R(inv-gnd) + 1 ] Vout = 3.14V for R39=17.4K, R44=4.99K

5 8 7

PVIN1 PVIN2 PVIN3 VIN1 NC1 NC2 VREFIN

DDR2/DDR3 Power
DCDC_3V15

Note: Freq=1Mhz, Tsoftstart=3.2ms

C54 R33 10.0K 0.1UF

R34 R37 0

5.1K

3 2

0.7V

ILIM FREQ

SW1 SW2 SW3 COMP INV

L7 1.0UH

2
R35 4.12K 15K R39 17.4K 560PF C57 470pF C58 100UF R44 4.99K +

SH2 0

GND 3V_VGEN2 SH71 DNP

VDDI R41 10K 24 R42 DNP 4.99K 6

10 4

VDDI PG SD PGND1 PGND2 PGND3GND1 GND2

C59 100UF

+ C60 100UF

C61 0.1UF

12

13

14

25 MC34713EP

GND

Figure 8. 3.15V Buck Regulator

SH84 1V8_SW4 SH85 0 SH86 DNP U1 LTC3409EDD

DNP

3 7 4 2
C3 10uF

VIN1 RUN VIN2 GND

MODE SW VFB SYNC

5
1V2_DDR

6 1 8

L1 1

2.2UH

2
R2 127.0K C4 20PF

E_PAD

C5 10uF

SH87 DNP

R5 133.0K

GND

Vout = 0.613 * [ R(Vout-Vfb) / R(Vfb-Gnd) + 1 ] Vout = 1.2V for R(Vout-Vfb) = 127K & R(Vfb-Gnd)=133K

Figure 9. 1.2V Buck Regulator

VDDO2P5 LDO
VSOURCE U3 VDDO2P5

1
C16 2.2uF C15 100 PF

VIN BYP ON/OFF GND

LP2992

VOUT

5
C14 4.7uF GND

4 3 2

GND Q4 IRLML6401 VSOURCE 2 R307 100K

3
R306 100K

GND R13 10K

1 2
GND

3
Q5 MMBT3904

1V2_SW2

VDD2P5 LDO
3V_VGEN2 U4 VDD2P5

1
10K R16

VIN BYP ON/OFF GND

LP2992

VOUT

5
C29 22UF GND

4
C30 100 PF

3 2

GND

Figure 10. 2.5V LDO Regulators

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

17

i.MX50 Power Management Design with MC13892

U12C PCIMX508DJV1A

i.MX50 - CONTROL PINS

NVCC_RESET

1V8_SW4

BOOT_MODE0 BOOT_MODE1 R73 10K GND 4,6 PMIC_STBY_REQ 4,6 PMIC_ON_REQ

AB1 AB2 AC2 W2 W1 Y1 Y2

BOOT_MODE0 BOOT_MODE1 TEST_MODE PMIC_STBY_REQ PMIC_ON_REQ CKIL ECKIL

NVCC_JTAG

4,6,15 RESET_IN_B 4,6 POR_B

AC1 AD2

RESET_IN_B POR_B

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRSTB JTAG_MOD CKIH

W4 Y4 AA4 U7 AA5 V7 AA6

SH33

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST_B DNP

R85 10K DNP JTAG_MOD R86 1K

NVCC_RTC

QZ1 1 C148 18PF DNP

EXTAL XTAL

AC5 AD5
GND R74 1.0M Y3 1V8_ANA_PLL

2
C149 18PF DNP SH31 SH0603 DNP

32.768KHZ DNP

Y2 GND

OSC.
3 2
GND

VCC EN/DIS DGND

4 1 2
10K R76 C154 0.1UF

4 1
C152 15PF

GND

3
C153 15PF

OUT

GND

24MHZ

22.5792MHZ DNP GND

4,6

ECKIL

GND

Figure 11. i.MX50 Control Signals

4.5

MC13892 PCB Layout Example

The following example shows the PMIC layout section for a reference design of the i.MX50 using the MC13892 power management. It is design in 10 layers with 4 inner planes (GND and PWR) form layer 4 to layer 7. For simplicity, only top, bottom and Inner signal layers are shown in figures x to y.

10 R319

D2 1 L6 U2

2 C7 R1 1 1 C A L2 1 1 Y1 C38 C31 R21 L3 C2 10 1 C1 J20 TP23 TP21 5 C30 4 1 JP5

R315

C48 TP4 TP5 C47 L4 L5 C49 1 4 C21 JP3 SH13 R93 R92 JP4 TP SH
18

1 R66 1 S

1 Y3 S

TP15

L9

Figure 12. Top Fabrication Drawing

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

C37 R316

1 1 1 C40 R20 1 C41

TP8

C22 TP3 C154

R16 1U6 U4 TP59 TP17 TP20 SH31

SH79 C233 TP18

R76 C44 C45 R67 R62 S

C 1

i.MX50 Power Management Design with MC13892

02
1HS

01

2 91C 8Q

04

2 03 1 02 01 38HS 1 03R 64C

5U

1 02J 1TB

921C 031C 431C 331C 1C 831C 6 H S 01C 8C 48C 9 841C

023R

6Q

2HS

611C 411C 911C 1C 811C

4PJ1

02HS 57C 7HS 62HS 36R 8HS 4HS 53C 43C 7R 23C

421C 121C

01Q 11Q 1

3PJ

7Q

19Q

51PT

Figure 13. Bottom Fabrication Drawing

2 10 1 1 1 1 1 1 4 1 1 1 C A 1 5 4 10 1

02C

92C

81R 91R 51R

1 93C 71R 01R 11R 1 21C 1

6C

72R 2 82R 52R 92R 62R 71C 34C 81C 22R 24C 5PJ 1 5 1 51 71

1 + 1
19

1 1

1
Figure 14. Top Layer

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with MC13892

Figure 15. Inner Layer 2 (Signal)

Figure 16. Inner Layer 3 (Signal)

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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with MC13892

Figure 17. Inner Layer 8 (Signal)

Figure 18. Inner Layer 9 (Signal)

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

21

i.MX50 Power Management Design with MC13892

02

01

04

2 03 1 02 01 1 1

1 1 1 1 1 1
Figure 19. Bottom Layer

1 2

1 1

1 51 71

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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with the MC34709

i.MX50 Power Management Design with the MC34709

Ten-bit ADC for monitoring. Four-wire resistive touchscreen interface Five buck converters for direct supply of the processor core and memory One boost converter for USB OTG support Eight LDO Regulators with internal and external pass devices for thermal budget optimization Power control logic with processor interface and event detection Real time clock and crystal oscillator circuitry with coin cell backup Support for external secure real time clock on a companion system processor IC Single SPI/I2C bus for control & register access Four general purpose low voltage I/Os with interrupt capability Two PWM outputs

The MC34709 is a power management IC that includes the necessary sources to supply the i.MX50. Its main features are:

5.1
Supply
SW1 SW2 SW3 SW4A SW4B SW5 SWBST VSRTC VPLL

MC34709 Voltage supplies

Table 6. MC34709 Voltage Supplies Summary Typical Application
Buck regulator for processor VDDGP domain Buck regulator for processor VCC domain Buck regulator for processor VDD domain and peripherals Buck regulator for DDR memory and peripherals Buck regulator for DDR memory and peripherals Buck regulator for I/O domain Boost regulator for USB OTG Secure Real Time Clock supply Quiet Analog supply DDR Ref supply TV DAC supply, external PNP VUSB/peripherals supply, internal PMOS VUSB/peripherals external PNP

Output Voltage (in V)

0.650 - 1.4375 0.650 - 1.4375 0.650 - 1.425 1.200 1.975: 2.5/3.15/3.3 1.200 1.975: 2.5/3.15/3.3 1.200 1.975 5.00/5.05/5.10/5.15 1.2 1.2/1.25/1.5/1.8 0.6-0.9V 2.5/2.6/2.7/2.775 2.5/2.6/2.75/3.0 2.5/2.6/2.75/3.0 1.2/1.25/1.3/1.35/ 1.4/1.45/1.5/1.55 2.5/2.7/2.8/2.9/3.0/ 3.1/3.15/3.3 2.5/2.7/2.8/2.9/3.0/ 3.1/3.15/3.3 3.3

Load Capability (in mA)

2000 1000 500 500 500 1000 380 0.05 50 10 250 65 350 250 50 250 100

VREFDDR VDAC VUSB2

VGEN1 VGEN2

General peripherals supply #1 General peripherals supply #2, internal PMOS General peripherals supply #2, external PNP

VUSB

USB Transceiver supply

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

23

i.MX50 Power Management Design with the MC34709

5.2

MC34709 Power-up Sequence

The MC34709 has 5 PUMS signals that enable to program the power up sequence as well as the default output voltage for specific rails, making the part suitable to supply DDR2, DDR3, LPDDR2, LVDDR3 memories with the correct power up sequence for many processors of the i.MX family. The following table shows the power up sequence and all possible voltage combinations to supply the i.MX50 in all possible modes. Table 7. Power-up Defaults i.MX50 PUMS[4:1]
PUMS5=0 VUSB2/VGEN2 PUMS5=1 VUSB2/VGEN2 SW1A (VDDGP) SW1B (VDDGP) SW2(8) (VCC) SW3(8) (VDDA) SW4A(8) (DDR/SYS) SW4B(8) (DDR/SYS) SW5(8) (I/O) VUSB(9) VUSB2 VSRTC VPLL VREFDDR VDAC VGEN1 VGEN2

mDDR 1010
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 1.8 1.8 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1

LPDDR2 1011
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 1.2 1.2 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1

LPDDR2 1100
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.2 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1

mDDR 1101
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.8 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 3.1

LPDDR2 1110
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.2 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 2.5

mDDR 1111
Ext PNP Internal PMOS 1.1 1.1 1.2 1.2 3.15 1.8 1.8 3.3 2.5 1.2 1.8 On 2.5 1.2 2.5

Not used on System SWBST Off Off Off Off Off Off

Notes 8. The SWx node are activated in APS mode when enabled by the start-up sequencer. 9. VUSB is supplied by SWBST.

24

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with the MC34709

Table 8. Power-up Sequence i.MX50 Tap x 2.0 ms

0 1 2 3 4 5 6 7 8 9

PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111]

SW2 SW3 SW1A/B VDAC SW4A/B, VREFDDR SW5 VGEN2, VUSB2 VPLL VGEN1 VUSB

VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer start-up. See Figure 2
Turn On Event Sequencer time slots System Core Active Turn On Verification Power Up Sequencer UV Masking RESETB INT WDI 8 ms 1 - Off 8 ms 20 ms 2 - Cold Start 12 ms 128 ms 3 - Watchdog 4 - On 3- Watchdog 1 - Off ow WDI Pulled Low

Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high Turn on Event is based on PWRON being pulled low = Indeterminate State

... or transition to Off state if WDI remains low

Figure 20. Complete MC34709 Power-up Sequence

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

25

i.MX50 Power Management Design with the MC34709

Power on event

SW2 SW3 SW1A/B VDAC SW4A/B VREFDDR

SW5

VGEN2 VUSB2 VPLL VGEN1 VUSB

2ms 2ms 2ms 2ms 2ms

2ms 2ms

2ms

2ms

Figure 21. MC3709 Power up Sequence for i.MX50 processors.

26

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with the MC34709

5.3

Interfacing the i.MX50 with the MC34709

Table 9, shows all the i.MX voltage rails, their power requirements and their associated MC34709 regulator. Most of the supply domains have flexible voltage and could be adjusted or supplied with a different regulator depending on each application needs Table 9. i.MX50 voltage domain supplies with the MC34709 I.MX50 Power Rail of i.MX50
NVCCSRTC VCC VDDA

MC34709 MIN TYP

1.2 1.2 1.2

Power Domain
32 kHz osc. power (when chip off) LP Transistor power Peripheral Memory + L2 Cache power L1 Cache power Core and G Transistor power Predriver for EMI pads Power to EMI pins DRAM Reference 3.0 V I/Os VDD2P5 LDO input + power to Bandgap, DCDC predriver, tempsensor, 480 MHz PLL Power to USB Host Power to USB OTG 1.8 V I/Os

MAX

Associated PUM[4:0] Curren PUS Regulator =1110 t (mA)

VSRTC SW2 SW3 1.2 1.2 1.2 1000 500 0 1

VDDAL1 VDDGP VDDO2P5 NVCC_EMI_DRAM VREF ALL 3.3V IO NVCC VDD3P0

1.2 1 2.5 1.2 0.9 3

SW3 SW1A/B VDAC SW4B

1.2 1 2.5 1.2

500 1600 50 500

1 2 3 4

SW4A

3.15

500

USB_OTG_VDDA33 USB_H1_VDDA33 All 1.8 IO NVCC

3.3 3.3 1.875 or 2.775

VUSB VUSB

3.3 3.3

100 100

9 9

NVCC_RESET (LVIO) Power to POR_B,RESET_I N_B, TESTMODE, & BOOTMODE[0:1]

SW5

1.8

1000

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27

i.MX50 Power Management Design with the MC34709

Table 9. i.MX50 voltage domain supplies with the MC34709 I.MX50 Power Rail of i.MX50
VDD2P5

MC34709 MIN TYP

2.5

Power Domain
Power to 24 MHz osc, efuse, xtalok, 32 kHz osc. power mux Power to USB Host Power to USB OTG Power to all PLLs Power to all PLL digital, 32 kHz osc. (when chip on), much of analog, digital

MAX

Associated PUM[4:0] Curren PUS Regulator =1110 t (mA)

VGEN2 2.5 250 6

USB_OTG_VDDA25 USB_H1VDDA25 VDD1P8 VDD1P2

2.5 2.5 1.8 1.2

VGEN2 VGEN2 VPLL VGEN1

2.5 2.5 1.8 1.2

250 250 50 250

6 6 7 8

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i.MX50 Power Management Design with the MC34709

5.3.1

Interfacing Block Diagram

The following block diagrams show all the power connections needed for the interface, as well as how the communication signals must be connected between the i.MX50 and MC34709.

MC34709 SW1A/B SW2 SW4 5.0V VUSB 4.2V regulator VDDGP VCC NVCC_EIM_DRAM USB_VDDA33 i.MX50

VIN SW5

POP_LPDDR2_18V NVCC_RESET NVCC_JTAG VDD1P8 NVCC_KEYPAD (OPT) VDDA VDDAL1 VDD2P5

VPLL VGEN2

VSW3

VUSB2

VDAC

VDDO25 VDD3P0 NVCC_MISC NVCC_SPI NVCC_SD1 NVCC_SD2 POP_NAND_VCC NVCC_NANDF NVCC_KEYPAD NVCC_SSI NVCC_UART NVCC_LCD NVCC_EPDC

VSW4A

VGEN1

VDD1P2

External DC/DC regulator

Peripherals 3.15 V CODEC HDMI ETHERNET 3G PCIe RS-232

Figure 22. i.MX50 Power Interface with MC34709 Block Diagram

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

29

i.MX50 Power Management Design with the MC34709

MC34709
RESETBMCU RESETB STANDBY POWERON1

SWx

i.MX50
POR_B RESET_IN_B PMIC_STBY_REQ PMIC_ON_REQ

SWx

WDI INT
SWx

WDOG GPIOX_X

UID CKL MISO/SDA

USB_OTG_ID CSPI_SCLK CSPI_MISO/MOSI

CLK32MCU PUMS1 PUMS2 PUMS3 PUMS4 PUMS5 VDC

CLK

Figure 23. i.MX50 Control Interface with MC34709 Block Diagram

5.3.1.1

3.15 V DC-DC power supply

For system stability, it is recommended that you use an extra 3.15 V DCDC power supply to support large current requirements (for example a 3G module or Wi-fi card). The MC34709 has limited 3.15 V output ability to supply al peripherals, however, in cases where Ethernet, 3G, or Wi-fi are not required, this buck converter may be eliminated from the power three.

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i.MX50 Power Management Design with the MC34709

5.3.2

Interface Power-up Sequence

The resulting power-up sequence of the interface is shown in the following figure

VCC

SW2

VDDA VDDA1 VDDGP

SW3

SW1A/B

VDDO2P5 VDAC

VDD3P0 NVCC_MISC NVCC_SPI NVCC_SD1 NVCC_SD2 POP_NAND_VCC NVCC_NANDP NVCC_KEYPAD NVCC_SSI NVCC_UART NVCC_LCD NVCC_EPDC POP_LPDDR2_18V NVCC_RESET NVCC_JTAG SW4A SW4B VREFDDR

Peripherals CODEC HDMI ETHERNET 3G PCIe RS-232

3.15V DC-DC regulator SW5

VDD2P5 USB_VDDA25

VGEN2 VUSB2

VDD1P8

VPLL

VDD1P2 HDMI (perpheral)

VGEN1

USB_VDDA33

VUSB

Figure 24. Power up Sequence Flow Chart

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

31

i.MX50 Power Management Design with the MC34709

5.4

Application Example with the MC34709

The following schematic is simplified application example for interfacing the MC34709 with an i.MX50 processor. note that this schematic only includes the block related to the power section as well as power management controlling signals.
U6E 5_VGEN2 DCDC_3V15 3V15_SW4A_CPU 1V_SW1 C63 0 DNP 0 VUSB2_2V5 2V5_VGEN2 0 R479 R92 C68 0 DNP 0.1UF 1V8_VPLL 0 R93 C84 0.1UF 1V2_VGEN1 0 R95 C90 22UF GND 1V8_SW5 0 R463 C76 0.1UF GND L10 1 VDD_DCDCO L17 VDDO2P5 C94 0.1UF GND GND GND 2V5_VGEN2 3V15_SW4A_CPU R465 R466 0 0 DNP C97 0.1UF GND 3V15_SW4A_CPU J5 C110 0.1UF GND L5 C114 0.1UF GND 3V15_SW4A_CPU K5 C124 0.1UF GND 3V15_SW4A R368 3V15_SW4A_CPU 0.001 C126 0.1UF GND 3V15_SW4A_CPU SH12 DNP C130 0.1UF GND 3V15_SW4A_CPU P5 C134 0.1UF 3V15_SW4A_CPU GND N5 C136 0.1UF NVCC_JTAG GND 3V15_SW4A_CPU M5 C138 0.1UF NVCC_RESET GND P6 NVCC_RESET C139 0.1UF GND_KEL GND NC1 NC2 NC3 NC4 NVCC_SPI GND 1V8_SW5 R460 R461 0 0 DNP 3V15_SW4A_CPU P9 NVCC_JTAG C137 0.1UF NVCC_SD1 GND R101 R459 0 0 DNP 1V8_SW5 3V15_SW4A_CPU NVCC_SD2 NVCC_SRTC R5 GND NVCC_SRTC C135 0.1UF 1V2_RTC SH14 DNP C131 0.1UF 0.1UF P11 P12 NVCC_NANDF2 NVCC_NANDF1 USB_OTG_VDDA25_1 USB_H1_VDDA25_1 W9 Y9 C132 0.1UF GND USB_2V5 C133 0.1UF R100 0 0.1UF VUSB2_2V5 P10 NVCC_LCD USB_OTG_VDDA33 USB_H1_VDDA33 Y11 W11 C128 USB_3V3 C129 R98 R99 0 0 DNP GND GND 3V3_USB 3V15_SW4A_CPU C125 22UF C127 0.01UF NVCC_SSI NVCC_EPDC1 NVCC_EPDC2 NVCC_EPDC3 NVCC_EPDC4 F9 F10 F11 F12 GND C118 0.1UF C119 0.1UF C120 0.1UF C121 0.1UF C122 0.01UF NVCC_EPDC C123 10UF SH10 DNP 3V15_SW4A_CPU 3V15_SW4A_CPU NVCC_UART NVCC_EIM1 NVCC_EIM2 NVCC_EIM3 NVCC_MISC H5 K14 N14 J15 K15 L15 N15 P15 H16 J16 K16 L16 M16 N16 P16 R16 F6 F7 F8 NVCC_EMI_DRAM C98 C99 C100 0.22UF GND 0.22UF 0.22UF JP4 HDR 1X2 DNP 1V2_SW4 NVCC_KEYPAD NVCC_EMI_DRAM_1 NVCC_EMI_DRAM_2 NVCC_EMI_DRAM_3 NVCC_EMI_DRAM_4 NVCC_EMI_DRAM_5 NVCC_EMI_DRAM_6 NVCC_EMI_DRAM7 NVCC_EMI_DRAM8 NVCC_EMI_DRAM9 NVCC_EMI_DRAM10 NVCC_EMI_DRAM11 NVCC_EMI_DRAM12 NVCC_EMI_DRAM13 NVCC_EMI_DRAM14 NVCC_EMI_DRAM15 C101 0.22UF C102 0.22UF C103 0.22UF C104 0.22UF C105 0.22UF C106 0.01UF C107 0.01UF C108 10UF C109 10UF 1 2 R97 0.001 FIUO: X VDD_DCDCI R7 VDD_DCDCI C91 0.1UF C69 22UF GND VDD1P2 U6 VDD1P2 GND VDD1P8 V6 VDD1P8 R462 0.1UF R499 GND VDD2P5 V5 VDD2P5 VDD3P0 VDDGP_1 VDDGP_2 VDDGP_3 VDDGP_4 VDDGP_5 VDDGP_6 VDDGP_7 VDDGP_8 VDDGP_9 VDDGP_10 VDDGP_11 VDDGP_12 VDDGP_13 VDDGP_14 VDDGP_15 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VDDA_1 VDDA_2 VDDAL_1 VDDAL_2 C64 0.22UF GND C65 0.22UF C66 0.22UF C77 0.22UF C78 0.22UF C79 0.22UF C80 0.22UF C67 0.01UF C81 0.01UF C82 10UF C83 22UF R91 1 2 0.001 1V2_SW2 K10 L10 M10 K11 L11 M11 J12 K12 L12 K9 J11 J9 J10 C70 0.22UF GND C85 0.22UF C71 0.22UF C86 0.22UF C87 0.22UF C88 0.01UF C72 0.01UF JP3 HDR 1X2 DNP C73 10UF C89 22UF R94 1 2 VCC 0.001 FCP: ___ DNP 0 R412 VDD3P0 U5 G6 H6 J6 K6 L6 G7 H7 J7 K7 G8 H8 G9 H9 G10 H10 VDDGP JP2 HDR 1X2 DNP

i.MX50 - POWER

JP1 HDR 1X2 DNP

1V2_SW3

C74 0.1UF

C92 0.1UF GND

C93 0.1UF

C75 0.1UF

R96

1 2

VDDA

0.001

Not used (tied off to 1.8V)

2V5_VDAC DNP 2 C95 68uFDNP C96 DNP 0.1UF 2.2UH R6 VDDO25 T6 VDD_DCDCO GND_DCDC R370 0

3V15_SW4A_CPU

NVCC_EIM 3V15_SW4A_CPU C111 0.1UF C112 0.1UF C113 0.1UF C115 0.01UF C116 0.01UF C117 10UF SH8 DNP

PLace close to MX50

T7

T5 W5 M6 N6 L7 M7 N7 P7 J8 K8 L8 M8 N8 P8 L9 M9 N9 N10 R10 G11 H11 N11 R11 G12 H12 M12 N12 R12 G13 H13 J13 K13 L13 M13 N13 P13 R13 G14 H14 J14 L14 M14 P14 R14 H15 M15 R15

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47

MCIMX508

A1 Y1 A20 Y20

GND

ICAP Classification: Drawing Title:

PU

i.MX50 Reference Desig

Figure 25. i.MX50 Voltage Domain Distribution

32

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i.MX50 Power Management Design with the MC34709

U3C VCC_BP VCC_BP C21 10UF SWBST C28 0.1UF

F15
L9 2.2UH

SWBSTIN

SW1IN1 SW1IN2

P11 P10

C15 4.7uF C22 0.1UF

2 1

G14
D6 MBR120LSFT1G

GND C46 22UF GND VCC_BP C20 4.7uF 1V8_SW5 GND 0.02 R367 BRL3225 2 L8 1 C252 0.01UF

SWBSTLX

SWBST 5.00, 5.05, 5.10, 5.15V 380mA Boost

SW1ALX

GND

1V_SW1 BRL3225

R9 1
L3

H15 1

SWBSTFB

P7
C27 0.1UF

SW5IN

SW1 0.650-1.4375V 2000mA Buck SW5 1.200-1.85V 1000mA Buck

2
C30 22UF C31

SW1BLX

R11

(PUS_3)
22UF

SW1FB SW1PWGD SW1CFG

P13 K10 L12

TP63 R35 R36 0 0 DNP GND GND VCOREDIG VCOREDIG for Parallel Single Phase Mode VCORE for Parallel Dual Phase Mode VCC_BP C16 4.7uF C23 0.1UF

R8
SW5LX

SW5LX

(PUS_6)

C45 22uF

M8
GND VCC_BP C19 4.7uF 1V2_SW4B 1V2_SW4B for EMI_DRAM_PAD GND C26 0.1UF

SW2IN1 SW5FB SW4BIN

B11

P5

R6

(PUS_5)

C39 22UF

BRL3225 2

L7 1

SW4BLX

SW4BLX

SW4B 1.200-1.85, 2.5, 3.15V 500mA Buck

SW2 0.650-1.4375V 1000mA Buck

SW2LX1

GND

1V2_SW2

A10

L4 SW2LX 1

BRL3225 2 C33

(PUS_1)

P2
GND VCC_BP C18 4.7uF 3V15_SW4A R369 0.02 C38 22UF VCOREDIG GND VCORE DNP 0 DNP 0 0 GND R56 R57 R58 GND C25 0.1UF

SW4BFB SW4AIN

SW2FB SW2PWGD SW3IN1

A12 A13 E14

C17 4.7uF C24 0.1UF TP64

22UF GND VCC_BP

P4

2
L6

1
BRL3225

SW4ALX

R3 N2 M6

SW4A 1.200-1.85, 2.5, 3.15V 500mA Buck

SW4ALX SW4AFB SW4CFG

SW3 0.650-1.4375V 500mA Buck

SW3LX1 SW3FB D15 B13
SW3LX

1V2_SW3 GND

(PUS_5)

1 L5

2 BRL3225

(PUS_2)
C35 10UF GND

MC34709
PC34709VK

VCORE for Parallel Dual Phase Mode VCOREDIG for Parallel Single Phase Mode GND for separate independent output mode

U3B VCC_BP 1V2_SW4B

J14
VREFDDR 0 R378 C49 1uF 0.1UF GND VCC_BP C48 C47 0.1UF

LDOVDD VINREFDDR

N15 R363

Support source for VUSB2,VDAC and VGEN2

K15

VREFDDR
VREFDDR

MC34709
VCC_BP

J15

0.6-0.9V 10mA LDO

VHALF

VUSB2 2.5, 2.6, 2.75, 3.0V

3
VUSB2DRV

Q8

(PUS_10)

VUSB2_2V5 0 R401

NSS12100XV6T1G

P14 R14

VUSB2DRV VUSB2

65mA INT. 350mA EXT. PNP VGEN1 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, 1.5, 1.55V 250mA INT VUSB LDO 3.3V

VPLL LDO 1.2, 1.25, 1.5, 1.8V 50mA LDO VDAC LDO 2.5, 2.6, 2.7, 2.775V 250mA

VINPLL

L15
C158 2.2UF

1V8_VPLL R366 0

1.8V for PLL Analog

(PUS_8)
VPLL K14
GND

C51 2.2UF GND

6 5 2 1
1V8_SW5 0 R373

VCC_BP

VDACDRV VDAC

N14 VDACDRV P15

3 1 2 5 6

H14

VINGEN1

Q9 NSS12100XV6T1G GND R364 C53 2.2UF

C50 2.2UF

2V5_VDAC 0

2.5V for VDDO2P5 (EMI PADS)

(PUS_9)

1.2V for PLL Digtal 1V2_VGEN1 0 R365

(PUS_4)

H12
C57 2.2UF

VGEN1

VGEN1 has an internal PMOS pass FET and is powered from the SW5 for an efficiency advantage and reduced power dissipation in the pass devices.

buck

3V3_USB

R65 R375

0 0 C52

D1 D2

VINUSB VUSB

VGEN2DRV VGEN2

L14 M15

VGEN2DRV

3 1 2 5 6
R362 C59 2.2UF GND 0

SWBST

GND

VGEN2 LDO 2.5, 2.7, 2.8, 2.9, 3.0, 3.1, 3.15, 3.3V, 50mA INT. 250mA EXT. PNP

VCC_BP GND Q10 NSS12100XV6T1G 2V5_VGEN2 Power for Keypad

(PUS_7)

(PUS_10)

100mA INT.

2.2UF GND

VCC_BP PC34709VK For VDAC (Q9) C55 0.1UF GND

VCC_BP For VGEN2(Q10) C58 0.1UF GND

Figure 26. MC34709 Power Supplies Schematic

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33

i.MX50 Power Management Design with the MC34709

3.15V/2A Regulator
VSOURCE R1 0 U30 L13 DCDC_3V15

5
J84 3V15_SW4A R8 C3 22UF R475 332K R474 13K GND C290 1000PF 0 DNP DCDC_3V15_EN R78 0

PVDD

LX

1
2.2uH

2
R2 294K

1 2

HDR 1X2

R1
VDD SHDN/RT COMP GND PGND PAD FB 7

6 1 8 2

4 9

R2

C2 22UF R3 100K

GND GND

GND

Vout = 3.15V for R1=294K, R2=100K Vout = 0.8v* (R(out-fb) / R(fb-gnd) + 1)

Figure 27. 3.15V DC-DC Regulator

Battery Regulator & Terminals

3-pin connector J2 allows the use of aftermarket Li-ION batteries. Recommended battery capacity is 800 - 1500 mAh.
BATT

J1

2 1
B2B-PH-K-S

J2

J3

Silkscreen Labels:

THERM CON_1X3
DNP

3 2 1
GND

3 2 1
HDR_1X3

+
VCC_BP C4 47uF

THERMISTOR
(pg6)

3 2 1
HDR_1X3 J4

BATT_NTC

GND

5V_MAIN SH1 DNP C7 10UF

U2

REG_4V2

2 1 3 6

IN EN

OUT

4 5
R4 42.2K C6 20PF C5 10UF R7 17.4K

NR/FB GND GND_TAB

R1

TPS78601

R2

GND

Vout = 1.2246 * [ R(out-fb) / R(fb-gnd) + 1 ] Vout = 4.19V for R1=42.2K, R2=17.4K

Figure 28. Main BP Supply (Battery or 4.2V)

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i.MX50 Power Management Design with the MC34709

U3A

VCC_BP TP1 DNP

ADIN9

H6 J5 J6

ADIN9 BP ADIN10 ADIN11

N1

R28 C14 10UF GND

General Purpose ADCs USB/Audio

NC_1 NC_2

R1 A14 B15

MBR120LSFT1G C LICELL A D15

U10 NCP4682

D14

3 4
BP

C32 GND

2.2UF

K6 K5 L4 L6 L3

TSREF TSX1/ADIN12 TSX2/ADIN13 TSY1/ADIN14 TSY2/ADIN15

NC_3

(pg17) (pg17) (pg17) (pg17)

TOUCH_X0 TOUCH_X1 TOUCH_Y0 TOUCH_Y1

Touch Screen Interface

A C C291 D16 0.1UF MBR120LSFT1G

VIN

GND TAB_GND

Sensitive analog lines. X1-X2 and Y1-Y2 make differential pairs.

CE

VOUT

VDDLP

MBR120LSFT1G C292 0.1UF

2 5

VSRTC WORKAROUND
3V15_SW4A

R46 0 C159 C161 0.1UF 1uF

PWM1 PWM2

A8 A7

PWM1

(pg10)

GPIOVDD
1.75V~3.6V SPI: Hold low when cold start I2C: Hold high when cold start. (pg9) (pg12,9) (pg12,9) (pg12,9) CSPI_SS0 CSPI_SCLK CSPI_MISO CSPI_MOSI GND

C8 C7 B7 B9 E10

R72 GPIOLV1

0 R77 0

1V8_SW5 DNP

1.8V logic level

A4
R49 R48 R51 R52 0 0 0 0

GPIOLV0 SPIVCC GPIOLV1 CS CLK MISO MOSI CLK32K CLK32KMCU

TP6

B2 B1 A2 B3

SPI/I2C Interface Control Logic

GPIOLV2 GPIOLV3

GPIOLV4

R82

DNP

TP7

Output, 0~SPIVCC

E3 G3 F3 H2
R76 0 Output, 0~1V2_RTC ECKIL 3V15_SW4A R73 C249 0 1V2_RTC 3V15_SW4A (pg10)

R54

4.7K GND

CLK32KVCC VSRTC

VCOREDIG 1.5V

VCORE R34

0 DNP VCOREDIG VCORE REFCORE

L1 J1 J2 K1

VDDLP VCOREDIG VCORE VCOREREF

3V15_SW4A 1V8_SW5

2.775V 1.2V

Reference Generation

0.1UF R454 GND 3V15_SW4A U20 10K Input, 0~3.6V

C40

C41

C42 1uF

C44 0.01UF R80 100K R79 10K

VCC

1 2

R86

WDOG_B

(pg9)

0.1UF 1uF

GND NC7SP125P5X

3
GND SYSTEM_DOWN(GP4_17) RESETB RESETBMCU (pg9)

GND

M2
C56 0.1UF GND

Coincell
LICELL WDI

K3 D6 B5 D5 B4 P1 A5 A6 E5 G6 G5 F6 F5 E6 A9
R75 0 DNP PWNON1 PWRON2 PUMS1 PUMS2 GND PUMS3 PUMS4 PUMS5 High: ICTEST mode Low: normal mode R74 0 10K R90 DNP VCOREDIG R89 R88 R87 R85 R84 R83 0 0 0 0 0 0 Output, 0~SPIVCC (active high) STANDBY GLBRST PMIC_INT(GP4_18) (pg9) Input, 0~3.6V, high level (1.0~3.6V) Input, 0~VCOREDIG(1.5V) open drain output (active low)

Battery Backup

SDWN RESET RESETBMCU INT

2 1

+ BT1 2994TR

Coin cell.
3
-

GND

STANDBY GLBRST PWRON1 PWRON2 G1 XTAL2

QZ1

E1 2
C62 15pF

Crystal Oscillator

PUMS1 PUMS2 PUMS3 PUMS4 PUMS5 ICTEST

XTAL1

1
C61 15pF

32.768KHZ

MC34709
GND PC34709VK GND

Power Up Mode
VCOREDIG 1V2_RTC C36 0.1UF R45 C37 0.1UF GND 0

1V8_SW5 VCOREDIG R66 10K GLBRST C54 (active high) GND (pg10,6) PMIC_STBY_REQ 1.2V level input R53 10K 0.1UF 1V8_SW5 GND GLBRST (pg17)

RESET

SW2

STANDBY
1 VCCA
R29 0 DNP R27 0 R30 0 R31 0 R32 0 DNP GND

3 4
SPST PB

1 2

GND

0 1 1 1 0

PUMS5 PUMS4 PUMS3 PUMS2 PUMS1 R37 0 R38 0 DNP R39 0 DNP R40 0 DNP R41 0

VCCB 4 5

B NC

R50

STANDBY

U4 NLSV1T34

GND RESETBMCU GND GND (pg10,6) PMIC_STBY_REQ R55 0 DNP RESETB R71 0 D13 BAT54A-7-F 1 C60 R70 0 POR_B (pg10) (pg10)

GLBRST

R67

DNP

R68 68K

R69 68K

RESET_IN_B

3
(pg10) U3D JTAG_RESET_B R397 0

0.1UF GND

SUBSLDO SUBSGND SUBSPWR SUBSPWR3 SUBSPWR2 SUBSPWR1_8 SUBSPWR1_7 SUBSPWR1_6 SUBSPWR1_5 SUBSPWR1_4 SUBSPWR1_3 SUBSPWR1_2 SUBSPWR1_1

SW1VSSSNS GNDSW2 R13 B10

GNDSWBST

GNDSW4B GNDSW4A GNDSW1A1

GNDSW1B1

SUBSREF SUBSANA1 SUBSANA2

GNDSPI GNDCORE GNDREF GNDUSB GNDGPIO GNDRTC GNDCTRL

GNDREG1 GNDREG2 GNDREF1 GNDREF2

GNDSW5

H10 J8 K9 G10 E11 J9 H9 H8 G9 G8 F9 F8 E8

A3 H1 M1 C1 C9 F1 B6

P8

K8 K12 F10

H5

M14 J12 N9 B12

P6 P3 P9

P12

F14

GND

GND

PC34709VK

Figure 29. MC34709 System/Control Signals

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

D14

GNDSW3

GNDADC

35

i.MX50 Power Management Design with the MC34709

U6C

i.MX50 - CONTROL PINS

(pg6) (pg10) (pg10)
NVCC_RESET

1V8_SW5 R8 R9 U8 T9 U7 T8 V4 SH21 JTAG_TCK (pg10) JTAG_TMS (pg10) JTAG_TDI (pg10) JTAG_TDO (pg10) JTAG_TRST_B (pg10) DNP R129 1K W6 Y6 GND R130 1.0M 1V8_VPLL Y1 VCC EN/DIS DGND 22.5792MHZ DNP GND GND 4 1 2 10K R134 C142 0.1UF R119 10K DNP JTAG_MOD

BOOT_MODE0 BOOT_MODE1 R128 10K

V3 U3 U4 Y2 Y3 Y4 W4

BOOT_MODE0 BOOT_MODE1 TEST_MODE PMIC_STBY_REQ PMIC_ON_REQ CKIL ECKIL MCIMX508

NVCC_JTAG

RESET_IN_B (pg6) POR_B

W3 Y5

RESET_IN_B POR_B

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRSTB JTAG_MOD CKIH

(pg6) (pg6)

NVCC_RTC

GND PMIC_STBY_REQ PMIC_ON_REQ

QZ2 1 C140 18PF DNP

EXTAL XTAL

2 C141 18PF DNP SH22 DNP

32.768KHZ DNP

Y2 GND 4 1 C144 15pF

GND

OSC.
3 2
GND

3 C143 15pF

OUT

GND

24MHZ

(pg6)

ECKIL

Figure 30. i.MX50 Control Signals If an external battery charger is required, it is recommended to use a charger with power path management which isolates the battery from the system node while charging. The main system voltage from the charger will be connected directly to the BP node while the external charging voltage and the battery are connected on the chargers end.

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i.MX50 Power Management Design with the MC34709

5.5

MC34709 layout example

The following is a layout example of the MC34709 implemented on a four layer board with all component on the top layer and using standard 8 mils vias.
2 J125 16 J122 2 12 VSWBST_SENSE1 BH2

BH1

15

1 R139 C73 R138 C77 C72

11 C A D23 R141 C A R142 C75 D18 C A R140 C76 D19 C A R143 C74 D24 C A D22 C A D21

R162

R163

R164

R161

4 5

U7 3 1 C D17

C92 C91 C89 C87 R132 C88 A

C82 R158 R159 24 25

C81 13 12 U6 BH5 C90 1

F1

TP1 1 L11

1 36 37 R131 48 4 3 C67 1 Y2 2 C79 R145 R144 C78 C68

S3

S1 1 5 J121

R135 R137 C85 R150 5 1 U5 4 3 SW4 C86

S4 L12

S2 1

1 R153 BH4

2 2 R152 J25 1 1 J65 1 1 PWRON2 J40 2 1 J64

5 J123

C50 C38 C39 Y1 R64 1 R65

D3

J58 CLKVCC1 1 1

2012 FREESCALE

KIT34709VKEVBE
S/N

700-XXXXX REV X SCH-XXXXX REV X

SW1

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

R165

R157

R156 5 J124 6 1 8 R134 C70 1 2 8 R133 C69 1 D25 C A D20 C A 1

R160

1 J68 J120 J3 1

8 R32 R136 C71 C 1 D5 R31 R34 A A C D4 R33 Q7 1

J2

4 U3 5 C83 + C93 R155 R154 C95 + C94

4 U2 5

4 U4 5

Q8

TP_XTAL2 WDI1 RESETBMCU1 TP_XTAL1 VCOREDIG1 VCORE1

R147 R146 R148 R149 SW3 SW2 2 2 GLBRST1 J29 1 1 C80 J69 1 J37 2 5 6 J31 1 J30 1 1 INT1 PWM2 PWRON1 R151 C84 A
C41 R58 R127

J60 1

J62 1

J67 1

J74

REFCORE1 VDDLP1 STANDBY1 VSRTC1 ADIN10 J118 GNDSW1B1 BP_SENSE1

R46 SW2LX1 ADIN9 ADIN11 SW3LX1 SWBSTLX1 C34

PWM1 C11 C33

20

19

SW2FB1 R56 R129 GNDSWBST2 SW3FB2 L5 R130 R57

L10 D9 R48 R47 GNDSW4A1 D10 1C66 C6 1 U1 GNDSW3 A BC D16 R124 J21 DE C59 C28 FG 1 C3 1 HJ C32 KL C30 C49 C40 Q3 M C31 C23 C46 VGEN2 VHALF1 PN C22 R Q4 C44 C21 C20 D11 VREFDDR1 VDAC1 C58 D13 D7 C37 R49 C15 L7 R53 C27 C13 D12 1 D8 LDOVDD1 C9 TSY2 L8 L9 J52 J56 VUSB2 1 Q6 C16 B 1 1 1 1 1 1 B SW4ALX1 C Q5 C19 GNDSWBST1 GNDSW4B1 1 C25 2 2 R125 SW4BLX1 R60 R128 VPLL1 Q2 J32 J43 1 J47 1 BAT1 1 1 Q1 1 J78 J79 J77 1 R41 1 J81 R44 SW1ALX1 SW1BLX1 1 R43 1 C R40 L2 L3 1 R38 R42 R35 J76 R37 C60 R121 C62 TSX1 J80 1 1 R66 R67 C53 R52 C57 TSREF1 C45 R59 R126 C7 C8 R55 GNDSW1A1 TSY1 SW5LX1 GNDSW5 SW1FB1 C29 R45 R39 R36 TSX2 J70 1 J71 1 J73 1 J72

GNDSW2 VUSB1

STANDOFFS REQUIRED
Figure 31. KIT34709VKEVBE FAB Drawing

R16 L4 R15 R122 R51 C61 R14 C64 1 16 1

C26 C14 1

BH6

J117

9 19 J66 20 8 BH3

37

i.MX50 Power Management Design with the MC34709

Figure 32. KIT34709VKEVBE Top Layer

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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with the MC34709

Figure 33. KIT34709VKEVBE Layer 2

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

39

i.MX50 Power Management Design with the MC34709

Figure 34. KIT34709VKEVBE Layer 3

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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

i.MX50 Power Management Design with the MC34709

A VER 83372-071

Figure 35. KIT34709VKEVBE Bottom Layer

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

41

i.MX50 Power Management Design with the MC34709

5.6

Migrating from MC34708 to MC34709

For customers migrating from the MC34708 platform to the MC34709 a very low design effort is required due to the high compatibility system between the to devices. Table 10 shows the main difference between both power management devices. Table 10. MC34708 and MC34709 difference Features
Control Logic Power control logic with processor interface and event detection Single SPI/I2C bus for control & register access Real time clock and crystal oscillator circuitry with coin cell backup Support for external secure real time clock on a companion system processor IC 10 bit ADC 4 wire resistive touchscreen interface 7 External ADC inputs. Dedicated ADC channel for Battery voltage sensing Dedicated ADC channel for battery current sensing Dedicated ADC channel for BP voltage Dedicated ADC channel for Die temperature Dedicated ADC channel for VBUS voltage. (USB device detection) Dedicated ADC channel for coin cell voltage Power Supplies(10) 5 Buck regulator 1 Boost regulator 8 LDO Regulators with internal and external pass devices. Auxiliary Circuits USB/UART/Audio switching for mini-micro USB connector Four general purpose low voltage I/Os with interrupt capability Two PWM outputs Two General purpose LED drivers Package 206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm pitch 206 MAPBGA - 13 x 13 mm - 0.8 mm pitch 130 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch Notes:
10. All Power supplies have the same voltage and current rating on both devices.

MC34708

MC34709

Yes Yes Yes Yes

Yes Yes Yes Yes

Yes Yes Yes Yes Yes Yes Yes Yes

Yes Yes No No No Yes No Yes

Yes Yes Yes

Yes Yes Yes

Yes Yes Yes Yes

No Yes Yes No

Yes Yes No

No No Yes

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Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

References

Firmware portability is straights forward, since register maps are bit to bit compatible. However, the MC34709 uses a reduced set of register which eliminate all registers/bits related to the functionality not supported on the MC34709, therefore care must be taken that RESERVED registers/bits are not addressed on the firmware when porting the application to the MC34709.

References
Description
Data Sheet Data Sheet Development Guide Reference Manual Data Sheet

Document Number
MC34709 MC13892 IMX50SDG IMX50RM IMX50CEC

Description / URL
http://cache.freescale.com/files/analog/doc/data_sheet/MC34709.pdf?fsrch=1&sr=2 http://cache.freescale.com/files/analog/doc/data_sheet/MC13892.pdf?fsrch=1&sr=1 http://cache.freescale.com/files/32bit/doc/user_guide/IMX50SDG.pdf?fsrch=1&sr=1 http://cache.freescale.com/files/32bit/doc/ref_manual/IMX50RM.pdf?fsrch=1&sr=10 http://cache.freescale.com/files/32bit/doc/data_sheet/IMX50CEC.pdf

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

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Revision History

Revision History
Revision
1.0

Date
12/2012 Initial release

Description of Changes

44

Power Management Design Guidelines for the i.MX50x Family of Microprocessors, Rev. 1.0 Freescale Semiconductor

Revision History

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45

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Document Number: AN4603 Rev. 1.0 12/2012