JOURNAL OF TELECOMMUNICATIONS, VOLUME 20, ISSUE 2, JUNE 2013

Design of 6T SRAM Cell Using Independent Double-Gate FinFET in Subthreshold Region

Mr Ngangbam Phalguni Singh1, Mr A.Ranjith2 and Mr R.Thandaiah Prabu3
Abstract Moore's law has enabled the scaling of CMOS technologies over the past several decades. However, the scaling of conventional transistors beyond 22nm is limited by various factors, such as power consumption and process variation effects. Increased transistor leakage and performance variation present challenges for scaling of conventional six-transistor (6-T) SRAM cells. It has been recently shown that advanced transistor structures such as FinFETs are more scalable and that FinFET-based 6-T SRAM cell designs offer improved static noise margin (SNM) with reduced variability, as compared with planar bulk-Si SRAM cells. Index Terms

Moores law, CMOS, 6-T SRAM, FinFET, SNM u

improvement in cell read margin can be achieved with no layout area penalty by using dynamic feedback on the passgate (PG) transistors. In this work, the impact of this pass-gate feedback (PGFB) technique on cell writeability is examined, and gate work function tuning for optimization of the trade-off with read margin is discussed. To further improve cell write-ability, the p-channel pull-up devices can also be operated in BG mode, with their back gates driven by a separate write word line. This pull-up write gating (PUWG) technique is effective for maintaining larger than 6 standard deviations yield down to 0.4V VDD without area penalty, making FinFET-based 6-T SRAM compelling for high-density memory applications.

1 INTRODUCTION
ith every successive technology generation, leakage current has been increasing exponentially due to the various short-channel effects, such as thresh- old voltage (Vth) roll off, rain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL). Double-gate field-effect-transistors (DGFETs) have been proposed as a promising alternative to the conventional transistor technology. Due to the superior electrostatic integrity of the channel, provided by the double-gate structure, they can significantly mitigate the effects of short-channel effects. FinFETs are quasiplanar structures in which the channel is made to stand up on its edge. Fin- FETs consist of a thin silicon fin around which a gate electrode is wrapped. This results in a dual/tri-gate structure, depending upon the thickness of the oxide at the top of the channel. Fin- FETs have also been shown to have a superior ION=IOFF ratio as compared to the conventional transistor at the same technology node. Hence, FinFETs can be used to increase performance and reduce leakage current of a chip simultaneously.

FEATURES OF DG-FINFET

The two gates of the FinFET can be made independent of each other by etching out the top portion of the FinFET. Such FinFETs have been exploited by researchers to develop various innovative standard cell designs. Also, the Vth of the front gate of the FinFET can be controlled by applying a bias to its back gate. Since Vth controls both the subthreshold leakage and the delay of a logic gate, the back-gate bias can be used as an important knob to optimize the delay and power of circuits that employ independent-gate FinFETs. Further, by leveraging the capability of the FinFET to be operated in back-gate (BG) mode (in which the gate electrodes on either side of the fin are separated and independently operated), dramatic
Mr Ngangbam Phalguni Singh1, Mr A.Ranjith2, Mr R.Thandaiah Prabu3, are with the School of Electronics & Telecommunication Engineering, St Joseph College of Engineering & Technology, St Joseph University in Tanzania, Tanzania, Dar es Salaam.

The following are the advantages in DG-FINFET: 1. Better control of short channel effects. 2. Low DIBL (Drain Induced Barrier Lowering). 3. Reduced Ioff 4. Better control of leakage current. For a symmetric, undoped Double-Gate FinFET, the same voltage is applied to the two gates having same work function.

Fig.1 Structure of DG-FINFET

JOURNAL OF TELECOMMUNICATIONS, VOLUME 20, ISSUE 2, JUNE 2013

Fig.2 Cross-Sectional View of DG-FINFET The equation showing the relationship between the gate voltage and electric potential is given below: s = Vg - i (tox/ ox) [2 sikTni(eqs/KT)]1/2 (1)

Fig.4 6T-SRAM cell There are some issues in SRAM cell scaling. They are listed below: 1. Occupy more than 50% of Micro-chip 2. Rapid increase of stand-by leakage 3. Trade-off between RM and WM 4. Yield reduction due to Vth variation The analysis for DG-FinFET has been done using two techniques: (a) PGFB technique (b) PUWG technique It has been compared with the following 6T-SRAM using DG-FinFET. With feedback, the pass-gate transistor on the node storing 'O' is weakened, reducing its ability to pull up the storage node during a read operation. As a result, higher SNM is achieved. Although a higher work function can be used to improve SNM, it is less effective than PGFB at high VDD. Additionally, a larger m will degrade writeability by increasing the Vth of the pass-gate transistors and lowering that of the pull-ups. This effect is most significant at low VDD, where a larger m can keep the pass-gate device in subthreshold operation. The PGFB technique allows for lower m and therefore higher lw at low VDD; however, lw is limited at high VDD by the reducing gate drive on the pass-gate as the cell switches (Fig.5). A further benefit of the low m is that the VCL bias at the lw point is larger.

The change in electric potential w.r.t gate voltage is shown in fig.3. The plot is between gate voltage and electric potential at W=20nm and tox=2nm. It has been observed that below 0.41v, s o V g - i. After that o becomes exponentially. (2) increases

constant

and

Fig.3 Electric Potential With Respect to Gate Voltage

ANALYSIS OF 6T-SRAM USING DG-FINFET

The following diagram is the 6T-SRAM cell using ordinary CMOS transistors.

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Fig.5 6T-FinFET SRAM in PGFB technique in subthreshold swing At low VDD, this bias approximately scales with VDD. The larger VCL results in smaller gate drive and the equivalent of a degraded subthreshold swing for the PU5 transistor. This is illustrated in Fig. 4, where the crossing of the PG and PU IV curves roughly corresponds to the minimum VDD at which the cell is write-able (lw > 0). Since the effects of a small Tsi variation in PG3 or PU5 will shift the respective I-V curve horizontally, the amount by which the crossing moves gives a rough approximation of the slope of the lw yield vs. VDD curve. The flatter PU5 curve of the PGFB design suggests a flatter yield vs. VDD curve at low VDD. The complete yield projection considering possible Lg and Tsi variations for all six transistors confirms this result. Just as feedback can be used to weaken the pass-gate transistor during a read operation, it is possible to weaken the pull-up transistors during a write operation using a write word line (WWL) as one of the gates on each pull-up. As illustrated in Fig.6, the shared WWL contact can be added without increasing cell area, but the routing may require an extra layer of metallization. During a write operation, VWWL=VDD weakens the pull-up transistor.

(a) PGFB configuration

Cell Area=0.35um2 (b) Layout of PGFB

(a)PUWG configuration (c)Read ability

(d) Write ability

Cell Area=0.35um2 (b)Layout of PUWG

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enables continued 6-T SRAM scaling and enhancement of noise margin and leakage current reduction.

ACKNOWLEDGMENTS

We would like to thank our University for supporting this work and allow us to use VLSI lab. We also thank our colleagues for their supports.

REFERENCES
[1] N. Lindert et al., DRC, 2001, pp.26-27. [2] Z. Guo et al., ISLPED, 2005, pp.2-7. [3] Taurus Device v.2005.10 (Synopsys, Inc.) [4] C. Wann et al. IEEE VLSI-TSA, 2005, pp.21-22. [5] K.Kim and J.Fossum Double-Gate CMOS: Symmtrical Versus Asymmetrical-Gate Devices, IEEE TransElec.Dev.,vol.48,no.2, 2001, pp.294-299. [6] F.BalestraS.Cristoloveanu, M.Benachir, J.Brini and T.elewa, Double-gate silicon-on-insulator transistor with volume inversion A newly device with greatly enhanced performance, IEEE Elec.Dev. Lett.,vol.8 ,no.9, 1987, pp.410-412. [7] K Boucart and A.M .Ionescu, Double-gate tunnel FET with high-k gate Dielectric. I EEE Trans. Electron Devices, vol.54, no.7, pp.1725-1733, Jul.2007.

(c) Write ability

(d) Read ability Fig.6 6T-FinFET SRAM in PUWG technique in subthreshold swing Enhanced lw for the pull-up write gating (PUWG) case, when m is chosen for 180mV SNM at VDD=0.7V, is illustrated. The PGFB and PUWG techniques can be combined to improve lw further through lower m. The bias to which WWL steps down after a write operation determines the range of m that meets a given SNM target. With PGFB, the range is much larger, enabling low m at moderate biases. A large VWWL turns both PMOS transistors on, degrading SNM. To maintain high yield at low VDD, VWWL should be chosen away from its maximum.

CONCLUSIONS

The various advantages and the structure of FinFET are studied. The analysis for DG-FinFET has been done using two techniques: PGFB technique and PUWG technique. Read and Write performances are improved without area penalty. PGFB enables greater write-ability at low VDD by allowing for low m. PUWG allows for further write-ability improvement by weakening the PMOS transistors during a write operation. Thus combination of these two techniques

NGANGBAM PHALGUNI SINGH received his Bachelor Degree in Engineering in ECE from Anna University, Chennai, India in 2009. He received the Master Degree in VLSI Design from Anna University, Chennai, India in 2012. He has attended five conferences and published a book Memristors and its applications in VLSI Design (ISBN: 9783847326113). He got best paper award also for DESIGN OF LOGICAL CIRCUITS USING MEMSESISTIVE COMPONENT FOR LOW POWER VLSI APPLICATIOS. Currently he is working as Asst. Lect. in the School of Electronics & Telecommunication Engineering, St Joseph College of Engineering & Technology, St Joseph University in Tanzania, Tanzania, Dar es Salaam. His areas of research include VLSI Design, Nanotechnology and applied electronics. A. RANJITH received his Bachelor Degree in Engineering in ECE from Anna University, Chennai, India in 2006. He received the Master of Engineering in Optical Communication from the Faculty of Engineering & Technology, Anna University, Trichy, India in 2009. He has attended 3 conferences and published 2 papers in

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international journal. Currently, he is a Lecturer in the Department of Electronics & Communication Engineering, at St.Joseph College of Engineering & Technology, Dar es Salaam, Tanzania. His areas of research include Optical Communication, Fabrication of VLSI Design. R.THANDAIAH PRABU received his Bachelor Degree in Engineering in ECE from Anna University, Chennai, India in 2007. He received the Master of Engineering in Optical Communication from the Faculty of Engineering & Technology, Anna University, Trichy, India in 2009. He has attended 4 conferences and published 2 papers in international journal. Currently, he is a Lecturer in the Department of Electronics & Communication Engineering, at St.Joseph College of Engineering & Technology, Dar es Salaam, Tanzania. His areas of research include Optical Networks, Wireless Communication and Fabrication of VLSI Design