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Download JNTU (NR) M.TECH 2-Semester DESIGN OF FAULT TOLERANT SYSTEMS JULY/AUG-2006 Exam Question Paper

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Code No: NR-54211/MT M.Tech. II-Semester Examinations, July/August 2006. DESIGN OF FAULT TOLERANT SYSTEMS (Common to Digital Systems and Computer Electronics and Digital Electronics and Communication Systems) Time: 3 hours Max. Marks: 60 Answer any FIVE questions All questions carry equal marks -1.a) Define Reliability and Failure rate and derive the relationship between these two parameters. b) Discuss about the reliability of series-parallel and parallel series systems. 2.a) With a neat diagram explain the principle of operation of sift out modular redundancy (SMR). Give its merits and demerits. b) Explain in detail about Time redundancy and Software redundancy schemes. 3.a) Design a totally self checking checker using m-out-of-n codes. b) Design a totally self checking checker using low cost residue code. 4.a) Discuss about the fail safe design of sequential circuits using partition theory. b) Discuss about totally self checking PLA design. 5.a) With a neat diagram, explain the Reed-Mullers expansion technique. b) Discuss about the use of control and syndrome testable design. 6.a) With a neat diagram explain how an LFSR is used as signature analyzer. b) Discuss in detail about the working of multiple-input signature register. 7.a) Using necessary diagrams, explain the principle of operation of level sensitive scan design (LSSD) b) Explain controllability and observability by means of scan register. 8.a) Distinguish between BIST exhaustive testing, pseudorandom testing and pseudo exhaustive testing. Give examples. b) Explain in detail about generic offline BIST architecture.

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