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Code No. B7008 NR JAWAHARLAL NEHRU TECHNOLOGY UNIVERSITY, HYDERABAD M .Tech. II Semester Supplementary Examinations, March 2009 FAULT TOLERANT SYSTEM DESIGN (Electronics & Communications) Time: 3 hours Max. Marks.60 Answer any Five questions All questions carry equal marks 1.a) Discuss indetail about different levels of modeling. Give necessary examples. b) With an example, explain how Hazards are detected in digital circuits. c) Discuss about delay models. 2.a) Describe the following terms: i) Fault detection and redundancy ii) Fault equivalence iii) Fault locations b) With an example, explain the principle of operations of path sensitizations for detecting faults in digital circuit. 3.a) Describe the various fault simulation techniques used for combinational circuits. b) What is fault sampling? Explain indetail with an example. 4.a) Discuss about ATPG (automated test pattern generation) for single stuck faults in combinational circuits. b) With necessary examples, discuss about compactions and compression. 5.a) Explain with necessary examples, how non-feedback bridging faults are detected in digital circuits. b) Discuss about Test generation for bridging faults. 6.a) Discuss about testability tradeoffs b) With necessary diagrams, explain about full integrated scan technique. c) Discuss about syndrome test and signature analysis. 7.a) Discuss about general aspects of compression techniques. Give necessary examples. b) Describe the following compression techniques. i) Ones-corent compression ii) Transition corent compression 8.a) Discuss about the following BIST architectures i) STUMPS ii) CEBS iii) CSTP iv) BILBO b) Discuss about memory test architectures and techniques. DIET CET

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DESIGN

OF

FAULT

TOLERANT

SYSTEMS

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