Three-phase phase-lock loop for distorted utilities

A.M. Salamah, S.J. Finney and B.W. Williams Abstract: A novel three-phase phase-locked loop (PLL) structure suitable for phase and angular frequency derivation from distorted ac utility voltages is presented. The proposed PLL has a simple structure; a conventional three-phase PLL followed by a proportional-integral (PI)-controlled moving average lter together with a phase-locking algorithm. The objective of the proposed technique is to capture the fundamental phase angle and angular frequency of three-phase clean, distorted, balanced or unbalanced ac utilities. The PLL gives fast, accurate angular frequency and phase locking and is robust to utility distortion such as line notching, random noise, voltage imbalance, phase loss, phase imbalance, harmonics, dc offsets and frequency variation. The analysis presented substantiates the immunity of the proposed PLL to unbalanced and distorted utility conditions. The PLL technique is simulated and digital signal processor (DSP)-implemented for a three-phase system to verify the analytical results. The simulated and experimental results, for numerous utility conditions, demonstrate its phase-tracking ability, whereas the conventional technique fails to lock accurately in highly distorted, three-phase grid-connected operation.

Introduction

Phase-lock loops (PLLs) have been extensively used in power system, power electronics for some time. Applications include the generation of thyristor ring angles [1] for highperformance sinusoidal inverters [2]. Numerous approaches have been proposed on the basis of a variety of techniques, principally, zero-crossing and two-axis transformation [1 6]. Excluding phase loss and high-distortion conditions, good performance is achieved using zero-crossing techniques for thyristor-based applications [1, 2]. The performance of sensitive utility-grid-connected systems such as active lters, UPS and distributed generation systems depends on the quality and precision of the utility-voltage information [3, 4]. Zero-crossing techniques fail to meet the sensitivity required by such applications [24]. Fig. 1 shows the general block diagram of a three-phase, grid-connected power converter. The phase angle of the utility-voltage vector is the basic information for most grid-connected power conditioning equipment. This information may be used to synchronise the turning on/off of power devices, to calculate and control the ow of active/reactive power or to transform the feedback variables to a reference frame suitable for control purposes. Besides utility-interface applications, PLL methods are also used in motor control to estimate the electrical angular speed of the rotor [5, 6]. The lock quality directly affects the performance of the control loops in the mentioned applications. In such applications, accurate, fast detection of the utility-voltage phase angle is essential in assuring the correct generation of the reference signals. Thus, PLL topologies must handle distorted utility voltages if intended for applications involving utility-voltage vector tracking [711]. The angle information is typically extracted using some form of PLL [3].
# The Institution of Engineering and Technology 2007 doi:10.1049/iet-epa:20070036 Paper rst received 22nd January and in revised form 19th April 2007 The authors are with the Department of Electrical and Electronic Engineering, Strathclyde University, 204 George Street, Royal College Building, Glasgow, G1 1XW, UK E-mail: ahmedsalamah@eee.strath.ac.uk IET Electr. Power Appl., 2007, 1, (6), pp. 937 945

Recently there has been increased interest in PLL topologies for grid-connected systems [37]. The three-phase PLL discussed in [7, 10] uses a synchronous reference frame (SRF) to detect the phase angle, frequency and amplitude of the utility-voltage vector. Better SRF PLL performance, for unbalanced utility voltages, is achieved by separating the positive and negative voltage sequences and feeding back only the positive sequence. The PLL structure introduced in [8] utilises a weighted least-square method as an alternative to calculating the positive and negative utility-voltage sequences; this improves PLL tracking performance. An important issue is tuning the PI or leadlag controller used in PLL topologies [9]. Some PLL structures that use the positive sequence approach [711], fail with some types of distortion, especially that typical in three-phase systems (asymmetrical distortion on the three phases). Conventional techniques do not function accurately in phase-loss conditions or in a highly distorted environment. The random noise, found in the supply voltage or generated by measurement devices, has not been previously investigated. The effect of random noise is detrimental to conventional PLL operation. This paper investigates a novel three-phase PLL which is capable of locking to the phase and frequency of the three-phase ac supply voltage under distorted conditions (amplitude distortion, frequency distortion, phase distortion, three-phase harmonics and phase loss; all having random noise). The PLL analysis, simulation and practical results will show that the proposed PLL has a fast, accurate response. 2 Conventional three-phase PLL

The conventional three-phase PLL topology is illustrated in Fig. 2 [6]. The instantaneous phase-angle u is detected by synchronising the PLL rotating reference frame to the utility-voltage vector [5 7]. The PI controller sets the direct (or quadrature) axis reference voltage Vd (or Vq) to zero. This results in the reference being locked to the utility-voltage vector phase angle. Consequentially, the voltage vector frequency and amplitude are by products. Tuning of the feedback gains requires determination of the equivalent linear model [10].
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[Va Vb Vc]T, input to d q components [Vd 2 3   Va Vq 4 5 V T b Vd Vc where " T ^ 2=3 cos u ^ 2=3 cos u

Vq]T (1)

p ^ 1= 3 sin u ^ 1=3 cos u p ^ 1= 3 cos u ^ 1=3 sin u # p ^ ^ 1= 3 sin u 1=3 cos u p ^ ^ 1=3 sin u 1= 3 cos u

Fig. 1 PLL in a three-phase system

is the rst controller output angle. and u Let the three-phase input time-variant vector [Va Vb Vc]T have the general form 2 3 2 3 2 3 va Va sin u 4 Vb 5 V 4 sin (u 2=3p) 5 4 vb 5 (2) Vc vc sin (u 2=3p) where V and u are the balanced voltage amplitude and instantaneous phase of the supply waveform and [Va Vb Vc]T, is an unbalancing voltage vector. Substituting (2) to (1) gives     ^ u) a(t) cos u ^ b(t) sin u ^ Vq cos ( u V (3) ^ u) a(t) sin u ^ b(t) cos u ^ Vd sin (u where

Fig. 2 Block diagram of the conventional PLL

It has been shown that this basic PLL is signicantly degraded in the presence of only slight disturbances [12]. Other techniques, such as zero crossing and the digital PLL discussed in [9 11, 13 22], show even poorer performance when subjected to slight supply distortion. 3 Proposed three-phase PLL

2 1 1 1 1 a(t) na nb nc and b(t) p nb p nc 3 3 3 3 3

Fig. 3 shows the block diagram of the proposed three-phase PLL. It has three cascaded stages: a conventional PLL followed by an average PI controller and a phase locker. Parameters of the conventional PLL are tuned as in [11, 12]. The rst phase-lock loop uses the supply voltage vector [Va Vb Vc]T, which is transformed into the d q frame. The direct voltage component Vd is regulated to zero using a PI controller. For a balanced supply, the controller output is the supply voltage angular frequency v which after integration gives the supply voltage phase u With distorted utilities, v and u are distorted proportionally to the supply distortion level. For applications sensitive to v and u, supply harmonics are ltered, which delays the PLL response by at least a few supply cycles. However, some distortion types require sluggish lters or cannot be corrected by lters (phase-loss and phase-angle imbalances). The proposed solution uses a controlled moving average algorithm in the process to extract v. The average of v and the rst stage output angle u are transferred to a phase locker, where u is recovered from any distortion. 4 Mathematical analysis of the proposed PLL

a(t ) and b(t ) represent the distortion content of the threephase ac supply voltage. Since most distortion has a dc shift periodic nature with integer multiples of the fundamental frequency, a(t ) and b(t ) are considered dc-shifted (a0 , b0) periodic functions with superimposed zero-mean random noise, namely 2 3 P an sin (nvt wn ) a0   n1,2,... a(t) 6 7 P 4 (4) 5 b(t) bn sin (nvt gn ) b0
n1,2,...

For a balanced source, a(t ) and b(t ) are both zero. Thus the controller must minimise (to zero) the direct voltage com u. Similarly, the controller must miniponent Vd when u mise (to zero) the quadrature voltage component Vq when u + p/2 (where the sign depends on the three-phase u supply sequence). From (3), for an unbalanced supply, reducing the direct voltage component to zero gives a u b(t )cos u ), and error in the v function of (a(t )sin u reducing the quadrature voltage component to zero gives b(t )sin u ). an error function of (a(t )cos u Generally, distorted v and u can be characterised as 2 3 P v cn sin (nvt 1n ) j(t)   n1,2,... v ^ 6 7 ^ 4 u P c sin (nvt 1 ) j(t)dt c 5 u n n u
n1,2,...

(5) where j(t ) is uniform random noise and Cu is the integration constant which equals +1/2p if the feedback is Vd and zero if the feedback is Vq (non-dc terms are inuenced by PI set tings). In (5), the non-dc terms are removed by averaging v over one complete supply cycle. The averaging window size
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Mathematical analysis can substantiate that the proposed PLL is capable of locking to distorted three-phase ac inputs. The rst PLL stage converts the three-phase
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Fig. 3 Proposed three-phase PLL

a Block diagram b PI-controlled averaging block diagram c Phase-locker block diagram of the proposed three-phase PLL

is determined by a PI controller as shown in Fig. 3. The error signal e(k), at an instant k, fed to the PI controller is given by v e(k ) s window(k 1) (6) v where vs 2p /Ts (Ts is the sampling period of the controller). The PI controller output represents the next averaging window for the average stage. The averaging stage computes the average using
i k P

components in the supply (mainly due to measurement and signal-conditioning circuitry) result in distortion in v with a frequency equal to that of the fundamental. and u Thus in worse case, a tuned controller locks to the required window in one ac supply cycle if the supply contains a dc component. Integration of v cannot be used to determine the phase angle u because the integration constant cu depends on the harmonics and the controller coefcients. gives, Instead, (5) shows that the subtraction of v from v . in steady state (v v), the distortion content, ev , in v That is ev v ^ v and in steady state ev X
n1,2,...

v(i)
, k ! window(k 1) (7)

 (k ) v

ik window(k 1)

(9)

window(k 1)

where window(k) is determined from the PI controller output as window(k ) window(k 1) kp2 (e(k ) e(k 1)) ki2 e(k ) (8)

cn sin (nvt 1n ) j(t)

(10)

where kp2 and ki2 are the controller proportional and integral coefcients. The average controller algorithm is programmed using MATLAB and the m-le is presented in the appendix (Section 10). From (4) and (5), the dc
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gives u Integrating the result and then subtracting from u ^ ev d t cu uu (12) Equation (12) is valid only if the initial integration condition is zero, otherwise a dc error appears in the integration
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Fig. 4 Relation between the input total harmonic distortion (THD), PU and vunbalance ,udeviation
a, c, e and g Conventional PLL b, d, f and h Proposed PLL

output which is proportional to the initial drift. This dc is eliminated by resetting the integration to zero at the beginning of the rst cycle, as shown in Fig. 3c. Thus one ac main cycle is needed before valid estimates are available. 5 Parameter selection for the proposed PLL

Parameters kpl and kil are selected using the conventional method mentioned in [9]. For a 220-V, 50-Hz system the optimum kpl and kil ranges are 30 kpl 70 and 10 000 kil 60 000 kp2 and ki2 selection in (8) for the proposed PLL is based on the required performance and
Table 1: Simulation parameter values used for the conventional PLL and the PI average controller
kp1 ki1 kp2 ki2 Tk 1/fk 940 30 10 000 0.1 0.01 0.0001 V/rad V/ (rad.s) rad/s rad/s2 s

the maximum permissible supply distortion level. Assume kp2 0. Since ki2 changes the averaging window size in proportion to the distortion level, large ki2 values, at certain distortion levels, may cause the controller to lock to the angular frequency but with undesired behaviour. For example if the window size is halved (for one corresponding cycle), the controller output angular frequency will oscillate around the actual angular frequency. On the other hand, if the window size is doubled (for one corresponding cycle), the controller output angular frequency will lock to the actual angular frequency but in double the supply period, that is a slower response is obtained. Thus ki2 should be as small as possible to maintain the windowsize change as follows 1 jwindow(k ) window(k 1)j ( windowactual 2 (13)

where windowactual vs/v. Substituting Ki2 0 from (8) in (13) gives ^( ki2 e 1 vs 2 v (14)

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Table 2: Parameters for slightly distorted utility

Va Vb 105 sin(vt 10) 5 sin(5vt 10) 1 sin(7vt 10) j(t ) 95 sin(vt 2 (2/3)p 10) 5 sin(5vt 2 (2/3)p 10) 1 sin(7vt 2 (2/3)p 10) j(t ) Vc 100 sin(vt (2/3)p 10) 5 sin(5vt (2/3)p 10) 1 sin(7vt (2/3)p 10) j(t ) V V V

j(t )
10

uniform random noise, 2 Vpp, zero mean

V rad

2.p.50

rad/s

Table 3: Parameters for high distortion utility

Va Vb 0 . sin(vt 10) 10 sin(5vt 10) 10 sin(7vt 10) j(t ) 10 50 sin(vt 2 (2/3)p 10) 10 sin(5vt 2 (2/3)p 10) 10 sin(7vt 2 (2/3)p 10) j(t ) 20 Vc 100 sin(vt (2/3)p 10) 10 sin(5vt (2/3)p 10) 10 sin(7vt (2/3)p 10) j(t ) 20 V V V

j(t )
10

uniform random noise, 20 Vpp, zero mean 1 2 . p . 50

V rad rad/s

^ is the maximum window-size error change and is where e given by ^ max{je(i)j}, e k i k window(k 1)

^ is a design parameter which depends on the supply distore ^ is estimated from tion level and the values of Kpl and Kil . e the simulation results under worst possible distortion and at maximum it should be half the window size. On the other hand, the smaller the ki2 , the more sluggish the response. Thus ki2 should be selected to have a reasonable settling time. Applications sensitive to the frequency information may require a shorter settling time. ki2 is selected to have the minimum possible settling time, which is one supply cycle. This may show an aggressive response to high distortion which compromises the settling time response. For a settling time of one supply cycle, ki2 should be able to compensate for the window-size error summation in one cycle, that is ki2 Since ^ e
i k X vs ! e(i) v ik window(k 1) ik X ik window(k 1)

Fig. 5 Angle simulation for slightly and highly distorted supply

a and b ac supply voltages c and d Conventional angular frequency output e and f Proposed angular frequency output g and h Supply actual phase angle i and j Conventional phase angle output (shifted by a quarter cycle) k and l Proposed phase angle output m Conventional angular frequency output with minimum PI settings
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e(i) !

1 vs 2 v

(15)

(16)

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Fig. 6 Simulation output for a transient frequency step change from 50 to 60 Hz and back to 50 Hz; angle simulation for slightly and highly distorted supply
a and b ac supply voltages c and d Conventional angular frequency output e and f Proposed angular frequency output g and h Supply actual phase angle i and j Conventional phase angle output k and l Proposed phase angle output m and n Supply frequency
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We have ki2 ! 1 ^ 2e (17)

From (14) and (17), the region for Ki2 is

where X vL is the output reactance of the inverter, and d is the phase angle between the inverter output voltage E and the grid voltage V From (21), the error in the grid phase angle will be transferred to d which in turn affects P and Q. The error in P and Q is directly proportional to d especially when d is small, since sin(d) d. 7 Simulation and practical results

vs 1 1 ) ki2 ! ^ ^ v 2e 2e

(18)

kp2 is selected such that the PI controller integral reset time Ti2 is faster than the system dynamics (window dynamics). Therefore l/Ti2 . Tsupply , where Tsupply is the supply period. Ti2 , 1 Tsupply (19)

Simulation and practical experiments were performed to verify that the proposed PLL is capable of tracking a distorted supply angular frequency and accurately locking to the supply phase. 7.1 Simulation

Since Ti2 kp2 =ki2 , kp2 , is given by kp2 , ki2 Tsupply (20)

For a sampling frequency of 10 kHz, in a 220-V, 50-Hz ac ^ is chosen to be 100 (half the window size). From system, e (18), ki2 is given by l ) ki2 ! 1/200. From (20), assuming ki2 0.01, kp2 is given by kp2 , 1/2. kp2 0.1 is used. 6 Qualitative analysis

To compare the operation of the conventional and proposed PLLs, a number of simulations are used to study distortion effects on both PLL outputs. The conventional PLL parameters are varied to cover the practical parameter ranges used in [8 12], and where kpl and kil take the minimum and maximum values mentioned in [9] (kpl [30 70] and kil [10 000 60 000]). In each simulation, the proposed PLL parameters kpl and kil are the same as the conventional values to allow a valid comparison. kp2 and ki2 are constant, ki2 0.01 and ki2 0.1. The results are for an input threephase supply THD of 0%, 25%, and 50% and an unbalance in phase (c) amplitude of 0%, 25%, 50%, 75% and 100%. Fig. 4 shows the results of the conventional and proposed PLLs for THD and PU, where PU stands for phase (c) unbalance and is dened by PU jVc Va j 100 Va

Simulation is carried out using MATLAB/SIMULINK. Table 1 shows the simulation parameter values used for the conventional PLL and the PI average controller. Fig. 5 shows two simulation outputs for a slightly distorted utility with parameters shown in Table 2, and a high distortion utility with parameters shown in Table 3. Fig. 5 illustrates the capability of the proposed controller to accurately lock to the supply angular frequency and phase, in one supply cycle (0.020 s). The conventional approach is unable to function accurately when the supply distortion increases, as shown in Fig. 5i and j. Fig. 5m shows the conventional PLL angular frequency output with minimum stable PI settings (kpl 1 V/rad kil 300 V/(rad s)) which shows high distortion plus a sluggish response in reaching steady state (0.15 s). Fig. 6 shows the simulation output for a transient frequency step change from 50 to 60 Hz and back to 50 Hz. The simulation is carried out for both ideal and distorted utilities. The parameters used in the simulation are shown in Tables 4 (ideal utility) and Table 5 (distorted).
Table 4: Ideal utility
Va Vb Vc 10 100 sin(vt 10) 100 sin(vt 2 (2/3)p 10) 100 sin(vt (2/3)p 10) 1 2 . p . 50 2 . p . 60 V V V rad rad/s

and vunbalance and udeviation are dened by

vunbalence

max jvoutput vexact j 100 vexact

Table 5: Distorted utility

Va Vb 0 . sin(vt 10) 10 sin(5vt 10) 10 sin(7vt 10) j(t ) 10 50 sin(vt 2 (2/3)p 10) 10 sin(5vt 2 (2/3)p 10) 10 sin(7vt 2 (2/3)p 10) j(t ) 20 Vc 100 sin(vt (2/3)p 10) 10 sin(5vt (2/3)p 10) 10 sin(7vt (2/3)p 10) j(t ) 20 V V V

and udeviation max juoutput uexact j where voutput and uoutput are the PLL output angular frequency and phase angle. Variables vexact and uexact are exact supply angular frequency and phase angle. Applications such as parallel inverter operation, interfacing to the grid, and active ltering are sensitive to supply phase-angle error. For example when interfacing inverters to the grid, the active power P and reactive power Q delivered to the grid are given by [23] P Q EV sin d X EV cos d V X
2

j(t )

uniform random noise, 20 Vpp, zero mean 1 2 . p . 50 2 . p . 60

V rad rad/s 943

(21)

10

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Table 7: Highly distorted parameters for the conventional and proposed PLL
Va Vb Vc 100 sin(vt 10) 5 sin(5vt 10) 1 sin(7vt 10) j(t ) V V V

j(t )
95 sin(vt (2/3)p 10) 5 sin(5vt (2/3)p 10) 1 sin(7vt (2/3)p 10) j(t )

j(t )
10

uniform random noise, 2 Vpp, zero mean random 2.p.50

V rad rad/s

Fig. 7 Angle simulation for a temporary phase loss

a ac supply voltages b Supply actual phase angle c and d Conventional angular frequency and phase angle output e and f Proposed angular frequency and phase angle output

The simulation results shown in Fig. 6 substantiate that the proposed controller can track step changes in supply frequency and can lock to the supply angular frequency and phase accurately in one ac supply cycle. As mentioned and shown in Fig. 6g, the proposed PLL takes one cycle to give the correct result. Under ideal clean and balanced conditions, the conventional PLL tracks the input supply parameters faster than the proposed technique but this is not practical as the supply is far from ideal (at least the voltage measurement produces offset and noise). The conventional approach has difculty tracking the frequency changes as the supply distortion increases, as shown in Figs. 6i and j. Fig. 7 compares the responses for a temporary loss of phase. The supply is purely sinusoidal, 50 Hz, with amplitude and initial phase shift as in Table 4. Phase (a) is lost at 0.05 s and regained at 0.15 s. Fig. 7c shows the conventional PLL angular frequency output, where the step changes in phase (a) cause an instantaneous angular frequency jump at the instances 0.05 s and 0.15 s. For the conventional approach, the angular frequency (Fig. 7c) and the phase angle output (Fig. 7d) are highly distorted. Figs. 7e and f show the robustness of the proposed algorithm to
Table 6: Slightly distorted parameters for the conventional and proposed PLLs
Va Vb 100 sin(vt 10) 5 sin(5vt 10) 1 sin(7vt 10) j(t ) 80 sin(vt 2 (2/3)p 10) 5 sin(5vt 2 (2/3)p 10) 1 sin(7vt 2 (2/3)p 10) j(t ) Vc 95 sin(vt (2/3)p 10) 5 sin(5vt (2/3)p 10) 1 sin(7vt (2/3)p 10) j(t ) V V V

phase-loss conditions, where the angular frequency output stabilises in one ac cycle, without the large oscillations that occur with the conventional PLL. In simulation results shown, the conventional PLL phase angle does not phase back like the proposed PLL, since the controller output angle is always shifted by +p/2 as mentioned in u+p/2). Thus the conventional output Section 4 (u angle will be leading or lagging by 0.005 s. This phase shift has been taken into consideration in the proposed PLL by adding p/2, as shown in Fig. 3c.

j(t )
10

uniform random noise, 2 Vpp, zero mean random 2 . p . 50

V rad rad/s

Fig. 8 Practical angle measurements for slightly and highly distorted supply
a and b Supply voltages c and d Conventional angular frequency output e and f Proposed angular frequency output g and h Conventional phase angle output i and j Proposed phase angle output
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v
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7.2

Practical experimentation

Practically, the algorithm has been implemented in a 150 Hz Inneon TC1796 microcontroller. The algorithm takes 3050 instruction cycles per sample. The controller parameters are as in Table 1. Tables 6 and 7 show the slightly and highly distorted supply parameters injected into the conventional and proposed PLLs. The practical results shown in Fig. 8 verify the ability of the proposed PLL controller to accurately lock to the supply angular frequency and phase in one ac supply cycle. Parts Figs. 8c and d conrm the limitations associated with the conventional PLL approach. 8 Conclusion

A novel three-phase PLL structure has been proposed, analysed, and compared with the traditional PLL approach. The algorithm was assessed by simulation and practically to validate the approach. The test conditions varied from pure to slightly and highly distorted threephase ac inputs. The simulation and practical results conrm the immunity of the proposed PLL to noise and distortion. Comparison between the proposed and conventional PLLs under a phase-loss condition highlights the accuracy and robustness of the proposed algorithm. Also, the transient response of the proposed PLL was tested and it responds in one ac supply cycle. Supply angular frequency locking and phase angle tracking are better than with the conventional PLL. The results conrm the adequacy of the proposed PLL for power system control applications. 9 References

11 Arruda, L.N., Cardoso, B.J., Silva, S.M., Silva, S.R. and Diniz, A.S.A.C.: Wide bandwidth single and three phase PLL structures for utility conditions. Proc. EPE, 2001, in press 12 Chung, S.K.: Phase-locked loop for grid-connected three-phase power conversion systems, IEE Proc., Elder. Power Appl., 2000, 147, (3), p. 213 13 Leonhard, W.: Control of electrical drives (Spinger-Verlag, Berlin, Heidelberg, New york, Tokyo, 1985) 14 Leonhard, W.: Introduction to control engineering and linear control system (trans. T. Rajagopalan and D.V.R.L. Rao) (Allied Publishers, New Delhi, 1976) 15 Hsieh, G., and Hung, J.C.: Phased-locked loop techniques a survey, IEEE Trans. Ind. Electron, 1996, 43, (6), pp. 609615 16 Nash, G.: Phase-locked lop design fundamentals1994 17 Fairchild Semiconductor Corpration, CD4046BC micropower phase-locked loop, Fairchild Semiconductor Corporation, product datasheet www.fairchild.com 18 Borle, L.J., Dymond, M.S. and Nayar, C.V.: Deveolpment and testing of a 20-kW grid interactive photovoltaic power conditioning system in Western Australia, IEEE Trans., 1997, 33, (2) 19 Gardner, R.M.: Phase-lock techniques (John Willey, 1979) 20 Razabi, B.: Monolithic phase-locked loop and clock recovery circuit (EEE Press, 1996) 21 Boyes, G.: Synchro and resolver conversion (Analong Devices Inc., 1980) 22 Hanseslman, D.C.: Resolver signal requirements for high accuracy resolver-to-digital conversion, IEEE Trans., 1990, E-37, (6), pp. 556561 23 Guerrero, J.M., de Vicuna, L.G., Matas, J., Castilla, M. and Miret, J.: A wireless controller to enhance dynamic performance of parallel inverters in distributed generation systems, IEEE Trans. Power Electron, 2004, 19, (5), pp. 1205 1213

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Appendix

1 Gardner, F.M.: phaselock techniques (wiley, Newyork, 1979) 2 Wolver, D.H.: A phase tracking system for three utility interface invertors, IEEE Trans. Power Electron., 2000, 15, (3), pp. 431438 3 Wolaver, D.H.: Phase-locked loop circuit design (Englewood Cliffs, Prentice Hall, NJ, 1991) 4 Mohan, N., Undeland, M. and Robbins, P.: Power elctronics: converters, applicationsd and design (John Wiley & Sons, Inc., New York, 1989) 5 Blasko, V., Moreira, J.C. and Lipo, T.A.: A new eld oriented controller utilizing spatial position measurement of rotor end ring current. Proc. PESC, 1989, pp. 295 299 6 Nozari, F., Mezs, P.A., Chiping, S. and Lipo, T.A.: Sensorless synchronous motor drive for use on commercial transport airplanes, IEEE Trans. Ind. Appl, 1995, 31, (4), pp. 850859 7 Lee, S., Kang, J. and Sul, S.: A new phase detecting method for power conversion system considering distorted conditions in power system. Proc. IAS Annual Meeting, 1999 8 Song, H., Park, H. and Nam, K.: An instanteous phase angle detection algorithm under unbalanced line voltage conditions. Proc. PESC, 1999 9 Arruda, L.N., Cardoso, B.J., Silva, S.M., Silva, S.R. and Diniz, A.S.A.C.: Wide bandwidth single and three-phase PLL structures for grid-tied PV systems. Proc. 228th IEEE Photovolatic Specialists Conf., September 2000, Anchorage (AK), pp. 1660 1663 10 Kaura, V., and Blasko, V.: Operation of a phase locked loop system under distorted utility conditions, IEEE Trans. Ind. Appl., 1997, 33, (1), pp. 5863

Fig. 9 Shows the MATLAB m-le. MATLAB m-le for the proposed average controller

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