CHAPTER 1 INTRODUCTION 1.1. POWER FACTOR CORRECTION 1.1.1.

INTRODUCTION
Today, our society has become very aware of the necessity of the natural environment protection of our living plant in the face of a programmed utilization of natural resource. Meanwhile, due to the intensive use of this utility, the power supply condition becomes polluted. However, public concern about the dirty environment in the power system has not been drawn until the mid 1980s. With the proliferation of utilization of electrical energy in industries and residence, more and more heavy loads have been connected into the power system. During 1960s, large electricity consumers such as electrochemical and electrometallurgical industries applied capacitors as VAR compensator to their systems to minimize the demanded charges from utility companies and to stabilize the supply voltages. As these capacitors present low impedance in the system, harmonic currents are drawn from the line. Owing to the non-zero system impedance, line voltage distortion will be incurred and propagated. The contaminative harmonics can decline power quality and affect the system performance in several ways: a) The line rms current harmonics do not deliver any real power in Watts to the load, resulting in inefficient use of equipment capacity (i.e. low power factor). b) Harmonics will increase conductor loss and iron loss in transformers, decreasing transmission efficiency and causing thermal problems.
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c) The odd harmonics are extremely harmful to a 3 phase system, causing overload of the unprotected neutral conductor. d) Oscillation in power system should be absolutely prevented in order to avoid endangering the stability of system operation. e) High peak harmonic currents may cause automatic relay protection devices to miss trigger. f) Harmonics could cause other problems such as electromagnetic interference to interrupt communication, increasing product defective ratio, insulation failure, audible noise, etc. Perhaps the greatest impact of harmonic pollution appeared in early 1970s when static VAR compensators (SVCs) were extensively used for electric arc furnaces, metal rolling mills, and other high power appliances. The harmonic currents produced by partial conduction of SVC are odd order, which are especially harmful to three-phase power system. Harmonics can affect operations of other devices that are connected to the same system and, in some situation, the operations of themselves that generate the harmonics. The ever deteriorated supply environment did not become a major concern until the early 1980s when the first technical standard IEEE519-1981 with respect to harmonic control at point of common coupling (PCC) was issued. The significance of issuing this standard was not only that it provided the technical reference for design engineers and manufactures, but also that it opened the door of research area of harmonic reduction and power factor correction (PFC). Stimulated by the harmonic control regulation, researchers and industry users started to develop low-cost
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devices and power electronic systems to reduce harmonics since it is neither economical nor necessary to eliminate the harmonics. Research on harmonic reduction and PFC has become intensified in the early nineties. With the rapid development in power semiconductor devices, power electronic systems have matured and expanded to new and wide application range from residential, commercial, aerospace to military and others. Power electronic interfaces, such as switch mode power supplies (SMPS), are now clearly superior over the traditional linear power supplies, resulting in more and more interfaces switched into power systems. While the SMPSs are highly efficient, but because of their non-linear behavior, they draw distorted current from the line, resulting in high total harmonic distortion (THD) and low power factor (PF). To achieve a smaller output voltage ripple, practical SMPSs use a large electrolytic capacitor in the output side of the single phase rectifier. Since the rectifier diodes conduct only when the line voltage is higher than the capacitor voltage, the power supply draws high rms pulsating line current. As a result, high THD and poor PF (usually less than 0.67) are present in such power systems. Even though each device, individually, does not present much serious problem with the harmonic current, utility power supply condition could be deteriorated by the massive use of such systems. In recent years, declining power quality has become an important issue and continues to be recognized by government regulatory agencies. With the introduction of compulsory and more stringent technical standard such as IEC1000-3-2, more and more researchers from both industries and universities are focusing in the area of harmonic reduction and PFC,
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resulting in numerous circuit topologies and control strategies. Generally, the solution for harmonic reduction and PFC are classified into passive approach and active approach. The passive approach offers the advantages of high reliability, high power handling capability, and easy to design and maintain. However, the operation of passive compensation system is strongly dependent on the power system and does not achieve high PF. While the passive approach can be still the best choice in many high power applications, the active approach dominates the low to medium power applications due to their extraordinary performance (PF and efficiency approach to 100%), regulation capabilities, and high density. With the power handling capability of power semiconductor devices being extended to megawatts, the active power electronic systems tend to replace most of the passive power processing devices.

1.1.2. NON-LINEAR LOAD ANALYSIS:

Power factor is a very important parameter in power electronics because it gives a measure of how effective the real power utilization in the system is. It also represents a measure of distortion of the line voltage and the line current and phase shift between them. Referring to Fig. 1.1a, we define the input power factor (PF) at terminal a-a as the ratio of the average power and the apparent power measured at terminals a-a as described in Eq. (1.1).

(1.1) where, the apparent power is defined as the product of rms values of Vs (t) and is (t).

Fig(1.1) Non-Linear loads draws distorted current

In a linear system, because load draws purely sinusoidal current and voltage, the PF is only determined by the phase difference between Vs (t) and is (t). Equation (1.1) becomes

(1.2) where, Is,rms and Vs,rms are rms values of line current and line voltage, respectively, and is the phase shift between line current and line voltage.
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Hence, in linear power systems, the PF is simply equal to the cosine of the phase angle between the current and voltage. However, in power electronic system, due to the non-linear behavior of active switching power devices, the phase-angle representation alone is not valid. Figure 1.1b shows that the non-linear load draws typical distorted line current from the line. Calculating PF for distorted waveforms is more complex when compared with the sinusoidal case. If both line voltage and line current are distorted, then, Eqs. (1.3) and (1.4) give the Fourier expansion representations for the line current and line voltage, respectively,

(1.3)

(1.4) Applying the definition of PF given in Eq. (1.1) to the distorted current and voltage waveforms of Eqs. (1.3) and (1.4), PF may be expressed as
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(1.5) where, Vsn,rms and Isn,rms are the rms values of the nth harmonic voltage and current, respectively, and n is the phase shift between the nth harmonic voltage and current. Since most of power electronic systems draw their input voltage from a stable line voltage source Vs (t), the above expression can be significantly simplified by assuming the line voltage is pure sinusoidal and distortion is only limited to is (t), i.e. Vs(t) = Vs sint (1.6) is(t) = distorted (non-sinusoidal) (1.7)

1.1.2.1. Power Factor:

Then it can be shown that the PF can be expressed as

(1.8) where, 1: the phase angle between the voltage vs (t) and the fundamental component of is (t); Is1,rms : rms value of the fundamental component in line current; Is,rms : total rms value of line current; kdist = Is1,rms /Is,rms : distortion factor; kdisp = cos 1: displacement factor.

1.1.3. IEEE STANDARD

The IEEE Standard 519-1992, entitled IEEE Recommended Practices and Requirements for Harmonics Control in Electrical Power Systems, Section 6.6 specifically addresses the issue of harmonics on electronic equipment: Power electronic equipment is susceptible to misoperation caused by harmonic distortion. This equipment is often dependent upon accurate determination of voltage zero crossings or other aspects of the voltage wave shape.

Harmonic distortion can result in a shifting of the voltage zero crossing or the point at which one phase-to-phase voltage becomes greater than another phase to- phase voltage. Other types of electronic equipment can be affected by transmission of ac supply harmonics through the equipment power supply or by magnetic coupling of harmonics into equipment components. Computers and allied equipment such as programmable controllers frequently require ac sources that have no more than a 5% harmonic voltage distortion factor, with the largest single harmonic being no more than 3% of the fundamental voltage.

1.1.3.1. IEEE 519 Application Considerations

In applying the recommendations of IEEE 519-1992, some of the more important concerns addressed in this standards include the following: Selecting the point-of-common-coupling. Measurement methods, problems, limitations. Calculation and simulation methods. Assumptions for harmonic studies (background harmonic levels, system impedance characteristics) Impacts experienced due to harmonic distortion (Effects of harmonics). Calculating impacts). the customer demand current (changing load Characteristic, energy conservation impacts, power factor correction

 Power factor correction considerations (evaluating limits, resonance concerns, measurement flows). Effect of unbalanced harmonic generation. Evaluating the time-varying characteristics of harmonics Evaluating non-integer harmonic components (cycloconverters, arc furnaces). Application of multi-pulse systems. Applying limits for small customers and in cases with large numbers of harmonic generating customers (e.g. residential). Cost of Solutions 1.2. SWITCHING TECHNIQUES 1.2.1 SOFT AND HARD SWITCHING Semiconductors utilized in Static Power Converters operate in the switching mode to maximize efficiency. Switching frequencies vary from 50 Hz in a SCR based AC-DC Phase Angle Controller to over 1.0 MHz in a MOSFET based power supply. The switching or dynamic behavior of Power Semiconductor devices thus attracts attention specially for the faster ones for a number of reasons: optimum drive, power dissipation, EMI/RFI issues and switching-aid-networks. With SCRs 'forced commutation' and 'natural (line) commutation' usually described the type of switching. Both refer to the turn-off mechanism of the SCR, the turn-on dynamics being inconsequential for most purposes. A protective inductive snubber to limit the turn-on di/dt is
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considerations, direction of harmonic

usually utilized. For the SCRs the turn-off data helps to dimension the 'commutation components' or to set the 'margin angle'. Conduction losses account for the most significant part of total losses. Present day fast converters operate at much higher switching frequencies chiefly to reduce weight and size of the filter components. As a consequence, switching losses now tend to predominate, causing the junction temperatures to rise. Special techniques are employed to obtain clean turn-on and turn-off of the devices. This, along with optimal control strategies and improved evacuation of the heat generated, permit utilization of the devices with a minimum of duration. 1.2.1.1. SOFT SWITCHING Hard switching and its consequences have been discussed above. Reduction of size and weight of converter systems require higher operating frequencies, which would reduce sizes of inductors and capacitors. However, stresses on devices are heavily influenced by the switching frequencies accompanied by their switching losses. It is obvious that switching-aid-networks do not mitigate the dissipation issues to a great extent. Turn-on snubbers though not discussed, are rarely used. Even if used, it would not be able to prevent the energy stored in the junction capacitance to discharge into the transistor at each turn-on. Soft switching techniques use resonant techniques to switch ON at zero voltage and to switch OFF at zero current. There are negligible switching losses in the devices, though there is a significant rise in conduction losses. There is no transfer of dissipation to the resonant network which is non-dissipative. The two basic configurations are as shown in Fig 1.2.
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Fig(1.2) Basic control topologies for (a) Hard switch (b)ZVS (c)ZCS

Fig(1.3) Comparison between hard and soft switching with and without switching aid network The switching trajectory in the voltage-current plane of a device is illustrated in Fig. 1.3 comparing the paths for that of a Hard-switched operation without any SAN, a Hard-switched with a R-C-D Switching-AidNetwork(SAN) and a resonant converter. It is indicative of the stresses and losses. A designer would prefer the path to be as close as possible to the origin. 1.2.2. LOSSES IN POWER SEMICONDUCTORS
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A converter consists of a few controlled and a few uncontrolled devices (diodes). While the first device is driven to turn-on or off, the uncontrolled device operates mainly as a slave to the former. Power loss in the converter is the aggregate of these losses. Occasionally the diode and the controlled device are housed in the same module. The losses corresponding to each contribute to the temperature rise of the integrated module.

Fig(1.4)flow chart for losses in system 1.2.2.1. Conduction Losses Conduction losses are caused by the forward voltage drop when the power semiconductor is on and can be described by (with reference to an IGBT) WC = Vce (sat)(Ic).Ic (2.1)
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where Ic is the current carried by the device and Vce(sat)(Ic) is the current dependant forward voltage drop. This drop may be expressed as Vce (sat) (Ic) = V0 + R . Ic (2.2) This relation defines the forward drop of an IGBT in a similar manner to a diode. A part of the drop is constant while another part is collector current dependent. The given data should be used as follows: Using the numerical value is the simplest way to determine conduction losses. The numerical value can be applied if the current in the device is equal or close to the specified current - data sheet numerical values are specified for typical application currents. The graph most accurately determines conduction losses. The conditions in which the data are used should correspond to the application. To estimate if a power semiconductor rating is appropriate, usually the values valid for elevated temperature, close to the maximum junction temperature TJmax , should be used to calculate power losses because this is commonly the operating point at nominal load. 1.2.2.2 Switching Losses IGBTs are designed for use in switching converters and not for linear operation. This means switching time intervals are short compared to the pulse duration at typical switching frequencies, as can be seen from their switching times, such as rise time tr and fall time tf in the data sheets. Switching losses occur during these switching intervals.
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For IGBTs they are specified as an amount of energy, E on/off for a certain switching operation. Eon/off are the energy dissipated at turn-on/turnoff respectively. Using the numerical value is again the simplest way to determine switching losses

Fig(1.5) Switching losses (approx) The numerical value can be applied if the switching operations are carried out at the same or similar conditions as indicated in the data sheet. Graphs for Eon(IC)/(RG ), Eoff (IC)/(RG) with collector current IC and gate resistance RG are provided. The graphs permit the most accurate determination of switching losses, given the parameters of the converter: RG and converter current IC. 1.2.3 CONTROL STRATEGIES In all cases, it is shown that the average value of the output voltage can be varied. The two types of control strategies (schemes) are employed in all cases. These are: (a) Time-ratio control, and (b) Current limit control. 1.2.3.1. Time-ratio Control

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In the time ratio control the value of the duty ratio, k = TON/T is varied. There are two ways, which are constant frequency operation, and variable frequency operation. 1.2.3.2. Constant Frequency Operation In this control strategy, the ON time, TON is varied, keeping the frequency ( f = 1/T ), or time period T constant. This is also called as Pulse width modulation control (PWM). Two cases with duty ratios, k as (a) 0.25 (25%), and (b) 0.75 (75%) are shown in Fig.1.5. Hence, the output voltage can be varied by varying ON time, TON .

Fig(1.6) Pulse width modulation control (constant frequency) 1.2.3.3. Variable Frequency Operation

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In this control strategy, the frequency (f = 1/T), or time period T is varied, keeping either (a) the ON time TON, constant, or (b) the OFF time T OFF, constant. This is also called as frequency modulation control. Two cases with (a) the ON time TON constant, and (b) the OFF time T OFF constant, with variable frequency or time period (T), are shown in Fig.1.6. The output voltage can be varied in both cases, with the change in duty ratio, k= TON/T

Fig(1.7) Output voltage waveforms for variable frequency system There are major disadvantages in this control strategy. These are:

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(a) The frequency has to be varied over a wide range for the control of output voltage in frequency modulation. Filter design for such wide frequency variation is, therefore, quite difficult. (b) For the control of a duty ratio, frequency variation would be wide. As such, there is a possibly of interference with systems using certain frequencies, such as signaling and telephone line, in frequency modulation technique. (c) The large OFF time in frequency modulation technique, may make the load current discontinuous, which is undesirable. Thus, the constant frequency system using PWM is the preferred scheme for dc-dc converters (choppers). 1.2.3.4. Current Limit Control As can be observed from the current waveforms for the types of dc-dc converters described earlier, the current changes between the maximum and minimum values, if it (current) is continuous. In the current limit control strategy, the switch in dc-dc converter (chopper) is turned ON and OFF, so that the current is maintained between two (upper and lower) limits. When the current exceed upper (maximum) limit, the switch is turned OFF. During OFF period, the current freewheels in say, buck converter (dc-dc) through the diode, DF, and decreases exponentially. When it reaches lower (minimum) limit, the switch is turned ON. This type of control is possible, either with constant frequency, or constant ON time, T ON. This is used only, when the load has energy storage elements, i.e. inductance, L. The reference values are load current or load voltage.

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Fig(1.8) Current limit control

This is shown in Fig.1.7. In this case, the current is continuous, varying between Imax and Imin, which decides the frequency used for switching. The ripple in the load current can be reduced, if the difference between the upper and lower limits is reduced, thereby making it minimum. This in turn increases the frequency, thereby increasing the switching losses.

1.3. PIC MICRO CONTROLLER 1.3.1. INTRODUCTION

The micro-controller that has been used for this project is from PIC series. PIC micro-controller is the first RISC based micro-controller fabricated in CMOS (complementary metal oxide semiconductor) that used separate bus for instruction and data allowing simultaneous access of program and data memory. The main advantage of CMOS and RISC combination is low power consumption resulting in a very small chip size with a small pin count. The main advantage of CMOS is that it has immunity to noise than other fabrication techniques.
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Various micro-controller

offer different

kinds of

memories.

EEPROM, EPROM, FLASH etc. are some of the memories of which FLASH is the most recently developed. Technology that is used in pic16F877 is flash technology, so that data is retained even when the power is switched off. Easy programming and Erasing are other features of PIC 16F877.

1.3.2. CORE FEATURES

High-performance RISC CPU Only 35 single word instructions to learn All single cycle instruction except for program branches which Operating speed: i. DC - 20 MHz clock input ii. DC 200 ns instruction cycle Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM data memory Pin out compatible to the PIC16C73/74/76/77 Interrupt capability (up to 14 internal/external) Eight level deep hardware stack Direct, indirect, and relative addressing modes Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) power-on Reset (POR) Watchdog Timer (WDT) with its own on-chip RC Oscillator for
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are two cycle

reliable operation

Programmable code-protection Power saving SLEEP mode Selectable oscillator options Low-power, high-speed CMOS EPROM/EEPROM technology Fully static design In-Circuit Serial Programming (ICSP) via two pins Only single 5V source needed for programming capability In-Circuit Debugging via two pins Processor read/write access to program memory Wide operating voltage range: 2.5V to 5.5V High Sink/Source Current: 25mA Commercial and Industrial temperature ranges Low-power consumption i. <2mA typical at 5V, 4 MHz ii. 20mAtypical at 3V, 32 kHz iii. <1mA typical standby current

1.3.3. TABLE SPECIFICATION

DEVICE PIC 16F877 PROGRAM FLASH DATA MEMORY 8K 368 Bytes DATA EEPROM 256 Bytes

Table(1.1) PIC specification

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Fig(1.9) PIN DIAGRAM OF PIC 16F877

1.3.4. PIN OUT DESCRIPTION

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23

_____________________________________________________________ _________ Table (1.2) Pin out description

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Legend:

I = input O = output I/O = input/output p = power = Not used TTL = TTL input ST = Schmitt Trigger input

NOTE: The buffer is a Schmitt Trigger input when configured as an This buffer is a Schmitt Trigger input when used in serial external interrupt.

programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port Mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a

1.3.5. I/O PORTS:

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional Information on I/O ports may be found in the IC micro Mid-Range Reference Manual. 1.3.5.1. Port A and TRISA register PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a Hi-impedance mode. Clearing a TRISA bit (=0) will make corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin.
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1.3.5.2. PORTB and TRISB register PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin. Three pin of PORTB are multiplexed with the Low Voltage Programming function. RB3/PGM, RB6/PGC and RB7/PGD. The alternate functions of these pins are described in the Special Features Section. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-up. This is performed be clearing bit RBPU (OPTION_REG<7>). The weak pull-ups are disabled on a Power-on Reset. 1.3.5.3. PORT D and TRISD register This section is not applicable to the 28-pin devices. PORTD is an8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide microprocessor Port (Parallel Slave Port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. 1.3.6. MEMORY ORGANIZAION: There are three memory blocks in each of the PIC16F877 MUC'S. The program memory and Data Memory have separate buses so that concurrent access can occur.

1.3.6.1. Program memory organization

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The PIC16f877 devices have a 13-bit program counter capable of addressing 8k *14 words of FLASH program memory. Accessing a location above the physically implemented address will cause a wraparound. 1.3.6.2. Data memory organization: The data memory is partitioned into multiple banks which contains the General Purpose Register and the special functions Registers. Bits RPI (STATUS<6) and RP0 (STATUS<5>) are the bank selected bits. RP1 : RP0 00 01 10 11 Banks 0 1 2 3

Each bank extends up to 7Fh (1238 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers is General Purpose Register, implemented as static RAM. All implemented banks contain special function registers. Some frequently used special function registers from one bank may be mirrored in another bank for code reduction and quicker access.

1.3.7. EEPROM
EEPROM (electrically erasable, programmable read only memory) technology supplies Non volatile storage of variable to a PIC-controlled device or instrument. That is variables stored in an EEPROM will remain there even after power has been turned off and then on again. Some instruments use an EEPROM to store calibration data during manufacture. In this way, each instrument is actually custom built, with customization that can be easily automated. Other instruments use and EEPROM to allow a user to store
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several sets of setup information. For an instrument requiring a complicated setup procedure, this permits a user to retrieve the setup required for any one of several very different measurements. Still other devices use an EEPROM in a way that is transparent. To a user, providing backup of setup parameters and thereby bridging over power outages The data EEPROM and flash program memory are readable and writable during normal operation over the entire VDD range. A bulk erase operation may not be issued from user code (which includes removing code-protection. The data memory is not directly mapped in the register file space. Instead it is indirectly addressed through the special function registers(SFR). There are six SFRS used to read and write the program and data EEPROM memory. These register are: EECON1 EECON2 EEDATA EEDATH EEADR EEADRH EEDATA holds the 8-bit data for read/write and EEADRR holds the address of the EEPROM location being accessed. The 8-bit EEADR register can access up to 256 locations of data EEPROM. The EEADR register can be thought of as the indirect addressing register of the data EEPROM. EEcon1 contains the control bits, while eecon2 is the register used to initiate the read/write. The EEPROM data memory allows bytes read and write. A byte
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write automatically erases the location and writes the new data. The write time is controlled by timer in-built. 1.3.8. ANALOG TO DIGITAL CONVERTER (ADC) There are two types of analog to digital converter is present in this IC. We use 10-bit ADC. The ADC module can have up to eight analog inputs for a device. The analog input charges a sample and hold capacitor. The output of sample and hold capacitor is the input into the converter. The converter than generates a digital result of this analog level via successive approximation. The A/D conversion of the analog input signal results in a Corresponding 10-bit digital number. The A/D module has high and low voltage reference input that is software selectable to some combination of VDD, VSS, and RA2 Or RA3. The A/D module has four registers. These registers are A/D result high register (ADRESH) A/D RESULT LOW REGISTER (ADRESL) A/D CONTROL REGISTER 0 (ADCON0) A/D CONTROL REGISTER 1 (ADCON1)

1.3.9. ADDRESSING MODES:

Direct addressing: In addressing, the operand specified by an 8-bit address field in the instruction. Only internal data RAM and SRF's can directly addressed. Indirect addressing: In direct addressing, the instruction specifies a register that contains the address of the operand. Both internal and external RAM can indirectly address.

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The address register for 8-bit addresses can be either the Stack Pointer or R0 or R1 of the selected register bank. The address register for 16-bit addresses can be only the 16-bit data pointer register, DPTR. Indexed addressing Program memory can only be accessed via indexed addressing this addressing mode is intended for reading look-up tables in program memory. A 16 bit register (Either DPTR or the Program Counter) points to the base of the table, and the accumulator is set up with the table entry number. Adding the accumulator data to the base pointer forms the address of the table entry in program memory. Another type of indexed addressing is used in the case jumpinstructions. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data.

1.3.10. APPLICATIONS OF MICRO-CONTROLLERS

Microcontrollers are designed for use in sophisticated real time applications such as 1. Industrial Control 2. Instrumentation and 3. intelligent computer peripherals They are used in industrial applications to controlled Motor Robotics Discrete and Continuous process control In medical instrumentation Telecommunication Automobiles
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1.4. PROGRAM FOR MICROCONTROLLER

#include <16F877A.h> #fuses XT,PROTECT oscillator,code protection enable #use delay(clock=4M) void main(void) { set_tris_b(0); while(true) { output_high(pin_b0); delay_us(100); output_low(pin_b1); delay_us(9900); output_high(pin_b1); delay_us(100); output_low(pin_b0); delay_us(9900); } } //B0 low //B1 high //B1 low //B0 high //port b as output //osc freq = 4 MHZ //pic reg & add //low freq crystal

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