VK3266

UART/SPI/8-bit parallel interface, Wide voltage 2.5V-5.5V 16-stage FIFO, 4-channel UART expansion UART
ByS.Lopez

VK3266 more four-channel universal asynchronous bus interface transceiver

1. Product Overview
VK3266 is the industry's first UART/SPI/8 bit parallel bus interface with 4-channel UART devices. Mode selection can be made by the chip works in any of a host interface mode: When the primary interface for the UART when, VK3266 a standard 3-wire asynchronous serial port (UART) expanded into four enhancements to the serial port (UART). UART data transfer in the main interface can select no escape character and escape character mode. In addition, the primary interface of the UART Pin can be configured through the infrared communication mode. When the primary interface for the SPI interface, VK3266 achieve SPI bridge / extension 4 enhancements serial (UART) function. When the primary interface for the 8-bit parallel port, VK3266 achieve an 8-bit parallel data bus and 4-channel UART serial bus data communication with each other Conversion function. Extended sub-channel UART has the following features: Each sub-channel UART baud rate, word length, parity format can be set independently to provide maximum communication speed 1Mbps. Sub-channel can be independently set for each work in the IrDA infrared communication, RS-485 automatic send and receive control, nine network address automatically identify, Software / hardware auto flow control, radio receivers and other advanced operating mode. With each sub-channel transmit / receive separate 16 BYTE FIFO, FIFO interrupt conditions for the 4-programmable trigger. A sub-channel modem (MODEM) control signal. VK3266 QFP44 green with lead-free package and can operate at 2.5 ~ 5.5V wide operating voltage range, with configurable Automatic sleep / wake function.

[Note]: SPI to MOTOLORA registered trademark.

2. Basic characteristics
2.1 General features

Support a variety of host interface: You can choose UART, SPI or 8-bit parallel port Low-power design, you can configure automatic sleep, automatic wake-up mode (uS-level wake-up) Wide working voltage design, the working voltage is 2.5V ~ 5.5V Streamlined configuration registers and control words, simple and reliable Programmable data broadcast model of innovation support sent to any subchannel data broadcast Provide industrial and commercial-grade products High-speed CMOS technology Consistent with environmental protection policies adopted lead-free package QFP44

2.2 Characteristics of extended sub-channel UART

Independent sub-channel serial port configuration, high-speed, flexible: Each child is full-duplex serial port, serial port for each child by software on / off Baud rate can be set independently, the child can reach 920K bps serial highest Serial character format for each child, including data length, stop bits, parity mode can be set independently Software serial port can be set for each child to receive data broadcast as to whether Improve the function of the sub-port status query FIFO functions: Each child has a separate serial port 16 9Bits send FIFO, transmit FIFO trigger points with four programmable serial port with each child's 16 independent receiving FIFO, Receive FIFO trigger points with four programmable Software to enable and clear the FIFO FIFO status and the counter output Flow Control: Support for RTS, CTS hardware flow control automatically Support XON / XOFF software flow control automatically, XON / XOFF character programmable automatic send / Recognition RS-485 features: RTS control automatically controls RS-485 Transceiver RS-485 network automatic address recognition Error detection: Support parity error, frame error and overrun error detection Support start-bit error detection Software serial port can be set for each child to receive data broadcast as to whether Built-in line with standard IrDA Infrared Transceiver SIR codec, the transmission speed of up to 115.2K bit / s

2.3 UART Host Interface features

The main interface is a standard three-wire UART serial port (RX, TX, GND), no other address signal, control signal line Programmable baud rate, the maximum speed of up to 1M bit / s Choose the odd parity, even parity and no parity mode Do not need to address the industry's first line of serial controlled expansion mode, through the processor chip multi-protocol serial port expansion UART host interface pins can be set to IR mode UART host interface pins can choose whether to use the escape character mode

2.4 SPI master interface features Maximum speed of 5M bit / s SPI Slave mode only supports 16-bit, SPI Mode 0

2.5 8-bit parallel Host Interface features Standard 8-bit MCU Bus Interface 8-bit command and address bus, data sharing, through A0 (data / control) to switch signal Sub-channel selection control and direction through the command word, no additional channel indication signal line Address space occupies only 2

3. Applications
Multiport Serial Server / Multiport Serial Cards Industrial / Automation Control RS-485 field Through CDMA / GPRS MODEM wireless data transmission Vehicle information platform / Car GPS positioning system Remote automatic meter reading (AMR) System POS / tax control POS / financial machinery DSP / embedded systems

4.Ordering information
Ordering Information Table 4.1 VK3266 Model VK3266-EQPG VK3266-IQPG VK3266-CQPG Package QFP44 QFP44 QFP44 Description lead-free package; working temperature -45 ~ +85 lead-free package; working temperature -45 ~ +85 lead-free package; Operating temperature 0 ~ +70

5. Block Diagram
5.1 Block diagram VK3266

6. Package Pin
6.1 Package

6.2 Pin description

Name

Pin

Type

M1 M2 IR/ SCS/ CS

1 2 3

I I I

MRX/ SCLK/ WR

TR/ SDIN/ RD

MTX/ SDOUT/ A0

D7-D0

7-14

I/O

RTS1 RTS2 RTS3 RTS4

34 25 36 15

CTS1

31

Description Host Interface Mode Select Signal: M1 M0 = 00 SPI interface; M1 M0 = 11 UART interface; M1 M0 = 01 8 bit parallel bus; M1 M0-chip pull-down circuit, left vacant when the M1 M0 = 00; When the primary interface for the UART, in order to IR (infrared communications port master mode) function pin: IR = 1 IR communication mode; IR = 0 normal UART communication mode; When the primary interface for the SPI, in order to SCS (SPI chip select) pin functions: active low When the primary interface for the 8-bit parallel port, in order to CS (chip select) pin functions: active low When the primary interface for the UART, in order to MRX (the main port UART receive) function pin; When the primary interface for the SPI, in order to SCLK (SPI clock input) function pin; When the primary interface for the 8-bit parallel port, in order to WR (write signal) function pin: Active low When the primary interface for the UART, in order to TR (an escape character transmission) function pin: TR = 1 choose the escape character serial port expansion mode; TR = 0 select no escape character in the serial port expansion mode; When the primary interface for the SPI, in order to SDIN (SPI data input) pin functions; When the primary interface for the 8-bit parallel port for the RD (read signal) function pin, active low When the primary interface for the UART, in order to MTX (the main port UART transmit) function pin; When the primary interface for the SPI, in order to SDOUT (SPI data output) function pin; When the primary interface for the 8-bit parallel port, in order to A0 (data address selection) function pin; Write register address A0 = 0 Write register data A0 = 1 When the primary interface for the 8-bit parallel port, in order to have a 3-state output of the 8-bit data lines. Used to achieve the VK3266 and CPU Between the data, two-way control and status information transmission. When the primary interface for the SPI or UART, the data bus is high impedance. Serial Port 1 to 4 sub-request to send signal (Request To Send), active low. When RTSx = 0, it indicates that the corresponding sub-serial VK3266 is ready to receive the request and its associated The MODEM or data UART to send data. RTS serial port status register through the sub-set. When the sub-port of work in automatic mode, flow control, RTS logic control with automatic flow control Control data transceiver. When a child work in the RS-485 serial port automatically send and receive mode, this pin is used to control RS-485 data Automatically send and receive conversion. 1 to 4 sub-serial clear to send signal (Clear To Send), active low. When CTSx = 0, the MODEM or data that UART is ready to

CTS2 CTS3 CTS4

22 35 18

RX1 RX2 RX3 RX4 TX1 TX2 TX3 TX4 RST IRQ VCC GND CSCI CSCO

33 24 37 16 32 23 36 17 19 21 20 39 28 44 43 42

receive the corresponding substring VK3266 Port to send data. You can read the sub-port status register read the corresponding state of CTS. When the sub-port flow control work in the auto mode, CTS flow control logic through the automatic control System control data transceiver. Sub-channel serial port serial data input. Connected to the UART RX serial data input of data corresponding pin VK3266. Sub-channel serial port serial data output. TX data output to the serial device connected to pins.

I O I O I I I I O I

Hardware reset pin, low-level reset effectively Interrupt output signal, active low. Recommended external pull-up resistor, the typical value of 5.1K Power Supply 2.5V ~ 5.5V operating range GND Crystal input; when CLKSEL = 0, the external crystal is connected to the pin and the OSCO pin to form a crystal Oscillation circuit. Crystal output; when CLKSEL = 0, the external crystal is connected to the OSCI pin pin and form a crystal Oscillation circuit. Clock options: CLKSEL = 0, select the crystal clock (default) CLKSEL = 1, select from the CLKIN pin of the clock as chip clock External clock input pin, when using the crystal, the pins need to take a fixed level Carrier Detect (active low). DCD = 0 to indicate the modem detects the carrier signal. Data Set Ready (active low). DSR = 0 for instructions or data device is a modem The power and ready for data exchange with the UART. Data Terminal Ready (active low). DTR = 0, it indicates that VK3266 has the power and ready. This pin can be set through the control register. Ring Indicator (active low). RI = 0 indicates the modem to the telephone line to receive the letter rings Number. The logic of 1 input pin will generate an interrupt transition.

CLKSEL 41 CLKIN DCD/ GPIO0 DSR/ GPIO1 DTR/ GPIO2 RI/ GPIO3 40 30 29 26 27

7. Register Description
7.1 Register list VK3266 number by address register 6 bit address code, address, 000000 ~ 111111, and sub-divided into the global register serial register. 2 of them for the channel number of high and low 4 bits of register address number. Global register 6, the address of global register XX0000-XX0101, XX is an arbitrary value (taking into account the compatibility of the device upgrade, Proposal to set XX = 00), low-order 4-bit address specific Table 8.1:

Table 7.1 lists the global register

Register address [3:0] Register Name Type Register functional description

(XX) 0000 (XX) 0001 (XX) 0010 (XX) 0011 (XX) 0100 (XX) 0101

RSV GCR GMUCR GIR GXOFF GXON

NO R/W R/W R/W R/W R/W

Reserve Global control register Global master serial control register Global Interrupt Register Global XOFF characters register Global XON character Register

Sub-serial register 10, the arrangement for the C1C0 REG [3:0], the high two serial channel number for the child, the lower 4 bits for the register address, press the lower 4-bit register address the specific arrangement shown in Table 8.2:

Table 7.2 lists sub-serial register

Register address [3:0] Register Name Type Description

(C1,C0) 0110 (C1,C0) 0111 (C1,C0) 1000 (C1,C0) 1001 (C1,C0) 1010

Sub Serial control register Sub serial configuration register Sub serial flow control register FIFO control register sub-serial Automatic identification of sub-port address register (C1,C0) 1011 SIER R/W Sub serial port interrupt enable register (C1,C0) 1100 SIFR R Sub serial port interrupt flag register (C1,C0) 1101 SSR R Sub serial status register (C1,C0) 1110 SFSR R/W Sub-serial FIFO status register (C1,C0) 1111 SFDR R/W Sub-serial FIFO data register C1, C0: sub-channel number, 00 to 11 correspond to sub-sub serial port 1 to 4 7.2 Register Description 7.2.1 GCR global control register: (0001)
Bit Reset Value Functional Description Type

SCTLR SCONR SFWCR SFOCR SADR

R/W R/W R/W R/W R/W

Bit7

Bit6

Bit5 Bit4 Bit3 Bit2 Bit1

0 0 0 0 0

GBDEN global broadcast enable bit 0: Disable data broadcasting 1: enable data broadcasting IDEL software IDEL Enable bit 0: Wake-up work 1: Go to IDEL mode DCDF flag carrier DCD pin state DSRF Data Ready flag DSR pin status DTRC Data Terminal Ready DTR pin control bits RIF ring instructions RI pin state MINT MODEM signal interrupt flag 0: No interrupt flag MODEM 1: MODEM interrupt flag (In the case of EMINT enabled, DCD, DSR, RI change in

W/R

W/R

R R W/R R R

Bit0

the state will generate the interrupt) ENMINT MINT interrupt enable control bit 0: Disable interrupt MINT 1: Enable interrupt MINT

W/R

7.2.2 GMUCR global master serial control register: (0010) Bit Bit74 ResetValue 0011 FunctionalDescription Themainserialportbaudrate,thespecificsettingsin Table8.9.1(Bit74correspondingtoB3B0) PAENmainUARTparitysetting(datalengthsettingbits) 0:8bitdata(withnoparitybit) 1:9bitdata(with9checkdigit) STPLStopbitlengthsettingbit Stopbits0:1 Stopbits1:2 PAM10paritymodeselection 00:Force0Check01:oddparity 10:evenparity11:Force1check Type W/R

Bit3

W/R

Bit2

W/R

Bit10

00

W/R

7.2.3 GIR Global Interrupt register: (0011) Bit Bit7 ResetValue 0 FunctionalDescription U4IENsubSerial4interruptenablecontrolbit 0:Disableinterruptsubserialport4 1:Enableinterruptsubport4 U3IENsubSerial3interruptenablecontrolbit 0:Disableinterruptsubserialport3 1:Enableinterruptsubport3 U2IENsubSerial2interruptenablecontrolbit 0:Disableinterruptsubserialport2 1:Enableinterruptsubport2 U1IENsubSerial1interruptenablecontrolbit 0:Disableinterruptsubserialport1 1:Enableinterruptsubport1 U4IFsubserialinterruptflagbit4 0:NointerruptsubSerial4 1:Subserialport4withinterrupt U3IFsubserialinterruptflagbit3 0:NointerruptsubSerial3 Type W/R

Bit6

W/R

Bit5

W/R

Bit4

W/R

Bit3

Bit2

1:Subserialport3withinterrupt Bit1 0 U2IFsubserialinterruptflagbit2 0:NointerruptsubSerial2 1:Subserialport2withinterrupt U1IFsubserialinterruptflagbit1 0:NointerruptsubSerial1 1:Subserialport1withinterrupt R

Bit0

7.2.4 GXOFF global XOFF character register: (0100) Bit Bit70 7.2.5 GXON global XON character register: (0101) Bit Bit70 ResetValue 00000000 FunctionalDescription XONspecialcharactersRegister Type W/R ResetValue 00000000 FunctionalDescription XOFFspecialcharactersRegister Type W/R

7.2.6 SCTLR child serial control register: (0110) Bit Bit74 ResetValue 0011 FunctionalDescription Type

Subsetserialportbaudrate,thespecificsettingsinTable W/R 8.9.1(Bit74correspondB3B0) UTENenablecontrolbitsubserial 0:notenabled,thenthesubtransceiverserialportfor datachannelcannot 1:enable,enablethechildafteranormalserialportcan sendandreceivedata MDSEL485and232modeselectioncontrolbit 0:RS232transceivermode 1:RS485automaticsendandreceivemode,thismode, RTSautomaticallysendandreceivecontrolsignalsas No. RBDENcontrolbitsallowedtoreceivebroadcastdata 1:Allowchildrentoreceivebroadcastdataport 0:Prohibitionofchildserialporttoreceivebroadcast data IRENInfraredModeSelectbits W/R

Bit3

Bit2

W/R

Bit1

W/R

Bit0

W/R

0:standardserialportmode 1:InfraredDataModel

7.2.7 SCONR sub serial port configuration register: (0111) Bit Bit7 ResetValue 0 FunctionalDescription
SSTPL child serial control bits Stop bit length Stop bits 0:1 Stop bits 1:2 SPAEN child serial check enabled (the number of 0: No parity bit (8-bit data) 1: parity bit (9-bit data) SFPAEN mandatory verification sub-serial 0: do not force the calibration sub-serial 1: Enable force validity of sub-serial PAM1-0 Parity mode selection: When SFPAEN = 1 sub-serial mandatory verification is enabled: 00: Compulsory 0 check; 01,10: force users to verify; 11: Force 1 check When SFPAEN = 0, sub-normal calibration mode the serial port: 00:0 verification; 01: Odd parity; 10: even parity; 11:1 check

Type W/R

Bit6

W/R

Bit5

W/R

Bit43

00

W/R

Bit2

Bit1

AOD sub-serial address / data mode selection bit (when operating in RS485 mode) 0: Allow all data bytes received 1: only allowed to receive the address byte AREN automatically identify the network address control bits 0: Disable automatic identification of network address 1: Allow automatic identification of network address See the detailed operation RS-485 mode of operation described

W/R

W/R

Bit0

AVEN control bit network address can be seen 0: Disable Network Address can be seen, the network address is not written to FIFO 1: Enable network address can be seen, the network address of write FIFO

W/R

7.2.8 SFWCR child serial flow control register: (1000) Bit Bit76 ResetValue 00 FunctionalDescription
HRTL1-0 trigger control sends pause (RS232 mode): 00 = 3bytes 01 = 7bytes 10 = 11bytes 11 = 15bytes In the flow control enabled condition, when the receiver FIFO of the data added to the trigger point, Start the appropriate software / hardware flow control, control channel connected to the device to pause data transmission. PRTL1-0 to send the trigger point control (RS232 mode): 00 = 1bytes 01 = 4bytes 10 = 8bytes 11 = 12bytes In the flow control enabled condition, when the receiver FIFO data down to the trigger point, Software / hardware flow control mechanisms, control devices connected to the channel to send data. FWCEN flow control enable control bit (RS232 mode): 0: Disable automatic flow control sub-serial 1: Allow automatic flow control sub-serial FWCM flow control mode (when the flow control when enabled): 0: automatic software flow control sub-serial 1: Child serial automatic hardware flow control AOMH hardware flow control options (when hardware flow control when enabled): 0: automatic hardware flow control 1: Manual Flow Control XVEN XON / XOFF visibility settings: 0: XON / XOFF characters are not visible 1: XON / XOFF characters to write FIFO, the host side can be seen XOFF

Type W/R

Bit54

00

W/R

Bit3

W/R

Bit2

W/R

Bit1

W/R

Bit0

W/R

7.2.9 SFOCR sub-serial FIFO control register: (1001) Bit Bit76 ResetValue 00 FunctionalDescription
TFTL1-0 transmit FIFO contact control: 00 = 0bytes 01 = 4bytes 10 = 8bytes 11 = 12bytes When the receiver FIFO data to the trigger point reduction, suggesting that the host can continue to write data to the transmit FIFO.

Type W/R

Bit54

00

RFTL1-0 Receive FIFO contact control: 00 = 1bytes 01 = 4bytes 10 = 8bytes 11 = 14bytes When the receiver FIFO, the data added to the trigger point, suggesting that the host interface to read data from the receiver FIFO. TFEN transmit FIFO enable control bit 0: disable sending FIFO, do not write data to be transmitted to send FIFO, directly into the transmit shift register 1: enable sending FIFO, write data to be transmitted to send FIFO, sent through the FIFO RFEN Receive FIFO Enable 0: Disable Receive FIFO, the received data is not written into the receive FIFO 1: Enable Receive FIFO, the received data is written to receive FIFO TFCL transmit FIFO Clear 0: TX FIFO is not cleared 1: Clear all the data sent in the TX FIFO RFCL Clear Receive FIFO 0: Receive FIFO data is not clear 1: Clear all the data receiving FIFO

W/R

Bit3

W/R

Bit2

W/R

Bit1 Bit0

0 0

W/R W/R

7.2.10 SADR automatic identification of sub-port address register: (1010) Bit Bit70 ResetValue 00000000 FunctionalDescription Automaticidentificationofsubnetworkaddressport register.(RS485mode) Type W/R

7.2.11 SIER sub serial port interrupt enable register: (1011) Bit Bit7 ResetValue 0 FunctionalDescription RXBYRX_BUSYstatusbit 0:ThechannelRXidle 1:ThechannelisreceivingdataRX FOEIENFIFOdataerrorinterruptenablebit: 0:DisableinterruptFIFOdataerror 1:EnableinterruptFIFOdataerrors RAIENReceiveinterruptenablebit: 0:DisableReceiverAddressinterruptsubserial 1:EnableReceiverAddressinterruptsubserial XFIENXOFFinterruptenablebit: 0:DisableinterruptXOFF 1:EnableXOFFinterrupt,whenthechildreceivestheserial Type W/R

Bit6

W/R

Bit5

W/R

Bit4

W/R

portinterruptwhenthespecialcharacterXOFF Bit3 0 RSTIENRTSinterrupt 0:DisableRTSinterrupt 1:EnableRTSinterrupt CTSIENCTSinterruptenablebit 0:DisableCTSinterrupt 1:EnableCTSinterrupt TRIENtransmitFIFOinterruptenablebitcontacts 0:disablesendingFIFOinterruptcontacts 1:EnablethetransmitFIFOinterruptcontacts RFIENtocontacttoreceiveFIFOinterrupt 0:DisableReceiveFIFOinterruptcontacts 1:EnableReceiveFIFOinterruptcontacts W/R

Bit2

W/R

Bit1

W/R

Bit0

W/R

7.2.12 SIFR sub serial port interrupt flag register: (1100) Bit Bit7 ResetValue 0 FunctionalDescription CTSRbitindicatesthestatusofCTS ThevalueofthecurrentCTSpin Type R

Bit6

FOEINTchildserialinterruptflagbitFIFOdataerrors W/R 0:NointerruptFIFOdataerror 1:FIFOdataerror(whentheFIFOdataerrorsgeneratedwhen theinterrupt) RAINTchildserialinterruptbitAutomaticAddressRecognition W/R 0:Nointerruptautomaticaddressrecognition 1:AutomaticAddressRecognitioninterrupt(whenthe receiveddatabyteandtheaddressmatchinterruptwith SDAR) XFINTXOFFinterruptflag 0:NoXOFFinterrupt 1:XOFFinterrupt RSTINTRTSinterruptflag 0:NoRTSinterrupt 1:RTSinterrupt CTSINTCTSinterruptflag 0:readtheregisterisclearedautomaticallyafter 1:CTSInterrupt TFINTsubserialportFIFO 0:NointerruptTFINT W/R

Bit5

Bit4

Bit3

W/R

Bit2

W/R

Bit1

W/R

1:InterruptTFINT Bit0 0 RFINTsubserialporttoreceiveFIFOinterruptflagcontact 0:NointerruptRFINT 1:InterruptRFINT W/R

7.2.13 SSR sub-port status register: (1101) Bit Bit7 ResetValue X FunctionalDescription OEsubserialporttoreceivethecurrentdataFIFO(firstwrite) Overflowerrorflag: 0:NoErrorOE 1:OEerrors FEinthecurrentsubserialporttoreceivedataFIFO(first write)theframeerrorflag: 0:NoerrorFE 1:FEerror PEinthecurrentsubserialporttoreceivedataFIFO(first write)theparityerrorflag 0:NoerrorPE 1:PEError RX8subserialporttoreceivethecurrentdataFIFO(first write)section9(Bit8)datavalues TFFLsubserialportFIFOFullFlag 0:childundertheageoftheserialtransmitFIFO 1:ChildserialportFIFOfull TFEMsubserialportFIFOemptyflag 0:subserialportFIFOemptybit 1:ChildserialportFIFOempty TXBYsubserialportTXbusyflag 0:emptychildserialportTX 1:TXbusysubserialport RFEMsubserialporttoreceiveFIFO 0:ReceiveFIFOisnotemptysubserial 1:ReceiveFIFOemptysubserial Type R

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

7.2.14 SFSR sub-Serial FIFO status register: (1110)

Bit Bit74

ResetValue 0000

FunctionalDescription TCNT30subserialnumbertosendthedatainthe FIFO RCNT30subserialnumbertoreceivethedatainthe FIFO

Type R

Bit30

0000

7.2.15: SFDR sub-serial FIFO data register: (1111) Bit Bit70 ResetValue xxxxxxxx FunctionalDescription Writes:writessubserialportdataFIFO Readoperation:readthesubserialdatareceiverFIFO Type W/R

8. Global Functional Description

8.1 Reset VK3266 low reset. Reset the value of the register listed in the table register, see 7.2. Reset during and after reset, the sub-transceiver serial port in the disabled state. When a child is in the serial interconnection mode, this feature allows Have the child where the child node in the serial port on the power, reset period will not interfere with other nodes in network. When the primary interface for the UART serial port, its default baud rate after reset in the shadow clipping part of the Table 8.6.1. 8.2 Clock Selection VK3266 can choose to use the crystal clock or an external clock as chip clock source. When CLKSEL connected high, the selection of an external clock source. When CLKSEL then low, the selected oscillator clock. CLKSEL internal pull-down, the default choice for the crystal clock. 8.3 Interrupt Control
VK3266 has two interrupt: sub-MODEM serial port and interrupt, the global interrupt. When the IRQ pin indicates an interrupt, the global interrupt register can be read through the current GIR to determine the type of interruption, and then to read the corresponding interrupt status register to determine the current interrupt source. VK3266 interrupt structure as shown below:

Figure 8.3 VK3266 interrupt structure VK3266 each child has a separate serial port interrupt system, including: FIFO data error interrupt, the interrupt receiving address (RS485 mode), XOFF transmit interrupts, RTS interrupt, CTS interrupt, transmit FIFO trigger interrupt, receive FIFO trigger interrupt. When any interrupt is enabled, the interrupt conditions meet the appropriate interrupt is generated. 8.3.1 FIFO data error interrupt FIFO data error interrupt indicates that the current receiver FIFO has one or more data errors, error conditions, including OE (data overrun errors), FE (data frame errors), and PE (parity error). Once there is an error to receive data FIFO, the interrupt will be generated until all the errors in the received data FIFO have been read, The break was only cleared. After the break clear that there is no error in the current received FIFO data. 8.3.2 Receive Interrupt Interrupt only when the work in the RS485 mode VK3266 generated. In RS232 mode the interrupt will not occur. In the automatic address recognition mode, the child receives its serial port set the same address byte addresses, resulting in the interruption. Until the corresponding interrupt register is read, the interrupt is cleared automatically. Address Recognition in the manual mode, once the address byte is received, will generate the interrupt. The corresponding interrupt register is read, the interrupt is cleared.

8.3.3 Send XOFF interrupt

Automatic flow control in software mode, when the data receiver is ready to send XOFF characters generated when the interrupt. XON character when it is ready to send when the characters interrupt is cleared. 8.3.4 RTS interrupt In automatic or manual mode, the hardware flow control, when the RTS signal from 0 to 1, can generate the interrupt. In the automatic hardware flow control mode, when receiving the data in the FIFO to reduce the number of set points to send the trigger, the interrupt is cleared. Manual hardware flow control mode, the RTS register will clear the interrupt write 0. 8.3.5 CTS interrupt CTS signal from 0 to 1, will generate the interrupt; CTS interrupt flag register when read will clear the interrupt. 8.3.6 Transmit FIFO trigger interrupt When sending the data in the FIFO is less than the set number of transmit FIFO trigger points, resulting in the interruption. When sending the data in the FIFO is greater than the number of transmit FIFO trigger point set, the interrupt is cleared. 8.3.7 Receive FIFO interrupt trigger When the receiver FIFO is greater than the number set in the transmit data FIFO trigger points, resulting in the interruption. When receiving the data in the FIFO is less than the number of transmit FIFO trigger point set, the interrupt is cleared. 8.4 Broadcast Mode Operation VK3266 supports sub-channel independently configurable serial data broadcast model. First, by setting the global register GCR in GBDEN bit, the main port of the global broadcast is set to Enable, and set the need to receive broadcast data corresponding subserial channel SCTLR the RDBEN bit, so the channel can receive data broadcasts. After setting, the main port of data sent to any channel can be set to enable the child to receive radio serial port to receive, without sub-set serial port to receive data broadcast data will be ignored. 8.5 Infrared mode operation VK3266 the main serial port and serial port can be set to sub-infrared communication mode. When VK3266 the UART is set to IrDA mode, you can meet the SIR infrared communication protocol with the standard device communication, or communication directly applied to optical isolator. In the IrDA mode, a data cycle time data to a common UART 3 / 16, less than 1 / 16 Porter cycle pulses will be ignored as interference.

8.5.1 IR receiver operating In the infrared data reception timing and the corresponding normal UART data reception as shown in Figure 8.5.1: IRX infrared data for the received signal, RX for the infrared data decoded by the data. Decoded data with the data on the IRX have a BIT

(16xCLOCK) delay. Receive mode is different from ordinary UART, RX in the middle of a sampling pulse (UART difference of 3 times with normal samples), IrDA decoder on the IRX 3 / 16 Porter cycle pulse decoding for data 0 Continued low decoding the data 1.

Figure 8.5.1 Timing infrared receiver

8.5.2 Infrared transmission operation Infrared data transmission and the corresponding normal UART data transmission as shown in Figure 8.5.2, TX UART data transmission timing for the general, IRTX for infrared transmission timing. When sending data 0, the infrared encoder will produce a 3 / 16 bit wide pulse sent through the TX. When sending data 0, to keep low the same.

Figure 8.5.2 Infrared transmission timing

8.6 Programmable baud rate generator VK3266 the main serial port and serial port using the same child independently programmable baud rate generator. The baud rate generator baud rate fixed 16X system clock, divided frequency can be set by software. The following table shows the system clock frequency in different serial port baud rate table: Table 8.6.1 BAUD Subfreq uenc y Baud Rate (MHz) Fosc= 1.8432 Baud Rate (MHz) Fosc= 3.6864 Baud Rate (MHz) Fosc= 7.3728 Baud Rate (MHz) Fosc= 11.0592 Baud Rate (MHz) Fosc= 14.7456

B3

B2 B1

B0

0 0 0 0 48 38400 76800 153600 230400 0 0 0 1 96 19200 38400 76800 115200 0 0 1 0 4 9600 19200 38400 57600 0 0 1 1 8 4800 9600 19200 28800 0 1 0 0 16 2400 4800 9600 14400 0 1 0 1 32 1200 2400 4800 7200 0 1 1 0 64 600 1200 2400 3600 0 1 1 1 128 300 600 1200 1800 1 0 0 0 3 115200 230400 460800 691200 1 0 0 1 6 57600 115200 230400 345600 1 0 1 0 12 28800 57600 115200 172800 1 0 1 1 24 14400 28800 57600 86400 1 1 0 0 48 7200 14400 28800 43200 1 1 0 1 96 3600 7200 14400 21600 1 1 1 0 192 1800 3600 7200 10800 1 1 1 1 384 900 1800 3600 5400 [Note] The table is set in the blue part of the initial value after reset VK3266. 8.7 Data Formatting 8.7.1 Model validation

307200 153600 76800 38400 19200 9600 4800 2400 921600 460800 230400 115200 57600 28800 14400 7200

VK3266 the UART to provide mandatory verification, calculate parity and no parity data format, through SCONT (sub serial port configuration registers) are set: Force validity of model 1 check VK3266 support strong, strong user-specified 0 checksum verification mode. In this mode, the calibration settings only affect the data transmission, data reception will ignore parity. In the RS-485 mode, the recommended mandatory verification mode, in this mode, you can easily distinguish between data and addresses. Compute the checksum mode VK3266 support a parity, 0 parity, odd parity, even parity mode. In this mode, the receive and transmit the data to calculate parity. 8.7.2 Data length VK3266 support 1 or 2 stop bit mode. 8.8 Sleep and automatic wake VK3266 support hibernation and automatic wake-up mode, the IDLE bit is written to the GCR 1, will go into sleep mode. In Sleep mode, VK3266 the system clock will be stopped to reduce power consumption. In Sleep mode, the child can be the main serial port and automatic wake-up: Once the SCS, CS, the main port MRX, child serial RX data is changed, VK3266 the system clock will be automatically wake up, into the normal delivery.

9.SPI Interface Mode Operation

9.1 SPI connection to the host:

SPI interface, as shown in Figure 3.2.1 include the following four signals: SDIN: SPI data input. SDOUT: SPI data output. SCLK: SPI serial clock. SCS: SPI Chip Select (Slave Select). VK3266 connection to the host as shown in Figure 9.1.

Figure 9.1 SPI host connection diagram

9.2 SPI Interface Timing VK3266 work in SPI slave synchronous serial communication mode, supports SPI Mode 0 standard. Host and VK3266 to achieve communication, the host side need to set CPOL = 0 (SPI clock polarity select bit), CPHA = 0 (SPI clock phase select bit.) VK3266 SPI interface operating sequence shown in Figure 9.2:

Figure 9.2 SPI Timing Diagram

9.3 SPI bus communication protocol description: 9.3.1.SPI write register SPI Bit DIN DOUT Control byte CMD
15 1
INT1

Data byte DB
11 A2
X

14 C1
INT2

13 C0
INT3

12 A3
INT4

10 A1
X

9 A0
X

8 D8t
X

7 D7t
TC3

6 D6t
TC2

5 D5t
TC1

4 D4t
TC0

3 D3t
RC3

2 D2t
RC2

1 D1t
RC1

0 D0t
RC0

9.3.2.SPI read register

SPI Bit DIN DOUT

Control byte CMD 15 14 13 12 11 10 9 8 0 C1 C0 A3 A2 A1 A0 0 INT1 INT2 INT3 INT4 X X X X

Data byte DB 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 D7r D6r D5r D4r D3r D2r D1r D0r

Description: C1 C0: Son serial channel number 00 to 11 correspond to sub-sub serial port 1 to 4 A3-A0: Register Address sub-serial D8t: 9-bit data length of the transmission of data when the 9th INT1-INT4: Channel 1 to 4 interrupt flag RC3-RC0: the number of received data FIFO TXF: = 1 to send FIFO full TXE: = 1 to send FIFO empty TXB: = 1 to send FIFO Busy RXE: = 1 received when FIFO empty

10.UART Interface Mode Operation

10.1 UART interface with the host computer When the primary interface for the UART VK3266, only need RX, TX connecting host. A standard UART protocol. After power on, reset the value of the host to VK3266 determined by baud rate and data format settings on the VK3266 to initialize the serial port to facilitate the realization of extension. VK3266 interface with the host as shown in Figure 10.1:

Figure 10.1 UART interface with the host connection diagram

10.2 UART Interface Timing Master Write operation, the first to write a command VK3266 the RX byte (Command Byte), then write the corresponding data byte, the operation timing (no parity, against escape and infrared mode) as shown in Figure 10.2:

Figure 10.2.1 UART host interface write timing

Read operation, the RX first VK3266 write command byte, the corresponding data byte read from the TX, the operation timing (no parity, against escape and infrared mode) as shown in Figure 10.3

Figure 10.2.2 UART host interface read timing

10.3 The main UART communication protocol description: 10.3.1. write register: Control byte CMD Bit TX RX
7 1 6 0 5 C1 4 C0 3 A3 2 A2 1 A1 0 A0

A data byte DB (downlink)

7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0

10.3.2. write FIFO: (multi-byte write) Control byte CMD Bit TX RX

7 1 6 1 5 C1 4 C0 3 N3 2 N2 1 N1 0 N0

[N3 N2 N1 N0] data bytes DB (downlink)

7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0

10.3.3. read register: Control byte CMD A data byte DB (uplink)

Bit TX RX

7 0

6 0

5 C1

4 C0

3 N3

2 N2

1 N1

0 N0

D7

D6

D5

D4

D3

D2

D1

D0

10.3.4. read FIFO: (multi-byte read) Control byte CMD Bit TX RX

7 0 6 1 5 C1 4 C0 3 N3 2 N2 1 N1 0 N0 D7 D6 D5 D4 D3 D2 D1 D0

[N3 N2 N1 N0] data bytes DB (uplink)

7 6 5 4 3 2 1 0

Description: C1, C0: Son serial channel number, 00 to 11 correspond to sub-sub serial port 1 to 4. A3, A2, A1, A0: sub-serial register address; N3, N2, N1, N0: write / read the number of bytes of data FIFO; when it is 0000, the show followed by a data byte; when it is 1111, the show followed by 16 data bytes ;

To the sub-serial read / write data in two ways: a. Read / write register means, the serial port FIFO register pair SFDR (1111) read / write operations, one can only read / write one byte; b. read / write FIFO mode, the receive / transmit FIFO directly read / write operation, a maximum of 16 can read and write data continuously

10.4 UART interface, the main operating mode escape character: When the main serial port pin connected high, TR, VK3266 work in escape mode. The model in the general UART interface communication mode, the main added an escape character (00H) as the frame synchronization, making the data transfer even if a data frame transmission in error, then the other will not affect data transmission. This mode is more suitable for long-distance and interference situations for data communications. In this mode, a complete data transmission frame includes an escape character (00H), a command byte, and followed by data bytes. The format is as follows Escape character (00H) Control byte CMD Data byte DB (1 or more bytes)

Note: When you need to transfer the data contains 00H, the need to send two consecutive 00H to the VK3266; 00H as the escape character first, the second only as a data 00H 00H reception.

When the TR then low, VK3266 work in the general transport protocol UART mode, the operation described operate in accordance with 10.1.3. In the escape mode, UART interface, the operation of the main sequence is as follows:

Figure 10.4.1 UART host interface write timing escape mode

Figure 10.4.1 UART host interface read timing escape mode

10.5 UART interface, the main operating mode IR

When the main serial port pin connected high, IR, VK3266 main UART work in infrared mode, the main host communication UART to comply with the infrared communication protocol, see 8.8 of its operation timing infrared mode operation. When the main serial port connected IR pin low, VK3266 work in normal mode.

11. Parallel 8-bit bus mode operation

11.1 8-bit parallel bus connection to the host:

VK3266 supports 8-bit parallel bus and the host connection, in 8-bit bus mode, VK3266 addresses only need to occupy two spaces, one for operating address register, a data register to operation. When using the query methods work, IRQ can not connect. The connection is shown in Figure 11.1:

Figure 11.1 Parallel 8-bit bus master interface connection diagram

11.2 8-bit parallel bus interface of the operating sequence: VK3266 8-bit parallel bus interface is fully compatible with mainstream 8-bit MCU (eg 8051) of the operation timing. 11.2.1. write operation sequence:

Figure 11.2.1 8-bit parallel bus write timing

11.2.2. Read Timing:

Figure 11.2.2 8-bit parallel bus read timing

11.3 8-bit parallel bus transfer protocol description: 11.3.1. write register: Control byte CMD (A0 = 0) Bit
7 0 6 1 5 C1 4 C0 3 A3 2 A2 1 A1 0 A0

A data byte DB (downstream) (A0 = 1)

7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0

11.3.2. read register: Control byte CMD (A0 = 0) Bit

7 0 6 0 5 C1 4 C0 3 A3 2 A2 1 A1 0 A0

A data byte DB (uplink) (A0 = 1)

7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0

Description: C1, CO: Son serial channel number, 00 to 11 correspond to sub-sub serial port 1 to 4 A3, A2, A1, A0: sub-serial register address

12. Described in sub-serial operation

12.1 Sub-Serial enable / disable VK3266 allow independent of each child to enable or disable serial channel. Can prohibit the use of sub-serial channel is not used to reduce power consumption. Only in sub-serial channel to enable the state to receive and send data. 12.2 Send and receive FIFO control VK3266 provides independent 16-stage FIFO receive and transmit FIFO. Receive FIFO contains an additional 3 bit, used to store the error status. Related operations through the SFOCR (sub-serial FIFO control register) is set. 12.2.1 transmit FIFO trigger operation VK3266 provided for each channel independently programmable transmit FIFO trigger points set to produce a corresponding transmit FIFO trigger interrupt.

Transmit FIFO trigger interrupt when enabled, sends the data in the FIFO is less than the number generated when the trigger point set the corresponding interrupt. 12.2.2 Receive FIFO trigger operation VK3266 independent for each channel programmable receiver FIFO trigger point is set to produce the corresponding receiver FIFO trigger interrupt. When the receiver FIFO trigger interrupt is enabled to receive data in the FIFO is greater than the number generated when the trigger point set by the corresponding interrupt. 12.2.3 transmit FIFO enable / disable After reset, transmit FIFO is disabled. If you want to write data to transmit FIFO, need to first enable the transmit FIFO. Transmit FIFO data is sent, depending on whether the corresponding sub-channel UART enabled. Once the appropriate sub-channel UART is enabled, the transmit FIFO data will be sent immediately, otherwise, sending the data in the FIFO will not be sent until the corresponding sub-channel is enabled. 12.2.4 Receive FIFO enable / disable After reset, the receiver FIFO is disabled. If the child wishes to receive data from serial port, you must first enable the corresponding sub-serial channels and receiving FIFO. And receive only the corresponding UART FIFO is enabled, the received data to be written to receive FIFO memory. If the child serial channel to enable the receiver FIFO disabled child can receive serial data, but data is not written into the receive FIFO is appreciated. 12.2.5 transmit FIFO empty When SFOCR send FIFO empty bit (TFCL) is set to 1, the sub-channel transmit FIFO data will be cleared, send FIFO counters and pointers are cleared. TFCL bit is set to 1, the hardware will be automatically cleared after a clock 0.

12.2.6 Receive FIFO Empty When the receive FIFO empty bit SFOCR (RFCL) is set to 1, the sub-channel received data in the FIFO will be cleared, receive FIFO counters and pointers are cleared. RFCL bit is set to 1, the hardware will be automatically cleared after a clock 0. 12.2.7 transmit FIFO Counter VK3266 with 4-bit register to reflect the current number of sending the data in the FIFO: When a byte of data written to the transmit FIFO, the transmit FIFO counter is automatically increased by 1; When a sending FIFO data is sent, the transmit FIFO Counter automatically by 1. Note: When sending FIFO counter is 15 (1111), if a data is then written to the counter to 0 (0000). When sending FIFO counter to 1 (0001), send a data counter has become 0 after the (0000). Therefore, when sending FIFO counter reaches 0, indicating that the transmit FIFO is full or empty, in this case, requires a combination of sub-serial status register (SSR) in the relevant status bit to judge. 12.2.8 Receive FIFO Counter K3200 4-bit register used to reflect the current number of received data in the FIFO: When a byte of data written into the receive FIFO, the receive FIFO counter is automatically increased by 1; When a receiver FIFO data is read, the receiver FIFO counter by 1

automatically. Note: When the receiver FIFO counter is 15 (1111), if data is to receive a counter to 0 (0000). When the receiver FIFO counter to 1 (0001), the read is a data counter has become 0 after the (0000). Therefore, when the receiver FIFO counter reaches 0, indicating that the receiving FIFO full or empty, in this case, requires a combination of sub-serial status register (SSR) in the relevant status bit to judge. 12.3 Flow Control VK3266 provide hardware flow control, software flow control and manual flow control three models to choose from. Hardware flow control CTS and RTS pins through the flow control can reduce the software overhead and increase system efficiency. Software flow control by XON and XOFF flow control to achieve special characters programmable operation. Related operations through the SFWCR (sub serial port flow control register) setting. In RS485 mode, the feature is disabled. 12.3.1 trigger point control When the VK3266 is set to automatic software / hardware flow control: SFWCR the HRTL1-0 is used to set suspend the sending trigger point, when the number of received data in the FIFO reaches the trigger point to suspend sending, VK3266 will issue a moratorium sends a signal to notify the sender to suspend transmission of data. SFWCR the PRTL1-0 to set to send the trigger point to send the suspended state, the host port can be read by reading the data operation to receive data in the FIFO, when the received data in the FIFO equals the number set to send a trigger Point, VK3266 will notify the sender continues to send data. Set, need to ensure that the trigger point to suspend sending more than continue to send the trigger point value. VK3266 do not automatically determine the conditions. 12.3.2 automatic software flow control operation When VK3266 work in the automatic software flow control mode, the sub-channels through the serial port to send and TX RX receiving XOFF and XON characters to achieve software flow control, no other control lines. XON and XOFF characters can be in the global register set XON and XOFF registers. Software flow control mode, the transmission of data bytes in the XON and XOFF characters can not appear, otherwise it will be used as XON and XOFF control characters, so the software flow control, the need for data in the XON and XOFF characters corresponding Escaping. 12.3.2.1 XON / XOFF transmit operation Software flow control in the automatic mode, once the data receiver to receive data FIFO has reached the set number of trigger points, in order to prevent the receiver FIFO overflow, VK3266 will automatically send an XOFF character through the TX, the data sender receives the XOFF Byte, suspended after sending the current byte of data sent. After the suspension of data transmission sender, the receiver reads the host interface receives the data in the FIFO to free space to receive FIFO, when the receiver FIFO to reduce the number of data to continue to send the trigger point, the receiver sends an XON to send character Send the character receives, it will resume sending data. Related to the timing of operation as shown below, XON / XOFF characters from the top software settings values:

Figure 12.3.2 XON / XOFF transmit operation

12.3.2.2 XON / XOFF receive operation Software flow control mode, VK3266 received data, with XOFF in the first comparison of the data when receiving the XOFF character, in the pause after sending the current byte of data sent. Data transmission pause state, the XON character is received, it will resume sending data. 12.3.2.2 XON / XOFF visible set Software flow control mode, special characters XON / XOFF can set SFWCR (sub serial flow control register) XVEN bit, so that the host side is visible or not visible. When set to visible, XON and XOFF characters as data is written to receive FIFO. When set to not visible, XON and XOFF characters will serve as a control character is not written to receive FIFO. 12.3.2.3 automatic hardware flow control When VK3266 work in sub-serial mode, automatic hardware flow control, including automatic control and automatic CTS RTS control. Were automatically set by hardware CTS RTS signal and the signal to determine the hardware flow control. Typical hardware flow control the RTS connection through the device A device B's CTS, CTS connection device A, device B of the RTS, the device A and B are set to the hardware auto flow control mode can be realized automatic hardware flow control. The connection diagram is as follows:

Hardware flow control diagram of Figure 12.3.3.1

Automatic hardware flow control mode, once the data receiver to receive data FIFO has reached the set number of trigger points, in order to prevent the receiver FIFO overflow, the receiver will automatically pulled RTS, the sender data corresponding CTS goes high, CTS receiver detects the data goes high, it will be suspended after sending the current byte of data sent. After the suspension of data transmission sender, the receiver reads the host interface receives the data in the FIFO to free space to receive FIFO, when the receiver FIFO to reduce the number of data to continue to send the trigger point, the CTS receiver automatically goes low, sending the corresponding RTS goes low, the sender detects RTS is low, it will resume sending data. The following figure shows the timing of hardware flow control operation (hardware flow control RTS and CTS mode of operation and MODEM operating under the same as RTS and CTS):

Figure 12.3.3.2 Operation timing diagram of the hardware flow

12.3.2.3 Manual hardware flow control When a child serial VK3266 work in manual mode, you can register by manually write RTS RTS pin high or low. In this mode, the other operating with the same hardware auto flow control, only RTS from the corresponding registers. Manually set RTS to 1 to suspend the data sender to send data, set the RTS to 0, the data sender continues to send data.

12.4 MODEM control MODEM control signals from the DCD, DTR, DSR, RI, RTS, and CTS composition. In these signals, DTR and RTS output signal, other signals are input signals. RTS and CTS hardware flow control operation and the same operation mode. Therefore, in the MODEM control, you need to set the RS232 serial child mode, and then select the appropriate flow control model. DCD, DTR, DSR, and RI by the corresponding registers. MODEM control signals can also used as a GPIO input signal is changed (high to low or from low to high), will generate a corresponding interrupt. 12.5 RS485 operation VK3266 child support RS584 serial control mode automatically receive and automatic address recognition mode network, network address visible settings. 12.5.1 RS485 transceiver automatically In RS485 mode, flow control will be disabled. RTS signal is used to control the automatic send and receive RS485 transceiver control. Only when sending data, RTS is high only, other situations, RTS has maintained low. VK3266 and the connection to the transceiver 485 shown in Figure:

Figure 12.5.1 RS485 connection diagram

12.5.2 Network Address and automatic address recognition RS485 mode, each UART has a unique network address, VK3266 provides an 8-bit register RS485 network settings. When the automatic network address recognition feature is enabled, VK3266 received data for automatic identification. If the received data byte or data in the address byte with the SADR does not match the address byte, VK3266 ignore these data. If the child receives the data port address byte and the data match with the SADR, the VK3266 entry into the receiving state, the address byte received after the data byte written to FIFO. When the sub-port in the state of data reception, an address byte is received, and the byte does not match with the SADR, the receiver will be automatically disabled. 12.5.3 Automatic and manual address recognition RS485 mode, SCONR child AOD serial configuration register address selection bits for data bits. The default value is 1, indicating that the sub-address byte serial receive only and ignore the data bytes. Automatic address in RS485 mode, when the received address and the address line when the SADR, AOD will automatically become 0, then the child can continue to receive serial

data. When a child receives the next serial address byte of the address is inconsistent with the SARD, AOD bit will be automatically set to 1, no longer receive the subsequent data bytes. Address identified in the manual mode, RS485, RS485 software to determine the address from the top, AOD bits need to manually set. AOD set to 0, that can receive all of the data later, when the AOD is set to 1, that will ignore all other data in addition to the address. When receiving the address byte, VK3266 will generate an interrupt to notify the received address byte MCU to judge, to decide whether to set the AOD to receive the subsequent data. 12.5.4 Setting the network address can be seen When the sub-address identifying the serial port is set to manual mode, RS485 network address is always visible. Community in the sub-serial mode is set to automatic address recognition, you can set SCONR serial port configuration registers in the sub-AVEN bit, change the network address visible property. When set to the address visible, the received network address into the receiver FIFO, or it will be ignored