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0.5 25 2006/11/30

Product Specification 6.5" COLOR TFT-LCD MODULE

MODEL NAME: C065VL01 V0

< >Draft Version < >Preliminary Specification < >Final Specification

2006 AU Optronics All Rights Reserved DO NOT COPY

Note: The content of this specification is subject to change

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Record of Revision Version 0.0 0.1 Revise Date 2006/02/10 2006/06/01 5 9 13 16 18 0.2 2006/07/21 5 14 17 19 21 0.3 0.4 2006/09/06 2006/10/03 10 10 Page First draft. D-1-a updated connector type, pin number & pin assignment D-3-c updated LED voltage, current and life time E updated response time G updated drawing Added typical application circuit and power on/off sequence Revise connector type, pin number & pin assignment Revise Viewing angle typical value in Optical characteristics Update outline drawing Revise application note Revise power on/off sequence Revise LED backlight driving voltage Revise AVDD & VGH typical value Content

19-24 Update Application Notes contents 0.5 2006/11/30 10 25 Revise AVDD values Add important note for customer system design

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Contents
A. B. C. D. Summary......................................................................................................................... 4 Features .......................................................................................................................... 4 Physical Specifications .................................................................................................... 4 Electrical Specifications................................................................................................... 5 1. Pin Assignment ........................................................................................................ 5 2. 3. E. F. G. H. I. Absolute Maximum Ratings...................................................................................... 9 Electrical Characteristics ........................................................................................ 10

Optical specifications..................................................................................................... 14 Reliability Test Items...................................................................................................... 16 Outline Dimension ......................................................................................................... 17 Packing Form ................................................................................................................ 18 Application Notes .......................................................................................................... 19 1. Typical Application Circuit....................................................................................... 19 2. Power On/Off Sequence ........................................................................................ 21

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A. Summary
C065VL01 is an LTPS (Low Temperature Poly-Silicon) type TFT (Thin Film Transistor) LCD (Liquid crystal Display). This model is composed of a TFT-LCD panel, a driver IC, a FPC (flexible printed circuit), and a backlight unit.

B. Features
6.5 display size in 16:9 aspect ratio 800RGBx480(WVGA) resolution for wide view format 550nits high brightness with high power LED backlight 300:1 high contrast Wide viewing angle technology, best at 6 oclock direction Parallel RGB I/F of 6-bit color depth Power supply: 3.3V for panel and 13.2V for LED

C. Physical Specifications
NO. 1 2 3 4 5 6 7 8 9 10 11 Item Display Resolution Active Area Screen Size Pixel Pitch Color Configuration Color Depth Overall Dimension Weight Panel surface treatment Display Mode Backlight Unit Unit dot mm inch mm --mm g ---Specification 800RGB(H)480(V) 143.40(H)79.2(V) 6.5(Diagonal) 0.05975RGB(H)0.165(V) R. G. B. Stripe 262K Colors 157.2(H) 89.2(V) 5.3(T) 1205% AG(25% haze) & with SWV film Normally White High Power LEDs Note 1 Note 2 Note 3 Remark

Note 1: Below figure shows the dot stripe arrangement.

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( 1..480)

R R

G G

B B

(1

Note 2: The 262K color display depends on 6-bit data signal input. Note 3: Not including the backlight cable. Refer to Section G, Outline Dimension for further information.

D. Electrical Specifications
1. Pin Assignment
a. TFT-LCD panel driving section Connector type: FH16-80S-0.3SH or compatible
Pin no 1 2 3 4 5 6 7 8 9 10 Symbol VGH DIO2 AVDD CHNSL1 CHNSL0 VCC POL REV LINV MUX2 I/O P I/O P I I P I I I I Description Power for LCD Start pulse signal Analog power for source driver Control signal, please set to 1 Control signal, please set to 1 Digital power for source driver Output data polarity control signal Data inversion control signal output for source driver Polarity control signal Source driver control signal Remark

G 2 B . 3. R

...2398 2399 2400)

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11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

MUX1 MUX0 GAMA LD2 LD1 OP1 OP0 MODE GND B5 B4 B3 B2 B1 B0 GND AGND V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 AVDD GND G5 G4 G3

I I I I I I I I P I I I I I I P P P P P P P P P P P P P P P P P P I I I

Source driver control signal Source driver control signal Source driver control signal ,please set to 1 Source driver control signal Source driver control signal Output buffer driving capacity control signal Output buffer driving capacity control signal Control signal , please set to 1 Digital ground Blue data Blue data Blue data Blue data Blue data Blue data Digital ground Analog ground Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Gamma reference voltage Analog power for source driver Digital ground Green data Green data Green data

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47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

G2 G1 G0 GND R5 R4 R3 R2 R1 R0 GND PRSEL1 PRSEL0 SHL CLK EDGSL RSTB VCC AGND DIO1 SW6 SW5 SW4 SW3 SW2 SW1 VGL VGH CK XCK VST NC NC VCOM

I I I P I I I I I I P I I I I I I P P I/O I I I I I I P P I I I

Green data Green data Green data Digital ground Red data Red data Red data Red data Red data Red data Digital ground Source driver control signal , please set to 0 Source driver control signal , please set to 1 Source driver horizontal shift direction control Output data clock for source driver Source driver control signal Reset pin, low active Digital power for source driver Analog ground Start pulse signal Control signal Control signal Control signal Control signal Control signal Control signal Power for LCD Power for LCD Control signal Control signal Control signal not connected not connected

Common electrode voltage

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I: Input pin; O: Output pin; P: Power pin Note1: For pin sequence arrangement, please refer to the figure as below:

Pin 80

Pin 1

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b.

Block Diagram

c.

Backlight driving section Connector type: JST PHR-2 or compatible No. 1 2 Symbol GND HI I/O I Description Ground for backlight unit Power supply for backlight unit (High voltage) Remark ---

2. Absolute Maximum Ratings

Items Symbol VCC AVDD Power Voltage VGH VGL VGH-VGL Input Signal Voltage Operating Temperature Storage Temperature Vin VCOM Topa Tstg Product Specification Min. -0.3 -0.5 -0.5 -17 -0.5 -0.3 -30 -40 Typ. Max. 4 13.5 17 0.5 26.5 VCC+0.3 85 95 Unit V V V V V V V C C

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3. Electrical Characteristics
a. Typical operating conditions Items Symbol VCC AVDD Power Voltage VGH VGL VCOM Input H/L level Voltage VIH VIL Product Specification Min. 3.0 8 10 -5 0.7*VCC 0 Typ. 3.3 10.5 13.5 -7 Max. 3.6 12 15 -9 VCC 0.3VCC Unit V V V V V V V

0.35*AVDD 0.5*AVDD 0.65*AVDD

Note 1: All value should be measured under the condition of GND=AVss=0V Note 2: The panel is designed to prevent the current leakage for the best display performance. If shorter discharge time is desired when system power off, then extra discharge circuit may be required at customers side. b. Current Consumption Parameter Current For Driver Symbol IGH IGL ICC IDD Condition VGH=12V VGL=-7V VCC=3.3V AVDD=10V Min. Typ. TBD TBD TBD TBD Max. Unit uA uA mA mA

c.

LED Backlight driving condition Parameter Voltage Current LED life time Symbol Condition Vf If Note 1 Note 1 Note 2 10000 Min. Typ. 16.5 Max. TBD 150 Unit Vrms mA Hrs

Note 1: Panel surface temperature should be kept less than content of D.2. Absolute maximum ratings. Note 2: The LED life time is defined as the module brightness decrease to 50% original brightness at Ta=25 , If=150mA d. AC Timing Conditions Characteristics (VCC=3V, AVDD=10V, AVSS=GND=0V, TA=25 )

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Parameter CLK frequency CLK frequency CLK pulse width Data set-up time Data hold time Propagation delay of DIO1/2 high to low level Propagation delay of DIO1/2 low to high level Time that the last data to LD1 LD1 pulse width Time that LD1 to DIO1/2 Time that LD1 to LD2 LD2 pulse width MUX/LINV/POL setup time MUX/LINV/POL hold time Output stable time

Symbol Fclk=1/Tclk Fclk=1/Tclk Tcw Tsu Thd Tphl Tplh Tld1 Twld1 Tlds Tld2 Twld2 Tsu2 Thd2 Tst

Min. Typ. Max. Unit 6 4 2 6 6 1 2 5 2 1 6 6 10 10 45 15 15 -

Conditions

MHz EDGSL=0 ns ns ns ns CL=25pF ns CL=25pF Tclk Tclk Tclk Tclk Tclk ns ns us Refer to LD2 timing chart X1 ~ X5, REV and DIO1/2 to CLK

22.5 MHz EDGSL=1

e.

Timing Diagrams

Timing Diagram 1 ( CHNSL=1, others setting = Default ) << EDGSL= 0, Default >>
70% >Thd Tsu 70% 70% Thd 70% 70% Tsu Thd 70% Second data Tplh Last data Tphl 70% 30% 70% Tcph 70% 30% Tcw 70% 70%

CLK

799

800

>Tsu Tcw

Dio1/2 (input) Data, REV

First data

Dio1/2

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<< EDGSL= 1>>

70% >Thd Tsu 70% 70% Thd 70% Tsu ThdTsu Thd 70%
First data Second data ------Last data

CLK

70%

Tcph 70% 30% Tcw

70%

399

70%

400

30%

>Tsu Tcw

Dio1/2 (input) Data, REV

Tplh

Tphl 70% 30%

Dio1/2

Timing Diagram 2 LD1 Timing Chart

70%

CLK
Last data

Tld1 LD1
70%

Twld1
30%

Tlds DIO1/2 (Input) Tld2 LD2

70% 70%

Remark: During source output pre-charging are no relationship (Tld2) of the LD1 and LD2.
LD2 Timing Chart

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Twld2
70%

LD2 Tsu2 MUX0 / MUX1 / MUX2 LINV / POL

70% 30%

70% 30% 30%

Thd2
70% 30% 6-bit accuracy

S1 ~ S400

Hi-Z
6-bit accuracy

Hi-Z
Tst

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E. Optical specifications
Item Response time Rise Fall Symbol Tr Tf CR Top Viewing angle Bottom Left Right Brightness White chromaticity YL x y =0 =0 =0 CR 10 Condition =0 At optimized Contrast ratio Viewing angle 450 40 60 55 55 550 0.33 0.33 Note 1, 2, 6,7 Note 1, 2, 6,7 deg. Note 5 200 300 Note 4, 5 Min. Typ. 10 15 Max. Unit ms ms Remark Note 3,5

Note 1: Ambient temperature =253C, Humidity=4585RH, and LED current If = 150 mA. To be measured in the dark room under 10 Lux. Note 2:To be measured on the center area of panel with a viewing cone of 1 by Topcon luminance meter BM-7, after 15 minutes operation. Note 3: Definition of response time: The response time is defined as the time interval between the 10% and 90% of amplitudes. The output signals of photo detector are measured when the input signals are changed from black to white(falling time) and from white to black(rising time).
"Black"

"White"
100% 90%
Signal(Relative value)

"White"

10% 0%

Tr

Tf

Note 4. Definition of contrast ratio: Contrast ratio is calculated with the following formula. Photo detector output when LCD is at White state
Photo detector output when LCD is at Black state

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Contrast ratio (CR)= Note 5. Black reference voltage data =V1 or V4 White reference voltage data =V2 or V3 (For definition of V1, V2, V3 & V4, please refer to section I.1) The 100% transmission is defined as the transmission of LCD panel when all the input terminals of module are electrically opened. Note 6. Brightness and White Chromaticity are measured at the display center. Note 7. For definition of viewing angle please refer to figure as below.

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F. Reliability Test Items

No. 1 2 3 4 5 6 7 Test items High temperature storage Low temperature storage High temperature operation Low temperature operation High temperature and high humidity Heat shock Electrostatic discharge Conditions Ta= 95 Ta= -40 Ta= 85 Ta= -30 Ta= 60C, 90% RH 240Hrs 240Hrs 240Hrs 240Hrs 240Hrs Operation Remark

-30C ~85C /100 cycles 1Hrs/cycle Non-operation 200V,200pF(0) once for each terminal Frequency range Stoke 8~33.3Hz 1.3mm 2.9G, 33.3~400Hz 15min. JIS D1601,A10 Condition A Non-operation

Vibration

Sweep Cycle

2 hours for each direction of X, Z 4 hours for Y direction 9 Mechanical shock 100G, 6ms, X,Y,Z 3 times for each direction Random vibration: 0.015G2/Hz from 5~200Hz 6dB/Octave from 200~500Hz Height: 60cm 1 corner, 3 edges, 6 surfaces IEC 68-34

10

Vibration (with carton)

11

Drop (with carton)

Note 1: Ta: Ambient temperature. Note 2: In the standard conditions, no display function NG is allowed. All the cosmetic specification is judged before the reliability stress.

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G. Outline Dimension

A-A 143.4mm*79.2mm

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H. Packing Form

FILM PROTECT

TAPE CREPED PAPER

I.

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J. Application Notes
1. Typical Application Circuit
DVCC VEEI C65 2 VEEO VDDI C67 AVDDFB CAP

SW 5 SW 6 DIO1 DCLK

R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2

C66 2

SHL R0 R1 R2

SW 1 SW 2 SW 3 SW 4

C56 C57 C58 C59 C60 C61 C62 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

C68

2 C69 1 10nF

2.2uF 1

2.2uF 1

0.1uF

8 7 6 5

8 7 6 5

8 7 6 5

PR13 33 AVCC 1 C63 0.1nF 2

PR14 33

8 7 6 5 8 7 6 5 8 7 6 5

PR15 33

PR16 33

PR17 33

PR18 33

1 2 3 4

1 2 3 4

1 2 3 4

1 2 3 4 1 2 3 4 1 2 3 4

1uF

VCC DVCC

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

DGND SW 1 SW 2 SW 3 SW 4 SW 5 SW 6 TSOUT1 DIO1 DGND DCLK SHL DVCC DGND RO0 RO1 RO2 RO3 RO4 RO5 GO0 GO1 GO2 GO3 GO4 GO5 BO0 BO1 BO2 DVCC

C34 10uF 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PR20 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 B3 B4 B5 LD1 LD2 MUX0 MUX1 MUX2 REV POL DIO2 R30 560 1

2 C35 0.1uF

L7 4.7uH

PR19 CK XCK VST 1 2 3 4 33 C64 2.2uF-1206 1 2 VEEI VEEO VDDI VDDO AVDDFB AVDD COMIN VCOM FB CAP AVCC PVGH DRV 1 R76 33 2 8 7 6 5 VGL VGH CVGH

91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

DVCC XSTBP XCS XCK SDI MXSL PSL0 PSL1 TSIN1 DGND XRST IMOD VSYNC HSYNC DE TSIN2 TSIN3 CLK DGND BI7 BI6 BI5 BI4 BI3 BI2 BI1 BI0 GI7 GI6 DGND

DVCC VCK XVCK VST D2U U2D VGL VGH CVGH CN CP VEEI VEEO VDDI VDDO AVDDFB AVDD COMIN VCOM AGND TSOUT2 FB CAP AVCC AGND PVGH NC DVCC DRV DGND

AUO-036Y1
(TQFP120)

DGND BO3 BO4 BO5 LD1 LD2 MUX0 MUX1 MUX2 REV POL DIO2 DVCC DGND TSIN4 RI0 RI1 RI2 RI3 RI4 RI5 RI6 RI7 GI0 GI1 GI2 GI3 GI4 GI5 DVCC

D3 VGH SB07 1 R28 88.7K 2 3

PR21 33 PR22 33

33 DRV

Q1 MCH3209 1

FB C36 10uF

C37

AGND_PWM

1nF

2 R34 8.66k 1

AVDD CVGH PVGH VDDI VEEO AVDDFB VGL AVDD VGH DVCC XSTBP MXSL PSL0 PSL1

VDDI VCC 1 R32 10k MXSL PSL0 R33 OPEN VCC 1 R35 OPEN PSL1 R36 0 VCC 1 R37 10k XSTBP R38 OPEN VCC 1 R? 10k VDDO 2 2 2 2 1 1 1 1 Q2 D 1 G

VCOM_DC_ADJ
3

100K 2

1 2 3 4

OUTA -INA +INA VS-

VS+ OUTB -INB +INB

8 7 6 5

T-CON setting

R22

U4 C21 OPEN 2 C22 OPEN

COMIN

R23 2 10K 1 3

EL5220C

R? OPEN

S CPH3414-N MOS 2

AVDDFB

AUO-036 Circuit design

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1 AVDD 0.1uF L8 BEAD 1 820 V1 R35 2 1 0 V2 R36 2 1 5.1K 0.1uF R37 2 1 2.2K V3 R38 2 1 2.7K 0.1uF R39 2 1 56 V4 R40 2 1 1.5K 0.1uF R41 2 1 100 V5 R42 2 1 2.7K 0.1uF R43 2 1 0 V6 R44 2 1 820 0.1uF R45 2 1 0 R46 2 V7 C38 2 C39 1 2 1 C40 2 C41 1 2 1 C42 2 1 C43 2

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C44 2 0.1uF R47 R48 2 15K 1 0 2

C45 1 2 0.1uF R49 1 820 V8 2 1 0 V9 R50 2 1 1

C46 2 0.1uF R51 2 2.7K 1 0 V10 R52 2

C47 1 2 0.1uF R53 1 1.5K 2 1 100 V11 R54 2 1 1

C48 2 0.1uF R55 2 2.7K 1 56 V12 R56 2

C49 2 0.1uF R57 R58 2 5.1K 1 2.2K 2

V7

C50 2 0.1uF R59 R60 2 820 1 0 V14 2

C51 1 2 0.1uF R61 1 1K 2 1 0 R62 2 AGND

V13

Gamma Circuit
81 VGL 1 VCOM 1 C74 C-1206-4.7uF-25V 2 C53 C-1206-4.7uF-25V 2 2 1 C52 C-1206-4.7uF-25V VGH AVDD 1 1 VCC C55 C-1206-4.7uF-25V 2 2 C54 C-1206-4.7uF-25V L9 AGND 1 Chip Bead 2 GND

Panel setting
VCC 1 1 R77 10k CHNSL0 CHNSL1 R86 OPEN VCC 1 R78 10k GAMA R87 OPEN VCC 1 R79 10k MODE R88 OPEN VCC 1 R80 10k PRSEL0 R89 OPEN VCC 1 R81 10k PRSEL1 R90 OPEN VCC 1 R82 OPEN OP0 R91 0 VCC 1 R83 OPEN OP1 R92 0 VCC 1 R84 10k EDGSL R93 OPEN VCC R85 OPEN LINV R94 0 1 VCC R? OPEN

R? 0

VCOM NC NC VST XCK CK VGH VGL SW1 SW2 SW3 SW4 SW5 SW6 DIO1 AGND VCC RSTB EDGSL DCLK SHL PRSEL0 PRSEL1 GND R0 R1 R2 R3 R4 R5 GND G0 G1 G2 G3 G4 G5 GND AVDD V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 AGND GND B0 B1 B2 B3 B4 B5 GND MODE OP0 OP1 LD1 LD2 GAMA MUX0 MUX1 MUX2 LINV REV POL VCC CHNSL0 CHNSL1 AVDD DIO2 VGH

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 82

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

Panel Setting

82

81

FH16-80S-0.3SH(05) 80pin 0.3mm

V13

CON1

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2. Power On/Off Sequence

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Note1: The using of standby mode signal XSTBP, please refer to AUO-036Y1 spec. P28. Note2: Panel reset signal RSTB and ASIC reset signal XSTBP, please follow the power on/off sequence. Note3: Input mode selection signal IMOD IMOD=Low : DE mode, please set VSYNC and HSYNC to high. IMOD=high : HSYNC/VSYNC mode, please set DE to low.

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AUO-036 Package (TQFP120)

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Signal DVCC XSTBP XCS XCK SDI MXSL PSL0 PSL1 TSIN1 DGND XRST IMOD VSYNC Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal BI6 BI5 BI4 BI3 BI2 BI1 BI0 GI7 GI6 DGND DVCC GI5 GI4 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 Signal RI4 RI3 RI2 RI1 RI0 TSIN4 DGND DVCC DIO2 POL REV MUX2 MUX1 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 Signal DVCC BO2 BO1 BO0 GO5 GO4 GO3 GO2 GO1 GO0 RO5 RO4 RO3 Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 Signal DGND DIO1 TSOUT1 SW6 SW5 SW4 SW3 SW2 SW1 DGND DVCC VCK XVCK Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 Signal CP VEEI VEEO VDDI VDDO AVDDFB AVDD COMIN VCOM AGND TSOUT2 FB CAP

Version Page: 14 15 16 17 18 19 20 HSYNC DE TSIN2 TSIN3 CLK DGND BI7 34 35 36 37 38 39 40 GI3 GI2 GI1 GI0 RI7 RI6 RI5 54 55 56 57 58 59 60 MUX0 LD2 LD1 BO5 BO4 BO3 DGND 74 75 76 77 78 79 80 RO2 RO1 RO0 DGND DVCC SHL DCLK 94 95 96 97 98 99 100 VST D2U U2D VGL VGH CVGH CN 114 115 116 117 118 119 120

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AUO-036 Pinout Recommended register setting Register Data Reg NO. 0 1 2 3 4 5 6 128 129 130 131 132 133 134 135 136 137 138 139 Reg Name
VDD_ADJ VEE_ADJ COMDC VPOSITION HPOSITION PANEL FUNCTION BLANK(1) PREC(1) SWITCH(1) INT(1) BLANK(2) PREC(2) SWITCH(2) INT(2) BLANK(3) PREC(3) SWITCH(3) INT(3)

Note 1 1 0 0 0 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 0 0 (Default) (Default) (Default) (Default) (Default) (Default) (Default) (Default) (Default) (Default) (Default) (Default) VDD=11v (Default) (Default) (Default)

D7 D6 D5 D4 D3 D2 D1 D0 X X 1 0 1 X X 0 0 0 0 1 0 0 0 1 0 0 0 X X 0 0 0 1 X 1 0 0 0 0 0 0 0 0 0 0 0 X X 0 1 1 1 X 1 0 0 0 0 0 1 0 0 0 1 0 0 X 0 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1

Important Note

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1. In customer system, the initial state of the pixel clock output (DCLK pin of AUO-036) must be set to Low.

2. Please do not cut off the pixel clock during system operation.