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Technical Seminar Report Submitted to Jawaharlal Nehru Technological University, Kakinada in Partial Fulfillment for the Award of Master degree of
Assistant Professor
(An ISO 9001:2008 Certified Institution) VENGAMUKKAPALEM, ONGOLE -523272, A.P, INDIA 2011-2013
Review Remarks
TITLE OF SEMINAR
INDEX CONTENTS 1. INTRODUCTION 2. MEMORY HEIRARCHY 2.1 Types of Memory 2.1.1 Ram 2.1.2 Static Ram 3. BASIC MEMORY CELL STRUCTURE 3.1 Ferro Electric1T-1C Structure 4. FERRO ELECTRIC CAPACITOR 5. BASIC MEMORY CELL OPERATION 5.1 Ferro Magnetic Core 5.2 Fram Write Operation 5.3 Fram Read Operation 6 SENSING SCHEMES 6.1 Ferro Electric Memory Architecture 6.1.1 Word Line-Parallel Plate Line (WL/PL) 6.1.2 Bit Line-Parallel Plate Line (BL/PL) 6.1.3 Segmented Plate Line (SEGMENTED PL) 24 17 20 15 PAGE NO 1 3
6.1.4 Merged Word Line-Parallel Plate Line (WL/PL) 7. COMPARISON 8. APPLICATIONS 8.1 Data Collection and Logging 8.2 Configuration Storage 8.3 Non Volatile Buffer 8.4 Sram Replacement and Comparison 8.5 Future Applications 8.6 Real Opportunities of Fram 8.6.1 Airbag 8.6.2 Telematics/Navigation 8.6.3 Entertainment 8.6.4 Instrument Cluster 8.6.5 Tire Pressure 8.6.6 ABS-Stability Control 8.6.7 Power Train 8.7 ADVANTAGES 8.8 DISADVANTAGE 8.9 FUTURE OF FRAM 32 33
REFERENCES
LIST OF FIGURES SNO 1 2 3 4 5 6 7 8 9 10 TITLE OF FIGURE Memory R/W Operation Memory Modules Basic Memory Cell Structure Ferro Electric Capacitor Layers on Top of Conventional CMOS Two Stable State in Ferro Electric Material Hysteresis Loop Characteristics of a Ferro Electric Capacitor Two Dimension Array of Ferro Magnetic Core Timing Diagram for Write Operation of Memory Cell Timing Diagram for Read Operation of Memory Cell Timing Diagram for Read Operation Based on Step Sensing Scheme and Pulse Sensing Scheme Block Diagram of Ferro Electric Memory With A) An Open Bit Line Architecture B) A Folded Bit Line Architecture PAGE NO 4 10 15 16 17 18 20 22 23 25
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Block Diagram of Ferro Electric Memory With WL//PL Architecture Block Diagram of Ferro Electric Memory With BL//PL Architecture Block Diagram of Ferro Electric Memory With Segmented Plate Architecture Circuit Diagram of a Pair of Ferro Electric Memory Cells for a Merged Line Architecture
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LIST OF TABLES