IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivatin........

Volume 1, Issue 1, June 2013

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm Email: editoriijec@ipasj.org ISSN 2321-5984

VLSI design fault tolerant network on chip

C. Chitra1 and T. Suganya Thevi2
1

Professor, PSNA College of Engineering and Technology, Dindigul.

T. Suganya thevi, Assistant Professor, PSNA College of Engineering and Technology, Dindigul.

ABSTRACT
It is a difficult task associate degree exceedingly in a terribly network-on-chip to style an on-chip switch/router to dynamically support (hard) bonded output underneath very tight on-chip constraints of power, timing, area, and time to promote. This paper presents the look and implementation of a completely unique pipeline circuit-switched switch to support bonded output. The projected Circuit-switched switch, supported a backtracking inquiring path setup, operates with a supply synchronous wavepipeline approach. The switch will support a dead-and live-lock free dynamic path-setup theme and might reach high information measure and high space and energy potency. A silicon-proven epitome of a 16-bit-data 5-bidirectional-port change a four-metal-layer zero.18-micrometer CMOS standard-cell technology will yield associate degree mixture information information measure of up to seventy three.84Gb/s, whereas occupying solely a modest space of zero.0315mm.The synthesizable implementation of the projected switch additionally leads to a cheap style, quick development time, and movableness. Backtracking wave-pipelining switch design is that the technique concerned within the base paper which can be followed by the hardware implementation. Multilayer accommodative error management parallel pipeline design is another technique that is to be worn out the bottom paper which can be followed by the hardware implementation to get bonded output with less power consumption.

Keywords: CMOS, power consumption, parallel pipeline, Network on chip.

1. INTRODUCTION
The increasing prominence of moveable systems and therefore the have to be compelled to limit power consumption (and thence, heat dissipation) in very-high density ULSI chips have LED to speedy and innovative developments in low-power style throughout the recent years. The driving forces behind these developments area unit moveable applications requiring low power dissipation and high output, like notebook computers, moveable communication devices and private digital assistants (PDAs). In most of those cases, the wants of low power consumption should be met along side equally strict goals of high chip density and high output. Hence, low-power style of digital integrated circuits has emerged as a awfully active and apace developing field of CMOS style. The need for low-power style is additionally turning into a significant issue in superior digital systems, like microprocessors, digital signal processors (DSPs) and different applications. Increasing chip density and better operational speed cause the look of terribly complicated chips with high clock frequencies. Typically, the ability dissipation of the chip, and thus, the temperature will increase linearly with the clock frequency. Since the dissipated heat should be removed effectively to stay the chip temperature at a suitable level, the value of packaging, cooling and warmth removal becomes a big issue. many superior micro chip chips designed within the early Nineties (e.g., Intel Pentium, DEC Alpha, PowerPC) operate at clock frequencies within the vary of one hundred to three hundred Mc, and their typical power consumption is between twenty and fifty W. VLSI dependableness is one more concern that points to the requirement for low-power style. The methodologies, that area unit accustomed reach low power consumption in digital systems, span a good vary, from device/process level to rule level. Device characteristics (e.g., threshold voltage), device geometries and interconnect properties area unit vital factors in lowering the ability consumption. Circuit-level measures like the right selection of circuit style designs, reduction of the voltage swing and duration ways is accustomed scale back power dissipation at the semiconductor device level. Architecture-level measures embody sensible power management of assorted system blocks, utilization of

Volume 1, Issue 1, June 2013

Page 38

IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivatin........

Volume 1, Issue 1, June 2013

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm Email: editoriijec@ipasj.org ISSN 2321-5984

pipelining and correspondence, and style of bus structures. Finally, the ability consumed by the system is reduced by a correct choice of the info process algorithms, specifically to attenuate the quantity of change events for a given task. In this thesis, varied sources of power consumption are going to be mentioned well, and style ways are going to be introduced to cut back the ability dissipation. The conception of adiabatic logic are going to be given a special stress since it emerges as a awfully effective suggests that for reducing the ability consumption.

2. NETWORK-ON-CHIP (NOC)
As the variety and practicality of process units (PUs) in SoCs increase, quality of point-to-point interconnections between the parts of the SoCs has additionally been inflated. Point-to-point interconnection maximizes chip performance, however its style quality takes high development price. Bus design has been improved to come back up with needs of high performance SoCs, but its inherently poor measurability limits the improvement. The shared bus design is shown in Figure one.

Fig. 1. Shared Bus design

3. FPGA DESIGN FLOW

The FPGA primarily based style Flow is extensively employed in todays world owing to its following advantage short style time, straightforward to promote etc. FPGA primarily based style Flow permits one to implement his/her VLSI style {in a|during a|in an exceedingly|in a terribly} very short length, cater to client desires and makes instant changes. 3.1 style Entry User will enter the look by writing the descriptions of any digital system exploitation high-density lipoprotein (Hardware Description Language), which might be written in 2 languages such as: -VHDL (Very High Speed microcircuit HDL),Verilog high-density lipoprotein. 3.2 Synthesis Synthesis is that the method, that converts high-density lipoprotein CODE into Gate level circuit within the style of internet LIST. This method is Target Technology dependent thence user should choose correct Device, Family, half variety and Speed Grade. additionally user could choose Synthesis Settings like Clock Frequency, improvement for Speed or space. 3.3 Simulation Simulation, user will verify the practicality of his style by applying varied sign combination and observant the output results. The simulation is performed on Gate level internet list. 3.4 Implementation Implementation is that the method during which the look is seasoned varied stages by TRANSLATE, FIT, and Programming file generation. 3.5 Programming

This is the method by that user will physically transfer the design from laptop to focus on device exploitation programming cable. In our project we've got used CPLD Development platform to transfer the info to the CPLD trainer. WINDOWS XP DUAL CORE PROCESSOR

Volume 1, Issue 1, June 2013

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IPASJ International Journal of Electronics & Communication (IIJEC)

A Publisher for Research Motivatin........

Volume 1, Issue 1, June 2013

512 Mount Rushmore State RAM FPGA JTAG CABLE SPARTAN a pair of

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm Email: editoriijec@ipasj.org ISSN 2321-5984

4. SOFTWARE ENVIRONMENT
The industry has achieved an exceptional growth over the last twenty years, in the main owing to the speedy advances in integration technologies, large-scale systems style - briefly, owing to the arrival of VLSI. The quantity of applications of integrated circuits in superior computing, telecommunications, and client physics has been rising steady, and at a awfully quick pace. Typically, the specified machine power (or, in different words, the intelligence) of those applications is that the drive for the quick development of this field. Figure 1.1 provides an outline of the outstanding trends in data technologies over ensuing few decades. the present leading-edge technologies (such as low bit-rate video and cellular communications) already give the end-users an explicit quantity of process power and movableness. The opposite necessary characteristic is that the knowledge services tend to become additional and additional personalised (as against collective services like broadcasting), which implies that the devices should be additional intelligent to answer individual demands, and at an equivalent time they need to be moveable to permit additional flexibility/mobility.

5. MERITS OF SYSTEM
Less power as a result of every of the devices consumes solely a little quantity of power. During a change circuit most of the ability is consumed change the charge on the capacitors that connect the switches to every different. During a giant IC the parts area unit therefore little and shut along that that capacitance is way smaller. Dependableness Over time, we've got found that the dependableness of associate degree IC may be a operate of what number connections it's to the surface world. Therefore if the operate is made with several smaller ICs connected along, then there area unit several connections, and therefore the dependableness is lower. The VLSI has fewer connections, and better dependableness. it's doable to realize larger practicality with an easier hardware style. needed|the specified|the desired} logic is keep in memory and thence the value of supporting extra options is reduced to the value of the memory required to store the logic style. By eliminating the ASIC style lower system price on a low-volume product is achieved. For higher-volume product, the assembly price of fastened hardware is truly a great deal lower.

6. CONCLUSION AND FUTURE ENHANCEMENT

In the current and coming back decades VLSI style that presently allows U.S.A. to make million-transistor chips can become Gigascale (GSI) style and Biu-Mandara scale Integration (TSI) style, severally. During this context, ''GIGASCALE'' and ''TERASCALE'' signifies over one billion and one trillion devices per chip, severally. From a system style perspective, this increase in integration levels is qualitatively totally different from past integration enhancements of comparable magnitudes. specifically, producing defects can increase, devices can get less reliable, interconnect are going to be orders of magnitude slower than transistors, new nano technologies can emerge, and signal and power management problems are going to be aggravated.

References
[1] L.Benini and G.De Micheli, Networks on chips:A new SoC paradigm, IEEE Computer, vol.35, no.1, pp.7078, Jan.2002. [2] K.Goossens, J.Dielissen and A.Radulescu, Ethereal network on chip: Concepts, architectures and implementations, IEEE Des.Test.comput., vol.22, no.5, pp.414-421, 2005. [3] R.Marculescu, U.Y.Ogras, P.Li-Shiuan, N.E.Jerger and Y.Hoskote, Outstanding research problems in NoC design:system,microarchitecture, and circuit perspectives, IEEE Trans.comput-aided design Integr.circuits syst., vol.28, no.1, pp.3-21, Jan.2009. [4] G.D.Micheli and L.Benini, Networks on chips:Technology and tools(systems on silicon).San Mateo, CA: Morgan Kaufmann, 2006.

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