EX.

NO: DATE: IMPLEMENTATION OF MICROPROCESSOR

AIM: To implement Microprocessor using SPARTAN 3E kit.

TOOLS REQUIRED: (i) SOFTWARE REQUIRED: XILINX 13.1 version (ii) HARDWARE REQUIRED: SPARTAN 3500 kit

THEORY: A microprocessor incorporates the functions of a computers central processing unit (CPU) on a single integrated circuit, (IC) or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and provides results as output. it consist of ALU,registers,decoders,control unit.This logic can be designed in verilog/VHDL using XILINX.After simulation it is implemented in SPARTAN 3E kit.

BLOCK DIAGRAM: MICROPROCESSOR MAIN MODULE

MEMORY

ADDER SUBTRACTER

ADDER SUBTRACTER:

ALGORITHM: STEP 1: Write a Verilog/VHDL code for a simple microprocessor. Each module is defined separately and their codes are written separately. STEP 2:Write a verilog coding for read and memory options ,addition, subtraction,multiplication,shift operations and memory operations. STEP 3:Then coding for adder subtracter is written. STEP 4:Similarly in Microprocessor VHDL code is written. STEP 5:These operations can be simulated and implemented in SPARTAN 3E kit. CODE FOR SIMPLE MICROPROCESSOR: module simpleprocess(cntrl,clk,en,m,w_nr,rst,data_in1,data_in2,addr_out1,addr_out2,q1,q2,out,co,out2, n_out); input [ 3:0] cntrl; input clk; input [7:0] data_in1,data_in2,addr_out1, addr_out2; output reg en,w_nr,m,rst; output [7:0] q1,q2; output [7:0] out; output reg [7:0] out2,n_out; output co; reg[7:0] ram_mem [15:0]; reg[7:0]data_reg; reg [3:0] a,b,m1,m2,m3,m4; reg [7:0] w,x,y,z;

ram_mem mm(data_in1,data_in2,rst, clk,w_nr,addr_out1, addr_out2,q1,q2); adder_sub as(q1,q2,m,out,co);

always @ (posedge clk) begin case (cntrl) 4'b0000:rst=1'b0; 4'b0001:w_nr = 1'b1;// memory write 4'b0010: w_nr = 1'b0; //memory read 4'b0011: m =1'b0; // addition 4'b0100: m = 1'b1; // subtraction

4'b0101: begin en=1'b1; // multiplacation if(en==1'b1) begin a= q1[3:0]; b=q2[3:0]; end m1 = {a[3]&b[0],a[2]&b[0],a[1]&b[0],a[0]&b[0]}; m2 = {a[3]&b[1],a[2]&b[1],a[1]&b[1],a[0]&b[1]}; m3 = {a[3]&b[2],a[2]&b[2],a[1]&b[2],a[0]&b[2]}; m4 = {a[3]&b[3],a[2]&b[3],a[1]&b[3],a[0]&b[3]}; w = m1; x = m2<<1; y = m3<<2; z = m4<<3; out2= w+x+y+z; end 4'b0110:// right shift begin data_reg=q1; data_reg= {1'b0, data_reg[7:1]}; assign out2=data_reg; end 4'b0111: // left shift begin data_reg=q2; data_reg= {data_reg [6:0],1'b0}; assign out2=data_reg; end 4'b1000 :out2= q1 & q2; 4'b1010: n_out= ~out2; 4'b1011:out2= q1|q2; 4'b1111: begin w_nr=1'b0; if (w_nr==1'b0) begin ram_mem[addr_out1]=out; ram_mem[addr_out2]=out2; end end 4'b1110: begin w_nr=1'b0; if (w_nr==1'b0)

ram_mem[addr_out1]=n_out; end endcase if ( cntrl==000) rst =1'b0; else rst=1'b1; end endmodule

module adder_sub(a,b,m,out,co); input [7:0] a,b; input m; output [7:0] out; output co; wire [7:0] cout; wire [7:0] d,s; assign d [0]= b[0]^ m; assign d [1]= b[1]^ m; assign d [2]= b[2]^ m; assign d [3]= b[3]^ m; assign d [4]=b[4]^ m; assign d [5]= b[5]^ m; assign d [6]= b[6]^ m; assign d [7]= b[7]^ m;

fa fa1 (s[0],cout[0],a[0],d[0],m); fa fa2 (s[1],cout[1],a[1],d[1] ,cout[0]); fa fa3 (s[2],cout[2],a[2],d[2],cout[1]); fa fa4 (s[3],cout[3],a[3], d[3],cout[2]); fa fa5 (s[4],cout[4],a[4], d[4],cout[3]); fa fa6 (s[5],cout[5],a[5], d[5],cout[4]); fa fa7 (s[6],cout[6],a[6], d[6],cout[5]); fa fa8 (s[7],cout[7],a[7], d[7],cout[6]); assign out = m?((b>a)? ((~s)+1'b1):s) :(s); assign co= cout[7];

endmodule

module ram_mem(data_in1,data_in2,rst, clk,w_nr,addr_out1, addr_out2,q1,q2); input [7:0] data_in1,data_in2; input clk, w_nr,rst; input [7:0] addr_out1,addr_out2; reg [7:0] ram_mem [15:0]; output reg[7:0] q1,q2; always @( posedge clk ) begin if(rst==1'b0) begin q1=8'b0; q2=8'b0; end else begin if( w_nr ==1'b0) begin q1= ram_mem[addr_out1]; q2= ram_mem[addr_out2]; end else begin ram_mem[addr_out1]=data_in1; ram_mem[addr_out2]=data_in2; end end end endmodule module fa(sout,cout,a,b,cin); output sout,cout; input a,b,cin; assign sout=(a^b^cin); assign cout=((a&b)|(a&cin)|(b&cin)); endmodule

CODE FOR MICROPROCESSOR VHDL:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_SIGNED.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity simpl is port ( cntrl : in std_logic_vector(3 downto 0); clk: in std_logic; data_in1,data_in2,addr1, addr2:in std_logic_vector(7 downto 0); en,w_nr,m,rst: buffer std_logic ; data_reg: buffer std_logic_vector(7 downto 0); co:out std_logic; q1,q2, out1,out2,n_out:inout std_logic_vector(7 downto 0) ); end simpl; architecture Behavioral of simpl is type ram_type is array (0 to (addr1'length)-1) of std_logic_vector(data_in1'range); signal ram : ram_type; signal w,x,y,z: std_logic_vector(7 downto 0); signal m1,m2,m3,m4:std_logic_vector(3 downto 0); signal a,b : std_logic_vector(3 downto 0); component sync_ram port ( clock : in std_logic; w_nr ,rst : in std_logic; addr1,addr2 : in std_logic_vector (7 downto 0); data_in1,data_in2 : in std_logic_vector (7 downto 0); q1,q2 : out std_logic_vector (7 downto 0) ); end component sync_ram; component add_subb port ( a,b: in std_logic_vector (7 downto 0); out1: out std_logic_vector (7 downto 0);

m: in std_logic; co:out std_logic); end component add_subb; begin mm : sync_ram port map( clk, w_nr,rst,addr1,addr2,data_in1,data_in2,q1,q2); a1 : add_subb port map(q1,q2,out1,m,co); p2:process(clk,cntrl) is begin case (cntrl) is when "0000"=> rst<='0'; when "0001"=> w_nr <='1';-- memory write when "0010"=> w_nr <= '0'; --memory read when "0011"=> m <='0'; -- addition when "0100"=> m <='1'; --subtraction when "0101"=> en<='1'; -- multiplacation if(en='1') then a <=q1(3 downto 0); b <= q2(3 downto 0); end if; m1<=(a(3)and b(0)) & (a(2)and b(0)) & (a(1)and b(0)) & (a(0)and b(0)); m2<=(a(3)and b(1)) & (a(2)and b(1)) & (a(1)and b(1)) & (a(0)and b(1)); m3<=(a(3)and b(2)) & (a(2)and b(2)) & (a(1)and b(2)) & (a(0)and b(2)); m4<=(a(3)and b(3)) & (a(2)and b(3)) & (a(1)and b(3)) & (a(0)and b(3)); w<='0'& '0' & '0' & '0' & m1; x<='0'& '0' & '0'& m2 & '0'; y<='0'& '0' & m3 & '0' &'0'; z<='0'& m4 & '0' &'0'& '0'; out2<=W + X + Y + Z; when "0110"=> -- right shift

data_reg<=q1; data_reg<='0' & data_reg(7 downto 1); out2<=data_reg; when"0111"=> -- left shift

data_reg<=q2; data_reg<=data_reg(6 downto 0)& '0'; out2<=data_reg;

when"1000"=> out2<= q1 and q2; when "1010"=> out2<= not out2; when "1011"=> out2<=q1 or q2; when "1111"=> w_nr<='0'; if (w_nr='0') then ram(to_integer(unsigned(addr1))) <= out1; ram(to_integer(unsigned(addr2))) <= out2; end if; when "1110"=> w_nr<='0'; if (w_nr='0') then ram(to_integer(unsigned(addr2))) <= n_out; end if; when others => out1<="ZZZZZZZZ"; out2<="ZZZZZZZZ"; n_out<="ZZZZZZZZ"; end case;

if ( cntrl="0000") then rst<='0'; else rst<='1'; end if;

end process p2; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all;

entity sync_ram is

port ( clock : in std_logic; w_nr ,rst : in std_logic; addr1,addr2 : in std_logic_vector (7 downto 0); data_in1,data_in2 : in std_logic_vector (7 downto 0); q1,q2 : out std_logic_vector (7 downto 0) ); end entity sync_ram; architecture RTL of sync_ram is

type ram_type is array (0 to (addr1'length)-1) of std_logic_vector(data_in1'range); signal ram : ram_type; begin RamProc: process(clock) is begin if (rst= '0') then q1<="00000000"; q2<="00000000"; elsif rising_edge(clock) then if (w_nr = '0') then q1<= ram(to_integer(unsigned(addr1))); q2<= ram(to_integer(unsigned(addr2))); else ram(to_integer(unsigned(addr1))) <= data_in1; ram(to_integer(unsigned(addr2))) <= data_in2; end if; end if; end process RamProc;

end architecture RTL;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_BIT.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity add_subb is port ( a,b: in std_logic_vector (7 downto 0); out1: out std_logic_vector (7 downto 0); m: in std_logic; co:out std_logic); end add_subb; architecture Behavioral of add_subb is signal cout, d,s,g:std_logic_vector (7 downto 0); component fa port ( sum : out STD_LOGIC; co : out STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC); end component; begin d (0)<= b(0)xor m; d (1)<= b(1)xor m; d(2)<= b(2) xor m; d (3)<= b(3) xor m; d (4)<=b(4) xor m; d (5)<= b(5) xor m; d (6)<= b(6) xor m; d (7)<= b(7) xor m; fa1: fa port map (s(0),cout(0),a(0),d(0),m); fa2: fa port map (s(1),cout(1),a(1),d(1) ,cout(0)); fa3: fa port map (s(2),cout(2),a(2),d(2),cout(1)); fa4: fa port map (s(3),cout(3),a(3), d(3),cout(2)); fa5: fa port map (s(4),cout(4),a(4), d(4),cout(3)); fa6: fa port map (s(5),cout(5),a(5), d(5),cout(4)); fa7: fa port map (s(6),cout(6),a(6), d(6),cout(5)); fa8: fa port map (s(7),cout(7),a(7), d(7),cout(6)); g<=("00000001") or ( not s); out1 <= g when cout(7)='0' and m='1' else s when cout(7)='1' and m='1' else

s when m='0'; co<= cout(7); end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fa is Port ( sum : out STD_LOGIC; co : out STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC); end fa; architecture Behavioral of fa is begin sum <=(a xor b xor cin); co <=((a and b) or (a and cin) or (b and cin)); end Behavioral;

SIMULATION OUTPUT (verilog):

SIMULATION OUTPUT(VHDL):

RESULT: Thus the microprocessor was simulated in VHDL using Xilinx and implemented using FPGA trainer kit.