################################################################################ ########################################## INTERVIEW QUESTIONS ################################################################################ ########################################## 1. Explain formal verification 2. Write assertion for clock switch 3.

Endianess of a processor 4. Difference between structure and union 5. Difference between task and function 6. Pointers - Program 7. What is Delta delay? Will it be present after synthesis and also in silicon? How to reduce it? 8. AXI,OCP protocol - timing diagram questions 9. Setup and hold violation. How to fix it? 10. Difference between latch and flip-flop? Which is more advantageous and why? 11. Draw latch and flip flop using gates and CMOS level. 12. Projects - M.TECH and B.E 13. Asynchronous FIFO and depth calculation 14. CMOS inverter 15. Power dissipation. When scaling down occurs which is dominant? 16. What is clock gating? Significance of it? 17. Sequence detector implementation in terms of Flops and gates 18. Sensitivity list - Program 19. Malloc function in C 20. Chip has burnt due to timing violations. How to fix it? 21. Divide by 3 counter 22. BJT Amplifiers 23. Operation of CMOS 24. Reference for setup and hold time? 25. Explain about signal gating, clock gating and power gating? Whether reset is required while restarting the gated power an d clock signal? Why? 26. What is Stack? 27. C programs - string copying using array and pointers 28. Difference between synchronous and asynchronous reset? 29. What are generics in vhdl and how to pass generics in vhdl? 30. Write state machine for traffic light control 31. Find the clock frequency with given parameters like setup time hold time, cl ock to q delay 32. For 2minutes how we will generate the clock frequency? 33. What is normal standard frequencies used for clocks? 34. Clock divider design and what about setup and hold time violations of the cl ock divider? 35. What happens if combinational logic is removed between flip-flops? What viol ations it will cause? 36. What happens if hold-time is increased greater than setup time? Will it caus e metastability? 37. What is the difference between ocp and axi? 38. Explain Clock Bridge and 2 flop synchronizer which will synchronize between 2 clock domains? 39. What will synthesis report when the write pointer is writing to next address location? 40. Difference between binary and grey code? How binary code will reduce the pow er dissipation? 41. How to minimize the switching power dissipation?