Micro-Controller

2. MICROCONTROLLER 2.1 EMBEDDED SYSTEMS:

An embedded system is a system which is going to do a predefined specified task and is even defined as combination of both software and hardware. A general-purpose definition of embedded systems is that they are devices used to control monitor or assist the operation of equipment, machinery or plant. "Embedded" reflects the fact that they are an integral part of the system. At the other extreme a general purpose computer may be used to control the operation of a large complex processing plant, and its presence will be obvious. All embedded systems are including computers or microprocessors. Some of these computers are however very simple systems as compared with a personal computer. The very simplest embedded systems are capable of performing only a single function or set of functions to meet a single predetermined purpose. In more complex systems an application program that enables the embedded system to be used for a particular purpose in a specific application determines the functioning of the embedded system. The ability to have programs means that the same embedded system can be used for a variety of different purposes. In some cases a microprocessor may be designed in such a way that application software for a particular purpose can be added to the basic software in a second process, after which it is not possible to make further changes. The applications software on such processors is sometimes referred to as firmware. The simplest devices consist of a single microprocessor (often called a "chip), which may itself be packaged with other chips in a hybrid system or Application Specific Integrated Circuit (ASIC). Its input comes from a detector or sensor and its output goes to a switch or activator which (for example) may start or stop the operation of a machine or, by operating a valve, may control the flow of fuel to an engine. As the embedded system is the combination of both software and hardware

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Processors are classified into four types like:

Micro Processor (p) Micro controller (c) Digital Signal Processor (DSP) Application Specific Integrated Circuits (ASIC)

Micro Controller (c): A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications. A microcontroller is a general purpose device, but that is meant to read data, perform limited calculations on that data and control its environment based on those calculations. The prime use of a microcontroller is to control the operation of a machine using a fixed program that is stored in ROM and that does not change over the lifetime of the system.

NOR flash In NOR gate flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR Flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.

PROM A programmable read-only memory (PROM) or field programmable read-only memory (FPROM) or one-time programmable non-volatile memory (OTP NVM) is a form of digital memory where the setting of each bit is locked by a fuse or antifuse. Such PROMs are used to store programs permanently. The key difference from a strict ROM is that the programming is applied after the device is constructed. These types of memories are frequently seen in video game consoles, mobile phones, radio-frequency identification (RFID) tags, implantable medical devices, high-definition

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multimedia interfaces (HDMI) and in many other consumer and automotive electronics products.

2.2 BLOCK DIGARAM

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2.3 Features
The ATmega128 provides the following features: 128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 4Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), 2 USARTs, a byte oriented Two-wire Serial Interface, an 8- channel, 10bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. High-performance, Low-power AtmelAVR8-bit Microcontroller Advanced RISC Architecture 32 x 8 General Purpose Working Registers + Peripheral Control Registers High Endurance Non-volatile Memory segments 128Kbytes of In-System Self-programmable Flash program memory 4Kbytes EEPROM 4Kbytes Internal SRAM Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Up to 64Kbytes Optional External Memory Space

JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard

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Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface

Real Time Counter with Separate Oscillator

Operating Voltages 4.5 - 5.5V ATmega128

2.4 CENTRAL PROCESSING UNIT

CPU has a role of connective element between other blocks in the microcontroller. It coordinates the work of other blocks and executes the user program.

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2.5 PIN DESCRIPTION:

1. VCC:- Digital supply voltage. 2. GND:- Ground. 3. Port A (PA7..PA0),Port B (PB7..PB0), Port C (PC7..PC0), Port D (PD7..PD0), Port E (PE7..PE0), Port F (PF7..PF0), Port G (PG4..PG0):- All Port has an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port pins that are externally pulled low will source current if the pull-up resistors are activated. The Port pins are tri-stated when a reset condition becomes active,even if the clock is not running. 4. RESET:- Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. 5. XTAL1:- Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 6. XTAL2:- Output from the inverting Oscillator amplifier. 7. AVCC:-AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 8. AREF:-AREF is the analog reference pin for the A/D Converter. 9. PEN:- PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation.

2.6 Architectural Overview

2.6.1 Program memory (FLASH) is used for storing a written program. Flash memory is an example of quite a recent type of storage technology known as solid state devices. This type of portable storage has become very popular because of its low price and high storage capacity compared to its rivals, e.g. floppy disk. Solid state devices are regarded as being robust and reliable because they have no moving parts with the data stored in semiconductor chips. This technology already exists in the form of flash memory used to store the Basic Input/Output System (BIOS) of a motherboard.

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Unlike ROM, flash memory can be read form and written to and unlike RAM does not require power to retain its data. Although these devices typically cannot hold as much data as hard disks, CD-ROMs and DVDs, the storage capacity is continually increasing. Since memory made in FLASH technology can be programmed and cleared more than once, it makes this microcontroller suitable for device development. 2.6.2 EEPROM:- This is the most flexible type of ROM that uses special softwares to erase the content of the device. The difference between EPROM and EEPROM is that; EEPROM uses electric current to erase the content while EPROM uses ultraviolet rays, data memory that needs to be saved when there is no supply. It is usually used for storing important data that must not be lost if power supply suddenly stops. For instance, one such data is an assigned temperature in temperature regulators. If during a loss of power supply this data was lost, we would have to make the adjustment once again upon return of supply. Thus our device looses on self-reliance.

2.6.3 RAM:- Data memory used by program during its execution. In ram are stored all inter results or temporary data during run-time.

2.6.4 INTERRUPT SYSTEM:An interrupt is an external or internal event that suspends the operation of microcontroller to inform it that a device needs its service. In interrupt method, whenever any device needs its service, the device notifies the micro controller by sending it an interrupt signal. Upon receiving an interrupt signal, the micro controller interrupts whatever it is doing and serves the device. The program associated with interrupt is called as interrupt service subroutine (ISR).Main advantage with interrupts is that the micro controller can serve many devices.

2.6.5 ALU Arithmetic Logic Unit:The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories arithmetic, logical, and bitfunctions.

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2.6.6 Status Register:The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt.

2.6.7 General Purpose Register File:The Register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register file: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input 2.6.8 Stack Pointer:The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.

2.6.9 Clock generator oscillator:Oscillator circuit is used for providing a microcontroller with a clock. Clock is needed so that microcontroller could execute a program or program instructions.

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2.6.10 Reset:Reset is used for putting the microcontroller into a 'known' condition. That practically means that microcontroller can behave rather inaccurately under certain undesirable conditions. In order to continue its proper functioning it has to be reset, meaning all registers would be placed in a starting position. Reset is not only used when microcontroller doesn't behave the way we want it to, but can also be used when trying out a device as an interrupt in program execution, or to get a microcontroller ready when loading a program.

2.6.12 Ports:Term "port" refers to a group of pins on a microcontroller which can be accessed simultaneously, or on which we can set the desired combination of zeros and ones, or read from them an existing status. Physically, port is a register inside a microcontroller which is connected by wires to the pins of a microcontroller. Ports represent physical connection of Central Processing Unit with an outside world. Microcontroller uses them in order to monitor or control other components or devices. 2.6.13 Reset and Interrupt Handling:Interrupts are a mechanism of a microcontroller which enables it to respond to some events at the moment they occur, regardless of what microcontroller is doing at the time. This is a very important part, because it provides connection between a microcontroller and environment which surrounds it. Generally, each interrupt changes the program flow, interrupts it and after executing an interrupt subprogram (interrupt routine) it continues from that same point on. The AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt vectors. The lower the address the higher is the priority level. RESET has the highest priority, When

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an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction RETI is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. The second type of interrupts will trigger as long as the interrupt condition is present.

2.6.14 Pull-up:The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep.

2.6.15 AVR ATmega128 Memories:This section describes the different memories in the Atmel AVR ATmega128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

In-System Reprogrammable Flash Program Memory:The ATmega128 contains 128Kbytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 64K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

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SRAM Data Memory:The Atmel AVR ATmega128 supports two different configurations for the SRAM data memory

EEPROM Data Memory:the Atmel AVRATmega128 contains 4Kbytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written

External Memory Interface:With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCDdisplay, A/D, and D/A.

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Program memory:Program memory has been carried out in FLASH technology which makes it possible to program a microcontroller many times before it's installed into a device, and even after its installment if eventual changes in program or process parameters should occur.

Data memory:Data memory consists of EEPROM and RAM memories. EEPROM memory consists of 256 eight bit locations whose contents is not lost during loosing of power supply. EEPROM is not directly addressable, but is accessed indirectly through EEADR and EEDATA registers. As EEPROM memory usually serves for storing important parameters (for example, of a given temperature in temperature regulators) , there is a strict procedure for writing in EEPROM which must be followed in order to avoid accidental writing. Locations of RAM memory are also called GPR registers which is an abbreviation for General Purpose Registers. GPR registers can be accessed regardless of which bank is selected at the moment

2.7 USART
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete Multi-processor Communication Mode Double Speed Asynchronous Communication Mode

2.7.1 Dual USART:The ATmega128 has two USARTs, USART0 and USART1. The functionality for both USARTs is described below. USART0 and USART1 have different I/O registers.in ATmega128 compatibility mode, USART1 is not available, neither is the UBRR0H or UCRS0C Registers. This means that in ATmega103 compatibility mode, the ATmega128 supports asynchronous operation of USART0 only. The three main parts of

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the USART: Clock Generator, Transmitter, and Receiver. Control registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, parity generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the receiver includes a parity checker, control logic, a Shift Register and a two level receive buffer (UDR). The receiver supports the same frame formats as the Transmitter, and can detect frame error, data overrun and parity errors.

Figure: Transmission Diagram

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Figure: Reception Diagram

2.8 MAX232:
Max 232 is a communications device used mainly for serial commands to and from a flash ROM. The MAX232 is an integrated circuit that converts signals from an RS232serial port to signals suitable for use in TTL compatible digital logic circuits. TheMAX232 is a dual driver/receiver and typically converts the RX, TX, CTS and RTS signals. The drivers provide RS-232 voltage level outputs (approx. 7.5 V) from a single +5 V supply via on-chip charge pumps and external capacitors. This makes it useful for implementing RS-232 in devices that otherwise do not need any voltages outside the 0V to +5 V range, as power supply design does not need to be made more complicated just for driving the RS-232 in this case. The receivers reduce RS-232 inputs (which may be as high as 25 V), to standard 5 VTTL levels. These receivers have a typical threshold of 1.3 V, and a typical hysteresis of 0.5 V. The later MAX232A is backwards compatible with the original MAX232 but may operate at higher baud rates and can use smaller external capacitors 0.1 F in place of the 1.0 F capacitors used with the original device. The newer MAX3232 is also backwards compatible, but operates at a broader voltage range, from 3 to 5.5V.

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