29834901

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Intel 815 Chipset Platform

For Use with Universal Socket 370
Design Guide
April 2001
Document Number: 298349-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel 815 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
2 2 I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation www.intel.com or call 1-800-548-4725 Intel, Pentium II, Pentium III, Celeron, and MMX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2001, Intel Corporation
Intel 815 Chipset Platform Design Guide
Contents
1 Introduction ........................................................................................................................13 1.1 1.2 1.3 Terminology ..........................................................................................................14 Reference Documents ..........................................................................................16 System Overview ..................................................................................................16 1.3.1 System Features ...................................................................................17 1.3.2 Component Features.............................................................................18 1.3.2.1 Graphics Memory Controller Hub (GMCH) ..........................18 1.3.2.2 Intel 82801AA I/O Controller Hub (ICH) .............................20 1.3.2.3 Firmware Hub (FWH)...........................................................20 1.3.3 Platform Initiatives .................................................................................21 1.3.3.1 Universal Socket 370 Design...............................................21 1.3.3.2 PC 133 .................................................................................21 1.3.3.3 Accelerated Hub Architecture Interface ...............................21 1.3.3.4 Internet Streaming SIMD Extensions...................................21 1.3.3.5 AGP 2.0................................................................................21 1.3.3.6 Manageability .......................................................................22 1.3.3.7 AC97 ...................................................................................23 1.3.3.8 Low-Pin-Count (LPC) Interface............................................23 Nominal Board Stackup ........................................................................................25
2 3 4
General Design Considerations.........................................................................................25 2.1 Component Quadrant Layouts...........................................................................................27 Universal Socket 370 Design ............................................................................................29 4.1 4.2 Universal Socket 370 Definitions ..........................................................................29 Processor Design Requirements ..........................................................................31 4.2.1 Use of Universal Socket 370 Design with Incompatible GMCH............31 4.2.2 Identifying the Processor at the Socket.................................................32 4.2.3 Setting the Appropriate Processor VTT Level .......................................33 4.2.4 VTT Processor Pin AG1 ........................................................................34 4.2.5 Identifying the Processor at the GMCH.................................................34 4.2.6 Configuring Non-VTT Processor Pins ...................................................36 4.2.7 VCMOS Reference................................................................................37 4.2.8 Processor Signal PWRGOOD...............................................................38 4.2.9 APIC Clock Voltage Switching Requirements .......................................39 4.2.10 GTLREF Topology and Layout..............................................................40 Power Sequencing on Wake Events ....................................................................41 4.3.1 Gating of Intel CK-815 to VTTPWRGD ...............................................41 4.3.2 Gating of PWROK to ICH......................................................................42 System Bus Routing Guidelines ...........................................................................43 5.1.1 Initial Timing Analysis ............................................................................43
4.3
System Bus Design Guidelines .........................................................................................43 5.1
5.2
5.3
5.4 5.5 5.6 5.7 5.8 5.9
5.10 5.11
5.12 5.13 6 6.1 6.2
General Topology and Layout Guidelines.............................................................46 5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals ...........................47 5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals .................................................................................49 5.2.1.2 THRMDP and THRMDN ......................................................50 5.2.1.3 Additional Routing and Placement Considerations ..............50 Electrical Differences for Universal PGA370 Designs ..........................................51 5.3.1 THERMTRIP Circuit ..............................................................................51 5.3.1.1 THERMTRIP Timing ............................................................51 PGA370 Socket Definition Details ........................................................................52 BSEL[1:0] Implementation Differences.................................................................56 CLKREF Circuit Implementation ...........................................................................57 Undershoot/Overshoot Requirements ..................................................................57 Processor Reset Requirements............................................................................58 Processor PLL Filter Recommendations ..............................................................59 5.9.1 Topology................................................................................................59 5.9.2 Filter Specification .................................................................................59 5.9.3 Recommendation for Intel Platforms.....................................................61 5.9.4 Custom Solutions ..................................................................................63 Voltage Regulation Guidelines..............................................................................63 Decoupling Guidelines for Universal PGA370 Designs ........................................63 5.11.1 VCCCORE Decoupling Design .................................................................63 5.11.2 VTT Decoupling Design ........................................................................64 5.11.3 VREF Decoupling Design......................................................................64 Thermal Considerations........................................................................................65 5.12.1 Heatsink Volumetric Keepout Regions..................................................65 Debug Port Changes ............................................................................................67 System Memory Routing Guidelines.....................................................................69 System Memory 2-DIMM Design Guidelines ........................................................70 6.2.1 System Memory 2-DIMM Connectivity ..................................................70 6.2.2 System Memory 2-DIMM Layout Guidelines .........................................71 System Memory 3-DIMM Design Guidelines ........................................................73 6.3.1 System Memory 3-DIMM Connectivity ..................................................73 6.3.2 System Memory 3-DIMM Layout Guidelines .........................................74 System Memory Decoupling Guidelines ...............................................................75 Compensation.......................................................................................................77 AGP Interface .......................................................................................................79 7.1.1 Graphics Performance Accelerator (GPA) ............................................80 7.1.2 AGP Universal Retention Mechanism (RM) ..........................................80 AGP 2.0 ................................................................................................................82 7.2.1 AGP Interface Signal Groups ................................................................83 Standard AGP Routing Guidelines .......................................................................84 7.3.1 1X Timing Domain Routing Guidelines .................................................84 7.3.1.1 Flexible Motherboard Guidelines .........................................84 7.3.1.2 AGP-Only Motherboard Guidelines......................................84 7.3.2 2X/4X Timing Domain Routing Guidelines ............................................84 7.3.2.1 Flexible Motherboard Guidelines .........................................85
System Memory Design Guidelines...................................................................................69
6.3
6.4 6.5 7 7.1
AGP/Display Cache Design Guidelines.............................................................................79
7.2 7.3
7.4
7.5
7.6
7.7 7.8
7.9 8 8.1
7.3.2.2 AGP-Only Motherboard Guidelines......................................86 7.3.3 AGP Routing Guideline Considerations and Summary.........................87 7.3.4 AGP Clock Routing ...............................................................................88 7.3.5 AGP Signal Noise Decoupling Guidelines.............................................88 7.3.6 AGP Routing Ground Reference...........................................................89 AGP Down Routing Guidelines .............................................................................90 7.4.1 1X AGP Down Option Timing Domain Routing Guidelines ...................90 7.4.2 2X/4X AGP Down Timing Domain Routing Guidelines .........................90 7.4.3 AGP Routing Guideline Considerations and Summary.........................91 7.4.4 AGP Clock Routing ...............................................................................92 7.4.5 AGP Signal Noise Decoupling Guidelines.............................................92 7.4.6 AGP Routing Ground Reference...........................................................92 AGP 2.0 Power Delivery Guidelines .....................................................................93 7.5.1 VDDQ Generation and TYPEDET#.......................................................93 7.5.2 VREF Generation for AGP 2.0 (2X and 4X) ..........................................95 Additional AGP Design Guidelines........................................................................97 7.6.1 Compensation .......................................................................................97 7.6.2 AGP Pull-Ups ........................................................................................97 7.6.2.1 AGP Signal Voltage Tolerance List......................................98 Motherboard / Add-in Card Interoperability...........................................................98 AGP / Display Cache Shared Interface.................................................................99 7.8.1 GPA Card Considerations .....................................................................99 7.8.1.1 AGP and GPA Mechanical Considerations..........................99 7.8.2 Display Cache Clocking.......................................................................100 Designs That Do Not Use The AGP Port............................................................100 Analog RGB/CRT................................................................................................101 8.1.1 RAMDAC/Display Interface .................................................................101 8.1.2 Reference Resistor (Rset) Calculation ................................................103 8.1.3 RAMDAC Board Design Guidelines ....................................................103 8.1.4 RAMDAC Layout Recommendations ..................................................105 8.1.5 HSYNC/VSYNC Output Guidelines.....................................................105 Digital Video Out .................................................................................................106 8.2.1 DVO Interface Routing Guidelines ......................................................106 2 8.2.2 DVO I C Interface Considerations.......................................................106 8.2.3 Leaving the DVO Port Unconnected ...................................................106
Integrated Graphics Display Output.................................................................................101
8.2
Hub Interface ...................................................................................................................107 9.1.1 Data Signals ........................................................................................108 9.1.2 Strobe Signals .....................................................................................108 9.1.3 HREF Generation/Distribution.............................................................108 9.1.4 Compensation .....................................................................................109 I/O Subsystem .................................................................................................................111 10.1 10.2 IDE Interface .......................................................................................................111 10.1.1 Cabling and Motherboard Requirements ............................................111 Cable Detection for Ultra ATA/66........................................................................113 10.2.1 Host Side Cable Detection ..................................................................114 10.2.2 Device Side Cable Detection...............................................................115 10.2.3 Primary IDE Connector Requirements ................................................116 10.2.4 Secondary IDE Connector Requirements ...........................................117
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10.3
10.4 10.5 10.6 10.7 10.8
10.9
10.2.5 Layout for Both Host-Side and Device-Side Cable Detection .............118 AC97 ..................................................................................................................119 10.3.1 AC97 Routing .....................................................................................119 10.3.2 AC97 Signal Quality Requirements ....................................................121 10.3.3 Motherboard Implementation ..............................................................121 Using Native USB Interface ................................................................................122 I/O APIC (I/O Advanced Programmable Interrupt Controller).............................123 SMBus ................................................................................................................124 PCI ......................................................................................................................124 LPC/FWH............................................................................................................125 10.8.1 In-Circuit FWH Programming..............................................................125 10.8.2 FWH VPP Design Guidelines ...............................................................125 RTC.....................................................................................................................125 10.9.1 RTC Crystal .........................................................................................126 10.9.2 External Capacitors .............................................................................126 10.9.3 RTC Layout Considerations ................................................................127 10.9.4 RTC External Battery Connection .......................................................127 10.9.5 RTC External RTCRESET Circuit .......................................................128 10.9.6 RTC-Well Input Strap Requirements...................................................128 10.9.7 RTC Routing Guidelines......................................................................129 10.9.8 Guidelines to Minimize ESD Events ....................................................129 10.9.9 VBIAS and DC Voltage and Noise Measurements .............................129 2-DIMM Clocking ................................................................................................131 3-DIMM Clocking ................................................................................................133 Clock Routing Guidelines....................................................................................135 Clock Decoupling ................................................................................................137 Clock Driver Frequency Strapping ......................................................................137 Clock Skew Assumptions ...................................................................................138 Intel CK-815 Power Gating On Wake Events ...................................................139 Thermal Design Power .......................................................................................144 12.1.1 Pull-Up and Pull-Down Resistor Values ..............................................144 ATX Power Supply PWRGOOD Requirements..................................................145 Power Management Signals ...............................................................................146 12.3.1 Power Button Implementation .............................................................147 1.85V/3.3V Power Sequencing ...........................................................................148 12.4.1 VDDQ/VCC1_85 Power Sequencing ..................................................152 12.4.2 1.85V/3.3V Power Sequencing............................................................152 12.4.3 3.3V/V5REF Sequencing.....................................................................154 Design Review Checklist ....................................................................................155 Processor Checklist ............................................................................................155 13.2.1 GTL Checklist......................................................................................155 13.2.2 CMOS Checklist ..................................................................................156 13.2.3 TAP Checklist for 370-Pin Socket Processors ....................................156 13.2.4 Miscellaneous Checklist for 370-Pin Socket Processors ....................156 GMCH Checklist .................................................................................................158
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Clocking ...........................................................................................................................131 11.1 11.2 11.3 11.4 11.5 11.6 11.7
12
Power Delivery.................................................................................................................141 12.1 12.2 12.3 12.4
13
System Design Checklist.................................................................................................155 13.1 13.2
13.3
13.4
13.5 13.6 13.7 13.8 13.9 13.10 14
13.3.1 AGP Interface 1X Mode Checklist.......................................................158 13.3.2 Designs That Do Not Use the AGP Port .............................................159 13.3.3 System Memory Interface Checklist....................................................160 13.3.4 Hub Interface Checklist .......................................................................160 13.3.5 Digital Video Output Port Checklist .....................................................160 ICH Checklist ......................................................................................................161 13.4.1 PCI Checklist.......................................................................................161 13.4.2 USB Checklist .....................................................................................162 13.4.3 AC 97 Checklist ..................................................................................162 13.4.4 IDE Checklist.......................................................................................163 13.4.5 Miscellaneous ICH Checklist...............................................................163 LPC Checklist .....................................................................................................165 System Checklist ................................................................................................166 FWH Checklist ....................................................................................................166 Clock Synthesizer Checklist................................................................................167 LAN Checklist .....................................................................................................168 Power Delivery Checklist ....................................................................................168 13.10.1 Power 169
Third-Party Vendor Information .......................................................................................171
Appendix A: Customer Reference Board (CRB) .....................................................................................173
Figures
Figure 1. System Block Diagram .......................................................................................17 Figure 2. GMCH Block Diagram ........................................................................................18 Figure 3. Board Construction Example for 60 Nominal Stackup ...................................25 Figure 4. GMCH 544-Ball BGA* CSP Quadrant Layout (Top View)................................27 Figure 5. ICH 241-Ball BGA* CSP Quadrant Layout (Top View).....................................28 Figure 6. Firmware Hub (FWH) Packages ........................................................................28 Figure 7. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370 Designs Using A-2 GMCH..........................................................................................31 Figure 8. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit ..................32 Figure 9. VTT Selection Switch .........................................................................................33 Figure 10. Switching Pin AG1............................................................................................34 Figure 11. Processor Identification Strap on GMCH .........................................................35 Figure 12. VTTPWRGD Configuration Circuit ...................................................................36 Figure 13. GTL_REF/VCMOS_REF Voltage Divider Network ..........................................37 Figure 14. Resistor Divider Network for Processor PWRGOOD.......................................38 Figure 15. Voltage Switch For APIC Clock from Clock Synthesizer to Processor.............39 Figure 16. GTLREF Circuit Topology ................................................................................40 Figure 17. Gating Power to Intel CK-815 .........................................................................41 Figure 18. PWROK Gating Circuit For ICH .......................................................................42 Figure 19. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)..46 Figure 20. AGTL/AGTL+ Trace Routing............................................................................47 Figure 21. Routing for THRMDP and THRMDN................................................................50 Figure 22. Example Implementation of THERMTRIP Circuit ............................................51 Figure 23. BSEL[1:0] Circuit Implementation for PGA370 Designs...................................56 Figure 24. Examples for CLKREF Divider Circuit..............................................................57 Figure 25. RESET#/RESET2# Routing Guidelines ...........................................................58 Figure 26. Filter Specification ............................................................................................60 Figure 27. Example PLL Filter Using a Discrete Resistor .................................................62 Figure 28. Example PLL Filter Using a Buried Resistor ....................................................62 Figure 29. Core Reference Model .....................................................................................63 Figure 30. Capacitor Placement on the Motherboard........................................................64 Figure 31. Heatsink Volumetric Keepout Regions.............................................................66 Figure 32. Motherboard Component Keepout Regions.....................................................66 Figure 33. TAP Connector Comparison ............................................................................67 Figure 34. System Memory Routing Guidelines ................................................................69 Figure 35. System Memory Connectivity (2 DIMM) ...........................................................70 Figure 36. System Memory 2-DIMM Routing Topologies..................................................71 Figure 37. System Memory Routing Example ...................................................................72 Figure 38. System Memory Connectivity (3 DIMM) ...........................................................73 Figure 39. System Memory 3-DIMM Routing Topologies..................................................74 Figure 40. Intel 815 Chipset Platform Decoupling Example ............................................76 Figure 41. Intel 815 Chipset Platform Decoupling Example ............................................77 Figure 42. AGP Left-Handed Retention Mechanism .........................................................81 Figure 43. AGP Left-Handed Retention Mechanism Keepout Information........................81 Figure 44. AGP 2X/4X Routing Example for Interfaces < 6 Inches and GPA/AGP Solutions.....................................................................................................................85 Figure 45. AGP Decoupling Capacitor Placement Example .............................................89 Figure 46. AGP VDDQ Generation Example Circuit .........................................................94 Figure 47. AGP 2.0 VREF Generation and Distribution.....................................................96 Figure 48. Display Cache Input Clocking.........................................................................100
Figure 49. Schematic of RAMDAC Video Interface.........................................................102 Figure 50. Cross-Sectional View of a Four-Layer Board .................................................103 Figure 51. Recommended RAMDAC Component Placement & Routing........................104 Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections 105 Figure 53. Hub Interface Signal Routing Example ..........................................................107 Figure 54. Single-Hub-Interface Reference Divider Circuit .............................................109 Figure 55. Locally Generated Hub Interface Reference Dividers ....................................109 Figure 56. IDE Minimum/Maximum Routing and Cable Lengths ....................................112 Figure 57. Ultra ATA/66 Cable.........................................................................................112 Figure 58. Host-Side IDE Cable Detection ......................................................................114 Figure 59. Drive-Side IDE Cable Detection .....................................................................115 Figure 60. Resistor Schematic for Primary IDE Connectors ...........................................116 Figure 61. Resistor Schematic for Secondary IDE Connectors.......................................117 Figure 62. Flexible IDE Cable Detection..........................................................................118 Figure 63. Recommended USB Schematic.....................................................................123 Figure 64. PCI Bus Layout Example for Four PCI Connectors .......................................124 Figure 65. External Circuitry of RTC Oscillator................................................................126 Figure 66. Diode Circuit to Connect RTC External Battery..............................................127 Figure 67. RTCRESET External Circuit for the ICH RTC................................................128 Figure 68. Platform Clock Architecture (2 DIMMs)..........................................................132 Figure 69. Universal Platform Clock Architecture (3 DIMMs)..........................................134 Figure 70. Clock Routing Topologies ..............................................................................135 Figure 71. Power Delivery Map........................................................................................142 Figure 72. Pull-Up Resistor Example ..............................................................................145 Figure 73. G3-S0 Transition ............................................................................................148 Figure 74. S0-S3-S0 Transition .......................................................................................149 Figure 75. S0-S5-S0 Transition .......................................................................................150 Figure 76. VDDQ Power Sequencing Circuit...................................................................152 Figure 77. Example 1.85V/3.3V Power Sequencing Circuit ............................................153 Figure 78. 3.3V/V5REF Sequencing Circuitry .................................................................154 Figure 79. V5REF Circuitry..............................................................................................169
Tables
Table 1. Processor Considerations for Universal Socket 370 Design...............................29 Table 2. GMCH Considerations for Universal Socket 370 Design ....................................30 Table 3. ICH Considerations for Universal Socket 370 Design .........................................30 Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design ..................31 Table 5. Determining the Installed Processor via Hardware Mechanisms ........................35 Table 6. Intel Pentium III Processor AGTL/AGTL+ Parameters for Example Calculations ................................................................................................................44 1 Table 7. Example TFLT_MAX Calculations for 133 MHz Bus ..............................................45 Table 8. Example TFLT_MIN Calculations (Frequency Independent) ....................................45 1, 2, 3 Table 9. Trace Guidelines for Figure 19 ....................................................................46 Table 10. Trace Width:Space Guidelines..........................................................................46 Table 11. Routing Guidelines for Non-AGTL/Non-AGTL+ Signals....................................49 Table 12. Processor Pin Definition Comparison................................................................52 Table 13. Resistor Values for CLKREF Divider (3.3V Source)..........................................57 Table 14. RESET#/RESET2# Routing Guidelines (see Figure 25)...................................58 Table 15. Component Recommendations Inductor........................................................61 Table 16. Component Recommendations Capacitor .....................................................61 Table 17. Component Recommendation Resistor .........................................................61 Table 18. System Memory 2-DIMM Solution Space..........................................................71 Table 19. System Memory 3-DIMM Solution Space..........................................................74 Table 20. AGP 2.0 Signal Groups .....................................................................................83 Table 21. AGP 2.0 Data/Strobe Associations....................................................................83 Table 22. AGP 2.0 Routing Summary ...............................................................................87 Table 23. AGP 2.0 Routing Summary ...............................................................................91 Table 24. TYPDET#/VDDQ Relationship ..........................................................................93 Table 25. Connector/Add-in Card Interoperability .............................................................98 Table 26. Voltage/Data Rate Interoperability.....................................................................98 Table 27. AC97 Configuration Combinations .................................................................119 Table 28. Intel CK-815 (2-DIMM) Clocks.......................................................................131 Table 29. Intel CK-815 (3-DIMM) Clocks.......................................................................133 Table 30. Simulated Clock Routing Solution Space ........................................................136 Table 31. Simulated Clock Skew Assumptions ...............................................................138 Table 32. Power Delivery Terminology............................................................................141 Table 33. Power Sequencing Timing Definitions.............................................................151 Table 34. Recommendations For Unused AGP Port ......................................................159
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Revision History
Rev. No. -001 Initial Release. Description Date April 2001
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Introduction
This design guide organizes Intels design recommendations for the Intel 815 chipset platform for use with the Universal Socket 370. In addition to providing motherboard design recommendations (e.g., layout and routing guidelines), this document also addresses system design issues (e.g., thermal requirements). This document contains design recommendations, board schematics, debug recommendations, and a system checklist. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. Board designers can use the schematics in Appendix A: Customer Reference Board (CRB) as a reference. While the schematics cover specific designs, the core schematics will remain the same for most Intel 815 chipset designs for use with the Universal Socket 370. Consult the debug recommendations when debugging your design. However, these debug recommendations should be understood before completing board design, to ensure that the debug port, in addition to other debug features, are implemented correctly. The Intel 815 chipset platform supports the following processors: Intel Pentium III processor based on 0.18 micron technology (CPUID = 068xh). Intel Celeron processor based on 0.18 micron technology (CPUID = 068xh). This applies to Celeron 533A MHz and 566 MHz processors Future 0.13 micron socket 370 processors Note: The system bus speed supported by the design is based on the capabilities of the processor, chipset, and clock driver. Note: The Intel 815 chipset for use with the universal socket 370 is not compatible with the Intel Pentium II processor (CPUID = 066xh) 370-pin socket.
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1.1
Terminology
This section describes some of the terms used in this document. Additional power delivery term definitions are provided at the beginning of Chapter 12, Power Delivery.
Term
Aggressor
Description
A network that transmits a coupled signal to another network is called the aggressor network. A network that transmits a coupled signal to another network is called the aggressor network. Accelerated Graphics Port Refers to processor bus signals that are implemented using either Assisted Gunning Transceiver Logic (AGTL+) or its lower voltage variant (AGTL), depending on which processor is being used. A component or group of components that, when combined, represent a single load on the AGTL+ bus. The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks. Backward Crosstalkcoupling that creates a signal in a victim network that travels in the opposite direction as the aggressors signal. Forward Crosstalkcoupling that creates a signal in a victim network that travels in the same direction as the aggressors signal. Even Mode Crosstalkcoupling from single or multiple aggressors when all the aggressors switch in the same direction that the victim is switching. Odd Mode Crosstalkcoupling from single or multiple aggressors when all the aggressors switch in the opposite direction that the victim is switching.
Aggressor
AGP AGTL/AGTL+
Bus Agent
Crosstalk
GMCH
Graphics and Memory Controller Hub. A component of the Intel 815 chipset platform for use with the Universal Socket 370 Intel 82801AA I/O Controller Hub component. Inter-symbol interference is the effect of a previous signal (or transition) on the interconnect delay. For example, when a signal is transmitted down a line and the reflections due to the transition have not completely dissipated, the following data transition launched onto the bus is affected. ISI is dependent upon frequency, time delay of the line, and the reflection coefficient at the driver and receiver. ISI can impact both timing and signal integrity. The distance between agent 0 pins and the agent pins at the far end of the bus. The electrical contact point of a semiconductor die to the package substrate. A pad is only observable in simulation. The contact point of a component package to the traces on a substrate such as the motherboard. Signal quality and timings can be measured at the pin.
ICH ISI
Network Length Pad
Pin
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Term
Ringback
Description
The voltage that a signal rings back to after achieving its maximum absolute value. Ringback may be due to reflections, driver oscillations, or other transmission line phenomena. The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of bus agent in the system. Simultaneous Switching Output (SSO) Effects refers to the difference in electrical timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., low-to-high) or in the same direction (e.g., high-to-low). These are respectively called odd-mode switching and even-mode switching. This simultaneous switching of multiple outputs creates higher current swings that may cause additional propagation delay (or push-out), or a decrease in propagation delay (or pull-in). These SSO effects may impact the setup and/or hold times and are not always taken into account by simulations. System timing budgets should include margin for SSO effects. The branch from the bus trunk terminating at the pad of an agent. The system bus is the processor bus. The main connection, excluding interconnect branches, from one end agent pad to the other end agent pad. Minimum voltage observed for a signal to extend below VSS at the device pad. Refers to the Intel 815 chipset using the universal PGA370 socket. In general, these designs support 66/100/133 MHz system bus operation, VRM 8.5 DC-DC converter guidelines, and Intel Celeron processors (CPUID=068xh), Intel Pentium III processor (CPUID=068xh), and future Pentium III processors in single-microprocessor based designs. A network that receives a coupled crosstalk signal from another network is called the victim network.
Setup Window
SSO
Stub System Bus Trunk
Undershoot Universal Socket 370
Victim
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1.2
Reference Documents
Document Intel 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet Intel 82802AB/82802AC Firmware Hub (FWH) Datasheet Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub Datasheet Pentium II Processor Developers Manual Pentium III Processor Specification Update (latest revision from website)

Document Number / Location 298351 290658 290655 243341 (http://developer.intel .com/design/Pentium III/specupdt/) 245085 243330 243332 (ftp://download.intel.c om/technology/agp/d ownloads/agp20.pdf)
AP 907 Pentium III Processor Power Distribution Guidelines AP-585 Pentium II Processor AGTL+ Guidelines AP-587 Pentium II Processor Power Distribution Guidelines Accelerated Graphics Port Specification, Revision 2.0

PCI Local Bus Specification, Revision 2.2 Universal Serial Bus Specification, Revision 1.0
1.3
System Overview
The Intel 815 chipset for use with the Universal Socket 370 contains a Graphics Memory Controller Hub (GMCH) component and I/O Controller Hub (ICH) component for desktop platforms. The GMCH provides the processor interface (optimized for the Pentium III processor (CPUID = 068xh) and future 0.13 micron 370 socket processors), DRAM interface, hub interface, and an accelerated Graphics Port (AGP) interface or internal graphics. This product provides flexibility and scalability in graphics and memory subsystem performance. Competitive internal graphics may be scaled via an AGP card interface, and PC100 SDRAM system memory may be scaled to PC133 system memory. The Accelerated Hub Architecture interface (i.e., the chipset component interconnect) is designed into the chipset to provide an efficient, high-bandwidth communication channel between the GMCH and the I/O controller hub. The chipset architecture also enables a security and manageability infrastructure through the Firmware Hub component. An ACPI-compliant Intel 815 chipset platform for use with the universal socket 370 can support the Full-on (S0), Stop Grant (S1), Suspend to RAM (S3), Suspend to Disk (S4), and Soft-off (S5) power management states. The chipset also supports Wake-on-LAN* for remote administration and troubleshooting. The chipset architecture removes the requirement of the ISA expansion bus that was traditionally integrated into the I/O subsystem of PCIsets/AGPsets. This removes many of the conflicts experienced when installing hardware and drivers into legacy ISA systems. The
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elimination of ISA provides true plug-and-play for the platform. Traditionally, the ISA interface was used for audio and modem devices. The addition of AC97 allows the OEM to use softwareconfigurable AC97 audio and modem coder/decoders (codecs), instead of the traditional ISA devices.
1.3.1
System Features
The Intel 815 chipset for use with the Universal Socket 370 platform contains two components: the Intel 82815 Graphics and Memory Controller Hub (GMCH) and the Intel 82801AA I/O Controller Hub (ICH). The GMCH integrates a 66/100/133 MHz, P6 family system bus controller, integrated 2D/3D graphics accelerator or AGP (2X/4X) discrete graphics card, 100/133 MHz SDRAM controller, and a high-speed accelerated hub architecture interface for communication with the ICH. The ICH integrates an Ultra ATA/66 controller, USB host controller, LPC interface controller, FWH interface controller, PCI interface controller, AC97 digital controller, and a hub interface for communication with the GMCH.
Figure 1. System Block Diagram
Processor
66/100/133 MHz system bus AGP G raphics Card or Display Cache (AGP in-line m em ory m odule) Chipset AG P 2X/4X G MCH (544 BGA)
Analog display out Digital video out Hub interface 2x USB 2x IDE Audio codec Modem codec AC97 ICH
100/133 MHz SDRAM
PCI bus PCI slots
LPC I/F
KBC/SIO
FW H Flash BIO S
sys_blk
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1.3.2
Component Features
Figure 2. GMCH Block Diagram

System bus (66/100/133 MHz)
Processor I/F
System memory I/F
SDRAM 100/133 MHz, 64 bit
Primary display GPA or AGP 2X/4X card AGP I/F Data stream control & dispatch Overlay H/W cursor 3D pipeline 2D (blit engine) Internal graphics RAMDAC FP / TVout Monitor Digital video out
Local memory I/F
Hub I/F
Hub
comp_blk_1
1.3.2.1
Graphics Memory Controller Hub (GMCH)

Processor/System Bus Support Optimized for Intel Pentium III processors (CPUID = 068xh) at 133 MHz system bus frequency Support for Intel Celeron processors (CPUID = 068xh); 66 MHz system bus Supports 32-bit AGTL or AGTL+ bus addressing Supports uniprocessor systems Utilizes AGTL and AGTL+ bus driver technology (gated AGTL/AGTL+ receivers for reduced power) Integrated DRAM controller 32 MB to 512 MB using 16-Mb/64-Mb/128-Mb technology Supports up to three double-sided DIMMS (six rows) 100 MHz, 133 MHz SDRAM interface 64-bit data interface Standard Synchronous DRAM (SDRAM) support (x-1-1-1 access) Supports only 3.3V DIMM DRAM configurations No registered DIMM support Support for symmetrical and asymmetrical DRAM addressing Support for x8, x16 DRAM device width Refresh mechanism: CAS-before-RAS only Support for DIMM serial PD (presence detect) scheme via SMbus interface STR power management support via self-refresh mode using CKE
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Accelerated Graphics Port (AGP) Interface Supports AGP 2.0, including 4X AGP data transfers, but not the 2X/4X Fast Write protocol AGP universal connector support via dual-mode buffers to allow AGP 2.0 3.3V or 1.5V signaling 32-deep AGP request queue AGP address translation mechanism with integrated fully associative 20-entry TLB High-priority access support Delayed transaction support for AGP reads that can not be serviced immediately AGP semantic traffic to the DRAM is not snooped on the system bus and is therefore not coherent with the processor caches Integrated Graphics Controller Full 2D/3D/DirectX acceleration Texture-mapped 3D with point sampled, bilinear, trilinear, and anisotropic filtering Hardware setup with support for strips and fans Hardware motion compensation assist for software MPEG/DVD decode Digital Video Out interface adds support for digital displays and TV-Out PC99A/PC2001 compliant Integrated 230 MHz DAC Integrated Local Graphics Memory Controller (Display Cache) 0 MB to 4 MB (via Graphics Performance Accelerator) using zero, one, or two parts 32-bit data interface 133 MHz memory clock Supports ONLY 3.3V SDRAMs Packaging/Power 544 BGA with local memory port 1.85V ( 3% within margins of 1.795V to 1.9V) core and mixed 3.3V, 1.5V, and AGTL/AGTL+ I/O
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1.3.2.2
Intel 82801AA I/O Controller Hub (ICH)

The I/O Controller Hub provides the I/O subsystem with access to the rest of the system, as follows: Upstream accelerated hub architecture interface for access to the GMCH PCI 2.2 interface (6 PCI Request/Grant pairs) Bus master IDE controller; supports Ultra ATA/66 USB controller I/O APIC SMBus controller FWH interface LPC interface AC97 2.1 interface Integrated system management controller Alert on LAN* IRQ controller
Packaging/Power 241 BGA 3.3V core and 1.8V and 3.3V standby
1.3.2.3
Firmware Hub (FWH)

The hardware features of the firmware hub include: An integrated hardware Random Number Generator (RNG) Register-based locking Hardware-based locking 5 GPIs
Packaging/Power 40-L TSOP and 32-L PLCC 3.3V core and 3.3V / 12V for fast programming
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1.3.3
1.3.3.1
Platform Initiatives
Universal Socket 370 Design
The Intel 815 chipset platform for use with the Universal Socket 370 allows systems designers to build one system that is compatible with the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors. When implemented, the Intel 815 chipset platform for use with the Universal Socket 370 can detect which processor is present in the socket and function accordingly.
1.3.3.2
PC 133
The Intel PC133 initiative provides the memory bandwidth necessary to obtain high performance from the processor and AGP graphics controllers. The platforms SDRAM interface supports 100 MHz and 133 MHz operations. The latter delivers 1.066 GB/s of theoretical memory bandwidth compared with the 800-MB/s theoretical memory bandwidth of 100 MHz SDRAM systems.
1.3.3.3
Accelerated Hub Architecture Interface

As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge becomes significant. With the addition of AC97 and Ultra ATA/66, coupled with the existing USB, I/O requirements could affect PCI bus performance. The chipset platforms accelerated hub architecture ensures that the I/O subsystem, both PCI and integrated I/O features (IDE, AC97, USB), receives adequate bandwidth. By placing the I/O bridge on the accelerated hub architecture interface instead of PCI, I/O functions integrated into the ICH and the PCI peripherals are ensured the bandwidth necessary for peak performance.
1.3.3.4
Internet Streaming SIMD Extensions

The Pentium III processor (CPUID = 068xh) provides 70 new SIMD (single-instruction, multipledata) instructions. The new extensions are floating-point SIMD extensions. Intel MMX technology provides integer SIMD instructions. The Internet Streaming SIMD extensions complement the MMX technology SIMD instructions and provide a performance boost to floatingpoint-intensive 3D applications.
1.3.3.5
AGP 2.0
The AGP 2.0 interface allows graphics controllers to access main memory at more than 1 GB/s, which is twice the bandwidth of previous AGP platforms. AGP 2.0 provides the infrastructure necessary for photorealistic 3D. In conjunction with the Internet Streaming SIMD Extensions, AGP 2.0 delivers the next level of 3D graphics performance.
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1.3.3.6
Manageability
The Intel 815 chipset platform integrates several functions designed to manage the system and lower the systems total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lock-ups, without the aid of an external microcontroller.
TCO Timer
The ICH integrates a programmable TCO Timer. This timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock.
Processor Present Indicator

The ICH looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the ICH will reboot the system.
Function Disable
The ICH provides the ability to disable the following functions: AC97 Modem, AC97 Audio, IDE, USB, and SMBus. Once disabled, these functions no longer decode I/O, memory or PCI configuration space. Also, no interrupts or power management events are generated by the disabled functions.
Intruder Detect
The ICH provides an input signal (INTRUDER#) that can be attached to a switch that is activated when the system case is opened. The ICH can be programmed to generate an SMI# or TCO event as the result of an active INTRUDER# signal.
Alert on LAN*
The ICH supports Alert on LAN. In response to a TCO event (intruder detect, thermal event, processor boot failure), the ICH sends a hard-coded message over the SMBus. A LAN controller supporting the Alert on LAN protocol can decode this SMBus message and send a message over the network to alert the network manager.
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1.3.3.7
AC97
The Audio Codec 97 (AC97) specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or both an AC and an MC. The AC97 specification defines the interface between the system logic and the audio or modem codec, known as the AC97 Digital Link. The chipset platforms AC97 (with the appropriate codecs) not only replaces ISA audio and modem functionality, but also improves overall platform integration by incorporating the AC97 digital link. Using the chipsets integrated AC97 digital link reduces cost and eases migration from ISA. The ICH is an AC97-compliant controller that supports up to two codecs, with independent PCI functions for audio and modem. The ICH communicates with the codec(s) via a digital serial link called the AC-link. All digital audio/modem streams and command/status information are communicated over the AC-link. Microphone input and left and right audio channels are supported for a high-quality, two-speaker audio solution. Wake-on-ring-from-suspend also is supported with an appropriate modem codec. By using an audio codec, the AC97 digital link allows for cost-effective, high-quality, integrated audio. In addition, an AC97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC97. The chipset platforms integrated digital link allows two external codecs to be connected to the ICH. The system designer can provide audio with an audio codec or a modem with a modem codec. For systems requiring both audio and a modem, there are two solutions: the audio codec and the modem codec can be integrated into an AMC, or separate audio and modem codecs can be connected to the ICH. Modem implementation for different countries must be taken into consideration, as telephone systems may vary. By implementing a split design, the audio codec can be on board and the modem codec can be placed on a riser. Intel is developing an AC97 digital link connector. With a single integrated codec, or AMC, both audio and modem can be routed to a connector near the rear panel where the external ports can be located.
1.3.3.8
Low-Pin-Count (LPC) Interface

In the Intel 815 chipset platform, the Super I/O (SIO) component has migrated to the Low-PinCount (LPC) interface. Migration to the LPC interface allows for lower-cost Super I/O designs. The LPC Super I/O component requires the same feature set as traditional Super I/O components. It should include a keyboard and mouse controller, floppy disk controller, and serial and parallel ports. In addition to the Super I/O features, an integrated game port is recommended, because the AC97 interface does not provide support for a game port. In systems with ISA audio, the game port typically existed on the audio card. The fifteen-pin game port connector provides for two joysticks and a two-wire MPU-401 MIDI interface. Consult your preferred Super I/O vendor for a comprehensive list of the devices offered and the features supported. In addition, depending on system requirements, specific system I/O requirements may be integrated into the LPC Super I/O. For example, a USB hub may be integrated to connect to the ICH USB output and extend it to multiple USB connectors. Other SIO integration targets include a device bay controller or an ISA-IRQ-to-serial-IRQ converter to support a PCI-to-ISA bridge. Contact your Super I/O vendor to ensure the availability of the desired LPC Super I/O features.
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General Design Considerations

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This document provides motherboard layout and routing guidelines for systems based on the Intel 815 chipset platform for use with the Universal Socket 370. The document does not discuss the functional aspects of any bus or the layout guidelines for an add-in device. If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations be completed for each design. Even when the guidelines are followed, it is recommended that critical signals be simulated to ensure proper signal integrity and flight time. Any deviation from these guidelines should be simulated. The trace impedance typically noted (i.e., 60 15%) is the nominal trace impedance for a 5-mil-wide trace. That is, it is the impedance of the trace when not subjected to the fields created by changing current in neighboring traces. When calculating flight times, it is important to consider the minimum and maximum impedance of a trace, based on the switching of neighboring traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce the settling time. Coupling between two traces is a function of the coupled length, the distance separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects of trace-to-trace coupling, the routing guidelines documented in this section should be followed. Additionally, the routing guidelines in this document are created using a PCB stack-up similar to that described in the following section.
2.1
Nominal Board Stackup

The Intel 815 chipset platform requires a board stack-up yielding a target impedance of 60 15%, with a 5-mil nominal trace width. Figure 3 shows an example stack-up that achieves this. It is a 4-layer printed circuit board (PCB) construction using 53%-resin, FR4 material.
Figure 3. Board Construction Example for 60 Nominal Stackup

Component-side layer 1: oz. Cu 4.5-mil prepreg Power plane layer 2: 1 oz. Cu
~48-mil Core
Ground layer 3: 1 oz. Cu 4.5-mil prepreg Solder-side layer 4: oz. Cu
Total thickness: 62 mils
board_4.5mil_stackup
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Component Quadrant Layouts

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Figure 4 illustrates the relative signal quadrant locations on the GMCH ballout. It does not represent the actual ballout. Refer to the Intel 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for the actual ballout. Figure 4. GMCH 544-Ball BGA* CSP Quadrant Layout (Top View)
Pin 1 corner
System M emory
Hub Interface
AGP / Display Cache
GM CH
System Bus
Video
quad_GM CH
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Figure 5 illustrates the relative signal quadrant locations on the ICH ballout. It does not represent the actual ballout. Refer to the Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub Datasheet for the actual ballout. Figure 5. ICH 241-Ball BGA* CSP Quadrant Layout (Top View)
Pin 1 corner PCI
Processor
ICH AC'97, SMBus
Hub interface
LPC
IDE
quad_ICH
Figure 6. Firmware Hub (FWH) Packages

4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 3 2 1 32 31 30
5 6 7 8 9 10 11 12 13 FWH interface (32-lead PLCC, 0.450" x 0.550") Top view
29 28 27 26 25 24 23 22 21
FWH interface (40-lead TSOP)
14
15
16
17
18
19
20
pkg_FWH
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4
4.1

Universal Socket 370 Definitions
The universal socket 370 platform supports Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors. The Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) have different requirements for functioning properly in a platform than the future 0.13 micron socket 370 processors. It is necessary to understand these differences and how they affect the design of the platform. Refer to Table 1 through Table 4 for a high-level description of the differences that require additional circuitry on the motherboard. Specific details on implementing this circuitry are discussed further in this chapter. For a detailed description of the differences between the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processor pins, refer to Section 5.4. Table 1. Processor Considerations for Universal Socket 370 Design
Signal Name or Pin Number Function In Intel Pentium III Processor (CPUID=068xh) and Intel Celeron Processor (CPUID=068xh) VSS Function In Future 0.13 Micron Socket 370 Processors Implementation for Universal Socket 370 Design
AF36
No connect
Addition of circuitry that generates a processor identification signal used to configure board-level operation. Addition of FET switch to ground or VTT, controlled by processor identification signal. Note: FET must have no more than 100 milliohms resistance between source and drain.
AG1
VSS
VTT
AJ3
VSS
RESET
Addition of stuffing option for pull-down to ground, which lets designer prevent future 0.13 micron socket 370 processors from being used with incompatible stepping of Intel 82815 GMCH. Addition of resistor-divider network to provide 1.0V, which will satisfy voltage tolerance requirements of the Intel Pentium III processor (CPUID=068xh) and Intel Celeron processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors. Addition of FET switch to provide proper voltage, controlled by processor identification signal.
AK22
GTL_REF
VCMOS_REF
PICCLK
Requires 2.5V
Requires 2.0V
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Signal Name or Pin Number
Function In Intel Pentium III Processor (CPUID=068xh) and Intel Celeron Processor (CPUID=068xh) Requires 2.5V
Function In Future 0.13 Micron Socket 370 Processors
Implementation for Universal Socket 370 Design
PWRGOOD
Requires 1.8V
Addition of resistor-divider network to provide 2.1V, which will satisfy voltage tolerance requirements of the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors. Modification to VTT generation circuit to switch between 1.5V or 1.25V, controlled by processor identification signal. Addition of VTTPWRGD generation circuit.
VTT
Requires 1.5V
Requires 1.25V
VTTPWRGD
Not used
Input signal to future 0.13 micron socket 370 processors to indicate that VID signals are stable
Table 2. GMCH Considerations for Universal Socket 370 Design

Pin Name/Number SMAA12 Issue New strap required for determining Pentium III Processor (CPUID=068xh) and Intel Celeron Processor (CPUID=068xh) or Future 0.13 micron socket 370 processors
Implementation For Universal Socket 370 Design Addition of FET switch controlled by processor identification signal.
Table 3. ICH Considerations for Universal Socket 370 Design

Signal PWROK Issue GMCH and Intel CK-815 must not sample BSEL[1:0] until VTTPWRGD asserted. ICH must not initialize before Intel CK-815 clocks stabilize Implementation For Universal Socket 370 Design Addition of circuitry to have VTTPWRGD gate PWROK from power supply to ICH. The ICH will hold the GMCH in reset until VTTPWRGD asserted plus 20 ms time delay to allow Intel CK-815 clocks to stabilize.
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Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design

Signal VDD Issue Intel CK-815 does not support VTTPWRGD Implementation For Universal Socket 370 Design Addition of FET switch which supplies power to VDD only when VTTPWRGD is asserted. Note: FET must have no more than 100 milliohms resistance between source and drain.
4.2
4.2.1
Processor Design Requirements

Use of Universal Socket 370 Design with Incompatible GMCH
The universal socket 370 design is intended for use with the Intel 815 chipset platform for use with the universal socket 370. A universal socket 370 design populated with an earlier stepping of the GMCH is not compatible with future 0.13 micron socket 370 processors and, if used, will cause eventual failure of these processors. To prevent a future 0.13 micron socket 370 processor from being used with an incompatible stepping of the GMCH, the recommendation is to lay out the site for a 0 pull-down to ground on processor pin AJ3. This pin is a RESET# signal on future 0.13 micron socket 370 processors and, by populating the resistor, these future processors will be prevented from functioning when placed in a board with an incompatible stepping of the GMCH. All Pentium III (CPUID=068xh) and Celeron (CPUID=068xh) processors will continue to boot normally. Not populating the resistor will allow future 0.13 micron socket 370 processors to boot. Refer to Figure 7 for an example implementation.
Figure 7. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370 Designs Using A-2 GMCH
Future 0.13 Micron Socket 370 Processors
AJ3
Tual_pin_aj3
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4.2.2
Identifying the Processor at the Socket

For the platform to configure for the requirements of the processor in the socket, it must first identify whether the processor is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or a future 0.13 micron socket 370 processors. Pin AF36 is a ground pin on a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh); pin AF36 is an unconnected pin on future 0.13 micron Socket 370 processors. Referring to Figure 8, the platform uses a detect circuit connected to this processor pin. If a future 0.13 micron Socket 370 processor is present in the socket, the TUAL5 reference schematic signal will be pulled to the 5V rail and the TUAL5# reference schematic signal will be pulled to ground. Otherwise, for a Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh), the TUAL5 reference schematic signal will be pulled to ground and the TUAL5# will be pulled to the 5V rail.
Figure 8. Processor Detect Mechanism at Socket/TUAL5 Generation Circuit

VCC5
VCC5 VT T 2.2 K
TUAL5 2.2 K 1 K M OSFET N
Processor Pin AF36
NPN TUAL5#
Proc_Detect
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4.2.3
Setting the Appropriate Processor VTT Level

Because the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors require different VTT levels, the platform must be able to provide the appropriate voltage level after determining which processor is in the socket. Referring to Figure 9, the TUAL5 reference schematic signal serves to control the FET, and by doing so determines whether the voltage regulator supplies 1.25V or 1.5V to VTT for AGTL or AGTL+, respectively.
Figure 9. VTT Selection Switch

VCC3_3
LT1587-ADJ Vin 10 F Vout ADJ 49.9 1% 22 F Tantalum VTT
0.1 F
MO SFET N TUAL5
10 1%
Vtt_Sel_Sw
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4.2.4
VTT Processor Pin AG1

Processor pin AG1 requires additional attention since it is a ground pin on a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) and a VTT pin on a future 0.13 micron socket 370 processor. A separate switch controlled by the TUAL5 reference schematic signal determines whether pin AG1 is pulled to ground or VTT. Refer to Figure 10 for an example implementation.
Figure 10. Switching Pin AG1

VTT
TUAL5 Processor Pin AG 1
1 K
Note: The FET m ust have no m ore than 100 m illiohm s resistance between the source and the drain.
AG 1_Switch
4.2.5
Identifying the Processor at the GMCH

The GMCH determines whether the socket contains a future 0.13 micron socket 370 processor or Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) based on the input to pin SMAA12 on the GMCH. In a system using future 0.13 micron socket 370 processors, SMAA12 will be pulled down during reset to indicate to the GMCH that a future 0.13 micron socket 370 processor is in the socket. Refer to Figure 11. for an example implementation.
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Figure 11. Processor Identification Strap on GMCH

SMAA[12]
10 K
TUAL5
Proc_ID_Strap
Table 5 provides the logic decoding to determine which processor is installed in a PGA370 design. Table 5. Determining the Installed Processor via Hardware Mechanisms
Processor Pin AF36 Hi-Z Low X CPUPRES# 0 0 1 Notes Future 0.13 micron socket 370 processor installed. Intel Pentium III processor (CPUID=068xh) or Intel Celeron processor (CPUID=068xh) installed. No processor installed.
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4.2.6
Configuring Non-VTT Processor Pins

When asserted, the VTTPWGRD signal must be level-shifted to 12V to properly drive the gating circuitry of the Intel CK-815. Furthermore, while the VTTPWRGD signal is connected to the VTTPWRGD pin on a future 0.13 micron socket 370 processor, on a Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh) that same pin is a ground. To provide proper functionality, a 1.0 k resistor must be placed in series between the circuitry that generates the signal VTTPWRGD and the processor pin VTTPWRGD. Refer to Figure 12 for an example implementation. Voltage regulators that generate the standard VTTPWRGD signal are available.
Figure 12. VTTPWRGD Configuration Circuit

VCC12
VCC5
2.2 K
VTT PW RGD12
BAT54C VCC5
2 1
VTT
VCC5 V1_8SB ASSERTED LOW VCC5 20 K 732 1% VTT

5 3 2
IN- 1 Vcc IN+ 1 O ut 1
MOSFET N
VTTPW RGD 1 K
V1_8SB
1 K
MOSFET N
1 K
8 1 7
IN+ 2 O ut 2 IN- 2
G nd
LM 393 Ch1 1 1%
0.1 F
LM393 Ch2 VTTPW RGD5#
2.0 m s delay nom inal
VTTPW RGD_Config
NOTE:
The diode is included so that repeated pressing of the reset or power button does not cause the capacitor to build up enough charge to circumvent the 20 ms delay.
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4.2.7
VCMOS Reference
In previous platforms supporting the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh), VCMOS was generated by the processor itself. The future 0.13 micron socket 370 processors do not generate VCMOS, and the universal platform is required to generate this separately on the motherboard. Processor pin AK22, which is a GTL_REF pin on a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh), has been changed to a VCMOS_REF pin on future 0.13 micron socket 370 processors. Referring to Figure 13, a network of resistors and a capacitor must be added so that this pin operates appropriately for whichever processor is in the socket.
Figure 13. GTL_REF/VCMOS_REF Voltage Divider Network

VCM OS
75 1% Processor Pin AK22 150 1% 0.1 F
GTL_CMOS_R ef
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4.2.8
Processor Signal PWRGOOD

The processor signal PWRGOOD is specified at different voltage levels depending on whether it is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or whether it is a future 0.13 micron socket 370 processor. As there is an overlap between the ranges of accepted voltage levels for these two processor groups, a resistor divider network that provides 2.1V will satisfy the requirements of all supported processors. See Figure 14 for an example implementation.
Figure 14. Resistor Divider Network for Processor PWRGOOD

VCC2_5
330
PW RGOO D from ICH2
PW RGOOD to Processor
1.8
PW RGOOD_D ivider
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4.2.9
APIC Clock Voltage Switching Requirements

The processors APIC clock is also specified at different voltage levels depending on whether it is for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) or whether it is for a future 0.13 micron socket 370 processor. There is no overlap in the range of accepted voltage levels for the two processor groups, so a voltage switch is required to ensure proper operation. Figure 15 shows an example implementation.
Figure 15. Voltage Switch For APIC Clock from Clock Synthesizer to Processor
IOAPIC
30
APICCLK_CPU
130
TUAL5
MOSFET N
API_CLK_SW
NOTE:
The 30 resistor represents the series resistor typically used in connecting the APIC clock to the processor.
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4.2.10
GTLREF Topology and Layout

In a platform supporting the future 0.13 micron socket 370 processors, the voltage requirements for GTLREF are different for the processor and the chipset. The GTLREF on the processor is specified to be 2/3 * VTT, while the GTLREF on the chipset is 0.7 * VTT. This difference requires that separate resistor sites be added to the layout to split the GTLREF sources. In a universal motherboard design, a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) will be unaffected by the difference in GTLREF. The recommended GTLREF circuit topology is shown in Figure 16.
Note: If an A-2 stepping of the GMCH is used with the universal motherboard design, the GTLREF for the GMCH should be set at 2/3 * VTT. This requires changing the 63.4 , 1% resistor on the GMCH side to 75 , 1%. Figure 16. GTLREF Circuit Topology
VTT
63.4
75
GMCH
Processor
150
150
gtlref_circuit
GTLREF Layout and Routing Guidelines

Place all resistor sites for GTLREF generation close to the GMCH. Route GTLREF with as wide a trace as possible. Use one 0.1 F decoupling capacitor for every two GTLREF pins at the processor (four capacitors total). Place as close as possible (within 500 mils) to the Socket 370 GTLREF pins. Use one 0.1 F decoupling capacitor for each of the two GTLREF pins at the GMCH (two capacitors total). Place as close as possible to the GMCH GTLREF balls. Given the higher GTLREF level for the GMCH, a debug test hook should be added for validation purposes. The debug test hook should be placed on the processor signal ADS# and consists of laying down the site for a 56 pull-up to VTT. The resistor site should be located within 150 mils of the GMCH, and placed as close to the ADS# signal trace as possible.
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4.3
Power Sequencing on Wake Events

In addition to the mechanism for identifying the processor in the socket, special handling of wake events is required for the Intel 815 chipset platform that support functionality of the future 0.13 micron socket 370 processors. When a wake event is triggered, the GMCH and the Intel CK-815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events: 1. Power is not connected to the Intel CK-815-compliant clock driver until VTTPWRGD12 is asserted. 2. Clocks to the ICH stabilize before the power supply asserts PWROK to the ICH. There is no guarantee this will occur as the implementation for the previous step relies on the 12V supply. Thus, it is necessary to gate PWROK to the ICH from the power supply while the Intel CK-815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms. 3. ICH takes the GMCH out of reset. 4. GMCH samples BSEL[1:0]. Intel CK-815 will have sampled BSEL[1:0] much earlier.
4.3.1
Gating of Intel CK-815 to VTTPWRGD

System designers must ensure that the VTTPWRGD signal is asserted before the Intel CK-815compliant clock driver receives power. This is handled by having the 3.3V rail of the clock driver gated by the VTTPWRGD12 reference schematic signal. Unlike previous Intel 815 chipset designs, the 3.3V standby rail is not used to power the clock as the VTTPWRGD12 reference schematic signal will cut power to the clock when going into any sleep state. Refer to Figure 17 for an example implementation.
Figure 17. Gating Power to Intel CK-815

VCC3_3
MO SFET N
VTT PW RGD12 VDD on CK-815

Note: The FET m ust have no m ore than 100 m illiohm s resistance between the source and the drain.
Gating_Pwr
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4.3.2
Gating of PWROK to ICH

With power being gated to the Intel CK-815 by the signal VTTPWRGD12, it is important that the clocks to the ICH are stable before the power supply asserts PWROK to the ICH. As the clocking power gating circuitry relies on the 12V supply, there is no guarantee that these conditions will be met. This is why an estimated minimum time delay of 20 ms must be added after power is connected to the Intel CK-815 to give the clock driver sufficient time to stabilize. This time delay will gate the power supplys assertion of PWROK to the ICH. After the time delay, the power supply can safely assert PWROK to the ICH, with the ICH subsequently taking the GMCH out of reset. Refer to Figure 18 for an example implementation.
Figure 18. PWROK Gating Circuit For ICH

VDD on CK-815 VCC3_3
43 k
Note: Delay 20 m s after VDD on CK-815 is powered ICH_PW ROK 8.2 k
1.0 F
PW ROK
ICH_PW R OK_GATING
NOTE:
The diode is included so that repeated pressing of the reset or power button does not cause the capacitor to build up enough charge to circumvent the 20 ms delay.
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System Bus Design Guidelines

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The Pentium III processor delivers higher performance by integrating the Level-2 cache into the processor and running it at the processors core speed. The Pentium III processor runs at higher core and system bus speeds than previous-generation Intel IA-32 processors while maintaining hardware and software compatibility with earlier Pentium III processors. The new Flip Chip-Pin Grid Array 2 (FC-PGA2) package technology enables compatibility with previous Flip Chip-Pin Grid Array (FC-PGA) packages using the PGA370 socket. This section presents the considerations for designs capable of using the Intel 815 chipset platform with the full range of Pentium III processors using the PGA370 socket.
5.1
System Bus Routing Guidelines

The following layout guide supports designs using Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors with the Intel 815 chipset platform for use with the universal socket 370. The solution covers system bus speeds of 66/100/133 MHz for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors. All processors must also be configured to 56 on-die termination.
5.1.1
Initial Timing Analysis

Table 6 lists the AGTL/AGTL+ component timings of the processors and GMCH defined at the pins. Note: These timings are for reference only. Obtain each processors specifications from the respective processor datasheet and the chipset values from the appropriate Intel 815 chipset datasheet.
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Table 6. Intel Pentium III Processor AGTL/AGTL+ Parameters for Example Calculations
IC Parameters Clock to Output maximum (TCO_MAX) Clock to Output minimum (TCO_MIN) Setup time (TSU_MIN) Intel Pentium III Processor at 133 MHz System Bus GMCH 4.1 ns 1.05 ns 2.65 ns Notes 1, 2 1, 2 1, 2,3
3.25 ns (for 66/100/133 MHz system bus speeds) 0.40 ns (for 66/100/133 MHz system bus) 1.20 ns (for BREQ Lines) 0.95 ns (for all other AGTL/AGTL+ Lines @ 133 MHz) 1.20 ns (for all other AGTL/AGTL+ Lines @ 66/100 MHz)
Hold time (THOLD)
1.0 ns (for 66/100/133 MHz system bus speeds)
0.10 ns
NOTES: 1. All times in nanoseconds. 2. Numbers in table are for reference only. These timing parameters are subject to change. Check the appropriate component datasheet for the valid timing parameter values. 3. TSU_MIN = 2.65 ns assumes that the GMCH sees a minimum edge rate equal to 0.3 V/ns.
Table 7 contains an example AGTL+ initial maximum flight time, and Table 8 contains an example minimum flight time calculation for a 133 MHz, uniprocessor system using the Pentium III processor and the Intel 815 chipset platforms system bus. Note that assumed values were used for the clock skew and clock jitter. Note: The clock skew and clock jitter values depend on the clock components and the distribution method chosen for a particular design and must be budgeted into the initial timing equations, as appropriate for each design. Table 7and Table 8 were derived assuming the following: CLKSKEW = 0.20 ns (Note: This assumes that the clock driver pin-to-pin skew is reduced to 50 ps by tying the two host clock outputs together (i.e., ganging) at the clock driver output pins, and that the PCB clock routing skew is 150 ps. The system timing budget must assume 0.175 ns of clock driver skew if outputs are not tied together as well as the use of a clock driver that meets the Intel CK-815 Clock Synthesizer/Driver Specification.) CLKJITTER = 0.250 ns See the respective processors datasheet, the appropriate Intel 815 chipset platform documentation, and the Intel CK-815 Clock Synthesizer/Driver Specification for details on clock skew and jitter specifications. Exact details regarding the host clock routing topology are provided with the platform design guideline.
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Table 7. Example TFLT_MAX Calculations for 133 MHz Bus

Driver Processor GMCH
2
Receiver Clk Period TCO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended TFLT_MAX GMCH Processor 7.50 7.50 3.25 4.1 2.65 1.20 0.20 0.20 0.25 0.25 0.40 0.40 1.1 1.35
NOTES: 1. All times in nanoseconds 2. BCLK period = 7.50 ns at 133.33 MHz
Table 8. Example TFLT_MIN Calculations (Frequency Independent)

Driver Processor GMCH Receiver GMCH Processor THOLD 0.10 1.00 ClkSKEW 0.20 0.20 TCO_MIN 0.40 1.05 Recommended TFLT_MIN 0.10 0.15
NOTES: All times in nanoseconds
The flight times in Table 7 include margin to account for the following phenomena that Intel observed when multiple bits are switching simultaneously. These multi-bit effects can adversely affect the flight time and signal quality and sometimes are not accounted for during simulation. Accordingly, the maximum flight times depend on the baseboard design, and additional adjustment factors or margins are recommended. SSO push-out or pull-in Rising or falling edge rate degradation at the receiver caused by inductance in the current return path, requiring extrapolation that causes additional delay Cross-talk on the PCB and inside the package which can cause variation in the signals Additional effects exist that may not necessarily be covered by the multi-bit adjustment factor and should be budgeted as appropriate to the baseboard design. These effects are included as MADJ in the example calculations in Table 7. Examples include: The effective board propagation constant (SEFF), which is a function of: Dielectric constant (r) of the PCB material Type of trace connecting the components (stripline or microstrip) Length of the trace and the load of the components on the trace. Note that the board propagation constant multiplied by the trace length is a component of the flight time, but not necessarily equal to the flight time.
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5.2
General Topology and Layout Guidelines
Figure 19. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)
G MCH
PGA370 socket
L(1):
Z 0 = 60 15%
sys_bus_topo_PGA370
Table 9. Trace Guidelines for Figure 19

Description GMCH to PGA370 socket trace
1, 2, 3
Min. Length (inches) 1.90
Max. Length (inches) 4.50
NOTES: 1. All AGTL/AGTL+ bus signals should be referenced to the ground plane for the entire route. 2. Use an intragroup AGTL/AGTL+ spacing : line width : dielectric thickness ratio of at least 2:1:1 for microstrip geometry. If r = 4.5, this should limit coupling to 3.4%. For example, intragroup AGTL+ routing could use 10-mil spacing, 5-mil traces, and a 5-mil prepreg between the signal layer and the plane it references (assuming a 4-layer motherboard design). 3. The recommended trace width is 5 mils, but not greater than 6 mils.
Table 10 contains the trace width space ratios assumed for this topology. Three types of cross-talk are considered in this guideline: Intragroup AGTL/AGTL+, Intergroup AGTL/AGTL+, and AGTL/AGTL+ to non-AGTL/AGTL+. Intragroup AGTL/AGTL+ cross-talk involves interference between AGTL/AGTL+ signals within the same group. Intergroup AGTL/AGTL+ cross-talk involves interference from AGTL/AGTL+ signals in a particular group to AGTL/AGTL+ signals in a different group. An example of AGTL/AGTL+ to non-AGTL/AGTL+ cross-talk is when CMOS and AGTL/AGTL+ signals interfere with each other. The AGTL/AGTL+ signals consist of the following groups: data signals, control signals, clock signals, and address signals. Table 10. Trace Width:Space Guidelines
Cross-Talk Type Intragroup AGTL/AGTL+ signals (same group AGTL/AGTL+) Intergroup AGTL/AGTL+ signals (different group AGTL/AGTL+) AGTL/AGTL+ to System Memory Signals AGTL/AGTL+ to non-AGTL/AGTL+ NOTES: 1. Edge-to-edge spacing. 2. Units are in mils. Trace Width:Space Ratios1, 2 5:10 or 6:12 5:15 or 6:18 5:30 or 6:36 5:25 or 6:24
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5.2.1
Motherboard Layout Rules for AGTL/AGTL+ Signals

Ground Reference
It is strongly recommended that AGTL/AGTL+ signals be routed on the signal layer next to the ground layer (referenced to ground). It is important to provide an effective signal return path with low inductance. The best signal routing is directly adjacent to a solid GND plane with no splits or cuts. Eliminate parallel traces between layers not separated by a power or ground plane. If a signal has to go through routing layers, the recommendations are in the following list. Note: Following these layout rules is critical for AGTL/AGTL+ signal integrity, particularly for 0.18-micron and smaller process technology. For signals going from a ground reference to a power reference, add capacitors between ground and power near the vias to provide an AC return path. One capacitor should be used for every three signal lines that change reference layers. Capacitor requirements are as follows: C=100 nF, ESR=80 m, ESL=0.6 nH. Refer to Figure 20 for an example of switching reference layers. For signals going from one ground reference to another, separate ground reference, add vias between the two ground planes to provide a better return path.
Figure 20. AGTL/AGTL+ Trace Routing

GMCH Layer 2 Layer 3
0-500 mils 1.5-3.5 inches
Processor 1.2V Power Plane Ground Plane Socket Pin
AGTL_trace_route
Reference Plane Splits

Splits in reference planes disrupt signal return paths and increase overshoot/undershoot due to significantly increased inductance.
Processor Connector Breakout

It is strongly recommended that AGTL/AGTL+ signals do not traverse multiple signal layers. Intel recommends breaking out all signals from the connector on the same layer. If routing is tight, break out from the connector on the opposite routing layer over a ground reference and cross over to main signal layer near the processor connector.
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Minimizing Cross-Talk
The following general rules minimize the impact of cross-talk in a high-speed AGTL/AGTL+ bus design: Maximize the space between traces. Where possible, maintain a minimum of 10 mils (assuming a 5-mil trace) between trace edges. It may be necessary to use tighter spacing when routing between component pins. When traces must be close and parallel to each other, minimize the distance that they are close together and maximize the distance between the sections when the spacing restrictions are relaxed. Avoid parallelism between signals on adjacent layers, if there is no AC reference plane between them. As a rule of thumb, route adjacent layers orthogonally. Since AGTL/AGTL+ is a low-signal-swing technology, it is important to isolate AGTL/AGTL+ signals from other signals by at least 25 mils. This will avoid coupling from signals that have larger voltage swings (e.g., 5V PCI). AGTL/AGTL+ signals must be well isolated from system memory signals. AGTL/AGTL+ signal trace edges must be at least 30 mils from system memory trace edges within 100 mils of the ball of the GMCH. Select a board stack-up that minimizes the coupling between adjacent signals. Minimize the nominal characteristic impedance within the AGTL/AGTL+ specification. This can be done by minimizing the height of the trace from its reference plane, which minimizes cross-talk. Route AGTL/AGTL+ address, data, and control signals in separate groups to minimize crosstalk between groups. Keep at least 15 mils between each group of signals. Minimize the dielectric used in the system. This makes the traces closer to their reference plane and thus reduces the cross-talk magnitude. Minimize the dielectric process variation used in the PCB fabrication. Minimize the cross-sectional area of the traces. This can be done by means of narrower traces and/or by using thinner copper, but the trade-off for this smaller cross-sectional area is higher trace resistivity, which can reduce the falling-edge noise margin because of the I*R loss along the trace.
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5.2.1.1
Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals
Table 11. Routing Guidelines for Non-AGTL/Non-AGTL+ Signals

Signal A20M# FERR# FLUSH# IERR# IGNNE# INIT# LINT[0] (INTR) LINT[1] (NMI) PICD[1:0] PREQ# PWRGOOD SLP# SMI# STPCLK THERMTRIP# NOTE: Trace Width 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils 5 mils Spacing to Other Traces 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils 10 mils Trace Length 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9 1 to 9
Route these signals on any layer or combination of layers.
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5.2.1.2
THRMDP and THRMDN

These traces (THRMDP and THRMDN) route the processors thermal diode connections. The thermal diode operates at very low currents and may be susceptible to cross-talk. The traces should be routed close together to reduce loop area and inductance.
Figure 21. Routing for THRMDP and THRMDN

Signal Y
1 Maximize (min. 20 mils)
THRMDP
2 Minimize
THRMDN
1 Maximize (min. 20 mils)
Signal Z
bus_routing_thrmdp-thrmdn
NOTES: 1. Route these traces parallel and equalize lengths within 0.5 inch. 2. Route THRMDP and THRMDN on the same layer.
5.2.1.3
Additional Routing and Placement Considerations

Distribute VTT with a wide trace. A 0.050 inch minimum trace is recommended to minimize DC losses. Route the VTT trace to all components on the host bus. Be sure to include decoupling capacitors. The VTT voltage should be 1.5V 3% for static conditions, and 1.5V 9% for worst-case transient conditions when the Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh) is present in the socket. If a future 0.13 micron socket 370 processor is being used, the VTT voltage should then be 1.25V 3% for static conditions, and 1.25V 9% for worst-case transient conditions. Place resistor divider pairs for VREF generation at the GMCH component. VREF also is delivered to the processor.
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5.3
Electrical Differences for Universal PGA370 Designs

There are several electrical changes between previous PGA370 designs and the universal PGA370 design, as follows: Changes to the PGA370 socket pin definitions. Addition of VTTPWRGD signal to ensure stable VID selection for future 0.13 micron socket 370 processors. Addition of THERMTRIP circuit to allow processor to detect catastrophic overheat. Addition of VID[25 mV] signal to support future 0.13 micron socket 370 processors. Processor VTT level is switchable to 1.25V or 1.5V, depending on which processor is present in the socket. In designs using future 0.13 micron socket 370 processors, the processor does not generate VCMOS_REF.
5.3.1
THERMTRIP Circuit
Figure 22. Example Implementation of THERMTRIP Circuit

VCC1_8SB VCC1.8 VCC3_3SB
R10 1 K
2 1 R11 1 K
2 1 1 2 R9 1 K
R12 22 K
Connect to ICH
1 SW _ON#
Q3 Q 2N3904
Therm trip#
Q2
Q2N3904
R8 1.6 K
Can Use M BT3904 Dual XSTR Part
Thermstrip
5.3.1.1
THERMTRIP Timing
When the THERMTRIP signal is asserted, both the VCC and VTT supplies to the processor must be turned off to prevent thermal runaway of the processor. The time required from THERMTRIP asserted to VCC rail at nominal is 5 sec and THERMTRIP asserted to VTT rail at nominal is 5 sec. System designers must ensure that the decoupling scheme used on these rails does not violate the THERMTRIP timing specifications.
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5.4
PGA370 Socket Definition Details

The following table compares the pin names and functions of the Intel processors supported in the Intel 815 chipset platform for use with the universal socket 370.
Table 12. Processor Pin Definition Comparison

Pin # Pin Name Intel Celeron Processor (CPUID=068xh) Reserved Reserved VCCCMOS Pin Name Intel Pentium III Processor (CPUID=068xh) VTT VTT VCCCMOS Pin Name Future 0.13 Micron Socket 370 Processors VTT VTT VTT Function
AA33 AA35 AB36
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage CMOS voltage level for Intel Pentium III processor (CPUID=068xh) and Intel Celeron processor (CPUID=068xh). AGTL termination voltage for future 0.13 micron socket 370 processors.
AD36
VCC1.5
VCC1.5
VTT
VCC1.5 for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). VTT for future 0.13 micron socket 370 processors.
AF36
VSS
VSS
NC
Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). No connect for future 0.13 micron socket 370 processors.
AG11
VSS
VSS
VTT
Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). VTT for future 0.13 micron socket 370 processors
AH4
Reserved
RESET#
RESET#
Processor reset for the Pentium III processor (068xh) and Future 0.13 micron socket 370 processors AGTL/AGTL+ termination voltage
AH20
Reserved
VTT
VTT
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Pin #
Pin Name Intel Celeron Processor (CPUID=068xh) VSS
Pin Name Intel Pentium III Processor (CPUID=068xh) VSS
Pin Name Future 0.13 Micron Socket 370 Processors RESET
Function
AJ31
Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). RESET for future 0.13 micron socket 370 processors
AK4
VSS
VSS
VTTPWRGD
Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). VID control signal on future 0.13 micron socket 370 processors.
AK16 AK22
Reserved GTL_REF
VTT GTL_REF
VTT VCMOS_REF
AGTL/AGTL+ termination voltage GTL reference voltage for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). CMOS reference voltage for future 0.13 micron socket 370 processors
AK36
VSS
VSS
VID[25mV]
Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). 25mV step VID select bit for future 0.13 micron socket 370 processors
AL13 AL21 AN3
Reserved Reserved GND
VTT VTT GND
VTT VTT DYN_OE
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). Dynamic output enable for future 0.13 micron socket 370 processors
AN11 AN15 AN21
Reserved Reserved Reserved
VTT VTT VTT
VTT VTT VTT
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage
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Pin #
Pin Name Intel Celeron Processor (CPUID=068xh) Reserved Reserved Reserved
Pin Name Intel Pentium III Processor (CPUID=068xh) VTT VTT Reserved
Pin Name Future 0.13 Micron Socket 370 Processors VTT VTT VTT
Function
E23 G35 G37
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). AGTL termination voltage for future 0.13 micron socket 370 processors
N372
NC
NC
NCHCTRL
No connect for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). NCHCTRL for future 0.13 micron socket 370 processors
S33 S37 U35 U37 W3 X41
Reserved Reserved Reserved Reserved Reserved RESET#
VTT VTT VTT VTT A34# RESET2#
VTT VTT VTT VTT A34# VSS
AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage AGTL/AGTL+ termination voltage Additional AGTL/AGTL+ address Processor reset for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). Ground for future 0.13 micron socket 370 processors
X6 X342
Reserved VCCCORE
A32# VCCCORE
A32# VTT
Additional AGTL/AGTL+ address Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). AGTL termination voltage for future 0.13 micron socket 370 processors
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Pin #
Pin Name Intel Celeron Processor (CPUID=068xh) Reserved
Pin Name Intel Pentium III Processor (CPUID=068xh) Reserved
Pin Name Future 0.13 Micron Socket 370 Processors NC
Function
Y1
Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). No connect for future 0.13 micron socket 370 processors
Y33 Z362
Reserved VCC2.5
CLKREF VCC2.5
CLKREF NC
1.25V PLL reference VCC2.5 for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). No connect for future 0.13 micron socket 370 processors
NOTES: 1. Refer to Chapter 4. 2. Refer to Section 13.2
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5.5
BSEL[1:0] Implementation Differences

A future 0.13 micron socket 370 processor will select the 133 MHz system bus frequency setting from the clock synthesizer. A Pentium III processor (CPUID=068xh) utilizes the BSEL1 pin to select either the 100 MHz or 133 MHz system bus frequency setting from the clock synthesizer. An Celeron processor (CPUID=068xh) will use both BSEL pins to select 66 MHz system bus frequency from the clock synthesizer. Processors in an FC-PGA or an FC-PGA2 are 3.3V tolerant for these signals, as are the clock and chipset. Intel CK-815 has been designed to support selections of 66 MHz, 100 MHz, and 133 MHz. The REF input pin has been redefined to be a frequency selection strap (BSEL1) during power-on and then becomes a 14 MHz reference clock output. The following figure details the new BSEL[1:0] circuit design for universal PGA370 designs. Note that BSEL[1:0] now are pulled up using 1 k resistors. Also refer to Figure 24 for more details. Note: In a design supporting future 0.13 micron socket 370 processors, the BSEL[1:0] lines are not valid until VTTPWRGD is asserted. Refer to Section 4.2.10 for details.
Figure 23. BSEL[1:0] Circuit Implementation for PGA370 Designs

3.3V 3.3V Processor
1 k
1 k
BSEL0
BSEL1
Clock Driver
Chipset
sys_ bus_BSEL_PG A370
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5.6
CLKREF Circuit Implementation

The CLKREF input (used by the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors) requires a 1.25V source. It can be generated from a voltage divider on the VCC2.5 or VCC3.3 sources using 1% tolerant resistors. A 4.7 F decoupling capacitor should be included on this input. See Figure 24 and Table 13 for example CLKREF circuits. Do not use VTT as the source for this reference!
Figure 24. Examples for CLKREF Divider Circuit
Vcc2.5
PGA370 CLKREF Y33
Vcc3.3
PGA370 CLKREF Y33
150
R1
150
4.7 F
R2
4.7 F
sys_bus_CLKREF_divider
Table 13. Resistor Values for CLKREF Divider (3.3V Source)

R1 (), 1% 182 301 374 499 R2 (), 1% 110 182 221 301 CLKREF Voltage (V) 1.243 1.243 1.226 1.242
5.7
Undershoot/Overshoot Requirements
Undershoot and overshoot specifications become more critical as the process technology for microprocessors shrinks due to thinner gate oxide. Violating these undershoot and overshoot limits will degrade the life expectancy of the processor. The Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors have more restrictive overshoot and undershoot requirements for system bus signals than previous processors. These requirements stipulate that a signal at the output of the driver buffer and at the input of the receiver buffer must not exceed the maximum absolute overshoot voltage limit or the minimum absolute undershoot voltage limit. Exceeding either of these limits will damage the processor. There is also a time-dependent, non-linear overshoot and undershoot requirement that depends on the amplitude and duration of the overshoot/undershoot. See the appropriate processor datasheet for more details on the processor overshoot/undershoot specifications.
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5.8
Processor Reset Requirements

Universal PGA370 designs must route the AGTL/AGTL+ reset signal from the chipset to two pins on the processor as well as to the debug port connector. This reset signal is connected to the following pins at the PGA370 socket: AH4 (RESET#). The reset signal is connected to this pin for the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors X4 (Reset2# or GND, depending on processor). The X4 pin is RESET2# for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). X4 is GND for future 0.13 micron socket 370 processors. An additional 1k resistor is connected in series with pin X4 to the reset circuitry since pin X4 is a ground pin in future 0.13 micron socket 370 processors. Note: The AGTL/AGTL+ reset signal must always terminate to VTT on the motherboard. Designs that do not support the debug port will not utilize the 240 series resistor or the connection of RESET# to the debug port connector. RESET2# is not required for platforms that do not support the Celeron processor (CPUID=068xh). Pin X4 should then be connected to ground. The routing rules for the AGTL/AGTL+ reset signal are shown in Figure 25.
Figure 25. RESET#/RESET2# Routing Guidelines

lenITP
VTT
VTT
91 cs_rtt_stub 240 86
ITP
Daisy chain cpu_rtt_stub 1 k Pin X4
Chipset lenCS lenCPU 22 10 pF
Processor Pin AH4
sys_bus_reset_routin
Table 14. RESET#/RESET2# Routing Guidelines (see Figure 25)

Parameter LenCS LenITP LenCPU cs_rtt_stub cpu_rtt_stub Minimum (in) 0.5 1 0.5 0.5 0.5 Maximum (in) 1.5 3 1.5 1.5 1.5
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5.9
Processor PLL Filter Recommendations

Intel PGA370 processors have internal phase lock loop (PLL) clock generators that are analog and require quiet power supplies to minimize jitter.
5.9.1
Topology
The general desired topology for these PLLs is shown in Figure 27. Not shown are the parasitic routing and local decoupling capacitors. Excluded from the external circuitry are parasitics associated with each component.
5.9.2
Filter Specification
The function of the filter is to protect the PLL from external noise through low-pass attenuation. The low-pass specification, with input at VCCCORE and output measured across the capacitor, is as follows: < 0.2 dB gain in pass band < 0.5 dB attenuation in pass band (see DC drop in next set of requirements) > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency The filter specification is graphically shown in Figure 26.
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Figure 26. Filter Specification
0.2dB 0dB -0.5 dB Forbidden Zone
Forbidden Zone -28dB
-34dB
DC
1Hz passband
fpeak
1 MHz
66 MHz
fcore
high frequency band

filter_spec
NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore. 3. fpeak should be less than 0.05 MHz.
Other requirements: Use shielded-type inductor to minimize magnetic pickup. Filter should support DC current > 30 mA. DC voltage drop from VCC to PLL1 should be < 60 mV, which in practice implies series R < 2 . This also means pass-band (from DC to 1 Hz) attenuation < 0.5 dB for VCC = 1.1V, and < 0.35 dB for VCC = 1.5V.
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5.9.3
Recommendation for Intel Platforms

The following tables contain examples of components that meet Intels recommendations, when configured in the topology of Figure 27.
Table 15. Component Recommendations Inductor

Part Number TDK MLF2012A4R7KT Murata LQG21N4R7K00T1 Murata LQG21C4R7N00 Value 4.7 H 4.7 H 4.7 H Tol. 10% 10% 30% SRF 35 MHz 47 MHz 35 MHz Rated Current 30 mA 30 mA 30 mA DCR (Typical) 0.56 (1 max.) 0.7 ( 50%) 0.3 max.
Table 16. Component Recommendations Capacitor

Part Number Kemet T495D336M016AS AVX TPSD336M020S0200 Value 33 F 33 F Tolerance 20% 20% ESL 2.5 nH 2.5 nH ESR 0.225 0.2
Table 17. Component Recommendation Resistor

Value 1 Tolerance 10% Power 1/16 W Note Resistor may be implemented with trace resistance, in which case a discrete R is not needed. See Figure 28.
To satisfy damping requirements, total series resistance in the filter (from VCCCORE to the top plate of the capacitor) must be at least 0.35 . This resistor can be in the form of a discrete component or routing or both. For example, if the chosen inductor has a minimum DCR of 0.25 , then a routing resistance of at least 0.10 is required. Be careful not to exceed the maximum resistance rule (2 ). For example, if using discrete R1 (1 1%), the maximum DCR of the L (trace plus inductor) should be less than 2.0 - 1.1 = 0.9 ; this precludes the use of some inductors and sets a maximum trace length. Other routing requirements: The capacitor (C) should be close to the PLL1 and PLL2 pins, < 0.1 per route. These routes do not count towards the minimum damping R requirement. The PLL2 route should be parallel and next to the PLL1 route (i.e., minimize loop area). The inductor (L) should be close to C. Any routing resistance should be inserted between VCCCORE and L. Any discrete resistor (R) should be inserted between VCCCORE and L.
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Figure 27. Example PLL Filter Using a Discrete Resistor

VCC CORE R Discrete resistor C Processor PLL2 L
<0.1 route
PLL1
<0.1 route
PLL_filter_1
Figure 28. Example PLL Filter Using a Buried Resistor

VCC CORE R T race resistance C Processor PLL2 L
<0.1 route
PLL1
<0.1 route
PLL_filter_2
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5.9.4
Custom Solutions
As long as designers satisfy filter performance and requirements as specified and outlined in Section 5.9.2, other solutions are acceptable. Custom solutions should be simulated against a standard reference core model (see Figure 29).
Figure 29. Core Reference Model

PLL1 0.1 Processor
120 pF PLL2 0.1
1 k
sys_bus_core_ref_model
NOTES: 1. 0.1 resistors represent package routing. 2. 120 pF capacitor represents internal decoupling capacitor. 3. 1 k resistor represents small signal PLL resistance. 4. Be sure to include all component and routing parasitics. 5. Sweep across component/parasitic tolerances. 6. To observe IR drop, use DC current of 30 mA and minimum VCCCORE level. 7. For other modules (interposer, DMM, etc.), adjust routing resistor if desired, but use minimum numbers.
5.10
Voltage Regulation Guidelines

A universal PGA370 design will need the voltage regulation module (VRM) or on-board voltage regulator (VR) to be compliant with Intel VRM 8.5 DC-DC Converter Design Guidelines.
5.11
Decoupling Guidelines for Universal PGA370 Designs

These preliminary decoupling guidelines for universal PGA370 designs are estimated to meet the specifications of VRM 8.5 DC-DC Converter Design Guidelines.
5.11.1
VCCCORE Decoupling Design

Sixteen or more 4.7 F capacitors in 1206 packages. All capacitors should be placed within the PGA370 socket cavity and mounted on the primary side of the motherboard. The capacitors are arranged to minimize the overall inductance between the VCCCORE/VSS power pins, as shown in Figure 30.
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Figure 30. Capacitor Placement on the Motherboard
5.11.2
VTT Decoupling Design

For Itt = 2.3 A (maximum) Twenty 0.1 F capacitors in 0603 packages placed as closed as possible to the processor VTT pins. The capacitors are shown on the exterior of the previous figure.
5.11.3
VREF Decoupling Design

Four 0.1 F capacitors in 0603 package placed near VREF pins (within 500 mils).
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5.12
5.12.1
Thermal Considerations
Heatsink Volumetric Keepout Regions
Current heatsink recommendations are only valid for supported Celeron and Pentium III processor frequencies. Figure 31 shows the system component keepout volume above the socket connector required for the reference design thermal solution for high frequency processors. This keepout envelope provides adequate room for the heatsink, fan and attach hardware under static conditions as well as room for installation of these components on the socket. The heatsink must be compatible with the Integrated Heat Spreader (IHS) used by higher frequency Pentium III processors. Figure 32 shows component keepouts on the motherboard required to prevent interference with the reference design thermal solution. Note portions of the heatsink and attach hardware hang over the motherboard. Adhering to these keepout areas will ensure compatibility with Intel boxed processor products and Intel enabled third party vendor thermal solutions for high frequency processors. While the keepout requirements should provide adequate space for the reference design thermal solution, systems integrators should check with their vendors to ensure their specific thermal solutions fit within their specific system designs. Ensure that the thermal solutions under analysis comprehend the specific thermal design requirements for higher frequency Pentium III processors. While thermal solutions for lower frequency processors may not require the full keepout area, larger thermal solutions will be required for higher frequency processors, and failure to adhere to the guidelines will result in mechanical interference.
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Figure 31. Heatsink Volumetric Keepout Regions
Figure 32. Motherboard Component Keepout Regions
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5.13
Debug Port Changes

Due to the lower voltage technology employed with newer processors, changes are required to support the debug port. Previously, test access port (TAP) signals used 2.5V logic, as is the case with the Intel Celeron processor in the PPGA package. Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors utilize 1.5V logic levels on the TAP. As a result, the type of debug port connecter used in universal PGA370 designs is dependent on the processor that is currently in the socket. The 1.5V connector is a mirror image of the older 2.5V connector. Either connector will fit into the same printed circuit board layout. Only the pin numbers change (see Figure 33). Also required, along with the new connector, is an In-Target Probe* (ITP) that is capable of communicating with the TAP at the appropriate logic levels.
Figure 33. TAP Connector Comparison

2.5 V connector, AMP 104068-3 vertical plug, top view
2 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29
RESET#
1.5 V connector, AMP 104078-4 vertical receptacle, top view

1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RESET#
sys_bus_TAP_conn
Caution: Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) require an intarget probe (ITP) compatible with 1.5V signal levels on the TAP. Previous ITPs were designed to work with higher voltages and may damage the processor if connected to any of these specified processors. See the processor datasheet for more information regarding the debug port.
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System Memory Routing Guidelines
Ground plane reference all system memory signals. To provide a good current return path and limit noise on the system memory signals, the signals should be ground referenced from the GMCH to the DIMM connectors and from DIMM connector-to-DIMM connector. If ground referencing is not possible, system memory signals should be, at a minimum, referenced to a single plane. If single plane referencing is not possible, stitching capacitors should be added no more than 200 mils from the signal via field. System memory signals may via to the backside of the PCB under the GMCH without a stitching capacitor as long as the trace on the topside of the PCB is less than 200 mils. Note: Intel recommends that a parallel plate capacitor between VCC3.3SUS and GND be added to account for the current return path discontinuity (See decoupling section). Use one 0.01 F X7R capacitor per every five system memory signals that switch plane references. No more than two vias are allowed on any system memory signal. If a group of system memory signals must to change layers, a via field should be created and a decoupling capacitor should be added at the end of the via field. Do not route signals in the middle of a via field; this causes noise to be generated on the current return path of these signals and can lead to issues on these signals (see Figure 34). The traces shown are on layer 1 only. The figure shows signals that are changing layer and two signals that are not changing layer. Note: The two signals around the via field create a keepout zone where no signals that do not change layer should be routed. Figure 34. System Memory Routing Guidelines
6.1
Do not route any signal in the middle of the via field that do not change layers
Add (1) 0.01 uf capacitor X7R (5) signals that via
Stagger vias in via field to avoid power/ground plane cut off because of the antipad on the internal layers
sys-mem-route
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6.2
6.2.1
System Memory 2-DIMM Design Guidelines

System Memory 2-DIMM Connectivity
Figure 35. System Memory Connectivity (2 DIMM)

Double-Sided, Unbuffered Pinout without ECC
SCSA[3:2]# SCSA[1:0]#
SCKE[1:0] SCKE[3:2] SCSB[3:2]# SCSB[1:0]# SRAS# SCAS# 82815 SWE# SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]# SDQM[7:0] SMD[63:0] CK815 DIMM_CLK[3:0] DIMM_CLK[7:4]
Notes: Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB Max. (128 Mbit) 512 MB
ICH
SMB_CLK SMB_DATA DIMM 0 & 1

sys_mem_conn_2DIMM
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6.2.2
System Memory 2-DIMM Layout Guidelines
Figure 36. System Memory 2-DIMM Routing Topologies

82815 Topology 1 Topology 2 Topology 3 Topology 4 Topology 5 E E 10 10 A C D F F DIMM 0 B DIMM 1
sys_mem_2DIMM_routing_topo
Table 18. System Memory 2-DIMM Solution Space

Signal Top. Trace (mils) Trace Lengths (inches)
Width
Spacing
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
SCS[3:2]# SCS[1:0]# SMAA[7:4] SMAB[7:4]# SCKE[3:2] SCKE[1:0] SMD[63:0] SDQM[7:0] SCAS#, SRAS#, SWE# SBS[1:0], SMAA[12:8,3:0]
3 2 4 5 3 2 1 1 1
5 5 10 10 10 10 5 10 5
10 10 10 10 10 10 10 10 10 1.75 1.5 1 4 3.5 4.0 0.4 0.4 0.4 0.5 0.5 0.5 3 4 1 4.5
4.5
0.4 0.4 3 4
0.5 0.5
2 2
4 4
10
4.0
0.4
0.5
In addition to meeting the spacing requirements outlined in Table 18, system memory signal trace edges must be at least 30 mils from any other non-system memory signal trace edge.
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Figure 37. System Memory Routing Example
sys_mem_routing_ex
NOTE:
Routing in this figure is for example purposes only. It does not necessarily represent complete and correct routing for this interface.
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6.3
6.3.1
System Memory 3-DIMM Design Guidelines

System Memory 3-DIMM Connectivity
Figure 38. System Memory Connectivity (3 DIMM)

Double-Sided, Unbuffered Pinout without ECC
SCSA[5:4]# SCSA[3:2]# SCSA[1:0]#
Notes: Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB Max. (128 Mbit) 512 MB
SCKE[1:0] SCKE[3:2] SCKE[5:4] SCSB[5:4]# SCSB[3:2]# SCSB[1:0]# SRAS# SCAS#
82815
SWE# SBS[1:0] SMAA[12:8,3:0] SMAA[7:4] SMAB[7:4]# SMAC[7:4]# SDQM[7:0] SMD[63:0]
CK815
DIMM_CLK[3:0] DIMM_CLK[7:4] DIMM_CLK[11:8] SMB_CLK SMB_DATA DIMM 0 & 1 & 2

sys_mem_conn_3DIMM
ICH
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6.3.2
System Memory 3-DIMM Layout Guidelines
Figure 39. System Memory 3-DIMM Routing Topologies

82815 Topology 1 Topology 2 Topology 3 Topology 4 Topology 5 Topology 6 Topology 7 Topology 8 G G G 10 10 10 A B C D E F C D E B B DIMM 0 DIMM 1 B DIMM 2
sys_mem_3DIMM_routing_topo
In addition to meeting the spacing requirements outlined in Table 19, system memory signal trace edges must be at least 30 mils from any other non-system memory signal trace edge. Table 19. System Memory 3-DIMM Solution Space
Signal Trace (mils) Trace Lengths (inches)
Top.
Width
Spacing
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
SCS[5:4]# SCS[3:2]# SCS[1:0]# SMAA[7:4] SMAB[7:4]# SMAC[7:4} SCKE[5:4] SCKE[3:2] SCKE[1:0] SMD[63:0] SDQM[7:0] SCAS#, SRAS#, SWE# SBS[1:0], SMAA[12:8,3:0]
4 3 2 6 7 8 4 3 2 1 1 5
5 5 5 10 10 10 10 10 10 5 10 5
10 10 10 10 10 10 10 10 10 10 10 10 1.75 1.5 4 3.5 0.4 0.4 0.4 0.5 0.5 0.5 3 4 3 4 1 2 4.5 4 2 4 1 4.5
4.5
0.4 0.4 2 3 4 4 0.4
0.5 0.5 0.5
10
0.4
0.5
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6.4
System Memory Decoupling Guidelines

A minimum of eight 0.1 F low-ESL ceramic capacitors (e.g., 0603 body type, X7R dielectric) are required and must be as close as possible to the GMCH. They should be placed within at most 70 mils to the edge of the GMCH package edge for VSUS_3.3 decoupling, and they should be evenly distributed around the system memory interface signal field including the side of the GMCH where the system memory interface meets the host interface. There are power and GND balls throughout the system memory ball field of the GMCH that need good local decoupling. Make sure to use at least 14 mil drilled vias and wide traces from the pads of the capacitor to the power or ground plane to create a low-inductance path. If possible, multiple vias per capacitor pad are recommended to further reduce inductance. To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (500 mils maximum). To further decouple the GMCH and provide a solid current return path for the system memory interface signals it is recommended that a parallel plate capacitor be added under the GMCH. Add a topside or bottom side copper flood under center of the GMCH to create a parallel plate capacitor between VCC3.3 and GND, see following figure. The dashed lines indicate power plane splits on layer 2 or layer 3 depending on stack-up. The filled region in the middle of the GMCH indicates a ground plate (on layer 1 if the power plane is on layer 2 or on layer 4 if the power layer is on layer 3).
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Figure 40. Intel 815 Chipset Platform Decoupling Example
Yellow lines in Figure 40 show layer-two plane splits. (Printed versions of this document will show the layer two plane splits in the left-side, bottom, right-side, and upper-right-side quadrants enclosed in gray lines.) Note that the layer 1 shapes do NOT cross the plane splits. The bottom shape is a VSS fill over VddSDRAM. The left-side shape is a VSS fill over VddAGP. The larger upper-right-side shape is a VSS fill over VddCORE. Additional decoupling capacitors shown in Figure 41 should be added between the DIMM connectors to provide a current return path for the reference plane discontinuity created by the DIMM connectors themselves. One 0.01 F X7R capacitor should be added per every ten SDRAM signals. Capacitors should be placed between the DIMM connectors and evenly spread out across the SDRAM interface. For debug purposes, four or more 0603 capacitor sites should be placed on the backside of the board, evenly distributed under the Intel 815 chipset platforms system memory interface signal field.
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Figure 41. Intel 815 Chipset Platform Decoupling Example
6.5
Compensation
A system memory compensation resistor (SRCOMP) is used by the GMCH to adjust the buffer characteristics to specific board and operating environment characteristics. Refer to the Intel 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for details on compensation. Tie the SRCOMP pin of the GMCH to 40 1% or 2% pull-up resistor to 3.3 Vsus (3.3Volt standby) via a 10-mil-wide, 0.5 inch trace (targeted for a nominal impedance of 40 ).
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AGP/Display Cache Design Guidelines

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For the detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms) refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This design guide focuses only on specific Intel 815 chipset platform recommendations and covers both standard add-in card AGP and down AGP solutions.
7.1
AGP Interface
A single AGP connector is supported by the GMCHs AGP interface. LOCK# and SERR#/PERR# are not supported. See the display cache discussion for a display cache/AGP muxing description and a description of the Graphics Performance Accelerator (GPA). The AGP buffers operate in one of two selectable modes to support the AGP universal connector: 3.3V drive, not 5V safe. This mode is compliant with the AGP 1.0 66 MHz specification. 1.5V drive, not 3.3V safe. This mode is compliant with the AGP 2.0 specification. The AGP 4X must operate at 1.5V and only use differential clocking mode. The AGP 2X can operate at 3.3V or 1.5V. The AGP interface supports up to 4X AGP signaling, though 4X fast writes are not supported. AGP semantic cycles to DRAM are not snooped on the host bus. The GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The GMCH contains a 32-deep AGP request queue. High-priority accesses are supported. All AGP semantic accesses hitting the graphics aperture pass through an address translation mechanism with a fully-associative 20-entry TLB. Accesses between AGP and the hub interface are limited to hub interface-originated memory writes to AGP. Cacheable accesses from the IOQ queue flow through one path, while aperture accesses follow another path. Cacheable AGP (SBA, PIPE#, and FRAME#) reads to DRAM all snoop the cacheable global write buffer (GWB) for system data coherency. Aperture AGP (SBA, PIPE#) reads to DRAM snoop the aperture queue (GCMCRWQ). Aperture AGP (FRAME#) reads and writes to DRAM proceed through a FIFO and there is no RAW capability, so no snoop is required. The AGP interface is clocked from the 66 MHz clock (3V66). The AGP-to-host/memory interface is synchronous with a clock ratio of 1:1 (66 MHz : 66 MHz), 2:3 (66 MHz : 100 MHz) and 1:2 (66 MHz : 133 MHz).
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7.1.1
Graphics Performance Accelerator (GPA)

The GMCH multiplexes the AGP signal interface with the integrated graphics display cache interface. As a result, for a universal motherboard that supports both integrated graphics and addin AGP video cards, display cache (for integrated graphics) must be populated on a card in the universal AGP slot. The card is called a Graphics Performance Accelerator (GPA) card. Intel provides a specification for this card in a separate document (Graphics Performance Accelerator Specification). AGP guidelines are presented in this section for motherboards that support the population of a GPA card in their AGP slot, as well as for those that do not. Where there are distinct guidelines dependent on whether or not a motherboard will support a GPA card, the section detailing routing guidelines is divided into subsections, as follows: If the motherboard supports a GPA card populated in the AGP slot, then the guidelines in the Flexible Motherboard subsections are to be followed. If the motherboard will NOT support a GPA card populated in the AGP slot, then the guidelines in the AGP-Only Motherboard subsections are to be followed.
7.1.2
AGP Universal Retention Mechanism (RM)

Environmental testing and field reports indicate that AGP cards and Graphics Performance Accelerator (GPA) cards may come unseated during system shipping and handling without proper retention. To avoid disengaged AGP cards and GPA modules, Intel recommends that AGP-based platforms use the AGP retention mechanism (RM). The AGP RM is a mounting bracket that is used to properly locate the card with respect to the chassis and to assist with card retention. The AGP RM is available in two different handle orientations: left-handed (see Figure 42) and right-handed. Most system boards accommodate the left-handed AGP RM. The manufacturing capacity of the left-handed RM currently exceeds the right-handed capacity, and as a result Intel recommends that customers design their systems to insure they can use the left-handed version of the AGP RM (see Figure 42). The right-handed AGP RM is identical to the left-handed AGP RM, except for the position of the actuation handle. This handle is located on the same end as the primary design, but extends from the opposite side (mirrored about the center axis running parallel to the length of the part). Figure 43 contains keepout information for the left hand AGP retention mechanism. Use this information to ensure the motherboard design leaves adequate space to install the retention mechanism. The AGP interconnect design requires that the AGP card must be retained to the extent that the card not back out more than 0.99 mm (0.039 in) within the AGP connector. To accomplish this it is recommended that new cards implement an additional notch feature in the mechanical keying tab to allow an anchor point on the AGP card for interfacing with an AGP RM. The retention mechanisms round peg engages with the AGP or GPA cards retention tab and prevents the card from disengaging during dynamic loading. The additional notch feature in the mechanical keying tab is required for 1.5V AGP cards and is recommended for the new 3.3V AGP cards.
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Figure 42. AGP Left-Handed Retention Mechanism
Figure 43. AGP Left-Handed Retention Mechanism Keepout Information
Engineering Change Request number 48 (ECR #48) of the AGP specification details the AGP RM, which is recommended for all AGP cards. These are approved changes to the Accelerated Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP Interface Specification. In addition, Intel has defined a reference design of a mechanical device to utilize the features defined in ECR #48.
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ECR #48 can be viewed on the Intel Web site at: http://developer.intel.com/technology/agp/ecr.htm More information regarding this component (AGP RM) is available from the following vendors.
Resin Color Black Supplier Part Number AMP P/N Foxconn P/N Green Foxconn P/N Left Handed Orientation (Preferred) 136427-1 006-0002-939 009-0004-008 Right Handed Orientation (Alternate) 136427-2 006-0001-939 009-0003-008
7.2
AGP 2.0
The AGP Interface Specification, Revision 2.0 enhances the functionality of the original AGP Interface Specification, Revision 1.0 by allowing 4X data transfers (4 data samples per clock) and 1.5V operation. The 4X operation of the AGP interface provides for quad-pumping of the AGP AD (address/data) and SBA (side-band addressing) buses. That is, data is sampled four times during each 66 MHz AGP clock, which means that each data cycle is of a 15 ns (66 MHz) clock, or 3.75 ns. Note that 3.75 ns is the data cycle time, not the clock cycle time. During 2X operation, data is sampled twice during a 66 MHz clock cycle, so the data cycle time is 7.5 ns. To allow for such high-speed data transfers, the 2X mode of AGP operation uses source-synchronous data strobing. During 4X operation, the AGP interface uses differential source-synchronous strobing. With data cycle times as small as 3.75 ns and setup/hold times of 1 ns, propagation delay mismatch is critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on the data lines causes the settling time to be long. If the mismatch between a data line and the associated strobe is too great or if there is noise on the interface, incorrect data will be sampled. The low-voltage operation on the AGP (1.5V) requires even more noise immunity. For example, during 1.5V operation, Vilmax is 570 mV. Without proper isolation, cross-talk could create signal integrity issues.
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7.2.1
AGP Interface Signal Groups

The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals. Each group has different routing requirements. In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements. However, trace length matching requirements only need to be met within each set of 2X/4X timing domain signals. The signal groups are listed in Table 20.
Table 20. AGP 2.0 Signal Groups

Group 1X timing domain 2X / 4X timing domain Signal
CLK (3.3V), RBF#, WBF#, ST[2:0], PIPE#, REQ#, GNT#, PAR, FRAME#, IRDY#, TRDY#, STOP#, DEVSEL# Set #1: AD[15:0], C/BE[1:0]#, AD_STB0, AD_STB0#11 Set #2: AD[31:16], C/BE[3:2]#, AD_STB1, AD_STB1#1 Set #3: SBA[7:0], SB_STB, SB_STB#1
Miscellaneous, async
USB+, USB-, OVRCNT#, PME#, TYPDET#, PERR#, SERR#, INTA#, INTB#
NOTES: 1. These signals are used in 4X AGP mode ONLY.
Table 21. AGP 2.0 Data/Strobe Associations

Data AD[15:0] and C/BE[1:0]# Associated Strobe in 1X Strobes are not used in 1X mode. All data is sampled on rising clock edges. Strobes are not used in 1X mode. All data is sampled on rising clock edges. Strobes are not used in 1X mode. All data is sampled on rising clock edges. Associated Strobe in 2X AD_STB0 Associated Strobes in 4X AD_STB0, AD_STB0# AD_STB1, AD_STB1# SB_STB, SB_STB#
AD[31:16] and C/BE[3:2]#
AD_STB1
SBA[7:0]
SB_STB
Throughout this section, the term data refers to AD[31:0], C/BE[3:0]#, and SBA[7:0]. The term strobe refers to AD_STB[1:0], AD_STB[1:0]#, SB_STB, and SB_STB#. When the term data is used, it refers to one of the three sets of data signals, as listed in Table 21. When the term strobe is used, it refers to one of the strobes as it relates to the data in its associated group. The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals) will be addressed separately.
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7.3
Standard AGP Routing Guidelines

These routing guidelines cover a standard AGP solution. This utilizes an AGP compliant device on an external add-in card that plugs into a connector on the motherboard.
7.3.1
7.3.1.1
1X Timing Domain Routing Guidelines

Flexible Motherboard Guidelines
The AGP 1X timing domain signals (Table 20) have a maximum trace length of 4 inches for motherboards that support a Graphics Performance Accelerator (GPA) card. This maximum applies to ALL signals listed as 1X timing domain signals in Table 20. AGP 1X signals multiplexed with display cached signals (listed in the following table) should be routed with a 1:3 trace width-to-spacing ratio. All other AGP 1X timing domain signals can be routed with 5-mil minimum trace separation. There are no trace length matching requirements for 1X timing domain signals. The following are multiplexed AGP1X Signals on Flexible Motherboards RBF# ST[2:0] PIPE# REQ# GNT# PAR FRAME# IRDY# TRDY# STOP# DEVSEL#
7.3.1.2
AGP-Only Motherboard Guidelines

The AGP 1X timing domain signals (refer to Table 20) have a maximum trace length of 7.5 inches for motherboards that will not support a Graphics Performance Accelerator (GPA) card. This maximum applies to ALL signals listed as 1X timing domain signals in Table 20. All AGP 1X timing domain signals can be routed with 5-mil minimum trace separation. There are no trace length matching requirements for 1X timing domain signals.
7.3.2
2X/4X Timing Domain Routing Guidelines

These trace length guidelines apply to ALL signals listed in Table 20 as 2X/4X timing domain signals. These signals should be routed using 5 mil (60 ) traces. The maximum line length and length mismatch requirements depend on the routing rules used on the motherboard. These routing rules were created to provide design freedom by making tradeoffs between signal coupling (trace spacing) and line lengths. The maximum length of the AGP interface defines which set of routing guidelines must be used. Guidelines for short AGP interfaces (e.g., < 6 inches) and long AGP interfaces (e.g., > 6 inches and < 7.25 inches) are documented
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separately. The maximum length allowed for the AGP interface (on AGP-only motherboards) is 7.25 inches.
7.3.2.1
Flexible Motherboard Guidelines

For motherboards that support either an AGP card or a GPA card in the AGP slot, the maximum length of AGP 2X/4X timing domain signals is 4 inches. 1:3 trace width-to-spacing is required for AGP 2X/4X signal traces. AGP 2X/4X signals must be matched their associated strobe (as outlined in Table 20), within 0.5 inch. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 3.7 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) can be 3.2 inches to 4 inches long (since there is a 4 inch maximum length). Another strobe set (e.g., SB_STB and SB_STB#) could be 3.1 inches long, so that the associated data signals (e.g., SBA[7:0]) can be 2.6 inches to 3.6 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Since each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed using 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than 0.1 inch (i.e., a strobe and its complement must be the same length within 0.1 inch).
Figure 44. AGP 2X/4X Routing Example for Interfaces < 6 Inches and GPA/AGP Solutions
5-mil trace 15 mils 5-mil trace 20 mils 5-mil trace 15 mils 5-mil trace 20 mils 5-mil trace 15 mils
2X/4X signal 2X/4X signal 2X/4X signal 2X/4X signal AGP STB AGP STB AGP STB# AGP STB# 2X/4X signal 2X/4X signal 2X/4X signal 2X/4X signal
STB/STB# length Associated AGP 2X/4X data signal length 0.5" Min. 0.5" Max.
AGP_2x-4x_routing
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7.3.2.2
AGP-Only Motherboard Guidelines

For motherboards that will not support a GPA card populated in the AGP slot, the maximum AGP 2X/4X signal trace length is 7.25 inches. However, there are different guidelines for AGP interfaces shorter than 6 inches (e.g., all AGP 2X/4X signals are less than 6 inches long) and those longer than 6 inches but shorter than the 7.25 inches maximum.
AGP Interfaces Shorter Than 6 Inches

These guidelines are for designs that require less than 6 inches between the AGP connector and the GMCH: 1:3 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces. AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 20), within 0.5 inch. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 5.3 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) can be 4.8 inches to 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be 3.7 inches to 4.7 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than 0.1 inch (i.e., a strobe and its complement must be the same length, within 0.1 inch).
AGP Interfaces Longer Than 6 Inches

Since longer lines have more cross-talk, they require wider spacing between traces to reduce the skew. The following guidelines are for designs that require more than 6 inches (but less than the 7.25 inches maximum) between the AGP connector and the GMCH: 1:4 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces. AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 20), within 0.125 inch. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 6.5 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) could be 6.475 inches to 6.625 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 6.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be 6.075 inches to 6.325 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 20 mils of space (1:4)
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between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than 0.1 inch (i.e., a strobe and its complement must be the same length, within 0.1 inch).
7.3.3
AGP Routing Guideline Considerations and Summary

This section applies to all AGP signals in any motherboard support configuration (e.g., flexible or AGP only), as follows: The 2X/4X timing domain signals can be routed with 5-mil spacing, when breaking out of the GMCH. The routing must widen to the documented requirements, within 0.3 inch of the GMCH package. When matching trace length for the AGP 4X interface, all traces should be matched from the ball of the GMCH to the pin on the AGP connector. It is not necessary to compensate for the lengths of the AGP signals on the GMCH package. Reduce line length mismatch to ensure added margin. Trace length mismatch for all signals within a signal group should be as close to zero as possible, to provide timing margin. To reduce trace-to-trace coupling (cross-talk), separate the traces as much as possible. All signals in a signal group should be routed on the same layer. The trace length and trace spacing requirements must not be violated by any signal.
Table 22. AGP 2.0 Routing Summary

Signal 1X Timing Domain 2X/4X Timing Domain Set 1 2X/4X Timing Domain Set 2 2X/4X Timing Domain Set 3 2X/4X Timing Domain Set 1 2X/4X Timing Domain Set 2 2X/4X Timing Domain Set 3 Max. Length 7.5 4 7.25 4 Trace Spacing (5-mil Traces) 5 mils 20 mils Length Mismatch No requirement 0.125 Relative to N/A AD_STB0 and AD_STB0# AD_STB1 and AD_STB1# SB_STB and SB_STB# AD_STB0 and AD_STB0# AD_STB1 and AD_STB1# SB_STB and SB_STB# None AD_STB0, AD_STB0# must be the same length AD_STB1, AD_STB1# must be the same length SB_STB, SB_STB# must be the same length AD_STB0, AD_STB0# must be the same length AD_STB1, AD_STB1# must be the same length SB_STB, SB_STB# must be the same length Notes
7.25 4
20 mils
0.125
7.254
20 mils
0.125
6 3
15 mils1
0.5
63
15 mils1
0.5
63
15 mils1
0.5
NOTES: 1. Each strobe pair must be separated from other signals by at least 20 mils. 2. These guidelines apply to board stack-ups with 15% impedance tolerance. 3. 4 inches is the maximum length for a flexible motherboards. 4. Solution valid for AGP-only motherboards.
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7.3.4
AGP Clock Routing

The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard, addin card, and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall within the switching range. The 1 ns skew budget is divided such that the motherboard is allotted 0.9 ns of clock skew. (The motherboard designer shall determine how the 0.9 ns is allocated between the board and the synthesizer.)
7.3.5
AGP Signal Noise Decoupling Guidelines

The following routing guidelines are recommended for an optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the GMCH. The following guidelines are not intended to replace thorough system validation for products based on the Intel 815 chipset platform. A minimum of six 0.01 F capacitors are required and must be as close as possible to the GMCH. These should be placed within 70 mils of the outer row of balls on the GMCH for VDDQ decoupling. The closer the placement, the better. The designer should evenly distribute placement of decoupling capacitors in the AGP interface signal field. It is recommended that the designer use a low-ESL ceramic capacitor (e.g., with a 0603 bodytype X7R dielectric). To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (1 inch maximum). In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias that transition the AGP signal from one reference signal plane to another. On a typical four layer PCB design, the signals transition from one side of the board to the other. One extra 0.01 F capacitor is required per 10 vias. The capacitor should be placed as close as possible to the center of the via field. The designer should ensure that the AGP connector is well decoupled, as described in the AGP Design Guide, Revision 1.0, Section 1.5.3.3.
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Figure 45. AGP Decoupling Capacitor Placement Example
AGP_decoupling_cap_placement
NOTE:
This figure is for example purposes only. It does not necessarily represent complete and correct routing for this interface.
7.3.6
AGP Routing Ground Reference

It is strongly recommended that, at a minimum, the following critical signals be referenced to ground from the GMCH to an AGP connector (or to an AGP video controller if implemented as a down solution on an AGP-only motherboard), using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0]. In addition to the minimum signal set listed previously, it is strongly recommended that half of all AGP signals be reference to ground, depending on board layout. In an ideal design, the entire AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all designs using the Intel 815 chipset platform for use with the universal socket 370.
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7.4
AGP Down Routing Guidelines

These routing guidelines cover an AGP down solution. This allows for an AGP compliant device to be implemented directly on the motherboard without the need for a connector or add-in card.
7.4.1
1X AGP Down Option Timing Domain Routing Guidelines

Routing guidelines for an AGP device on the motherboard are very similar to those when the device is implemented with an AGP connector. AGP 1X timing domain signals (Table 20) have a maximum trace length of 7.5 inches. This maximum applies to ALL signals listed as 1X timing domain signals in Table 20. All AGP 1X timing domain signals can be routed with 5-mil minimum trace separation There are no trace length matching requirements for 1X timing domain signals
7.4.2
2X/4X AGP Down Timing Domain Routing Guidelines

These trace length guidelines apply to ALL signals listed in Table 20 as 2X/4X timing domain signals. These signals should be routed using 5-mil (60 ) traces. The maximum AGP 2X/4X signal trace length is 6 inches. 1:3 trace width-to-spacing is required for AGP 2X/4X timing domain signal traces. AGP 2X/4X signals must be matched with their associated strobe (as outlined in Table 20), within 0.5 inch. For example, if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) is 5.3 inches long, the data signals associated with those strobe signals (e.g., AD[15:0] and C/BE[2:0]#) could be 4.8 inches to 5.8 inches long. Another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long, and the data signals associated with those strobe signals (e.g., SBA[7:0]) could be 3.7 inches to 4.7 inches long. The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act as clocks on the source-synchronous AGP interface. Therefore, special care must be taken when routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should be routed on 5-mil traces with at least 15 mils of space (1:3) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than 0.2 inch (i.e., a strobe and its complement must be the same length, within 0.2 inch).
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Figure 1. AGP Down 2X/4X Routing Recommendations

Length: 0.5" - 6.0" Width to spacing: 1:3 Strobe-to-Data Mismatch: 0.5" Signals AGP Compliant Graphics Device
Intel 82815
Strobes Length: Dependent on Data Width: 5 mil Spacing: 15 mils Strobe-to-Strobe Mismatch: 0.2"
AGP_Down_1x-2x
7.4.3
AGP Routing Guideline Considerations and Summary

This section applies to all AGP signals, as follows: The 2X/4X timing domain signals can be routed with 5-mil spacing, when breaking out of the GMCH. The routing must widen to the documented requirements, within 0.3 of the GMCH package. When matching the trace length for the AGP 4X interface, all traces should be matched from the ball of the GMCH to the ball on the AGP compliant device. It is not necessary to compensate for the lengths of the AGP signals on the GMCH package. Reduce line length mismatch to ensure added margin. Trace length mismatch for all signals within a signal group should be as close to zero as possible, to provide timing margin. To reduce trace-to-trace coupling (cross-talk), separate the traces as much as possible. All signals in a signal group should be routed on the same layer. The trace length and trace spacing requirements must not be violated by any signal.
Table 23. AGP 2.0 Routing Summary

Signal 1X Timing Domain 2X/4X Timing Domain Set 1 2X/4X Timing Domain Set 2 2X/4X Timing Domain Set 3 Max. Length 7.5 6 Trace Spacing (5-mil Traces) 5 mils 15 mils1 Length Mismatch No requirement 0.5 Relative to N/A AD_STB0 and AD_STB0# AD_STB1 and AD_STB1# SB_STB and SB_STB# None AD_STB0, AD_STB0# must be the same length AD_STB1, AD_STB1# must be the same length SB_STB, SB_STB# must be the same length Notes
15 mils1
0.5
15 mils1
0.5
NOTES: 1. Each strobe pair must be separated from other signals by at least 20 mils.
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7.4.4
AGP Clock Routing

The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall within the switching range. For AGP clock routing guidelines for the Intel 815 chipset platform, refer to Section 11.3.
7.4.5
AGP Signal Noise Decoupling Guidelines

The following routing guidelines are recommended for the optimal system design. The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the GMCH. The following guidelines are not intended to replace thorough system validation for products based on the Intel 815 chipset platform. A minimum of six 0.01 F capacitors are required and must be as close as possible to the GMCH. These should be placed within 70 mils of the outer row of balls on the GMCH for VDDQ decoupling. The closer the placement, the better. The designer should evenly distribute placement of decoupling capacitors in the AGP interface signal field. It is recommended that the designer use a low-ESL ceramic capacitor, such as with a 0603 body-type X7R dielectric. To add the decoupling capacitors within 70 mils of the GMCH and/or close to the vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of space between traces should be minimal and for as short a distance as possible (1 inch maximum). In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias that transition the AGP signal from one reference signal plane to another. On a typical four-layer PCB design, the signals transition from one side of the board to the other. One extra 0.01 F capacitor is required per ten vias. The capacitor should be placed as close as possible to the center of the via field.
7.4.6
AGP Routing Ground Reference

It is strongly recommended that at least the following critical signals be referenced to ground from the GMCH to an AGP video controller on an AGP-only motherboard, using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT#, and ST[2:0]. In addition to the minimum signal set listed previously, it is strongly recommended that half of all AGP signals be referenced to ground, depending on the board layout. In an ideal design, the complete AGP interface signal field would be referenced to ground. This recommendation is not specific to any particular PCB stack-up, but should be applied to all designs using the Intel 815 chipset platform.
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7.5
7.5.1
AGP 2.0 Power Delivery Guidelines

VDDQ Generation and TYPEDET#
AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics controller. This voltage is always 3.3V. VDDQ is the interface voltage. In AGP 1.0 implementations, VDDQ was also 3.3V. For the designer developing an AGP 1.0 motherboard, there is no distinction between VCC and VDDQ, as both are tied to the 3.3V power plane on the motherboard. AGP 2.0 requires that these power planes be separate. In conjunction with the 4X data rate, the AGP 2.0 Interface Specification provides for low-voltage (1.5V) operation. The AGP 2.0 specification implements a TYPEDET# (type detect) signal on the AGP connector that determines the operating voltage of the AGP 2.0 interface (VDDQ). The motherboard must provide either 1.5V or 3.3V to the add-in card, depending on the state of the TYPEDET# signal. (see Table 24). 1.5V low-voltage operation applies only to the AGP interface (VDDQ). VCC is always 3.3V. Note: The motherboard provides 3.3V to the VCC pins of the AGP connector. If the graphics controller needs a lower voltage, then the add-in card must regulate the 3.3VCC voltage to the controllers requirements. The graphics controller may only power AGP I/O buffers with the VDDQ power pins. The TYPEDET# signal indicates whether the AGP 2.0 interface operates at 1.5V or 3.3V. If TYPEDET# is floating (i.e., No Connect) on an AGP add-in card, the interface is 3.3V. If TYPEDET# is shorted to ground, the interface is 1.5V.
Table 24. TYPDET#/VDDQ Relationship

TYPEDET# (on add-in card) GND N/C VDDQ (supplied by MB) 1.5V 3.3V
As a result of this requirement, the motherboard must provide a flexible voltage regulator or key the slot to preclude add-in cards with voltage requirements incompatible with the motherboard. This regulator must supply the appropriate voltage to the VDDQ pins on the AGP connector. For specific design recommendations, refer to the schematics in Appendix A. VDDQ generation and AGP VREF generation must be considered together. Before developing VDDQ generation circuitry, refer to both the above requirements and the AGP 2.0 Interface Specification.
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Figure 46. AGP VDDQ Generation Example Circuit

+3.3V VDDQ
+12V
C2
47 F
U1
1 2 VIN R1 2.2 k C1 1 F 3 4 GND FB SHDN
LT1575
IPOS INEG GATE COMP 6 5 8 7 5 R2 C3 220 F
10 pF .001 F C4 R5 7.5 k - 1% 301 - 1% TYPEDET# 1.21 k - 1% R4 R3
C5
AGP_VDDQ_gen_ex_circ
The previous figure demonstrates one way to design the VDDQ voltage regulator. This regulator is a linear regulator with an external, low-Rdson FET. The source of the FET is connected to 3.3V. This regulator converts 3.3V to 1.5V or passes 3.3V, depending on the state of TYPEDET#. If a linear regulator is used, it must draw power from 3.3V (not 5V) to control thermals (i.e., 5V regulated down to 1.5V with a linear regulator will dissipate approximately 7 W at 2 A). Because it must draw power from 3.3V and, in some situations, must simply pass that 3.3V to VDDQ (when a 3.3V add-in card is placed in the system), the regulator MUST use a low-Rdson FET. AGP 1.0 ECR #44 modified VDDQ 3.3min to 3.1V. When an ATX power supply is used, the 3.3 Vmin is 3.168V. Therefore, 68 mV of drop is allowed across the FET at 2 A. This corresponds to a FET with an Rdson of 34 m. How does the regulator switch? The feedback resistor divider is set to 1.5V. When a 1.5V card is placed in the system, the transistor is Off and the regulator regulates to 1.5V. When a 3.3V card is placed in the system, the transistor is On, and the feedback will be pulled to ground. When this happens, the regulator will drive the gate of the FET to nearly 12V. This will turn the FET on and pass 3.3V (2 A * Rdson) to VDDQ.
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7.5.2
VREF Generation for AGP 2.0 (2X and 4X)

VREF generation for AGP 2.0 is different, depending on the AGP card type used. The 3.3V AGP cards generate VREF locally. That is, they have a resistor divider on the card that divides VDDQ down to VREF (see Figure 47). To account for potential differences between VDDQ and GND at the GMCH and graphics controller, 1.5V cards use source-generated VREF. That is, the VREF signal is generated at the graphics controller and sent to the GMCH, and another VREF is generated at the GMCH and sent to the graphics controller (see Figure 47). Both the graphics controller and the GMCH must generate VREF and distribute it through the connector (1.5V add-in cards only). The following two pins defined on the AGP 2.0 universal connector allow this VREF passing: VREFGC : VREFCG : VREF from the graphics controller to the chipset VREF from the chipset to the graphics controller
To preserve the common mode relationship between the VREF and data signals, the routing of the two VREF signals must be matched in length to the strobe lines, within 0.5 inch on the motherboard and within 0.25 inch on the add-in card. The voltage divider networks consist of AC and DC elements, as shown in Figure 47. The VREF divider network should be placed as close as practical to the AGP interface, to get the benefit of the common-mode power supply effects. However, the trace spacing around the VREF signals must be a minimum of 25 mils to reduce cross-talk and maintain signal integrity. During 3.3V AGP 2.0 operation, VREF must be 0.4 VDDQ. However, during 1.5V AGP 2.0 operation, VREF must be 0.5 VDDQ. This requires a flexible voltage divider for VREF. Various methods of accomplishing this exist, and one such example is shown in Figure 47.
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Figure 47. AGP 2.0 VREF Generation and Distribution

a) 1.5V AGP Card
+12V R7 (See note 2) 1 K TYPEDET# VrefGC R9 300 1% R2 200 1%
1.5V AGP Card
VDDQ C8 500 pF
U6
VDDQ REF
R6 1 K
R5 82
GMCH
R2 1 K R4 82 C9 500 pF
VDDQ AGP REF Device GND
mosfet
C9 0.1 uF
GND
VrefCG Notes: 1. The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 10 mils from adjacent signals. 2. R7 is the same resistor seen in AGP VDDQ generation example circuit figure (R1)
b) 3.3V AGP Card

+12V R7 (See note 2) 1 K TYPEDET# R9 300 1% R2 200 1%
3.3V AGP Card
VDDQ C8 500 pF
VrefGC
U6 VDDQ AGP Device REF mosfet C10 0.1 uF
VDDQ REF
R6 1 K
R5 82
GMCH
R2 1 K R4 82
GND
GND
C9 500 pF
VrefCG The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 25 mils from adjacent signals.
agp_2.0ref_gen_dist
The flexible VREF divider shown in Figure 47 uses a FET switch to switch between the locally generated VREF (for 3.3V add-in cards) and the source-generated VREF (for 1.5V add-in cards). Use of the source-generated VREF at the receiver is optional and is a product implementation issue beyond the scope of this document.
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7.6
7.6.1
Additional AGP Design Guidelines

Compensation
The GMCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a 40 , 2% (or 39 , 1%) pull-down resistor (to ground) via a 10-mil-wide, very short (<0.5 inch) trace.
7.6.2
AGP Pull-Ups
AGP control signals require pull-up resistors to VDDQ on the motherboard, to ensure that they contain stable values when no agent is actively driving the bus.
1X Timing Domain Signals Requiring Pull-Up Resistors

The signals requiring pull-up resistors are: FRAME# TRDY# IRDY# DEVSEL# STOP# SERR# PERR# RBF# PIPE# REQ# WBF# GNT# ST[2:0]
Note: It is critical that these signals be pulled up to VDDQ, not 3.3V. The trace stub to the pull-up resistor on 1X timing domain signals should be kept at less than 0.5 inch, to avoid signal reflections from the stub. Note: The strobe signals require pull-ups/pull-downs on the motherboard to ensure that they contain stable values when no agent is driving the bus. Note: INTA# and INTB# should be pulled to 3.3V, not VDDQ.
2X/4X Timing Domain Signals

AD_STB[1:0] SB_STB AD_STB[1:0]# SB_STB# (pull-up to VDDQ) (pull-up to VDDQ) (pull-down to ground) (pull-down to ground)
The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be kept to less than 0.1 inch to avoid signal reflections from the stub.
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The pull-up/pull-down resistor value requirements are Rmin = 4 k and Rmax = 16 k. The recommended AGP pull-up/pull-down resistor value is 8.2 k.
7.6.2.1
AGP Signal Voltage Tolerance List

The following signals on the AGP interface are 3.3V tolerant during 1.5V operation: PME# INTA# INTB# GPERR# GSERR# CLK RST
The following signals on the AGP interface are 5V tolerant (refer to the USB specification): USB+ USB OVRCNT# The following special AGP signal is either GROUNDED or NOT CONNECTED on an AGP card. TYPEDET# Note: All other signals on the AGP interface are in the VDDQ group. They are not 3.3V tolerant during 1.5V operation.
7.7
Motherboard / Add-in Card Interoperability

There are three AGP connectors: 3.3V AGP connector, 1.5V AGP connector, and Universal AGP connector. To maximize add-in flexibility, it is highly advisable to implement the universal connector in a system based on the Intel 815 chipset platform. All add-in cards are either 3.3V or 1.5V cards. The 4X transfers at 3.3V are not allowed due to timings.
Table 25. Connector/Add-in Card Interoperability

Card 1.5V Card 3.3V Card 1.5V Connector Yes No 3.3V Connector No Yes Universal Connector Yes Yes
Table 26. Voltage/Data Rate Interoperability

Voltage 1.5V VDDQ 3.3V VDDQ 1X Yes Yes 2X Yes Yes 4X Yes No
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7.8
AGP / Display Cache Shared Interface

As described earlier, the AGP and display cache interfaces of the Intel 815 chipset platform are multiplexed or shared. In other words, the same component pins (balls) are used for both interfaces, although obviously only one interface can be supported at any given time. As a result, almost all display cache interface signals are mapped onto the new AGP interface. The Intel 815 chipset platform can be configured in either AGP mode or Graphics mode. In the AGP mode, the interface supports a full AGP 4X interface. In the Graphics mode, the interface becomes a display cache interface similar to the Intel 810E chipset. Note, however, that in the Graphics mode, the display cache is optional. There do not have to be any SDRAM devices connected to the interface. The only dedicated display cache signals are OCLK and RCLK, which need not connect directly to the SDRAM devices. These are not mapped onto existing AGP signals.
7.8.1
GPA Card Considerations

To support the fullest flexibility, the display cache exists on an add-in card (Graphics Performance Accelerator, or GPA) that complies with the AGP connector form factor. If the motherboard designer follows the flexible routing guidelines for the AGP interface detailed in previous sections, the customer can choose to populate the AGP slot in a system based on the Intel 815 chipset platform with either an AGP graphics card, with a GPA card to enable the highest-possible internal graphics performance, or with nothing to get the lowest-cost internal graphics solution. Some of the GPA/ Intel 815 chipset platform for use with the universal socket 370 interfacing implications are listed below. For a complete description of the GPA card design, refer to the Graphics Performance Accelerator Card Specification available from Intel. A strap is required to determine which frequency to select for display cache operation. This is the L_FSEL pin of the GMCH. The GPA card will pull this signal up or down, as appropriate to communicate to the appropriate operating frequency to the Intel 815 chipset platform. The platform will sample this pin on the deasserting edge of reset. Since current SDRAM technology is always 3.3V rather than the 1.5V option also supported by AGP, the GPA card should set the TYPEDET# signal correctly to indicate that it requires a 3.3V power supply. Furthermore, the GPA card should have only the 3.3V key and not the 1.5V key, thereby preventing it from being inserted into a 1.5V-only connector. The pad buffers on the chip will be the normal AGP buffers and will work for both interfaces. In internal graphics mode, the AGPREF signal, which is required for the AGP mode, should remain functional as a reference voltage for sampling 3.3V LMD inputs. The voltage level on AGPREF should remain exactly the same as in the AGP mode, as opposed to VCC/2 used for previous products.
7.8.1.1
AGP and GPA Mechanical Considerations

The GPA card will be designed with a notch on the PCB to go around the AGP universal retention mechanism. To guarantee that the GPA card will meet all shock and vibration requirements of the system, the AGP universal retention mechanism will be required on all AGP sockets that are to support a GPA card.
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7.8.2
Display Cache Clocking

The display cache is clocked source-synchronously from a clock generated by the GMCH. The display cache clocking scheme uses three clock signals. LTCLK clocks the SDRAM devices, is muxed with an AGP signal, and should be routed according to the flexible AGP guidelines. LOCLK and LRCLK clock the input buffers of the universal platform. LOCLK is an output of the GMCH and is a buffered copy of LTCLK. LOCLK should be connected to LRCLK at the GMCH, with a length of PCB trace to create the appropriate clock skew relationship between the clock input (LRCLK) and the SDRAM capacitor clock input(s). The guidelines are illustrated in Figure 48.
Figure 48. Display Cache Input Clocking

GM CH 15 1% LO CL LRCL 15 pF 5% 0.5" 1.5"
disp_cache_in_clk
The capacitor should be placed as close as possible to the GMCH LRCLK pin. To minimize skew variation, Intel recommends a 1% series termination resistor and a 5% NP0 (also known as C0G) capacitor, to stabilize the value across temperatures. In addition to the 15 , 1% resistor and the 15 pF, 5% NP0 capacitor. The following combination also can be used: 10 , 1% and 22 pF, 5% NP0.
7.9
Designs That Do Not Use The AGP Port

Universal platform designs that do not use the AGP port should terminate the AGP pins of the GMCH. Except for the GPAR pin (that requires a 100 k pull-down resistor to ground), the pullup or pull-down resistor value should be 8.2 k. Any external graphics implementation not using the AGP port should terminate the GMCH AGP control and strobe signals as recommended in Section 13.3.2.
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Analog RGB/CRT
RAMDAC/Display Interface
Figure 49 shows the interface of the RAMDAC analog current outputs with the display. Each DAC output is doubly terminated with a 75 resistance. One 75 resistance is from the DAC output to the board ground and the other termination resistance exists within the display. The equivalent DC resistance at the output of each DAC output is 37.5 . The current output from each DAC flows into this equivalent resistive load to produce a video voltage without the need for external buffering. There is also an LC pi-filter that is used to reduce high-frequency glitches and noise and to reduce EMI. To maximize performance, the filter impedance, cable impedance, and load impedance should be the same. The LC pi-filter consists of two 3.3 pF capacitors and a ferrite bead with a 75 impedance at 100 MHz. The LC pi-filter is designed to filter glitches produced by the RAMDAC while maintaining adequate edge rates to support high-end display resolutions.
8.1
8.1.1
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Figure 49. Schematic of RAMDAC Video Interface

Graphics Board
1.8 V board power plane Cf LC Filter 1.8 V board power plane D1 VCCDACA1/ VCCDACA2 VCCDA Red Rt C1 D2 C2 FB
Display PLL power connects to this segmented power plane 1.8 V board power plane
Analog power plane Lf 1.8 V
Termination resistor, R 75 1% (metal film) Diodes D1, D2: Schottky diodes LC filter capacitors, C1, C2: 3.3 pF Ferrite bead, FB: 7 @ 100 MHz (Recommended part: Murata BLM11B750S)
Graphics Chip
RAMDAC
Pixel clock (from DPLL) 1.8 V board power plane D1 Green Rt
Pi filter
Coax Cable Zo = 75 Red
Display
75 75
FB
Video connector
Green Blue
C1 D2
C2
75
Pi filter 1.8 V board power plane D1 Blue Rt IWASTE IREF VSSDACA C1 D2 C2 FB
Pi filter
Rset 1% reference current resistor (metal film)
Ground plane
display_RAMDAC_video_IF
NOTE:
Diodes D1, D2 are clamping diodes with low leakage and low capacitive loading. An example is: California Micro Devices PAC DN006 (6 channel ESD protection array).
In addition to the termination resistance and LC pi-filter, there are protection diodes connected to the RAMDAC outputs to help prevent latch-up. The protection diodes must be connected to the same power supply rails as the RAMDAC. An LC filter is recommended to connect the segmented analog 1.85V power plane of the RAMDAC to the 1.85V board power plane. The LC filter should be designed for a cut-off frequency of 100 kHz.
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8.1.2
Reference Resistor (Rset) Calculation

The full-swing video output is designed to be 0.7V according to the VESA video standard. With an equivalent DC resistance of 37.5 (two 75 in parallel; one 75 termination on the board and one 75 termination within the display), the full-scale output current of a RAMDAC channel is 0.7/37.5 = 18.67 mA. Since the RAMDAC is an 8-bit current-steering DAC, this full-scale current is equivalent to 255 I, where I is a unit current. Therefore, the unit current or LSB current of the DAC signals equals 73.2 A. The reference circuitry generates a voltage across this Rset resistor equal to the bandgap voltage divided by three (407.6 mV). The RAMDAC reference current generation circuitry is designed to generate a 32-I reference current using the reference voltage and the Rset value. To generate a 32-I reference current for the RAMDAC, the reference current setting resistor, Rset, is calculated using the following equation: Rset = VREF / 32*I = 0.4076 V / 32*73.2 A = 174
8.1.3
RAMDAC Board Design Guidelines

Figure 50 shows a general cross-section of a typical four-layer board. The recommended RAMDAC routing for a four-layer board is such that the red, green, and blue video outputs are routed on the top (bottom) layer over (under) a solid ground plane to maximize the noise rejection characteristics of the video outputs. It is essential to prevent toggling signals from being routed next to the video output signals to the VGA connector. A 20-mil spacing between any video route and any other routes is recommended.
Figure 50. Cross-Sectional View of a Four-Layer Board

Board Cross Section
Avoid clock routes or high-frequency routes in the area of the RAMDAC output signals and reference resistor. Top of board Video connector
Graphics chip One solid, continuous ground plane
RAMDAC / PLL circuitry
Board components
Analog traces Ground plane
Low-frequency signal traces Digital power plane Bottom of board Segmented analog power plane for RAMDAC / PLL
RAMDAC_board_xsec
Matching the video routes (i.e., red, green, blue) from the RAMDAC to the VGA connector also is essential. The routing for these signals should be as similar as possible (i.e., same routing layer(s), same number of vias, same routing length, same bends, and jogs).
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Figure 51 shows the recommended RAMDAC component placement and routing. The termination resistance can be placed anywhere along the video route from the RAMDAC output to the VGA connector, as long as the trace impedances are designed as indicated in the following figure. It is advisable to place the pi-filters in close proximity with the VGA connector, to maximize the EMI filtering effectiveness. The LC filter components for the RAMDAC/PLL power plane, the decoupling capacitors, the latch-up protection diodes, and the reference resistor should be placed in close proximity with the respective pins. Figure 52 shows the recommended reference resistor placement and the ground connections. Figure 51. Recommended RAMDAC Component Placement & Routing
Place LC filter components and high-frequency decoupling capacitors as close as possible to power pins
Analog power plane Lf 1.8 V 1.8 V board power plane
1.8 V board power plane
Cf
LC filter 1.8 V board power plane D1
Place pi filter near VGA connector
Graphics Chip
VCCDACA1/ VCCDACA2 VCCDA Red
37.5 route Red route D2 Rt
75 routes FB C1 C2
RAMDAC
Pixel clock (from DPLL) 1.8 V board power plane D1 Green D2 37.5 route Green route Rt
Pi filter
75 routes FB VGA C1 C2
Pi filter 1.8 V board power plane D1 Blue D2 IWASTE IREF VSSDACA Place diodes close to RGB pins 37.5 route Blue route Rt 75 routes FB C1
C2
Pi filter Avoid routing toggling signals in this shaded area
Place reference resistor near IREF pin
Rset
- Match the RGB routes - Space between the RGB routes a min. of 20 mils Via straight down to the ground plane
RAMDAC comp placement routing
NOTE:
Diodes D1, D2 are clamping diodes with low leakage and low capacitive loading. An example is: California Micro Devices PAC DN006 (6 channel ESD protection array).
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Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections
Graphics Chip
IREF ball/pin
Position resistor near IREF pin.
Short, wide route connecting resistor to IREF pin
No toggling signals should be routed near Rset resistor.
Rset
Resistor for setting RAMDAC reference current 178 , 1%, 1/16 W, SMT, metal film
Large via or multiple vias straight down to ground plane

RAMDAC_ref_resistor_place_conn
8.1.4
RAMDAC Layout Recommendations

The primary concern with regard to the RGB signal length is that the RGB routes are matched and routed with the correct impedance. The impedance should be 37.5 , single-ended trace to the 75 , termination resistor. Routing from the 75 resistor to the video pi-filter and to the VGA connector should be 75 impedance. The trace width for the RGB signal should be selected for a 37.5 impedance (single-ended route) to the 75 termination resistor. The 75 termination resistor should be placed near the VGA connector. The spacing for each DAC channel routing (i.e., between red and green, green and blue outputs) should be a minimum of 20 mils. The space between the RGB signal route and other routes should be a minimum of 20 mils for each DAC route. All RGB signals should be referenced to ground. The trace width for the HSYNC and VSYNC signal routes should be selected for an approximately 40 impedance. The spacing between the HSYNC /VSYNC signal routes should be at least 10 mils, preferably 20 mils. The space between HSYNC/VSYNC signal routes and other routes should be at least 10 mils, preferably 20 mils. Route the HSYNC and VSYNC over the ground plane, if possible. The HSYNC and VSYNC signals should not route over or near any clock signals or any other high switching routing.
8.1.5
HSYNC/VSYNC Output Guidelines

The HSYNC and VSYNC output of the GMCH may exhibit up to 1.26V P-P noise when driven high under high traffic system memory conditions. To minimize this, the following is required: Add external buffers to HSYNC and VSYNC. Examples include: Series 10 resistor with a 74LVC08
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8.2
Digital Video Out

The Digital Video Out (DVO) port is a scaleable, low-interface port that ranges from 1.1V to 1.8V. This DVO port interfaces with a discrete TV encoder to enable platform support for TVOut, with a discrete TMDS transmitter to enable platform support for DVI-compliant digital displays, or with an integrated TV encoder and TMDS transmitter. The GMCH DVO port controls the video front-end devices via an I2 C interface, by means of the LTVDA and LTVCK pins. I2C is a two-wire communications bus/protocol. The protocol and bus are used to collect EDID (extended display identification) from a digital display panel and to detect and configure registers in the TV encoder or TMDS transmitter chips.
8.2.1
DVO Interface Routing Guidelines

Route data signals (LTVDATA[11:0]) with a trace width of 5 mils and a trace spacing of 20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for navigation around components or mounting holes. To break out of the GMCH, the DVO data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils. The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils, within 0.3 inch of the GMCH component. The maximum trace length for the DVO data signals is 7 inches. These signals should each be matched within 0.1 inch of the LTVCLKOUT[1] and LTVCLKOUT[0] signals. Route the LTVCLKOUT[1:0] signals 5 mils wide and 20 mils apart. This signal pair should be a minimum of 20 mils from any adjacent signals. The maximum length for LTVCLKOUT[1:0] is 7 inches and the two signals should be the same length.
8.2.2
DVO I2C Interface Considerations

LTVDA and LTVCK should be connected to the TMDS transmitter, TV encoder or integrated TMDS transmitter/TV encoder device, as required by the specifications for those devices. LTVDA and LTVCK should also be connected to the DVI connector as specified by the DVI specification. Pull-ups of 4.7 k (or pull-ups with the appropriate value derived from simulation) are required on each of LTVDA and LTVCK.
8.2.3
Leaving the DVO Port Unconnected

If the motherboard does not implement any of the possible video devices with the universal platforms DVO port, the following are recommended on the motherboard: Pull-up LTVDA and LTVCK with 4.7 k resistors at the GMCH. This will prevent the universal platforms DVO controller from confusing noise on these lines for false I2C cycles. Route LTVDATA[11:0] and LTVCLKOUT[1:0] out of the BGA to test points for use by automated test equipment (if required). These signals are part of one of the GMCH XOR chains.
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Hub Interface
The GMCH ball assignment and the ICH ball assignment have been optimized to simplify hub interface routing. It is recommended that the hub interface signals be routed directly from the GMCH to ICH with all signals referenced to VSS (see Figure 53). Layer transition should be kept to a minimum. If a layer change is required, use only two vias per net and keep all data signals and associated strobe signal on the same layer. The hub interface signals are divided into two groups: data signals (HL) and strobe signals (HL_STB). For the 8-bit hub interface, HL[0:7] are associated with HL_STB and HL_STB#. Data Signals: HL[10:0] Strobe Signals: HL_STB HL_STB# Note: HL_STB/HL_STB# is a differential strobe pair. No pull-ups or pull-downs are required on the hub interface. HL11 on the ICH should be brought out to a test point for NAND Tree testing. Each signal should be routed such that it meets the guidelines documented for its signal group. Figure 53. Hub Interface Signal Routing Example
NAND tree test point HL11 ICH
HL_STB HL_STB# HL[10:0] GMCH
CLK66
GCLK
Clocks
hub link sig routin
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9.1.1
Data Signals
Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of 20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for navigation around components or mounting holes. To break out of the GMCH and the ICH, the hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils. The signals should be separated to a trace width of 5 mils and a trace spacing of 20 mils, within 0.3 inch of the GMCH/ICH components. The maximum trace length for the hub Interface data signals is 7 inches. These signals should each be matched within 0.1 inch of the HL_STB and HL_STB# signals.
9.1.2
Strobe Signals
Due to their differential nature, the hub interface strobe signals should be 5 mils wide and routed 20 mils apart. This strobe pair should be a minimum of 20 mils from any adjacent signal. The maximum length for the strobe signals is 7 inches, and the two strobes should be the same length. Additionally, the trace length for each data signal should be matched to the trace length of the strobes, within 0.1 inch.
9.1.3
HREF Generation/Distribution
HREF is the hub interface reference voltage. It is 0.5 * 1.85V = 0.92V 2%. It can be generated using a single HREF divider or locally generated dividers (see Figure 54 and Figure 55). The resistors should be equal in value and rated at 1% tolerance (to maintain 2% tolerance on 0.9V). The value of these resistors must be chosen to ensure that the reference voltage tolerance is maintained over the entire input leakage specification. The recommended range for the resistor value is from a minimum of 100 to a maximum of 1 k (300 shown in example). The single HREF divider should not be located more than 4 inches away from either the GMCH or ICH. If the single HREF divider is located more than 4 inches away, then the locally generated hub interface reference dividers should be used instead. The reference voltage generated by a single HREF divider should be bypassed to ground at each component with a 0.01 F capacitor located close to the component HREF pin. If the reference voltage is generated locally, the bypass capacitor must be close to the component HREF pin.
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Figure 54. Single-Hub-Interface Reference Divider Circuit
1.85 V
GMCH
HUBREF
300
ICH
HUBREF
0.01 F 300
0.01 F 0.1 F
hub_IF_ref_div_1
Figure 55. Locally Generated Hub Interface Reference Dividers

1.85 V 1.85 V
GMCH
HUBREF
300
300
ICH
HUBREF
300
0.01 F
0.01 F
300
hub_IF_ref_div_2
9.1.4
Compensation
Independent hub interface compensation resistors are used by the GMCH and ICH to adjust buffer characteristics to specific board characteristics. Refer to the Intel 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet and the Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub Datasheet for details on compensation. The resistive compensation (RCOMP) guidelines are as follows: RCOMP: Tie the HLCOMP pin of each component to a 40 1% or 2% pull-up resistor (to 1.85V) via a 10-mil-wide, 0.5 inch trace (targeted at a nominal trace impedance of 40 ). The GMCH and ICH each requires their own RCOMP resistor.
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10
I/O Subsystem
This chapter provides guidelines for connecting and routing the IDE, AC97, USB, I/O APIC, SMBus, PCI, LPC/FWH, and RTC subsystems.
10.1
IDE Interface
This section contains guidelines for connecting and routing the ICH IDE interface. The ICH has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement and signal termination for both IDE channels. The ICH has integrated the series resistors that typically have been required on the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. Intel does not anticipate requiring additional series termination, but OEMs should verify the motherboard signal integrity via simulation. Additional external 0 resistors can be incorporated into the design to address possible noise issues on the motherboard. The additional resistor layout increases flexibility by providing future stuffing options. The IDE interface can be routed with 5-mil traces on 5-mil spaces, and it should be less than 8 inches long (from ICH to IDE connector). Additionally, the shortest IDE signal (on a given IDE channel) must be less than 1 inch shorter than the longest IDE signal (on the channel).
10.1.1
Cabling and Motherboard Requirements

Length of Cable: Each IDE cable must be equal to or less than 18 . Cable Capacitance: Less than 30 pF. Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is placed on the cable, it should be placed at the end of the cable. If a second drive is placed on the same cable, it should be placed on the connector next closest to the end of the cable (6 inches away from the end of the cable). Grounding: Provide a direct low-impedance chassis path between the motherboard ground and hard disk drives. Ultra ATA/66: Ultra ATA/66 requires the use of an 80-conductor cable. ICH Placement: The ICH must be placed at most 8 inches from the ATA connector(s). Termination Resistors: There is no need for series termination resistors on the data and control signals, since series termination is integrated into these signal lines on the ICH. Capacitance: The capacitance of each pin of the IDE connector on the host should be less than 25 pF when the cables are disconnected from the host. IDE Absent: If no IDE is implemented with the ICH, the input signals (xDREQ and xIORDY) can be grounded and the output signals can be left as no connects.
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Figure 56. IDE Minimum/Maximum Routing and Cable Lengths

8 in. max.
10-18 in. Traces ICH
IDE connector
5-12 in.
4-6 in.
IDE_routing_cable_len
Figure 57. Ultra ATA/66 Cable
IDE connector
Black wires: ground Grey wires: signals

ATA66_cable
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10.2
Cable Detection for Ultra ATA/66

An 80-conductor IDE cable is required for Ultra ATA/66. This cable uses the same 40-pin connector as the old 40-pin IDE cable. The wires in the cable alternate: ground, signal, ground, signal,. . . . All ground wires are tied together on the cable (and they are tied to the ground on the motherboard through the ground pins in the 40-pin connector). This cable conforms to the Small Form Factor Specification SFF-8049, which is obtainable from the Small Form Factor Committee. To determine whether the ATA/66 mode can be enabled, the chipset using the ICH requires the system BIOS to attempt to determine the type of cable used in the system. The BIOS does this in one of two ways: Host-side detection Device-side detection To determine whether the ATA/66 mode can be enabled, the ICH requires that the system software attempt to determine the type of cable used in the system. If the system software detects an 80conductor cable, it may use any Ultra DMA mode up to the highest transfer mode supported by both the chipset and the IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33).
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10.2.1
Host Side Cable Detection

BIOS Detects Cable Type Using GPIOs
Host-side detection requires the use of two GPI pins (one per IDE controller). The proper way to connect the PDIAG#/CBLID# signal of the IDE connector to the host is shown in Figure 58. All Ultra ATA/66 devices have a 10 k pull-up resistor to 5V. Most GPIO pins on the ICH and all GPIs on the FWH are not 5V tolerant. This requires a resistor divider so that 5V will not be driven to the ICH or FWH pins. The proper value of the series resistor is 15 k (as shown in the following figure). This creates a 10 k/15 k resistor divider and will produce approximately 3V for a logic high. This mechanism allows the host to sample PDIAG#/CBLID#, after diagnostics. If PDIAG#/CBLIB# is high, then there is 40-conductor cable in the system and ATA modes 3 and 4 should not be enabled. If PDIAG#/CBLID# is low, then there is an 80-conductor cable in the system.
Figure 58. Host-Side IDE Cable Detection

IDE Drive 5V To secondary IDE connector GPIO ICH GPIO 40-conductor cable
10 k
PDIAG
15 k IDE Drive 5V To secondary IDE connector
GPIO ICH GPIO 15 k
80-conductor IDE cable
10 k
PDIAG
Open
IDE_cable_det_host
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10.2.2
Device Side Cable Detection

BIOS Queries IDE Device for Cable Type
Device-side detection requires only a 0.047 F capacitor on the motherboard, as shown in Figure 59. This mechanism creates a resistor-capacitor (RC) time constant. The ATA mode 3 or 4 device will drive PDIAG#/CBLID# low and then release it (pulled up through a 10 k resistor). The device will sample the PDIAG# signal after releasing it. In an 80-conductor cable, PDIAG#/CBLID# is not connected through; therefore, the capacitor has no effect. In a 40-conductor cable, PDIAG#/CBLID# is connected through to the device; therefore, the signal will rise more slowly. The device can detect the difference in rise times and it will report the cable type to the BIOS when it sends the IDENTIFY_DEVICE packet during system boot, as described in the ATA/66 specification.
Figure 59. Drive-Side IDE Cable Detection

IDE Drive 5V
40-conductor cable ICH
10 k
PDIAG
0.047 F 5V
IDE Drive
80-conductor IDE cable ICH
10 k
PDIAG
0.047 F
Open
iDE_cable_det_drive
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10.2.3
Primary IDE Connector Requirements
Figure 60. Resistor Schematic for Primary IDE Connectors

22 - 47 PCIRST_BUF#* PDD[15:8] PDD[7] PDD[6:0] PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW# PDDREQ 5V 1 k PIORDY IRQ14 PDDACK# 470 CSEL N.C. ICH
*Due to ringing, PCIRST# must be buffered.
IDE_resistor_schem_primary
Reset#
5V 8.2 k 5.6 k 10 k
Pin 32
Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to pin 1 of the IDE connectors as the IDE reset signal. Because of high loading, the PCI_RST# signal should be buffered. 22 to 47 series resistors are required on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. IRQ14 and IRQ15 each require an 8.2 k pull-up resistor to VCC. A 1 k pull-up to 5V is required on PIORDY and SIORDY. A 470 pull-down is required on pin 28 of each connector. A 5.6 k pull-down is required on PDREQ and SDREQ. The primary IDE connector uses IRQ14, and the secondary IDE connector uses IRQ15. There is no internal pull-up or pull-down on PDD7 or SDD7 of the ICH. Devices must not have a pull-up resistor on DD7. It is recommended that a host have a 10 k pull-down resistor on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as required by the ATA-4 specification).
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10.2.4
Secondary IDE Connector Requirements
Figure 61. Resistor Schematic for Secondary IDE Connectors

22 - 47 PCIRST_BUF#* SDD[15:8] SDD[7] SDD[6:0] SDA[2:0] SDCS1# SDCS3# SDIOR# SDDREQ Secondary IDE connector 470 N.C. ICH
* Due to high loading, PCIRST# must be buffered.
IDE_resistor_schem_secondary
Reset#
SDIOW# 5V 5V 5.6 k 10 k
1 k SIORDY IRQ15 SDDACK#
8.2 k
CSEL Pin 32
Due to the elimination of the ISA bus from the ICH, PCI_RST# should be connected to pin 1 of the IDE connectors as the IDE reset signal. Because of high loading, the PCI_RST# signal should be buffered. 22 to 47 series resistors are required on RESET#. The correct value should be determined for each unique motherboard design, based on signal quality. IRQ14 and IRQ15 each require an 8.2 k pull-up resistor to VCC. A 1 k pull-up to 5V is required on PIORDY and SIORDY. A 470 pull-down is required on pin 28 of each connector. A 5.6 k pull-down is required on PDREQ and SDREQ. The primary IDE connector uses IRQ14, and the secondary IDE connector uses IRQ15. There is no internal pull-up or pull-down on PDD7 or SDD7 of the ICH. Devices must not have a pull-up resistor on DD7. It is recommended that a host have a 10 k pull-down resistor on PDD7 and SDD7 to allow the host to recognize the absence of a device at power-up (as required by the ATA-4 specification).
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10.2.5
Layout for Both Host-Side and Device-Side Cable Detection

The Intel 815 chipset platform (using the ICH) can use two methods to detect the cable type. Each mode requires a different motherboard layout. It is possible to lay out for both host-side and device-side cable detection and decide the method to be used during assembly. Figure 62 shows the layout that allows for both host-side and drive-side detection. For Host-Side Detection: R1 is a 0 resistor. R2 is a 15 k resistor. C1 is not stuffed. For Device-Side Detection: R1 is not stuffed. R2 is not stuffed. C1 is a 0.047 F capacitor.
Figure 62. Flexible IDE Cable Detection
ICH
R1 R2 C1
IDE_cable_det_flex
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10.3
AC97
The ICH implements an AC97 2.1-compliant digital controller. Any codec attached to the ICH AC-link must be AC97 2.1 compliant as well. Contact your codec IHV for information on 2.1compliant products. The AC97 2.1 specification is available on the Intel website: http://developer.intel.com/pc-supp/platform/ac97/index.htm The ICH supports the codec combinations listed in Table 27.
Table 27. AC97 Configuration Combinations

Primary Audio (AC) Modem (MC) Audio (AC) Audio/Modem (AMC) Secondary None None Modem (MC) None
As shown in Table 27, the ICH does not support two codecs of the same type on the link. For example, if an AMC is on the link, it must be the only codec. If an AC is on the link, another AC may not be present.
10.3.1
AC97 Routing
To ensure the maximum performance of the codec, proper component placement and routing techniques are required. These techniques include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground planes, from the rest of the motherboard. This includes plane splits and proper routing of signals not associated with the audio section. Contact your vendor for device-specific recommendations.
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The basic recommendations are as follows: Special consideration must be given for the ground return paths for the analog signals. Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines. Analog and digital signals should be located as far as possible from each other. Partition the board with all analog components grouped together in one area and all digital components in another. Separate analog and digital ground planes should be provided, with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. The split between planes must be a minimum of 0.05 inch wide. Keep digital signal traces, especially the clock, as far as possible from the analog input and voltage reference pins. Do not completely isolate the analog/audio ground plane from the rest of the board ground plane. There should be a single point (0.25 inch to 0.5 inch wide) where the analog/isolated ground plane connects to the main ground plane. The split between planes must be a minimum of 0.05 inch wide. Any signals entering or leaving the analog area must cross the ground split in the area where the analog ground is attached to the main motherboard ground. That is, no signal should cross the split/gap between the ground planes, which would cause a ground loop, thereby greatly increasing EMI emissions and degrading the analog and digital signal quality. Analog power and signal traces should be routed over the analog ground plane. Digital power and signal traces should be routed over the digital ground plane. Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the shortest connections to pins, with wide traces to reduce impedance. All resistors in the signal path or on the voltage reference should be metal film. Carbon resistors can be used for DC voltages and the power supply path, where the voltage coefficient, temperature coefficient, and noise are not factors. Regions between analog signal traces should be filled with copper, which should be electrically attached to the analog ground plane. Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. Locate the crystal or oscillator close to the codec. Clocking is provided from the primary codec on the link via BITCLK, and it is derived from a 24.576 MHz crystal or oscillator. Refer to the primary codec vendor for the crystal or oscillator requirements. BITCLK is a 12.288 MHz clock driven by the primary codec to the digital controller (ICH) and by any other codec present. The clock is used as the time base for latching and driving data. The ICH supports wake-on-ring from S1S4 via the AC97 link. The codec asserts SDATAIN to wake the system. To provide wake capability and/or caller ID, standby power must be provided to the modem codec. If no codec is attached to the link, internal pull-downs will prevent the inputs from floating. Therefore, external resistors are not required.
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10.3.2
AC97 Signal Quality Requirements

In a lightly loaded system (e.g., single codec down), AC97 signal integrity should be evaluated to confirm that the signal quality on the link is acceptable to the codec used in the design. A series resistor at the driver and a capacitor at the codec can be implemented to compensate for any signal integrity issues. The values used will be design dependent and should be verified for correct timings. The ICH AC-link output buffers are designed to meet the AC97 2.1 specification, with the specified load of 50 pF.
10.3.3
Motherboard Implementation
The following design considerations are provided for the implementation of an ICH platform using AC97. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. These recommendations are not the only implementation or a complete checklist, but they are based on the ICH platform. Codec Implementation Any valid combination of codecs may be implemented on the motherboard and on the riser. For ease of homologation, it is recommended that a modem codec be implemented on a CNR module. However, nothing precludes a modem codec on the motherboard. Only one primary codec may be present on the link. A maximum of two codecs can be supported in an ICH platform. Components (e.g., FET switches, buffers or logic states) should not be implemented on the AC-link signals, except for AC_RST#. Doing so would potentially interfere with timing margins and signal integrity. The ICH supports wake-on-ring from S1S4 states via the AC97 link. The codec asserts SDATAIN to wake the system. To provide wake capability and/or caller ID, standby power must be provided to the modem codec. If no codec is attached to the link, internal pull-downs will prevent the inputs from floating, so external resistors are not required. The ICH does not wake from the S5 state via the AC97 link. The SDATAIN[0:1] pins should not be left in a floating state if the pins are not connected and the AC-link is active. Rather, they should be pulled to ground through a weak (approximately 10 k) pull-down resistor. If the AC-link is disabled (by setting the shutoff bit to 1), then the ICHs internal pull-down resistors are enabled, so there is no need for external pull-down resistors. However, if the AC-link is to be active, then there should be pull-down resistors on any SDATAIN signal that might not be connected to a codec. For example, if a dedicated audio codec is on the motherboard and cannot be disabled via a hardware jumper or stuffing option, then its SDATAIN signal does not need a pulldown resistor. However, if the SDATAIN signal has no codec connected or is connected to an on-board codec that can be hardware-disabled, then the signal should have an external pull-down resistor to ground. The ICH provides internal weak pull-downs. Therefore, the motherboard does not need to provide discrete pull-down resistors. PC_BEEP should be routed through the audio codec. Care should be taken to avoid the introduction of a pop when powering the mixer up or down.
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10.4
Using Native USB Interface

The following are general guidelines for the native USB interface: Unused USB ports should be terminated with 15 k pull-down resistors on both P+/P- data lines. 15 series resistors should be placed as close as possible to the ICH (<1 inch). These series resistors provide source termination of the reflected signal. 47 pF capacitors must be placed as close as possible to the ICH as well as on the ICH side of the series resistors on the USB data lines (P0, P1). These capacitors are for signal quality (rise/fall time) and to help minimize EMI radiation. 15 k 5% pull-down resistors should be placed on the USB side of the series resistors on the USB data lines (P0, P1). They provide the signal termination required by the USB specification. The stub should be as short as possible. The trace impedance for the P0 and P1 signals should be 45 (to ground) for each USB signal P+ or P-. This may be achieved with 9-mil-wide traces on the motherboard based on the stack-up recommended in Figure 3. The impedance is 90 between the differential signal pairs P+ and P-, to match the 90 USB twisted-pair cable impedance. Note that the twistedpair characteristic impedance of 90 is the series impedance of both wires, which results in an individual wire presenting a 45 impedance. The trace impedance can be controlled by carefully selecting the trace width, trace distance from power or ground planes, and physical proximity of nearby traces. USB data lines should be routed as critical signals (i.e., hand-routing preferred). The P+/Psignal pair should be routed together and not parallel to other signal traces, to minimize crosstalk. Doubling the space from the P+/P- signal pair to adjacent signal traces will help to prevent cross-talk. The P+/P- signal traces should also be the same length, which will minimize the effect of common mode current on EMI.
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Figure 63. Recommended USB Schematic
Driver P+ < 1"
Motherboard trace 15 45 15 k Motherboard trace < 1" 15 45 47 pF 15 k USB connector
47 pF
90
Driver P-
ICH
Transmission line
USB twisted-pair cable
USB_schem
The recommended USB trace characteristics are as follows: Impedance Z0 = 45.4 Line delay = 160.2 ps Capacitance = 3.5 pF Inductance = 7.3 nH Res at 20 C = 53.9 m
10.5
I/O APIC (I/O Advanced Programmable Interrupt Controller)

Systems not using the I/O APIC should comply with the following recommendations: On the ICH Connect PICCLK directly to ground. Connect PICD0, PICD1 to ground through a 10 k resistor. On the processor PICCLK requires special implementation for universal motherboard designs. See Section 4.2.9 Connect PICD0 to 2.5V through 10 k resistors. Connect PICD1 to 2.5V through 10 k resistors.
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10.6
SMBus
The Alert on LAN signals can be used as: Alert on LAN signals: 4.7 k pull-up resistors to 3.3VSB are required. GPIOs: Pull-up resistors to 3.3VSB and the signals must be allowed to change states on power-up. (For example, on power-up the ICH drives heartbeat messages until the BIOS programs these signals as GPIOs.) The values of the pull-up resistors depend on the loading on the GPIO signal. Not Used: 4.7 k pull-up resistors to 3.3VSB are required. If the SMBus is used only for the three SPD EEPROMs (one on each RIMM), both signals should be pulled up with a 4.7 k resistor to 3.3V.
10.7
PCI
The ICH provides a PCI bus interface that is compliant with the PCI Local Bus Specification, Revision 2.2. The implementation is optimized for high-performance data streaming when the ICH is acting as either the target or the initiator on the PCI bus. For more information on the PCI bus interface, refer to the PCI Local Bus Specification, Revision 2.2. The ICH supports 6 PCI Bus masters by providing 6 REQ#/GNT# pairs. In addition, the ICH supports 2 PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair. Based on simulations performed by Intel, a maximum of 4 PCI slots should be connected to the ICH. This limit is due to timing and loading considerations established during simulations. If a system designer wants 5 PCI slots connected to the ICH, then the designers company should perform its own simulations to verify a proper design.
Figure 64. PCI Bus Layout Example for Four PCI Connectors
ICH
IO_subsys_PCI_layout
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10.8
10.8.1
LPC/FWH
In-Circuit FWH Programming
All cycles destined for the FWH will appear on the PCI. The ICH hub interface to the PCI bridge puts all processor boot cycles out on the PCI (before sending them out on the FWH interface). If the ICH is set for subtractive decode, these boot cycles can be accepted by a positive decode agent on PCI. This enables booting from a PCI card that positively decodes these memory cycles. To boot from a PCI card, it is necessary to keep the ICH in subtractive decode mode. If a PCI boot card is inserted and the ICH is programmed for positive decode, there will be two devices positively decoding the same cycle. In systems with the Intel 82380AB (ISA bridge), it also is necessary to keep the NOGO signal asserted when booting from a PCI ROM. Note that it is not possible to boot from a ROM behind the Intel 82380AB. After booting from the PCI card, one potentially could program the FWH in circuit and program the ICH CMOS.
10.8.2
FWH VPP Design Guidelines

The VPP pin on the FWH is used for programming the flash cells. The FWH supports a VPP of 3.3V or 12V. If VPP is 12V, the flash cells will program about 50% faster than at 3.3V. However, the FWH only supports 12 V VPP for 80 hours. The 12 V VPP would be useful in a programmer environment, if it typically is an event that occurs very infrequently (much fewer than 80 hours). The VPP pin must be tied to 3.3V on the motherboard.
10.9
RTC
The ICH contains a real-time clock (RTC) with 256 bytes of battery-backed SRAM. This internal RTC module provides two key functions: keeping the date and time and storing system data in its RAM when the system is powered down. This section explains the recommended hookup for the RTC circuit for the ICH. Note: This circuit is not the same as the circuit used for the PIIX4.
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10.9.1
RTC Crystal
The ICH RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 pins.
Figure 65. External Circuitry of RTC Oscillator

3.3 V VCCSUS 1 k 1 F RTCX23 Vbatt 1 k 32768 Hz Xtal R1 10 M RTCX14 C1 0.047 F C3 18 pF
1
VCCRTC2
R2 10 M VBIAS5
C2 18 pF
VSSRTC6
RTC_osc_circ
NOTES: 1. The exact capacitor value should be based on the crystal vendors recommendations. 2. VCCRTC: Power for RTC well 3. RTCX2: Crystal input 2 Connected to the 32.768 kHz crystal 4. RTCX1: Crystal input 1 Connected to the 32.768 kHz crystal 5. VBIAS: RTC bias voltage This pin is used to provide a reference voltage. This DC voltage sets a current, which is mirrored through the oscillator and buffer circuitry. 6. VSS: Ground
10.9.2
External Capacitors
To maintain RTC accuracy the external capacitor C1 must be 0.047 F. The external capacitor values for C2 and C3 should be chosen to provide the manufacturer-specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package. When the external capacitor values are combined with the capacitance of the trace, socket, and package, the closer the capacitor value can be matched to the actual load capacitance of the crystal used, the more accurate will be the RTC. The following equation can be used to choose the external capacitance values (C2 and C3): Cload = (C2 * C3) / (C2 + C3) + Cparasitic C3 can be chosen such that C3 > C2. Then C2 can be trimmed to obtain 32.768 kHz.
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10.9.3
RTC Layout Considerations

Keep the RTC lead lengths as short as possible. Approximately 0.25 inch is sufficient. Minimize the capacitance between Xin and Xout in the routing. Put a ground plane under the XTAL components. Do not route any switching signals under the external components (unless on the other side of the board). The oscillator VCC should be clean. Use a filter, such as an RC low-pass or a ferrite inductor.
10.9.4
RTC External Battery Connection

The RTC requires an external battery connection to maintain its functionality and its RAM while the ICH is not powered by the system. Example batteries are the Duracell* 2032, 2025 or 2016 (or equivalent), which give many years of operation. Batteries are rated by storage capacity. The battery life can be calculated by dividing the capacity by the average current required. For example, if the battery storage capacity is 170 mAh (assumed usable) and the average current required is 3 A, the battery life will be at least: 170,000 Ah / 3 A = 56,666 h = 6.4 years The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage decays, the RTC accuracy also decreases. High accuracy can be obtained when the RTC voltage is within the range of 3.0V to 3.3V. The battery must be connected to the ICH via an isolation diode circuit. The diode circuit allows the ICH RTC well to be powered by the battery when the system power is not available, but by the system power when it is available. To do this, the diodes are set to be reverse-biased when the system power is not available. Figure 66 is an example of a diode circuitry that can be used.
Figure 66. Diode Circuit to Connect RTC External Battery

VCC3_3SBY
1 k VccRTC 1.0 F
+ -
RTC_ext_batt_diode_circ
A standby power supply should be used to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy.
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10.9.5
RTC External RTCRESET Circuit

The ICH RTC requires some additional external circuitry. The RTCRESET (RTC Well Test) signal is used to reset the RTC well. The external capacitor (2.2 F) and the external resistor (8.2 k) between RTCRESET and the RTC battery (Vbat) were selected to create a RC time delay, such that RTCRESET will go high some time after the battery voltage is valid. The RC time delay should be within the range 1020 ms. When RTCRESET is asserted, bit 2 (RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration 3) register is set to 1, and it remains set until cleared by software. As a result, when the system boots, the BIOS knows that the RTC battery has been removed.
Figure 67. RTCRESET External Circuit for the ICH RTC
VCC3_3SBY
Diode / battery circuit 1 k Vcc RTC 1.0 F
8.2 k
RTCRESET 2.2 F
RTC_RTCRESET_ext_circ
This RTCRESET circuit is combined with the diode circuit (Figure 67), which allows the RTC well to be powered by the battery when the system power is not available. Figure 67 shows an example of this circuitry, which is used in conjunction with the external diode circuit.
10.9.6
RTC-Well Input Strap Requirements

All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC or pulled down to ground while in G3 state. RTCRST# when configured as shown in Figure 67 meets this requirement. RSMRST# should have a weak external pull-down to ground and INTRUDER# should have a weak external pull-up to VCCRTC. This prevents these nodes from floating in G3, and correspondingly prevents ICCRTC leakage that can cause excessive coin-cell drain. The PWROK input signal should also be configured with an external weak pull-down.
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10.9.7
RTC Routing Guidelines

All RTC OSC signals (RTCX1, RTCX2, VBIAS) should be routed with trace lengths shorter than 1 inch. The shorter, the better. Minimize the capacitance between RTCX1 and RTCX2 in the routing (optimally, there would be a ground line between them). Put a ground plane under all of the external RTC circuitry. Do not route any switching signals under the external components (unless on the other side of the ground plane).
10.9.8
Guidelines to Minimize ESD Events

Guidelines to minimize ESD events that may cause loss of CMOS contents: Provide a 1 F 805 X5R dielectric, monolithic, ceramic capacitor on the VCCRTC pin. This capacitor connection should not be stubbed off the trace run and should be as close as possible to the ICH. If a stub is required, its maximum length should be a few mm. The ground connection should be made through a via to the plane, with no trace between the capacitor pad and the via. Place the battery, the 1 k series current limit resistor, and the common-cathode isolation diode very close to the ICH. If this is not possible, place the common-cathode diode and the 1 k resistor as close as possible to the 1 F capacitor. Do not place these components between the capacitor and the ICH. The battery can be placed remotely from the ICH. On boards that have chassis intrusion utilizing inverters powered by the VCCRTC pin, place the inverters as close as possible to the common-cathode diode. If this is not possible, keep the trace run near the center of the board. Keep the ICH VCCRTC trace away from the board edge. If this trace must run from opposite ends of the board, keep the trace run towards the board center, away from the board edge where contact could be made by those handling the board.
10.9.9
VBIAS and DC Voltage and Noise Measurements

Steady-state VBIAS will be a DC voltage of about 0.38V 0.06V. VBIAS will be kicked when the battery is inserted, to about 0.71.0 V, but it will return to its DC value within a few msec. Noise on VBIAS must be kept to a minimum (200 mV or less). VBIAS is very sensitive and cannot be probed directly. It can be probed through a 0.01 F capacitor. Excessive noise on VBIAS can cause the ICH internal oscillator to misbehave or even stop completely. To minimize the VBIAS noise, it is necessary to implement the routing guidelines described previously as well as the required external RTC circuitry.
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11
Clocking
For an Intel 815 chipset platform, there are two clock specifications. One is for a 2-DIMM solution, and the other is for a 3-DIMM solution. In both specifications only single-ended clocking is supported. Intel 815 chipset platforms using a future 0.13 micron socket 370 processors cannot implement differential clocking.
11.1
2-DIMM Clocking
Table 28 shows the characteristics of the clock generator for a 2-DIMM solution.
Table 28. Intel CK-815 (2-DIMM) Clocks

Number 3 9 7 2 2 3 1 Clock processor clocks SDRAM clocks PCI clocks APIC clocks 48 MHz clocks 3V, 66 MHz clocks REF clock Frequency 66/100/133 MHz 100 MHz 33 MHz 16.67/33 MHz 48 MHz 66 MHz 14.31818 MHz
The following bullets list the features of the Intel CK-815 clock generator in a 2-DIMM solution: Nine copies of 100 MHz SDRAM clocks (3.3V) [SDRAM07, DClk] Seven copies of PCI clock (33 MHz ) (3.3V) Two copies of APIC clock at 33 MHz, synchronous to processor clock (2.5V) One copy of 48 MHz USB clock (3.3V) (non-SSC) (type 3 buffer) One copy of 48 MHz DOT clock (3.3V) (non-SSC) (see DOT details) Three copies of 3V, 66 MHz clock (3.3V) One copy of REF clock at 14.31818 MHz (3.3V) Ref. 14.31818 MHz xtal oscillator input Power-down pin Spread-spectrum support I2C support for turning off unused clocks 56-pin SSOP package Figure 68 shows the Intel 815 chipset platform clock architecture for a 2-DIMM solution.
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Figure 68. Platform Clock Architecture (2 DIMMs)

ITP
CPU 2_ITP APIC 0 CPU 1 CPU 0 52 55 50 49
Processor
2.5 V
Clock Synthesizer PW RDW N# SEL1 SEL0 SData SClk 32 29 28 30 31
AGP Host unit
Data 46 45 43 42 40 39 37 36 34
SDRAM(0) SDRAM(1) SDRAM(2) SDRAM(3) SDRAM(4) SDRAM(5) SDRAM(6) SDRAM(7) DCLK 3.3 V 3V66 0 DOT
M ain Mem ory 2 DIM Ms
Address
Graphics
GM CH
Mem ory unit
Control
Hub I/F
7 26 14.318 MHz Dot clock
3V66 1 REF PCI 0 / ICH USB
8 1 11 25
I/O Controller Hub
32.768 kHz
APIC 1 2.5 V
54
PCI 1 3.3 V PCI PCI PCI PCI PCI PCI 2 3 4 5 6 7
12
SIO
13 15 16 18 19 20
PCI total of 6 devices (ATX ) 5 slots + 1 down
clk_arch_2DIMM
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11.2
3-DIMM Clocking
Table 29 shows the characteristics of the clock generator for a 3-DIMM solution.
Table 29. Intel CK-815 (3-DIMM) Clocks

Number 2 13 2 1 2 3 1 Clock processor clocks SDRAM clocks PCI clocks APIC clocks 48 MHz clocks 3V, 66 MHz clocks REF clock Frequency 66/100/133 MHz 100 MHz 33 MHz 33 MHz 48 MHz 66 MHz 14.31818 MHz
The following bullets list the features of the Intel CK-815 clock generator: Thirteen copies of SDRAM clocks Two copies of PCI clock One copy of APIC clock One copy of 48 MHz USB clock (3.3V) (non-SSC) (type 3 buffer) One copy of 48 MHz DOT clock (3.3V) (non-SSC) (see DOT details) Three copies of 3V, 66 MHz clock (3.3V) One copy of ref. clock @ 14.31818 MHz (3.3V) Ref. 14.31818 MHz xtal oscillator input Spread-spectrum support I2C support for turning off unused clocks 56-pin SSOP package Figure 69 shows the Intel 815E chipset platform clock architecture for a 3-DIMM solution.
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Figure 69. Universal Platform Clock Architecture (3 DIMMs)

Processor
APIC CPU 1 CPU 0 1 53 54
2.5 V
CK 815 3D
Host I/F
3V66 AGP 12
AGP / local m em ory
AGIP / local m em ory
SDRAM(0) SDRAM(1) SDRAM(2) SDRAM(3) SDRAM(4) SDRAM(5) SDRAM(6) SDRAM(7) SDRAM(8) SDRAM(9) SDRAM(10) SDRAM(11) SDRAM(12) 3V66 0 3V66 1 DOT
51 50 47 46 45 42 41 38 37 36 33 32 29 10 11 27
GM CH Main Mem ory 3 DIMMs System m em ory Hub I/F 66/266
GFX Dot CLK
USB
26
REF 0 14.3 MHz
I/O Controller Hub
PCI 0 / ICH PCI 1
15 16
SIO
PCI 1 to zero delay
PCI slots / down

clk_arch_3DIMM
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11.3
Clock Routing Guidelines

This section presents the generic clock routing guidelines for both 2-DIMM and 3-DIMM boards. For 3-DIMM boards, additional analysis must be performed by the motherboard designer to ensure that the clocks generated by the external PCI clock buffer meet the PCI specifications for clock skew at the receiver, when compared with the PCI clock at the ICH.
Figure 70. Clock Routing Topologies

Layout 1 CK815 Section 1
33 Section 2 Connector
33 Section 2 10 pF Section 3 22 pF
33 Section 2
Processor
Section 0
33 CK815 Section 1 Section 3
GMCH
33 Section 2
Layout 5 33 CK815 Section 1 22 pF

clk_routing_topo
Section 2
Connector
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Table 30. Simulated Clock Routing Solution Space

Destination SDRAM MCLK GMCH SCLK
3
Topology from Previous Figure Layout 5 Layout 2 Layout 3
Section 0 Length N/A N/A < 0.1
Section 1 Length < 0.5 < 0.5=L1 < 0.5 <0.5
Section 2 Length A1 A + 3.5 L1 A + 5.2
Section 3 Length N/A 0.5 A + 8
Processor BCLK GMCH HCLK GMCH HUBCLK ICH HUBCLK ICH PCICLK AGP CLK
Layout 4 Layout 4 Layout 4 Layout 4
N/A N/A N/A N/A
<0.5 <0.5 <0.5 <0.5
A + 8 A + 8 A + 8 A + 3 to A + 4 A + 8.5 to A + 14 A + 5 to A + 11
N/A N/A N/A N/A
PCI down2
Layout 4
N/A
<0.5
N/A
PCI slot2
Layout 1
N/A
<0.5
NOTES: 1. Length A has been simulated up to 6 inches. The length must be matched between SDRAM MCLK lines by 100 mils. 2. All PCI clocks must be within 6 inches of the ICH PCICLK route length. Routing on PCI add-in cards must be included in this length. In the presented solution space, the ICH PCICLK was considered to be the shortest in the 6 inches trace routing range, and other clocks were adjusted from there. The system designer may choose to alter the relationship of PCI device and slot clocks, as long as all PCI clock lengths are within 6 inches. Note that the ICH PCICLK length is fixed to meet the skew requirements of the ICH PCICLK to ICH HUBCLK. 3. 22 pF Load capacitor should be placed 0.5 inch from GMCH Pin.
General Clock Layout Guidelines

All clocks should be routed 5 mils wide with 15-mil spacing to any other signals. It is recommended to place capacitor sites within 0.5 inch of the receiver of all clocks. They are useful in system debug and AC tuning. Series resistor for clock guidelines: 22 for GMCH SCLK and SDRAM clocks. All other clocks use 33 . Each DIMM clock should be matched within 10 mils.
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11.4
Clock Decoupling
Several general layout guidelines should be followed when laying out the power planes for the Intel CK-815 clock generator. Isolate the power plane to each clock group. Place local decoupling as close as possible to power pins and connect with short, wide traces and copper. Connect pins to the appropriate power plane with power vias (larger than signal vias). Bulk decoupling should be connected to plane with 2 or more power vias. Minimize clock signal routing over plane splits. Do not route any signals underneath the clock generator on the component side of the board. An example signal via is a 14-mil finished hole with a 24-mil to 26-mil path. An example power via is an 18-mil finished hole with a 33-mil to 38-mil path. For large decoupling or power planes with large current transients, a larger power via is recommended
11.5
Clock Driver Frequency Strapping

An Intel CK-815-compliant clock driver device uses two of its pins to determine whether processor clock outputs should run at 133 MHz, 100 MHz, or 66 MHz. The pin names are SEL0 and REF0. In addition, a third strapping pin is defined (SEL1) that must be pulled high for normal clock driver operation. Refer to the appropriate Intel CK-815 clock driver specification for detailed strap timings and the logic encoding of straps. SEL0 and REF0 are driven by either the processor, which depends on the processor populated in the 370-pin socket, or pull-up resistors on the motherboard. While SEL0 is a pure input to a Intel CK-815-compliant clock driver, REF0 is also the 14 MHz output that drives the ICH and other devices on the platform. In addition to sampling BSEL[1:0] at reset, Intel CK-815-compliant clock drivers are configured by the BIOS via a two-wire interface to drive SDRAM clock outputs at either 100 MHz (default) or 133 MHz (if all system requirements are met).
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11.6
Clock Skew Assumptions

The clock skew assumptions in the following table are used in the system clock simulations.
Table 31. Simulated Clock Skew Assumptions

Skew Relationships HCLK @ GMCH to HCLK @ processor HCLK @ GMCH to SCLK @ GMCH SCLK @ GMCH to SCLK @ SDRAM HLCLK @ GMCH to SCLK @ GMCH HLCLK @ GMCH to HCLK @ GMCH HLCLK @ GMCH to HLCLK @ ICH HLCLK @ ICH to PCICLK @ ICH PCICLK @ ICH to PCICLK @ other PCI devices HLCLK @ GMCH to AGPCLK @ connector Target 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns Tolerance () 200 ps 600 ps 630 ps 900 ps 700 ps 375 ps 900 ps 2.0 ns window Notes
Assumes ganged clock outputs will allow maximum of 50 ps skew 500 ps pin-to-pin skew 100 ps board/package skew 250 ps pin-to-pin skew 380 ps board + DIMM variation 500 ps pin-to-pin skew 400 ps board/package skew 500 ps pin-to-pin skew 200 ps board/package skew 175 ps pin-to-pin skew 200 ps board/package skew 500 ps pin-to-pin skew 400 ps board/package skew 500 ps pin-to-pin skew 1.5 ns board/add-in skew Total electrical length of AGP connector + add-in card is 750 ps (according to AGP2.0 specification and AGP design guide 1.0). Motherboard clock routing must account for this additional electrical length. Therefore, AGPCLK routed to the connector must be shorter than HLCLK to the GMCH, to account for this additional 750 ps.
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11.7
Intel CK-815 Power Gating On Wake Events

For systems providing functionality with future 0.13 micron socket 370 processors, special handling of wake events is required. When a wake event is triggered, the GMCH and the Intel CK815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events: 1. Power is not connected to the Intel CK-815-compliant clock driver until VTTPWRGD12 is asserted. 2. Clocks to the ICH stabilize before the power supply asserts PWROK to the ICH. There is no guarantee this will occur as the implementation for the previous step relies on the 12V supply. Thus, it is necessary to gate PWROK to the ICH from the power supply while the Intel CK-815 is given sufficient time for the clocks to become stable. The amount of time required is a minimum 20 ms. 3. ICH takes the GMCH out of reset. 4. GMCH samples BSEL[1:0]. Intel CK-815 will have sampled BSEL[1:0] much earlier. Refer to Chapter 4 for full implementation details.
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12
Power Delivery
This chapter contains power delivery guidelines. Table 32 provides definitions fro power delivery terms used in this chapter.
Table 32. Power Delivery Terminology

Term Suspend-To-RAM (STR) Description In the STR state, the system state is stored in main memory and all unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered. This state is used in the Customer Reference Board (CRB) to satisfy the S3 ACPI power management state. During full-power operation, all components on the motherboard remain powered. Note that full-power operation includes both the full-on operating state and the S1 (CPU stop-grant state) state. During suspend operation, power is removed from some components on the motherboard. The CRB supports two suspend states: Suspend-to-RAM (S3) and Soft-off (S5). An ATX power supply has 6 power rails: +5V, -5V, +12V, -12V, +3.3V, 5VSB. In addition to these power rails, several other power rails are created with voltage regulators on the CRB. A power rail that is only on during full-power operation. These power rails are on when the PSON signal is asserted to the ATX power supply. The core power rails that are distributed directly from the ATX power supply are: 5V, 12V and +3.3V. A power rail that in on during suspend operation (these rails are also on during full-power operation). These rails are on at all times (when the power supply is plugged into AC power). The only standby power rail that is distributed directly from the ATX power supply is: 5VSB (5V Standby). There are other standby rails that are created with voltage regulators on the motherboard. A derived power rail is any power rail that is generated from another power rail. For example, 3.3VSB is usually derived (on the motherboard) from 5VSB using a voltage regulator (on the CRB, 3.3VSB is derived from 5V_DUAL). A dual power rail is derived from different rails at different times (depending on the power state of the system). Usually, a dual power rail is derived from a standby supply during suspend operation and derived from a core supply during full-power operation. Note that the voltage on a dual power rail may be misleading.
Full-power operation
Suspend operation
Power rails
Core power rail
Standby power rail
Derived power rail
Dual power rail
Figure 71 shows a power delivery architecture example for a system based on the Intel 815 chipset platform. This power delivery architecture supports the Instantly Available PC Design Guidelines via the suspend-to-RAM (STR) state. During STR, only the necessary devices are powered. These devices include: main memory, the ICH resume well, PCI wake devices (via 3.3 Vaux), AC97, and optionally USB (USB can be powered only if sufficient standby power is available.). To ensure that enough power is available during STR, a thorough power budget should be completed. The power requirements should include each devices power requirements, both in suspend and in full-power. The power requirements should be compared with the power budget
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supplied by the power supply. Due to the requirements of main memory and the PCI 3.3 Vaux (and possibly other devices in the system), it is necessary to create a dual power rail. The solutions in this Design Guide are only examples. Many power distribution methods achieve the similar results. When deviating from these examples, it is critical to consider the effect of a change. Figure 71. Power Delivery Map
Intel 815 Chipset Platform Power Map
ATX P/S with 720 mA 5 VSB 5% 5V 5% 3.3 V 5% 12 V -12 V 5% 10% VRM 8.5 Processor Core: VCC_VID: 1.5 V 28.5 A S0, S1 Core: VCC_VID: 2.0V Core: VCC_VID: 1.75 V 15.6A S0,S1 S1 22.6 A S0, VTT: 1.25 V 2.7 A S0, S1 VTT: 1.5 V 0.135 V 2.7 A S0, S1 VCC3_3: 3.3 V 0.165 V 15 mA S0, S1 Fan Serial ports Serial xceivers-12: 12 V 1.2 V 22 mA S0, S1 Serial xceivers-N12: -12 V 1.2 V 28 mA S0, S1 Serial xceivers-5: 5 V 0.25 V 30 mA S0, S1 -12 V
VTT regulator
5 V dual switch 2.5 V regulator CK815-2.5: 2.5 V 0.125 V 100 mA S0, S1 CK815-3.3: 3.3 V 0.165 V 280 mA S0, S1
CLK Super I/O LPC super I/O: 3.3V 0.3V 50 mA S0, S1 PS/2 keyboard/mouse 5 V 0.5 V 1 A S0, S1 Intel 815 chipset
5V_DUAL
VDDQ regulator 1.8 V regulator
GMCH VDDQ 2.0 A S0, S1 GMCH core: 1.8 V 3% 1.40 A S0, S1 GMCH: 3.3 V 0.165 V 1.40 A S0, S1
3.3 VSB regulator
GMCH: 3.3 VSB 0.165 V 110 mA S3, S5 ICH hub I/O: 1.8 V 0.09 V 55 mA S0, S1 ICH core: 3.3 V 0.3 V 300 mA S0, S1 ICH resume: 3.3 VSB 0.3 V 1.5 mA S0, S1; 300 A S3, S5 ICH RTC: 3.3 VSB 0.3 V 5 A S0, S1, S3, S5 FWH core: 3.3 V 0.3 V 67 mA S0, S1
AC'97 AC'97 12V: 12 V 0.6 V 500 mA S0, S1 AC'97 -12 V: -12 V 1.2 V 100 mA S0, S1 AC'97 5 V: 5 V 0.25 V 1.00 A S0,S1 AC'97 5 VSB: 5 VSB 0.25 V 500 mA S0, S1 AC'97 3.3 V: 3.3 V 0.165 V 1.00 A S0,S1 AC'97 3.3 VSB: 3.3 VSB 0.165 V 150 mA S3, S5
2 DIMM slots: 3.3 VSB 0.3 V 4.8 A S0, S1; 64 mA S3 PCI 82559 LAN down 3.3 VSB 0.3 V 195 mA S0,S1; 120 mA S3, S5 (3) PCI 3.3 Vaux: 3.3 VSB 0.3 V 1.125 A S0, S1; 60 mA S3, S5
USB cable power: 5 V 0.25 V 1 A S0, S1; 1 mA S3, S5
Notes: Shaded regulators / components are ON in S3 and S5. KB / mouse will not support STR. Total max. power dissipation for GMCH = 4 W. Total max. power dissipation for AC'97 = 15 W.
pwr_del_map
In addition to the power planes provided by the ATX power supply, an instantly available Intel 815 chipset platform (using Suspend-to-RAM) requires six power planes to be generated on the board. The requirements for each power plane are documented in this section. In addition to onboard voltage regulators, the CRB will have a 5V Dual Switch.
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5V Dual Switch
This switch will power the 5V Dual plane from the 5V core ATX supply during full-power operation. During Suspend-to-RAM, the 5V Dual plane will be powered from the 5V Standby power supply. Note: The voltage on the 5V Dual plane is not 5V! There is a resistive drop through the 5V Dual Switch that must be considered. Therefore, NO COMPONENTS should be connected directly to the 5V Dual plane. On the CRB, the only devices connected to the 5V Dual plane are voltage regulators (to regulate to lower voltages). Note: This switch is not required in an Intel 815 chipset platform that does not support Suspend-to-RAM (STR).
VTT
This power plane is used to power the AGTL/AGTL+ termination resistors. Refer to the latest revisions of: Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) Datasheets Note: This regulator is required in ALL designs.
1.85V
The 1.85V plane powers the GMCH core and the ICH hub interface I/O buffers. This power plane has a total power requirement of approximately 1.7A. The 1.85V plane should be decoupled with a 0.1 F and a 0.01 F chip capacitor at each corner of the GMCH and with a single 1 F and 0.1 F capacitor at the ICH. Note: This regulator is required in ALL designs.
VDDQ
The VDDQ plane is used to power the GMCH AGP interface and the graphics component AGP interface. Refer to the AGP Interface Specification, Revision 2.0 (http://www.agpforum.org) and ECR#43 and ECR#44 for specific VDDQ delivery requirements. For the consideration of component long term reliability, the following power sequence is strongly recommended while the GMCHs AGP interface is running at 3.3V. If the AGP interface is running at 1.5V, the following power sequence recommendation is no longer applicable. The power sequence recommendations are: During the power-up sequence, the 1.85V must ramp up to 1.0V before 3.3V ramps up to 2.2V. During the power-down sequence, the 1.85V CAN NOT ramp below 1.0V before 3.3V ramps below 2.2V. The same power sequence recommendation also applies to the entrance and exit of S3 state, since the GMCH power is compete off during the S3 state.
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Refer to Section 12.4.1 for more information on the power ramp sequence requirement between 3.3V and 1.85V. System designers need to be aware of this requirement while designing the voltage regulators and selecting the power supply. For further details on the voltage sequencing requirements, refer to the Intel 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) For Use With Universal Socket 370 Datasheet. Note: This regulator is required in ALL designs (unless the design does not support 1.5V AGP, and therefore does not support 4X AGP).
3.3VSB
The 3.3VSB plane powers the I/O buffers in the resume well of the ICH and the PCI 3.3Vaux suspend power pins. The 3.3Vaux requirement state that during suspend, the system must deliver 375 mA to each wake-enabled card and 20 mA to each non wake-enabled card. During full-power operation, the system must be able to supply 375 mA to each card. Therefore, the total current requirement is: Full-power Operation: 375 mA * number of PCI slots Suspend Operation: 375+20 mA * (number of PCI slots 1) In addition to the PCI 3.3Vaux, the ICH suspend well power requirements must be considered as shown in Figure 71. Note: This regulator is required in all designs.
1.85VSB
The 1.85VSB plane powers the logic to the resume well of the ICH. This should not be used for VCMOS.
12.1
Thermal Design Power

Thermal Design Power (TDP) is defined as the estimated maximum possible expected power generated in a component by a realistic application. It is based on extrapolations in both hardware and software technology over the life of the product. It does not represent the expected power generated by a power virus. The TDP for the GMCH component is 5.1 W.
12.1.1
Pull-Up and Pull-Down Resistor Values

The pull-up and pull-down values are system dependent. The appropriate value for a system can be determined from an AC/DC analysis of the pull-up voltage used, the current drive capability of the output driver, the input leakage currents of all devices on the signal net, the pull-up voltage tolerance, the pull-up/pull-down resistor tolerance, the input high-voltage/low-voltage specifications, the input timing specifications (RC rise time), etc. Analysis should be performed to determine the minimum/maximum values usable on an individual signal. Engineering judgment should be used to determine the optimal value. This determination can include cost concerns, commonality considerations, manufacturing issues, specifications, and other considerations.
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A simplistic DC calculation for a pull-up value is:
RMAX = (VCCPU MIN - VIH MIN) / ILEAKAGE MAX RMIN = (VCCPU MAX - VIL MAX) / IOL MAX
Since ILEAKAGE MAX is normally very small, RMAX may not be meaningful. RMAX also is determined by the maximum allowable rise time. The following calculation allows for t, the maximum allowable rise time, and C, the total load capacitance in the circuit, including the input capacitance of the devices to be driven, the output capacitance of the driver, and the line capacitance. This calculation yields the largest pull-up resistor allowable to meet the rise time t.
RMAX = -t / (C * In(1-(VIH MIN / VCCPU MIN) ) )

Figure 72. Pull-Up Resistor Example
Vccpu min. Vccpu max.
Rmax ILeakage max. VIH min. IOL max.
Rmin VIL max.

pwr_pullup_res
12.2
ATX Power Supply PWRGOOD Requirements

The PWROK signal must be glitch free for proper power management operation. The ICH sets the PWROK_FLR bit (ICH GEN_PMCON_2, General PM Configuration 2 Register, PM-dev31: function 0, bit 0, at offset A2h). If this bit is set upon resume from S3 power-down, the system will reboot and control of the system will not be given to the program running when entering the S3 state. System designers should insure that PWROK signal designs are glitch free.
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12.3
Power Management Signals

A power button is required by the ACPI specification. PWRBTN# is connected to the front panel on/off power button. The ICH integrates 16 ms debouncing logic on this pin. AC power loss circuitry has been integrated into the ICH to detect power failure. It is recommended that the ATXPWROK signal from the power supply connector be routed through a Schmitt trigger to square-off and maintain its signal integrity. It should not be connected directly to logic on the board. PWROK logic from the power supply connector can be powered from the core voltage supply. RSMRST# logic should be powered by a standby supply, while making sure that the input to the ICH is at the 3V level. The RSMST# signal requires a minimum time delay of 1 ms from the rising edge of the standby power supply voltage. A Schmitt trigger circuit is recommended to drive the RSMRST# signal. To provide the required rise time, the 1-ms delay should be placed before the Schmitt trigger circuit. The reference design implements a 20 ms delay at the input of the Schmitt trigger to ensure that the Schmitt trigger inverters have sufficiently powered up before switching the input. Also ensure that voltage on RSMRST# does not exceed VCC(RTC). It is recommended that 3.3V logic be used to drive RSMRST# to alleviate rise time problems when using a resistor divider from VCC5. The PWROK signal to the chipset is a 3V signal. The core well power valid to PWROK asserted at the chipset is a minimum of 1 ms. PWROK to the chipset must be deasserted after RSMRST#. PWRGOOD signal to processor is driven with an open-collector buffer pulled up to 2.5V, using a 330 resistor. RI# can be connected to the serial port if this feature is used. To implement ring indicate as a wake event, the RS232 transceiver driving the RI# signal must be powered when the ICH suspend well is powered. This can be achieved with a serial port transceiver powered from the standby well that implements a shutdown feature. SLP_S3# from the ICH must be inverted and then connected to PSON of the power supply connector to control the state of the core well during sleep states. For an ATX power supply, when PSON is low, the core wells are turned on. When PSON is high, the core wells from the power supply are turned off.
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12.3.1
Power Button Implementation

The following items should be considered when implementing a power management model for a desktop system. The power states are as follows: S1 Stop Grant (processor context not lost) S3 - STR (Suspend to RAM) S4 - STD (Suspend to Disk) S5 - Soft-off Wake: Pressing the power button wakes the computer from S1S5. Sleep: Pressing the power button signals software/firmware in the following manner: a. If SCI is enabled, the power button will generate an SCI to the operating system (OS). 1. The OS will implement the power button policy to allow orderly shutdowns. 2. Do not override this with additional hardware. b. If SCI is not enabled: 1. Enable the power button to generate an SMI and go directly to soft-off or a supported sleep state. 2. Poll the power button status bit during POST while SMIs are not loaded and go directly to soft-off if it gets set. 3. Always install an SMI handler for the power button that operates until ACPI is enabled. Emergency Override: Pressing the power button for 4 seconds goes directly to S5. a. This is only to be used in EMERGENCIES when system is not responding. b. This will cause the user data to be lost in most cases. Do not promote pressing the power button for 4 seconds as the normal mechanism to power the machine off. This violates ACPI. To be compliant with the latest PC9x specification, machines must appear to the user to be off when in the S1S4 sleeping states. This includes: a. All lights, except a power state light, must be off. b. The system must be inaudible: silent or stopped fan, drives off.
1. 2.
3.
4. 5.
Note: Contact Microsoft for the latest information concerning PC9x or PC200x and Microsoft Logo programs.
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12.4
1.85V/3.3V Power Sequencing

This section shows the timings among various signals during different power state transitions.
Figure 73. G3-S0 Transition

Vcc3.3sus t1 RSMRST# t2 SLP_S3# t4 SLP_S5# t5 SUS_STAT# t6 Vcc3.3core t7 CPUSLP# t8 PWROK t9 Clocks Clocks invalid t10 t11 PCIRST# t12 Cycle 1 from GMCH Cycle 1 from ICH t13 Cycle 2 from GMCH Cycle 2 from ICH t14 STPCLK# t15 Freq straps t17 CPURST# t16 Clocks valid t3
pwr_G3-S0_trans
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Figure 74. S0-S3-S0 Transition

Vcc3.3sus RSMRST# t24 STPCLK# Stop grant cycle t18 CPUSLP# Go_C3 from ICH Ack_C3 from GMCH DRAM
DRAM active
t7
DRAM in STR (CKE low)
DRAM active
t19 SUS_STAT# t20 PCIRST# t12 Cycle 1 from GMCH Cycle 1 from ICH t13 Cycle 2 from GMCH Cycle 2 from ICH t17 CPURST# t21 SLP_S3# SLP_S5# t8 PWROK t22 Vcc3.3core t9 Clocks Clocks valid Clocks invalid t15 Freq straps Wake event
pwr_S0-S3-S0_trans
t11
t23
Clocks valid t16
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Figure 75. S0-S5-S0 Transition

Vcc3.3sus RSMRST# t24 STPCLK# Stop grant cycle t18 CPUSLP# Go_C3 from ICH Ack_C3 from GMCH DRAM
DRAM active
t7
DRAM in STR (CKE low) t19
DRAM active
SUS_STAT# t20 PCIRST# t12 Cycle 1 from GMCH Cycle 1 from ICH t13 Cycle 2 from GMCH Cycle 2 from ICH t17 CPURST# t21 SLP_S3# t25 t26 SLP_S5# t8 PWROK t22 Vcc3.3core t9 Clocks Clocks valid Clocks invalid t15 Freq straps Wake event
pwr_S0-S5-S0_trans
t11
t23
Clocks valid t16
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Table 33. Power Sequencing Timing Definitions

Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 Parameter VccSUS Good to RSMRST# inactive VccSUS Good to SLP_S3#, SLP_S5#, and PCIRST# active RSMRST# inactive to SLP_S3# inactive RSMRST# inactive to SLP_S5# inactive RSMRST# inactive to SUS_STAT# inactive SLP_S3#, SLP_S5#, SUS_STAT# inactive to Vcc3.3core good Vcc3.3core good to CPUSLP# inactive Vcc3.3core good to PWROK active Vcc3.3core good to clocks valid Clocks valid to PCIRST# inactive PWROK active to PCIRST# inactive PCIRST# inactive to Cycle 1 from GMCH Cycle 1 from ICH to Cycle 2 from GMCH PCIRST# inactive to STPCLK deassertion PCIRST# to frequency straps valid Cycle 2 from ICH to frequency straps invalid Cycle 2 from ICH to CPURST# inactive Stop Grant Cycle to CPUSLP# active CPUSLP# active to SUS_STAT# active SUS_STAT# active to PCIRST# active PCIRST# active to SLP_S3# active PWROK inactive to Vcc3.3core not good Wake event to SLP_S3# inactive PCIRST# inactive to STPCLK# inactive SLP_S3# active to SLP_S5# active SLP_S5# inactive to SLP_S3# inactive 2 1 20 2 1 1 2 3 4 2 3 1 -4 * * 500 0.9 1.1 1 60 4 4 180 110 8 1 3 2 1 1 1 * Min. 1 Max. 25 50 4 4 4 * 50 * * ns Units ms Ns RTC clocks RTC clocks RTC clocks
s
ms ms ns PCI clocks PCI clocks ns ns PCI clocks RTC clock RTC clocks RTC clocks ns RTC clocks PCI clocks RTC clocks RTC clocks
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12.4.1
VDDQ/VCC1_85 Power Sequencing

For the consideration of long term component reliability, the following power sequence is strongly recommended while the AGP interface of the GMCH is running at 3.3V. If the AGP interface is running at 1.5V, the following power sequence recommendation is no longer applicable. The power sequence recommendation is: During the power-up sequence, the 1.85V must ramp up to 1.0V before 3.3V ramps above 2.2V During the power-down sequence, the 1.85V cannot ramp below 1.0V before 3.3V ramps below 2.2V The same power sequence recommendation also applies to the entrance and exit of S3 state System designers need to be aware of this requirement while designing the voltage regulators and selecting the power supply. An example VDDQ power sequencing circuit is shown in Figure 76.
Figure 76. VDDQ Power Sequencing Circuit

3.3V
1.85V 1 K
1 K SHDN VIN IPOS INEG GATE COMP

vddq_pwr_seq
1 K
GND FB
12.4.2
1.85V/3.3V Power Sequencing

The ICH has two pairs of associated 1.85V and 3.3V supplies. These are {Vcc1_8, Vcc3_3} and {VccSus1_8, VccSus3_3}. These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0V. The 1.85V supply may come up before the 3.3V supply without violating this rule (though this is generally not practical in a desktop environment, since the 1.85V supply is typically derived from the 3.3V supply by means of a linear regulator). One serious consequence of violation of the 2V Rule, is electrical overstress of oxide layers, resulting in component damage. The majority of the ICH I/O buffers are driven by the 3.3V supplies, but are controlled by logic that is powered by the 1.85V supplies. Thus, another consequence of faulty power sequencing arises if the 3.3V supply comes up first. In this case the I/O buffers will be in an undefined state until the 1.85V logic is powered up. Some signals that are defined as Input-only actually have
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output buffers that are normally disabled, and the ICH may unexpectedly drive these signals if the 3.3V supply is active while the 1.85V supply is not. Figure 77 shows an example power-on sequencing circuit that ensures the 2V Rule is obeyed. This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.85V supply tracks the 3.3V supply. The NPN transistor controls the current through PNP from the 3.3V supply into the 1.85V power plane by varying the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.85V plane, current will not flow from the 3.3V supply into 1.85V plane when the 1.85V plane reaches 1.85V. Figure 77. Example 1.85V/3.3V Power Sequencing Circuit
+3.3V +1.8V
220 220 Q2 NPN Q1 PNP
470
When analyzing systems that may be marginally compliant to the 2V Rule, pay close attention to the behavior of the ICHs RSMRST# and PWROK signals, since these signals control internal isolation logic between the various power planes: RSMRST# controls isolation between the RTC well and the Resume wells. PWROK controls isolation between the Resume wells and Main wells If one of these signals goes high while one of its associated power planes is active and the other is not, a leakage path will exist between the active and inactive power wells. This could result in high, possibly damaging, internal currents.
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12.4.3
3.3V/V5REF Sequencing
V5REF is the reference voltage for 5V tolerance on inputs to the ICH. V5REF must be powered up before or simultaneously to VCC3_3. It must also power down after or simultaneous to VCC3_3. The rule must be followed to ensure the safety of the ICH. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the VCC3_3 rail. Figure 78 shows a sample implementation of how to satisfy the V5REF/3.3V sequencing rule. This rule also applies to the stand-by rails, but in most platforms, the VCCSus3_3 rail is derived from the VCCSus5 and therefore, the VCCSus3_3 rail will always come up after the VCCSus5 rail. As a result, V5REF_Sus will always be powered up before VCCSus3_3. In platforms that do not derive the VCCSus3_3 rail from the VCCSus5 rail, this rule must be comprehended in the platform design. As an additional consideration, during suspend the only signals that are 5V tolerant are USBOC. If these signals are not needed during suspend, V5REF_Sus can be hooked to the VCCSus3_3 rail.
Figure 78. 3.3V/V5REF Sequencing Circuitry Vcc Supply (3.3V) 1 K 1.0 uF 5V Supply
To System
VREF
To System
vref_circuit
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13.1

Design Review Checklist
Introduction
This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an Intel 815 chipset platform for use with the universal socket 370. This is not a complete list and does not guarantee that a design will function properly. For items other than those in the following text, refer to the latest revision of the design guide for moredetailed instructions regarding motherboard design.
Design Checklist Summary

The following set of tables provides design considerations for the various portions of a design. Each table describes one of those portions and is titled accordingly. Contact your Intel Field Representative in the event of questions or issues regarding the interpretation of the information in these tables.
13.2
13.2.1
Processor Checklist
GTL Checklist
Checklist Items Recommendations
A[35:3]# BNR#, BPRI#, DBSY#, DEFER#, DRDY#, D[63:0]#, HIT#, HITM#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY# ADS# BREQ[0]# (BR0#) RESET# (AH4)
Connect A[31:3]# to GMCH. Leave A[35:32]# as No Connect (not supported by chipset). Connect to GMCH.
Resistor site for 56 pull-up to VTT placed within 150 mils of GMCH for debug purpose. Connect to GMCH. 33 pull-down resistor to ground Terminate to VTT through 86 resistor, decoupled through 22 resistor in series with 10 pF capacitor to ground. Connect to GMCH. For ITP, also connect to ITP pin 2 (RESET#) with 240 series resistor. 1 k series resistor to RESET#.
RESET2# (X4)
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13.2.2
CMOS Checklist
IERR# PREQ# THERMTRIP# A20M#, IGNNE#, INIT#, INTR, NMI, SLP#, SMI#, STPCLK# FERR# FLUSH# PWRGOOD
150 pull-up resistor to VCCCMOS if tied to custom logic, or leave as No Connect (not used by chipset) 200300 pull-up resistor to VCCCMOS / Connect to ITP or else leave as No Connect. See Section 5.3.1. 150 pull-up to VCMOS / Connect to ICH
Requires 150 pull-up to VCCCMOS/Connect to ICH. Requires 150 pull-up to VCCCMOS. (Not used by chipset.) 330 pull-up to VCC2_5 /1.8 k pull-down resistor to ground /Connect to POWERGOOD logic.
13.2.3
TAP Checklist for 370-Pin Socket Processors

TCK TMS TDI TDO TRST# PRDY#
39 pull-down resistor to ground / Connect to ITP. 39 pull-up resistor to VCMOS / Connect to ITP 200330 pull-up resistor to VCMOS / Connect to ITP. 150 pull-up resistor to VCMOS / Connect to ITP. 500-680 pull-down resistor to ground / Connect to ITP. Pull-up resistor that matches GTL characteristic impedance to VTT / 240 series resistor to ITP.
Resistors need to be placed within 1 inch of the TAP connector.
NOTE:
13.2.4
Miscellaneous Checklist for 370-Pin Socket Processors

BCLK
Connect to clock generator. / 2233 series resistor (though OEM needs to simulate based on driver characteristics). To reduce pin-to-pin skew, tie host clock outputs together at the clock driver then route to the GMCH and processor. Case 1 (66/100/133 MHz support): 1 k pull-up resistor to 3.3V. Connect to Intel CK-815 SEL0 input. Connect to GMCH LMD29 pin via 10 k series resistor. Case 2 (100/133 MHz support): 1 k pull-up resistor to 3.3V. Connect to PWRGOOD logic such that a logic Low on BSEL0 negates PWRGOOD.
BSEL0
BSEL1
1 k pull-up resistor to 3.3V. Connect to Intel CK-815 REF pin via 10 k series resistor. Connect to GMCH LMD13 pin via 10 k series resistor.
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Recommendations
CLKREF
Connect to divider on VCC2.5 or VCC3.3 to create 1.25V reference with a 4.7 F decoupling capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VTT as source voltage for this reference! Tie to ground. Leave as No Connect or connect to PWRGOOD logic to gate system from powering on if no processor is present. If used, 1 k to 10 k pull-up resistor to VCCCMOS. 1 k pull-up resistor to VTT. See Section 10.5. 150 pull-up resistor to VCCCMOS/Connect to ICH. Low-pass filter on VCCCORE provided on motherboard. Typically a 4.7 H inductor in series with VCCCORE is connected to PLL1, and then through a series 33 F capacitor to PLL2. 56 1% pull-down resistor to ground. 110 1% pull-down resistor to ground. Connect to ICH. No Connect if not used. Otherwise, connect to thermal sensor using vendor guidelines. No connect for Intel Pentium III processors Connect to a 1.0V voltage divider derived from VCCCMOS. See Section 4.2.7. 16 ea. (minimum) 4.7 F in 1206 package all placed within the PGA370 socket cavity. 8 ea. (minimum) 1 F in 0612 package placed in the PGA370 socket cavity.
CPUPRES#
DYN_OE PICCLK PICD[1:0] PLL1, PLL2
RTTCTRL5 (S35) SLEWCTRL (E27) STPCLK# (AG35) THERMDN, THERMDP VCC2.5 GTL_REF/VCMOS_REF (AK22) VCCCORE
VID[25mV, 3:0]
Connect to on-board VR or VRM. 25mV should connect to VID25mV. For on-board VR, 10 k pull-up resistor to power solution-compatible voltage is required (usually pulled up to input voltage of the VR). Some of these solutions have internal pull-ups. Optional override (jumpers, ASIC, etc.) could be used. May also connect to system monitoring device. Pull-up to VTT through 1 k resistor and connect to VTTPWRGD circuitry. See Section 4.2.6. Connect to VREF voltage divider made up of 75 and 150 1% resistors connected to VTT. Processor VREF must be able to be separate from chipset VREF. Decoupling Guidelines: 4 ea. (minimum) 0.1 F in 0603 package placed within 500 mils of VREF pins
VTTPWRGD VREF [6:0]
VTT
Connect AH20, AK16, AL13, AL21, AN11, AN15, G35, G37, AD36, AB36, X34, AA33, AA35, AN21, E23, S33, S37, U35, and U37 to VRM 8.5-compliant regulator. Provide high- and low-frequency decoupling. Decoupling Guidelines: 20 ea (minimum) 0.1 F in 0603 package placed as near the VTT processor pins as possible. 4 ea (minimum) 0.47 F in 0612 package
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Checklist Items
Recommendations
NO CONNECTS
The following pins must be left as no-connects: A29, A31, A33, AC37, AJ3, AK24, AK30, AL1, AL11, AM2, AN13, AN23, B36, C29, C31, C33, C35, E21, E29, E31, E35, E37, F10, G33, L33, N33, N35, Q33, Q35, Q37, R2, V4, W35, X2, Y1, Z36. 14 pull-up resistor to VTT.
NCHCTRL (N37)
13.3
13.3.1
GMCH Checklist
AGP Interface 1X Mode Checklist
RBF#, WBF#, PIPE#, GREQ#, GGNT#, GPAR, GFRAME#, GIRDY#, GTRDY#, GSTOP#, GDEVSEL#, GPERR#, GSERR# , ADSTB0, ADSTB1, SBSTB ADSTB0#, ADSTB1#, SBSTB# PME# TYPEDET# PIRQ#A, PIRQ#B
Pull-up to VDDQ through 8.2 k
Pull-down to ground through 8.2 k Connect to PCI connector 0 device Ah. / Connect to PCI connector 1 device Bh. / Connect to Intel 82559 LAN (if implemented). Connect to AGP voltage regulator circuitry / AGP reference circuitry. Pull-up to 5 V through 2.7 k. / Follow ref. schematics (other device connections).
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13.3.2
Designs That Do Not Use the AGP Port

Any external graphics implementation not using the AGP port should terminate the GMCH AGP control and strobe signals in the following way:
Table 34. Recommendations For Unused AGP Port

Signal Pull-up / Pull-Down
FRAME# TRDY# IRDY# DEVSEL# STOP# SERR# PERR# RBF# WBF# INTA# INTB# PIPE# REQ# GNT# GPAR AD_STB[1:0] SB_STB AD_STB[1:0]# SB_STB# ST[2:0]
Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-up to +VDDQ Pull-down to Ground using a 100 k resistor Pull-up to +VDDQ Pull-up to +VDDQ Pull-down to Ground Pull-down to Ground Pull-up to +VDDQ
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13.3.3
System Memory Interface Checklist

SM_CSA#[0:3, SM_CSB#[3:0, SMAA[11:8,3:0], SM_MD[0:63], SM_CKE[0:3], S_DQM[0:7] SM_MAA[7:4], SM_MAB[7:4]# SMAA[12] SM_CAS# SM_RAS# SM_WE# CKE[5..0] (For 3 DIMM implementation) REGE WP(Pin 81 on the DIMMS) SRCOMP
Connect from GMCH to DIMM0, DIMM1
Connect from GMCH to DIMM0, DIMM1 through 10 ohm resistors Connect GMCH through 10 k resistor to transistor junction as per Chapter 4 for systems supporting the universal PGA370 design. Connected to R_REFCLK through 10 k resistor. Jumpered to GND through 10 k resistor Connected to R_BSEL0# through 10 k resistor. When implementing a 3 DIMM configuration, all six CKE signals on the GMCH are used. (0,1 for DIMM0; 2, 3 for DIMM1; 4,5 for DIMM2) Connect to GND (since the Intel 815 chipset platform does not support registered DIMMS). Add a 4.7 k pull-up resistor to 3.3V. This recommendation write-protects the DIMMs EEPROM. Needs a 40 resistor pulled up to 3.3V standby.
13.3.4
Hub Interface Checklist

HUBREF HL_COMP
Connect to HUBREF generation circuitry. Pull-up to VCC1.85 through 40 (both GMCH and ICH side).
13.3.5
Digital Video Output Port Checklist

DVI Input Reference Circuit
See reference schematics in the documentation of the third party vendor of the device of choice in your design. The Third-Party Vendor information is a part of this Design Guide and its associated Design Guide Updates.
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13.4
13.4.1
ICH Checklist
PCI Checklist
AD[31:0] ACK 64# REQ 64#
AD16,17 pass through 100 resistor. (5V PCI environment) 2.7 k (approximate) pull-up resistors to VCC5. (3V PCI environment) 8.2 k (approximate) pull-up resistors to VCC3_3. Each REQ 64# and ACK 64# requires its own pull-up.
PTCK
Pull-down through 5.6 k to GND Connect to PCI Connectors only.
PTDI, PTRST#, PTMS
Pull-up through 5.6 k resistor to VCC5 Connect to PCI Connectors only.
PRSNT#21, PRSNT#22, PRSNT#31, PRSNT#32 PIRQ#C, PIRQ#D, U2_ACK64#, U2_REQ64#, U3_ACK64#, U3_REQ64#, PREQ#1, PLOCK#1, STOP#, TRDY#, SERR#, PREQ#3, PIRQ#A, PERR#, PREQ#0, PREQ#2 DEVSEL#, FRAME#, IRDY# PCIRST# PCPCI_REQ#A, REQ#B/GPIO1, GNT#B/GPIO17, PGNT#0, PGNT#1, PGNT#2, PGNT#3 PCLK_3 PCIRST_BUF#
Decoupled with 0.1 F capacitor to GND Pull-up through 2.7 k resistor to VCC5
Pull signal down through 0.1 F capacitor when input for USB. Input to buffer for PCIRST_BUF#. Pull-up through 8.2 k resistor to VCC3_3
Signal coming from Intel CK-815 device pass through a 33 resistor to PCI connector. Signal comes from buffered PCIRST# Pull-up through 8.2 k resistor to VCC3_3 Passes through 33 resistor
SDONEP2, SDONEP3, SBOP2, SBOP3 R_RSTP#, R_RSTS# IDSEL lines to PCI connectors 3V_AUX
Pull-up through 5.6 k resistor to VCC5 Signal is from PCIRST_BUF# and passes through a 33 resistor 100 series resistor. Optional to 3VSB, but required if PCI devices supporting wake up events.
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13.4.2
USB Checklist
USBP0P, USBP0N, USB_D1_N, USB_D1_P
Decouple through a 47 pF capacitor to GND Signal goes through 15 resistor Pull-down through a 15 k resistor to GND
OC#0 USB_D2_N, USB_D2_P, USB_D3_N, USB_D3_P, USB_D4_N, USB_D4_P, USBP1P, USBP1N, USBP0P, USBP0N D-/D+ data lines VCC USB
Connected to AGP/AC97 Circuitry (See Intel CRB Schematic pg. 20) Pull-down through a 15 k resistor to GND
Use 15 series resistors. Power off 5V standby if wake on USB is to be implemented IF there is adequate standby power. It should be powered off of 5 V core instead of 5 V standby if adequate standby power is not available. The resistive component of the fuses, ferrite beads and traces must be considered when choosing components and Power/GND trace width. This must be done such that the resistance between the VCC5 power supply and the host USB port is minimized. Minimizing this resistance will minimize voltage drop seen along that path during operating conditions. A minimum of 1A fuse should be used. A larger fuse may be necessary to minimize the voltage drop. Sufficient bypass capacitance should be located near the host USB receptacles to minimize the voltage droop that occurs on the hot attach of new device. See most recent version of the USB specification for more information.
Voltage Drop Considerations
Fuse Voltage Droop Considerations
13.4.3
AC 97 Checklist
AC_SDOUT AC_SDIN0 AC_SDIN1
Pulled up to VCC3_3 through a 10 K resistor and a jumper to AC97 Connector and AC97 codec from ICH. Pull-down through a 10 k resistor to GND. The SDATAIN[0:1] pins should not be left in a floating state if the pins are not connected and the AC-link is active they should be pulled to ground through a weak (approximately 10 k) pull-down resistor (see Section 5.9.3 for more information). Connects to OC# circuitry. (see CRB schematics page 20). Signal comes from Oscillator Y4 Decouple through a 22 pF capacitor to GND Connected through jumper to PRI_DWN_U or GND. (see CRB schematic page 27) If the motherboard implements an active primary codec on the motherboard and provides and AMR connector, it must tie PRI_DN# to GND. Pull-up through a 4.7 k resistor to VCC3SBY From FB9 decouple through a 100 pF NPO capacitor to AGND. Run signal through 1 F TANT capacitor
AC97_OC# AC_XTAL_OUT, AC_XTAL_IN PRI_DWN#
PRI_DWN_U LINE_IN_R
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13.4.4
IDE Checklist
PDCS3#, SDCS3#, PDA[2:0], SDA[2:0], PDD[15:0], SDD[15:0], PDDACK#, SDDACK#, PRIOR#, SDIOR#, PDIOW#, SDIOW# PDD7, SDD7 PDREQ, SDREQ PIORDY, SIORDY PDCS1#, SDCS1# PRI_PD1, PRI_SD1 IDE_ACTIVE CBLID#/PDIAG#
Connect from ICH to IDE Connectors. No external series termination resistors required on those signals with integrated series resistors.
Pull-down through a 10 k resistor to GND. Pull-down through a 5.6 k resistor to GND. Pull-up through a 1 k resistor to VCC5 Connect from ICH to IDE Connectors Pull-down through a 470 resistor to GND. From IDEACTP# and IDEACTS# connect to HD LED circuitry (see CRB Schematic page 35) Refer to Section 10.2 for the correct circuit. NOTE: All ATA66 drives will have the capability to detect cables.
IDE Reset IRQ14, IRQ15 CSEL IDEACTP#, IDEACTS#
This signal requires a 22 47 series termination resistor and should be connected to buffered PCIRST#. Need 8.2 k resistor to 10 k pull-up resistor to 5V. Pull-down to GND through 4.7 k resistor (approximate). For HD LED implementation use a 10 k (approximate) pull-up resistor to 5V.
13.4.5
Miscellaneous ICH Checklist

RTC circuitry PME#, PWRBTN#, LAD[3..0]#/FWH[3..0]# SPKR
Refer to Section 10.9 for exact circuitry. No external pull-up resistor on those signals with integrated pull-ups. Optional strapping: Internal pull-up resistor is enabled at reset for strapping after - reset the internal pull-up resistor is disabled. Otherwise connect to motherboard speaker logic. (When strapped, use strong pullup, e.g., 2 k) Optional strapping: Internal pull-up resistor is enabled at reset for strapping after - reset the internal pull-up resistor is disabled. Otherwise connect to AC97 logic. Internal pull-down resistor is enabled only when the AC link hut-off bit in the ICH is set. Use 10 k (approximate) pull-down resistors on both signals if using AMR. For onboard AC97 devices, use a 10 k (approximate) pull-down resistor on the signal that is not used. Otherwise, connect to AC97 logic.
AC_SDOUT, AC_BITCLK
AC_SDIN[1:0]
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Checklist Items
Recommendations
PDD[15:0], PDIOW#, PDIOR#, PDREQ, PDDACK#, PIORDY, PDA[2:0], PDCS1#, PDCS3#, SDD[15:0], SDIOW#, SDIOR#, SDREQ, SDDACK#, SIORDY, SDA[2:0], SDCS1#, SDCS3#, IRQ14, IRQ15 PCIRST# No floating inputs (including bi-directional signals):
No external series termination resistors on those signals with integrated series resistors.
The PCIRST# signal should be buffered to the IDE connectors. Unused core well inputs should be tied to a valid logic level (either pulled up to 3.3V or pulled down to ground). Unused resume well inputs must be either pulled up to 3.3VSB or pulled down to ground. Ensure all unconnected signals are OUTPUTS ONLY! PDD7 and SDD7 need a 10 k (approximate) pull-down resistor. No other pull-ups/pull-downs are required. Refer to ATA ATAPI-4 specification. Use approximately 1 k pull-up resistor to 5V. Use approximately 5.6 k pull-down resistor to ground. Need 8.2 k (approximate) pull-up resistor to 5V. No pull-up resistor required. A test point or no stuff resistor is needed to be able to drive the ICH into a NAND tree mode for testing purposes. No clear CMOS jumper on VCCRTC. Use a jumper on RTCRST# or a GPI, or use a safe-mode strapping for clear CMOS. The value of the SMBus pull-ups should reflect the number of loads on the bus. For most implementations with 45 loads, 4.7 k resistors are recommended. OEMs should conduct simulation to determine exact resistor value. If the APIC is used: 150 (approximate) pull-ups on APICD[0:1] and connect APICCLK to the clock generator. If the APIC is not used: The APICCLK can either be tied to GND or connected to the clock generator, but not left floating.
PDD[15:0], SDD[15:0]
PIORDY, SDIORDY PDDREQ, SDDREQ IRQ14, IRQ15 HL11 VCCRTC SMBus: SMBCLK SMBDATA APICD[0:1], APICCLK
GPI[8:13]
Ensure all wake events are routed through these inputs. These are the only GPIs that can be used as ACPI-compliant wake events because they are the only GPI signals in the resume well that have associated status bits in the GPE1_STS register. RCOMP Method: Tie the COMP pin to a 40 1% or 2% (or 39 1%) pull-up resistor to 1.85V via a 10-mil wide, very short(-0.5 inch) trace (targeted for a nominal trace impedance of 40 ) Refer to Section 12.4.3 for implementation of the voltage sequencing circuit. Pull-up through 8.2 k resistor (approximate) to 3.3V No pull-ups required. These signals are always driven by the ICH. Use 18 pF tuning capacitor as close as possible to ICH. Add a 10 k pull-up resistor to 3VSB (3 V standby) on both of these signals. No external pull-ups are required on PCI_GNT# signals. However, if external pull-ups are implemented, they must be pulled up to 3.3V.
HL_COMP
5V_REF SERIRQ SLP_S3#, SLP_S5# CLK66 GPIO27/ALERTCLK GPIO28/ALERTDATA PCI_GNT#
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13.5
LPC Checklist
RCIN# LPC_PME#
Pull-up through 8.2 k resistor to VCC3_3 Pull-up through 8.2 k resistor to VCC3_3. Do not connect LPC PME# to PCI PME#. If the design requires the Super I/O to support wake from any suspend state, connect Super I/O LPC_PME# to a resume well GPI on the ICH. Pull-up through 8.2 k resistor to VCC3_3. This signal can be connected to any ICH GPI. The GPI_ROUTE register provides the ability to generate an SMI# from a GPI assertion. Pull-up through 4.7 k resistor to VCC3_3 Jumper for decoupling option (decouple with 0.1 F capacitor).
LPC_SMI#
TACH1, TACH2
J1BUTTON1, JPBUTTON2, J2BUTTON1, J2BUTTON2 LDRQ#1 A20GATE MCLK, MDAT L_MCLK, L_MDAT RI#1_C, CTS0_C, RXD#1_C, RXD0_C, RI0_C, DCD#1_C, DSR#1_C, DSR0_C, DTR#1_C, DTR0_C, DCD0_C, RTS#1_C, RTS0_C, CTS#1_C, TXD#1_C, TXD0_C L_SMBD SERIRQ SLCT#, PE, BUSY, ACK#, ERROR# LDRQ#0 STROBE#, ALF#, SLCTIN#, PAR_INIT# PWM1, PWM2 INDEX#, TRK#0, RDATA#, DSKCHG#, WRTPRT# PDR0, PDR1, PDR2, PDR3, PDR4, PDR5, PDR6, PDR7 SYSOPT
Pull-up through 1 k resistor to VCC5. Decouple through 47 pF capacitor to GND
Pull-up through 4.7 k resistor to VCC3SBY Pull-up through 8.2 k resistor to VCC3_3 Pull-up through 4.7 k resistor to PS2V5. Decoupled using 470 pF to ground Decoupled using 100 pF to GND
Pass through 150 resistor to Intel 82559 Pull-up through 8.2 k to VCC3_3 Pull-up through 2.2 k resistor to VCC5_DB25_DR Decouple through 180 pF to GND Connect to ICH from SIO. This signal is actively driven by the Super I/O and does not require a pull-up resistor. Signal passes through a 33 resistor and is pulled up through 2.2 k resistor to VCC5_DB25_CR. Decoupled using a180 pF capacitor to GND. Pull-up to 4.7 k to VCC3_3 and connected to jumper for decouple with 0.1 F capacitor to GND. Pull-up through 1 k resistor to VCC5
Passes through 33 resistor Pull-up through 2.2 k to VCC5_DB5_CRDecouple through 180 pF capacitor to GND Pull-down with 4.7 k resistor to GND or IO address of 02Eh
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13.6
System Checklist
KEYLOCK# PBTN_IN PWRLED R_IRTX IRRX
Pull-up through 10 k resistor to VCC3_3 Connects to PBSwitch and PBin. Pull-up through a 220 resistor to VCC5 Signal IRTX after it is pulled down through4.7 k resistor to GND and passes through 82 resistor Pull-up to 100 k resistor to VCC3_3 When signal is input for SI/O Decouple through 470 pF capacitor to GND
IRTX
Pull-down through 4.7 k to GND Signal passes through 82 resistor When signal is input to SI/O Decouple through 470 pF capacitor to GND
FP_PD
Decouple through a 470 pF capacitor to GND Pull-up 470 to VCC5
PWM1, PWM2 INTRUDER#
Pull-up through a 4.7 k resistor to VCC3_3 Pull signal to VCCRTC (VBAT), if not needed.
13.7
FWH Checklist
No floating inputs WPROT, TBLK_LCK R_VPP FGPI0_PD, FGPI1_PD, FGPI2_PD, FPGI3_PD, FPGI4_PD, IC_PD FWH_ID1, FWH_ID2, FWH_ID3 INIT# RST# ID[3:0]
Unused FGPI pins need to be tied to a valid logic level. Pull-up through a 4.7 k to VCC3_3 Pulled up to VCC3_3, decoupled with two 0.1 F capacitors to GND. Pull-down through a 8.2 k resistor to GND
Pull-down to GND FWH INIT# must be connected to processor INIT#. FWH RST# must be connected to PCIRST#. For a system with only one FWH device, tie ID[3:0] to ground.
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13.8
Clock Synthesizer Checklist

REFCLK GMCH_3V66/3V66_1 ICH_3V66/3V66_0, DOTCLK
Connects to R-RefCLK, USB_CLK, SIO_CLK14, and ICHCLK14. Passes through 33 resistor Passes through 33 resistor When signal is input for ICH it is pulled down through a 18 pF capacitor to GND Passes through 33 resistor When signal is input for GMCH it is pulled down through a 22 pF capacitor to GND
DCLK/DCLK_WR
CPUHCLK/CPU_0_1
Passes through 33 resistor When signal is input for 370PGA, Decouple through a 18 pF capacitor to GND
R_REFCLK
REFCLK passed through 10 k resistor When signal is input for 370PGA, pull-up through 1 k resistor to VCC3_3 and pass through 10 k resistor
USB_CLK, ICH_CLK14 XTAL_IN, XTAL_OUT
REFCLK passed through 10 resistor Passes through 14.318 MHz Osc Pulled down through 18 pF capacitor to GND Pulled up via MEMV3 circuitry through 8.2 k resistor. Connected to clock frequency selection circuitry through 10 k resistor. (see CRB schematic, page 4) Connects to VDD2_5[0..1] through ferrite bead to VCC2_5. Passes through 33 resistor
SEL1_PU FREQSEL L_VCC2_5 GMCHHCLK/CPU_1, ITPCLK/CPU_2, PCI_0/PCLK_OICH, PCI_1/PCLK_1, PCI_2/PCLK_2, PCI_3/PCLK_3, PCI_4/PCLK_4, PCI_5/PCLK_5, PCI_6/PCLK_6, APICCLK_CPU/APIC_0, APICCLK)ICH/APIC_1, USBCLK/USB_0, GMCH_3V66/3V66_1, AGPCLK_CONN MEMCLK0/DRAM_0, MEMCLK1/DRAM_1, MEMCLK2/DRAM_2, MEMCLK3/DRAM_3, MEMCLK4/DRAM_4, MEMCLK5/DRAM_5, MEMCLK6/DRAM_6, MEMCLK7/DRAM_7, SCLK VCC3.3
Pass through 10 resistor
Pass through 22 resistor. Connected to VTTPWRGD gating circuit as per Section 4.3.1 for systems supporting the universal PGA370 design.
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13.9
LAN Checklist
TDP, TDN, RDP, RDN LANAPWR LANCLKRUN LAN_ISOLATE# LAN_TEST LAN_XTAL1, LAN_XTAL2
Pull-down through 50 resistor to GND Passes through 3 k resistor Pull-down through 62 k resistor Connect to SUS_STAT# and PWROK Pull-down through a 4.7 k resistor to GND Signal from 25 MHz oscillator Decouple through a 22 pF capacitor to GND Pull-down through a 619 resistor to GND Passes through 330 resistor Connect to jumper, pull-up through 330 resistor to VCC3SBY Pull-up through 330 resistor to VCC3SBY Pull-down RDP through 50 resistor and to RDN through 50 resistor to GND Pull-down TDP through 50 resistor and to TDN through 50 resistor to GND Connect LED anode to VCC3SBY through 330 resistor and cathode to Intel 82559. Jumper to VCC3SBY through 330 resistor Use plane for this signal. Pull-up through 330 resistor to VCC3SBY Pass through 100 resistor to AD20 from Intel 82559 pin IDSEL.
FLD5_PD, FLD6_PD, RBIAS10, RBIAS100 ACTLED/LI_CR LILED ACT_CR RD_PD TD_PD SPEEDLED CHASSIS_GND JP7_PU, JP18_PU, JP23_PU R_LANIDS
13.10
Power Delivery Checklist

All voltage regulator components meet maximum current requirements All regulator components meet thermal requirements VCC1_8 If devices are powered directly from a dual rail (i.e., not behind a power regulator), then the RDSon of the FETs used to create the dual rail must be analyzed to ensure there is not too much voltage drop across the FET. Dropout Voltage
Consider all loads on a regulator, including other regulators. Ensure the voltage regulator components and dissipate the required amount of heat. VCC1_8 power sources must supply 1.85V Dual voltage rails may not be at the expected voltage.
The minimum dropout for all voltage regulators must be considered. Take into account that the voltage on a dual rail may not be the expected voltage. See individual component specifications for each voltage tolerance.
Voltage tolerance requirements are met
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13.10.1
Power
V_CPU_IO[1:0] VCCRTC VCC3.3 VCCSus3.3 VCC1.85 VCCSus1.85 5V_REF SUS
The power pins should be connected to the proper power plane for the processor s CMOS compatibility signals. Use one 0.1 F decoupling capacitor. No clear CMOS jumper on VCCRTC. Use a jumper on RTCRST# or a GPI, or use a safemode strapping for Clear CMOS Requires six 0.1 F decoupling capacitors Requires one 0.1 F decoupling capacitor. Requires two 0.1 F decoupling capacitors. Requires one 0.1 F decoupling capacitor. Requires one 0.1 F decoupling capacitor. V5REF_SUS only affects 5V-tolerance for USB OC[3:0] ins and can be connected to VCCSUS3_3 if 5V tolerance on these signal is not required.
5V_REF
5VREF is the reference voltage for 5V tolerant inputs in the ICH. Tie to pins VREF[2:1]. 5VREF must power up before or simultaneous to VCC3_3. It must power down after or simultaneous to VCC3_3. Refer to the figure below for an example circuit schematic that may be used to ensure the proper 5VREF sequencing. VCMOS power source must supply 1.5V and be generated by circuitry on the motherboard. See Appendix A: Customer Reference Board (CRB).
VCMOS
Figure 79. V5REF Circuitry Vcc Supply (3.3V) 1 K 1.0 uF 5V Supply
To System
VREF
To System
vref_circuit
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Third-Party Vendor Information

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14

This design guide has been compiled to give an overview of important design considerations while providing sources for additional information. This chapter includes information regarding various third-party vendors who provide products to support the Intel 815 chipset platform for use with the universal socket 370. The list of vendors can be used as a starting point for the designer. Intel does not endorse any one vendor, nor guarantee the availability or functionality of outside components. Contact the manufacturer for specific information regarding performance, availability, pricing and compatibility.
Super I/O (Vendors Contact Phone)

SMSC National Semiconductor ITE Winbond Dave Jenoff (909) 244-4937 Robert Reneau (408) 721-2981 Don Gardenhire (512)388-7880 James Chen (02) 27190505 - Taipei office
Clock Generation (Vendors Contact Phone)

Cypress Semiconductor ICS IMI PERICOM John Wunner 206-821-9202 x325 Raju Shah 408-925-9493 Elie Ayache 408-263-6300, x235 Ken Buntaran 408-435-1000
Memory Vendors
http://developer.intel.com/design/motherbd/se/se_mem.htm
Voltage Regulator Vendors (Vendors Contact Phone)

TBD
GPA (a.k.a. AIMM) Card (Vendors Contact Phone)

Kingston Smart Modular Micron Semiconductor JK_TSAI@kingston.com Richard_Kanadjian@kingston.com James.Lee@smartm.com Arthur.SAINIO@smartm.com TBD
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TMDS Transmitters
Silicon Images Texas Instrument Chrontel John Nelson (408) 873-3111 Greg Davis [gdavis@ti.com] (214) 480-3662 Chi Tai Hong [cthong@chrontel.com] (408) 544-2150
TV Encoders
Chrontel Conexant Focus Philips Texas Instrument Chi Tai Hong [cthong@chrontel.com] (408)544-2150 Eileen Carlson [eileen.carlson@conexant.com] (858) 713-3203 Bill Schillhammer [billhammer@focusinfo.com] (978) 661-0146 Marcus Rosin [marcus.rosin@philips.com] Greg Davis[gdavis@ti.com] (214) 480-3662
Combo TMDS Transmitters/TV Encoders

Chrontel Texas Instrument Chi Tai Hong [cthong@chrontel.com] (408) 544-2150 Creg Davis[gdavis@ti.com] (214) 480-3662
LVDS Transmitter
National Semiconductor 387R Jason Lu [Jason.Lu@nsc.com] (408) 721-7540
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Appendix A: Customer Reference Board (CRB)

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Appendix A: Customer Reference Board (CRB)

This section provides a set of Customer Reference Board (CRB) schematics for the Intel 815 chipset platform for use with the universal socket 370.
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Intel(R) Pentium(R) III Processor (CPUID = 068xh), Intel(R) Celeron(TM) Processor (CPUID = 068xh), and Future 0.13 Micron Socket 370 Processors With Intel(R) 815 Chipset For Use With Universal Socket 370
D
UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS REVISION 1.0

** PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE
Title
Cover Sheet Block Diagram 370-pin Socket Clock Synthesizer GMCH AGP Socket DIMM Sockets
C
Page
1 2 3, 4 5 6, 7, 8 9 10, 11 12, 13 14 15 16, 17 18 19 20 21 22 23 24 25 26 27 28 29 30, 31 32 33 34 35, 36 37, 38 39 40
A
ICH FWH Super I/O PCI Connectors IDE Connectors USB Hub Parallel Port Serial Ports Kybrd/Mse/F. Disk Connectors Game Port Digital Video Out Video Connectors
THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLES Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilites arising from future changes to them. The Intel 815 B-step universal platform may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses frrom various entities, including Philips electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel(R), Pentium(R), Pentium(R) III, Celeron(TM), are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (C) 2001, Intel Corporation.
AC'97 Riser Connector AC'97 Audio Codec AC'97 Audio Connections LAN System Voltage Regulators AGP, VCMOS Voltage Regulators Processor Voltage Regulators System Pullup Resistors and Unused Gates Decoupling Hub Interface Connector
A
Thermtrip
Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD
REV.
COVER SHEET
1.0
3-26-01
intel
5 4 3 2
Platform Apps Engineering

R
Last Revision Date: Sheet:

1
1900 Prairie City Road Folsom, CA 95630
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40
BLOCK DIAGRAM
VRM
D
370-PIN SOCKET PROCESSOR

ADDR ADDR CTRL CTRL DATA
CLOCK
D
AGTL BUS
DATA
AGP Connector
GMCH
Digital Video Out Device
C
2 DIMM Modules
PCI CONN 1
PCI CONN 2
IDE Primary
UDMA/66
PCI CNTRL
IDE Secondary
ICH
USB PORTS
USB
PCI ADDR/DATA
LPC BUS
AMR Connector
AC'97 LINK
SIO Audio Codec FirmWare Hub

Keyboard Mouse
A A
Floppy
Game Port
Serial 1
Serial 2
Parallel
REV.
BLOCK DIAGRAM
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
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370PGA SOCKET, PART 1

B26 C3 AK2 AF2 AB2 T2 P2 K2 F4 E5 AM4 AE5 AA5 W5 S5 N5 J5 F2 D6 B6 AM8 AJ9 E9 B10 AM12 AJ13 E13 B14 AM16 AJ5 AJ17 E17 B18 AM20 AJ21 D20 F22 AM24 AJ25 D24 F26 AM28 AJ29 D28 AK34 F30 B30 AM32 AH32 Z32 V32 R32 M32 H32 AF34 AB34 6 HD#[63:0] HD#[63:0] HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 6 RS#[2:0] RS#[2:0] W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9 A9 D8 D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16 X1-1 VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 RS#2 RS#1 RS#0
VCCVID
T34 P34 K34 F34 B34 AH36 B22 V36 R36 H36 D36 D32 AD32 AH24 F14 K32 AA37 Y35
HA#[31:3] HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 X6 AC1 W3 AF4 AL35 AM36 AL37 AJ37 AK36 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
HA#[31:3]
VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID VCCVID
370-Pin Socket Part 1
VID[4:0] VID0 VID1 VID2 VID3 VID4
VID[4:0]
33
VID0 VID1 VID2 VID3 GND/VID4 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 DEP#0 DEP#1 DEP#2 DEP#3 DEP#4 DEP#5 DEP#6 DEP#7 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 VTT1_5 GND NC
AK18 HREQ#0 AH16HREQ#1 AH18HREQ#2 AL19 HREQ#3 AL17 HREQ#4 C33 C31 A33 A31 E31 C29 E29 A29 AH20 AK16 AL21 AN11 AN15 G35 AL13 U37 U35 S37 S33 E23 AN21 AA35 AA33 X34 AL1
HREQ#[4:0]
VTT
RS#2 AK28 RS#1 AH22 RS#0 AH26
370 PIN SOCKET

A
AM34 GND AH2 GND AD2 GND Z2 GND V2 GND M2 GND D18 GND H2 GND D2 GND AL3 GND AG5 GND AC5 GND Y5 GND U5 GND Q5 GND L5 GND G5 GND D4 GND B4 GND AM6 GND AJ7 GND E7 GND B8 GND AM10 GND AJ11 GND E11 GND B12 GND AM14 GND AJ15 GND E15 GND B16 GND AM18 GND AJ19 GND E19 GND F20 GND B20 GND AM22 GND AJ23 GND D22 GND F24 GND B24 GND AM26 GND AJ27 GND D26 GND F28 GND B28 GND AM30 GND D30 GND AF32 GND AB32 GND X32 GND T32 GND P32 GND F32 GND B32 GND AH34 GND AD34 GND Z34 GND V34 GND R34 GND M34 GND H34 GND D34 GND X36 GND T36 GND P36 GND K36 GND F36 GND A37 GND AC33 GND
Y37
REV.
370-PIN SOCKET, PART 1
1.0
3-26-01
intel
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370PGA SOCKET, PART 2

VCMOS VTT
D
VCMOS 1
VCMOS 21 VCC3SBY VCC3SBY
R303 75 1% CMOSREF 1
D
R7 8 7 6 2 1 1 1K 1 6 35 CPURST# DBRESET# 1 R1 243 2 1 R2 0 R_TCK R_TMS R1_J3A 1 5 J3A 2 4 1 2 2 1 6 8 10 12 14 16 18 20 22 24 26 1 28 30 ITP30RA R16 150 1% 2 C12 4.7uF 2 C13 0.1uF 2 CLKREF 1 R306 1k 1 R15 150 1% R_ITPRDY# 2 R4 243 1 ITPRDY# R_TMS R_TMS ITPREQ# ITPRDY# 1 VCC2_5 2 R3 680 VTT 1 VTT 1 TDI TDO TRST# R_TCK RP2A R10 150 330
VTT GTLREF0 CMOSREF AB36 AD36 2
R8 39
R9 39
E33 F18 K4 R6 V6 AD6 AK12 AK22
2 R_DBRST#3 5 7
R_TCK R_TMS
X4-2 AN35 AN37 AN33 AL33 AK32 J37 A35 G33 E37 C35 E35 TDI TDO TRST# TCK TMS PREQ# PRDY# BP2# BP3# BPM0# BPM1# RSRVD6 RSRVD7 RSRVD8 RSRVD9 RSRVD10 RSRVD11
Z36
VCMOS AH14 AN17 AN25 AN19 AK20 AN27 AL23 AL25 AL27 AN31 AE37 AJ33 AJ31 AK30 AN29 AL31 AL29 AH28 AE33 AG35 AH30 AJ35 M36 L37 AG33 AC35 AG37 AE35 W33 U33 AC37 AL11 AN13 AN23 B36 AK24 V4 AF36 E27 S35 E21 PLL1 PLL2 2 1 BNR# 6 BPRI# 6 HTRDY# 6 DEFER# 6 HLOCK# 6 DRDY# 6 HITM# 6 HIT# 6 DBSY# 6 HADS# 6 FLUSH# R_BSEL0# 7 R_REFCLK 5,7 BR0# THERMDP 12 THERMDN 12 THERMTRIP# 40 A20M# 12,36 STPCLK# 12,36 CPUSLP# 12,36 SMI# 12,36 INTR 12,36 NMI 12,36 INIT# 12,14,36 FERR# 12,36 IGNNE# 12,36
V_CMOS V1_5
VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7
RSVD
ITP_PON 9 11 13 15 17
C
R_TCK 2 R5 0 2 R6 0
1 TCK 1 TMS
19 21 23 25 27 5 ITPCLK 29
R56 90.9
R305 14 N33 N35 N37 Q33 Q35 Q37 AM2 F10 W35 Y1 R2 G37 L33 X2 AN3 AK4 J35 L35 J33 W37 Y33 AK26 AH4 2 X4
370-Pin Socket Part 2
BNR# BPRI# HTRDY# DEFER# LOCK# DRDY# HITM# HIT# DBSY# ADS# FLUSH# BSEL0# BSEL1# RSRVD12/JBSEL1# BR0# THRMDP THRMDN THERMTRIP# A20M# STPCLK# CPUSLP# SMI# LINT0/INTR LINT1/NMI INIT# FERR# IGNNE# IERR# PLL1 PLL2 RSP# AP0# AP1# RP# BINIT# AERR# BERR# TUALDET SLEWCNTR RTTCTRL VCOREDET
R17 150 2
R20 1K
R19 1K
R304 150 1%
C436 0.1uF
ITP Test Port Option

31 1 VTTPWRGD 1 R307 1k
B
RSRVD13 RSRVD15 RSRVD16 RSRVD17 RSRVD18 RSRVD19 RSRVD20 RSRVD21(BR1#) DYN_OE VTTPWRGD PICD0 PICD1 PICCLK BCLK CLKREF PWRGOOD RESET# RESET2# RSVD - NC EDGCTRL/VRSEL CPUPRES#
2 1
VCCVID
VCC5 1
R_VTTPWRGD 12,36 APICD0 12,36 APICD1 5 APICCLK_CPU 5 CPUHCLK 35 PWRGOOD 6 CPURST#
1 L8 4.7uH VTT 1
2 VCC5 1 2
R308 2.2k TUAL5 5,7,31

B
R327 1K 2
VTT Q19 MOSFET N 5,7,31 TUAL5 2 EDGCTRL 1 R58 22 1 C130_R58 2 Do Not Stuff C10 Place within 0.5" of clock pin (W37) 2 SM_BS0 7,10,11 1 1 R309 1k
C8 33uF 20%
Stuff resistor only on non-UMB platforms. VTT
AJ3 AG1 C37
R310 2.2k 2 R311 1k
Q18 MOSFET N
Debug Only R312 0 1 2 2
TUAL5#
Q20 NPN
R313 1k 1
JP1A_R63
R27 1 R21
56 2 33 7 R_BSEL0# BR0# R18 1 1K
Debug sites only. FB12 BEAD VTT 1 2 R346 75,1% C478 0.1uF
GTLREF Generation Circuit

Use 0603 Packages and distribute GTLREF Inputs ( 1 cap for every 2 inputs) within 500 mils of processor
R322 56, %1
ITPRDY#
R63 1
10K
C10 18pF
370 PIN SOCKET_9 R323 110, %1
JP29 JUMPER
Debug Only! Do NOT place jumper before removing 0 ohm resistor
R72 1
10K 2 FREQSEL 5
C130 10pF
GTLREF0
A
JP1A
Clock Frequency Selection
GTLREF0 R347 R348 C479 C480 0.1UF C481 0.1UF C482 0.1UF 150,1% 0.1UF
GTLREF 6 X0 Do not stuff R347 GTLREF0 to CPU. GTLREF to GMCH.
REV.
370-PIN SOCKET, PART 2
1.0
3-26-01
intel
2

R

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Clock Synthesizer
VCC_CLK L14A 1
D
1 VCC3_3 VCC3SBY 1 1
2 2
C155 22uF
USBV3 C154 1 0.1uF
L16A 2
VCC_CLK
D
R293 1K 14 U10D_R293 12 1 R67 R67_U10D 2 11 33 13 U10D_R292 7 1 2 C143 2 U10D 13 ICH_CLK14
C144 22uF
C146 0.1uF
C147
C156 0.1uF
C157
C158
PCIV3 C159 0.001uF 1 MEMV3 L11A 2 VCC_CLK
0.001uF 2 2
0.001uF 2 2
0.1uF 2
XTAL_IN 2
C107
C108 0.1uF
C109
C149
C150
C151
C106 22uF APICCLK_CPU 4
SN74LVC08A 1 18pF 10 2 R292
0.001uF 2 2 Y1A 14.318MHz XTAL
0.001uF 2 2
0.1uF 2
0.001uF 2
0.1uF 2
R44 8.2K 1 2 SEL1_PU U4 XTAL_OUT 3 XTAL_IN XTAL_OUT REF0 3V66_0 3V66_1 PCI_0/ICH PCI_1 PCI_2 PCI_3 PCI_4 PCI_5 PCI_6 AGP USB_0 USB_1 VDD_A VSS_A VSS3_3[0] VSS3_3[1] VSS3_3[2] VSS3_3[3] VSS3_3[4] VSS3_3[5] VSS3_3[6] VSS3_3[7] VDD2_5[0] VDD2_5[1] VSS2_5[1] VSS2_5[0] 2 10 11 21 27 33 38 44 2 VDD3_3[0] VDD3_3[1] VDD3_3[2] VDD3_3[3] VDD3_3[4] VDD3_3[5] VDD3_3[6] VDD3_3[7] R338 APIC_0 APIC_1 CPU_0 CPU_1 CPU_2/ITP SDRAM_0 SDRAM_1 SDRAM_2 SDRAM_3 SDRAM_4 SDRAM_5 SDRAM_6 SDRAM_7 DCLK PWRDWN# SCLK SDATA SEL1 SEL0 55 54 52 50 49 46 45 43 42 40 39 37 36 34 32 31 30 29 28 51 53 56 48 2 APIC_0 APIC_1 1 R38 R41 CPU_2 DRAM_0 DRAM_1 DRAM_2 DRAM_3 DRAM_4 DRAM_5 DRAM_6 DRAM_7 DCLK 1 R42 1 R45 1 R47 1 R49 1 R51 2 33 2 33 2 33 2 22 2 22 2 22 2 22 1 1 R39 CPU_0_1 1 1 R40 1 R43 1 R46 1 R48 1 R50 1 R52 2 33 2 33 2 22 2 22 2 22 2 22 2 22 MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3 MEMCLK4 MEMCLK5 MEMCLK6 MEMCLK7 APICCLK_ICH 12 R339 0 4,7,31 10,11 TUAL5 2 1 130
C
1 4,7 R_REFCLK1 R65 15 SIO_CLK141 R64 2 10K REFCLK 13 8 39 12 15 16 17 29 14 9 19 13 8 ICH_3V66 GMCH_3V66 HUBPRB_3V66 PCLK_0/ICH PCLK_1 PCLK_3 PCLK_4 PCLK_5 PCLK_6 AGPCLK_CONN USB_CLK USBCLK DOTCLK
2 18pf
C145
4 2 10 1 1 1 R74 33 1 R73 1 R75 1 R77 1 2 R70 10 1 R80 1 2 33 2 33 2 33 2 33 1 2 33 L_CKVDDA R79 2 10 1 2 R69 2 22 1 R71 R68 2 22 2 33 3V66_0 3V66_1 PCI_0 PCI_1 PCI_3 PCI_4 PCI_5 PCI_6 AGP USB_0 USB_1 7 8 12 13 15 16 18 19 20 9 25 26 22 1 1 C152 0.1uF 2 2 C153 0.001uF 23
CK-815 2-DIMM
CPUHCLK 4 GMCHHCLK 6 ITPCLK 4 MEMCLK[7:0]
Q27 MOSFET N
1 R76 1 R78
2 33 2 33
DCLK_WR
1 R66 L15A 2
VCC_CLK
B
CK_PWRDN# 35 CK_SMBCLK 25 CK_SMBDATA 25 FREQSEL L_VCC2_5 C100 1 1 1 1 4 L12A 2 C102 C101 0.1uF VCC2_5
B
0.001uF 2
4.7uF 2
Notes:
Place all decoupling caps as close to VCC/GND pins as possible PCI_0/ICH pin must go to ICH. This clock cannot be turned off through SMBus CPU_ITP pin must go to ITP Only CPU_ITP can be turned off through SMBus
VCC3_3
31
VTTPW RGD12
Q28 MOSFET N
5 6 14 17 24 35 41 47 VCC_CLK
A
CK_815_2DIMM
REV.
CLOCK SYNTHESIZER
1.0
3-26-01
intel
5 4 3 2

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82815B GMCH, PART 1, 4, AND 5

HOST INTERFACE, POWER & GND
VTT 1 R135 75 1% 4 GTLREF
D
VDDQ VCC3SBY VCC1_8 VCC1_8A U71-4 AA21 W6 Y9 Y18 AA6 AA8 AA11 AA13 AA15 AA17 AA19 AB16 AB20 AC22 AD19 C25 E24 F23 G22 J7 K6 M6 P6 T6 V7 G26 Y7 E23 AF26 AF25 B2 B5 B8 B11 B14 B19 B22 B25 E2 F10 F14 F17 G6 G8 G19 H2 H5 H7 K20 Y24 L21 M23 U25 N25 R21 U20 U23 W20 AF24 AE25 VCC1_8A VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VCC3SBY VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ GND GND 82815 GMCH GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AB4 E7 AC2 AC5 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC25 AE2 AE4 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 B26 C3 C6 C9 C12 C15 C18 C21 C24 D1 E5 E10 E12 E15 E17 E20 E22 F1 F3 F11 F13 T21 U2 U7 K24 V4 V6 V20 V22 W2 W7 W23 W25 Y4 Y6 Y8 Y10 Y17 Y19 AA2 AA9 AA12 AA14 AA16 P11 P12 P13 P14 P15 P16 R2 R6 R11 R12 R13 R14 R15 R16 R23 R25 T4 T11 T12 T13 T14 T15 T16 L15 L16 L22 M4 M11 M12 M13 M14 M15 M16 U71-5
D
C123 0.1UF
R134 150 1%
C124 0.1UF
VTT 1
HD#[63:0]
VTT
DO NOT STUFF C122 PLACE SITE W/IN 0.5" OF CLOCK BALL (V6) Place near GMCH R345 56 C122 18pF
R55 90.9 U6-1 HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# AA1 AB2 AF2 AD4 AB1 AB3 AA3 AC4 AC1 AF3 AD1 AE3 AD2 AD3 AF1 AA4 AD6 AC3 AE1 AB6 AF4 AE5 AC8 AB5 AF5 AC6 AF6 AD11 AF8 AD8 AD5 AB7 AF7 AD7 AB8 AE7 AE9 AB9 AF9 AD10 AF12 AB11 AB10 AD9 AC10 AF10 AD14 AD12 AB12 AE11 AE15 AF11 AF13 AB14 AF14 AB13 AB15 AE13 AC14 AD13 AD15 AF16 AF15 AC12 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 1 2
U6 AA10 AA7 H3 AA5 L4 M3 G1 N4 M5 J3 J1 K1 L3 K3 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 3 RS#[2:0] RS#0 RS#1 RS#2 K2 L1 H1 R4 P1 T2 R3 N5 P5 R1 U1 P2 T1 T3 P3 T5 R5 V5 Y2 V3 W1 U4 V2 W3 W4 U5 Y5 Y3 U3 Y1 W5 V1 M1 N1 M2 L5 N3
GTLREFA GTLREFB HCLK RESET# CPURST# HLOCK# DEFER# ADS# BNR# BPRI# DBSY# DRDY# HIT# HITM# HTRDY# HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# RS0# RS1# RS2#
4 HADS#
5 GMCHHCLK 9,12,14,15,16,17,18,19,24,29 4 4 4 4 4 4 4 4 4 4 3
PCIRST# CPURST# HLOCK# DEFER# BNR# BPRI# DBSY# DRDY# HIT# HITM# HTRDY# HA#[31:3]
82815 GMCH PART 4: POWER AND GND
82815 GMCH PART 1: HOST INTERFACE
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
82815 GMCH PART 5: GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
L25 N2 N6 N11 N12 N13 N14 N15 N16 N23 AA23 F16 F25 G9 G17 G21 G23 P24 H6 H22 J2 J5 J23 J25 K4 K7 K21 L2 L6 L11 L12 L13 L14 AA25 P4
82815 GMCH
VCC1_8
VCC1_8A
L23 1 22nH 0.3A 2 1 1 C41 33UF 20% 2 C33 0.1UF 2 + 0.01UF 2 1 C40
NOTE: VCC1_8 IS A NOMINAL 1.85V
HREQ#[4:0]
REV.
82815 GMCH: HOST INTERFACE
1.0
3-26-01
82815 GMCH
5 4 3
intel
2

R

1
of
40
82815B GMCH, PART 2

MEMORY INTERFACE
10,11
D
SM_MAA[12:0] SM_MAA0 SM_MAA1 SM_MAA2 SM_MAA3 RP43 SM_MAA4 SM_MAA5 SM_MAA6 SM_MAA7 SM_MAA8 SM_MAA9 SM_MAA10 SM_MAA11 SM_MAA12 11 SM_MAB[7:4]# SM_MAB4 SM_MAB5 SM_MAB6 SM_MAB7 5 6 7 8 RP44 10 4 3 2 1 SMAB4# SMAB5# SMAB6# SMAB7# B15 A15 C14 A14 B10 A10 C10 A9 SM_BS0 SM_BS1 10,11 SM_CSA#[3:0] SM_CSA#0 SM_CSA#1 SM_CSA#2 SM_CSA#3 R166 301 1% 2 10,11 SM_CSB#[3:0] SM_CSB#0 SM_CSB#1 SM_CSB#2 SM_CSB#3 D15 A17 D14 E14 E13 B17 F9 F8 D10 D9 B9 A8 C16 D18 E16 SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 D8 E8 E9 D7 C8 C7 F7 G10 SM_DQM[7:0] SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 SRCOMP 2 D16 F15 A7 A6 A18 C17 B6 A5 G7 B13 D11 5 6 7 8 10 4 3 2 1 SMAA4# SMAA5# SMAA6# SMAA7# U6-2 D13 B16 F12 A16 B12 A12 C11 A11 D12 C13 E11 A13 B7 SMAA0 SMAA1 SMAA2 SMAA3 SMAA4 SMAA5 SMAA6 SMAA7 SMAA8 SMAA9 SMAA10 SMAA11 SMAA12 SMAB4# SMAB5# SMAB6# SMAB7# SMAC4# SMAC5# SMAC6# SMAC7# SBS0 SBS1 SCSA0# SCSA1# SCSA2# SCSA3# SCSA4# SCSA5# SCSB0# SCSB1# SCSB2# SCSB3# SCSB4# SCSB5$ SRAS# SCAS# SWE# SCKE0 SCKE1 SCKE2 SCKE3 SCKE4 SCKE5 SCLK NC SDQM0 SDQM1 SDQM2 SDQM3 SDQM4 SDQM5 SDQM6 SDQM7 SRCOMP 82815 GMCH SMD0 SMD1 SMD2 SMD3 SMD4 SMD5 SMD6 SMD7 SMD8 SMD9 SMD10 SMD11 SMD12 SMD13 SMD14 SMD15 SMD16 SMD17 SMD18 SMD19 SMD20 SMD21 SMD22 SMD23 SMD24 SMD25 SMD26 SMD27 SMD28 SMD29 SMD30 SMD31 SMD32 SMD33 SMD34 SMD35 SMD36 SMD37 SMD38 SMD39 SMD40 SMD41 SMD42 SMD43 SMD44 SMD45 SMD46 SMD47 SMD48 SMD49 SMD50 SMD51 SMD52 SMD53 SMD54 SMD55 SMD56 SMD57 SMD58 SMD59 SMD60 SMD61 SMD62 SMD63 D23 C23 D22 F21 E21 G20 F20 D20 F19 E19 D19 E18 B18 F18 G18 D17 A3 A1 C1 F2 G3 D6 C5 B4 D4 C2 D3 E4 F5 G4 J6 K5 A26 A25 B24 A24 B23 A23 C22 A22 D21 B21 A21 C20 B20 A20 C19 A19 A4 A2 B1 E1 G2 E6 D5 C4 B3 D2 E3 F4 F6 G5 H4 J4 SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63 SM_MD[63:0] 10,11
82815 GMCH PART 2: SYSTEM MEMORY
4,5
R_REFCLK
R_BSEL0# 4 8 7 6 5 RP37 10K 1 2 3 4
SM_WE# SM_MAA9
10,11 10,11
C
Host freq; high = 100, low = 66
Place HUBREF generation circuit in the middle of GMCH and ICH.

VCC1_8
FSB PMOS kicker
4,10,11
SM_BS[1:0]
SM_CAS# RP35_JP7 RP35_JP8 RP35_JP9

66JP7 1
10,11 SM_BS0 4,10,11 10,11 10,11 10,11 10,11 10,11
Host freq; high = 133, low = 100 or
1 JP8
Reserved Strap 2 SM_BS1
SM/LM muxing strap, active low 1 JP9 2 SM_MAA11
HUBREF R167 301 1%
8,12,39
IOQ depth; high = 4, low = 1 RP36_JP101 JP10 2 SM_MAA12 Reserved Strap RP36_JP11 1 JP11 2 SM_MAA10 ALL-Z low 1 JP12 2 SM_RAS# RP36_JP12 XOR low
C244 1 2 0.01UF
B
10,11 10,11 10,11 10,11
SM_RAS# SM_CAS# SM_WE# SM_CKE[3:0]
8 7 6 5
SM_MAA12 1
RP35 10K
8 7 6 5 RP36 10K 1 2 3 4
R340 10k
DCLK_WR C140 22PF 1 10,11
4,5,31
TUAL5
Q29 MOSFET N
VCC3SBY R60 40 1%
1 2 3 4
REV.
82815 GMCH: SYSTEM MEMORY
1.0
3-26-01
intel
5 4 3 2

R

1
of
40
82815B GMCH, PART 3

AGP/DISPLAY CACHE & VIDEO INTERFACE
9 GAD[31:0] GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 GCBE#0 GCBE#1 GCBE#2 GCBE#3 GCBE#0 GCBE#1 GCBE#2 GCBE#3 K26 J22 K25 J21 L24 J20 L26 K23 K22 M25 M24 M26 M21 N24 N22 N26 T26 T22 U24 T23 U26 T24 V24 U21 V25 V21 V26 W21 W24 W22 W26 Y21 H23 N21 T25 Y26 R26 P26 P23 P21 P25 R24 AE26 AD25 AC26 M22 L23 U22 V23 Y23 AA24 ST0 ST1 ST2 AD24 AC24 AC23 U6-3 GAD0/LDQM0 GAD1/LMD4 GAD2/LMD7 GAD3/LMD3 GAD4/LMD6 GAD5/LMD2 GAD6/LMD5 GAD7/LMD1 GAD8/LMD0 GAD9/LMA4 GAD10/LDQM1 GAD11/LMA2 GAD12/LMD8 GAD13/LMA5 GAD14/LMD9 GAD15/LMA1 GAD16/LMA8 GAD17/LMD14 GAD18/LMA11 GAD19/LMD15 GAD20/LMA9 GAD21/LMD16 GAD22/LMA0 GAD23/LMD17 GAD24 GAD25/LMD18 GAD26/LCAS# GAD27/LMD19 GAD28/LTCLK1 GAD29/LMD20 GAD30/LTCLK0 GAD31/LMD21 LTVDATA0 LTVDATA1 LTVDATA2 LTVDATA3 LTVDATA4 LTVDATA5 LTVDATA6 LTVDATA7 LTVDATA8 LTVDATA9 LTVDATA10 LTVDATA11 LTVBLANK# LTVCLKIN LTVCLKOUT0 LTVCLKOUT1 LTVVSYNC LTVHSYNC LTVDA LTVCL AD16 AF17 AE17 AD17 AF18 AD18 AF20 AD20 AC20 AF21 AE21 AD21 AB19 AC18 AE19 AF19 AC16 AB17 AA20 AB21 AB18 AA18 AE24 Y20 AD23 AF22 AF23 AD22 AE22 AE23 F22 H24 H26 H25 G24 F24 E26 E25 D26 D25 D24 C26 H21 G25 F26 H20 AB22 AB25 AB23 AB26 AA22 AA26 Y22 Y25 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 GMCH_3V66 FTD0 FTD1 FTD2 FTD3 FTD4 FTD5 FTD6 FTD7 FTD8 FTD9 FTD10 FTD11 FTD[11:0] 24
D D
VDDQ C280 500PF GMCH_AGPREF_CV 1 2 1 R170 1K 1% 9 GMCH_AGPREF 2 2 1 R169 1K 1% 1 R168 82 1% 1 R171 82 1%
1
C
GMCH_AGPREF_CQ 2
82815 GMCH PART 3: DISPLAY CACHE, VIDEO, AND DDCCK DDCDA HUB INTERFACE DCLKREF
FTBLNK# 24 SL_STALL 24 FTCLK0 24 FTCLK1 24 FTVSYNC 24 FTHSYNC 24 3VFTSDA 24,25 3VFTSCL 24,25 3VDDCCL 3VDDCDA 25 25 DOTCLK IREFPD CRT_VSYNC 25 CRT_HSYNC 25 VID_RED 25 VID_GREEN 25 VID_BLUE 25 5 HL[10:0] 12,39 5
C
C279 500PF
IWASTE IREF VSYNC HSYNC RED GREEN BLUE HLCLK HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HUBREF HLSTB HLSTB# HCOMP SBA0/LMD31 SBA1/LMD25 SBA2/LDQM2 SBA3/LMD26 SBA4/LMD23 SBA5/LWE# SBA6/LMD22 SBA7/L_FSEL
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 ST[2:0]
GCBE0#/LMA3 GCBE1#/LMD10 GCBE2#/LMD13 GCBE3#/LRAS# GFRAME#/LMA10 GDEVSEL#/LMD11 GIRDY#/LMD12 GTRDY#/LMA7 GSTOP#/LCS# GPAR/LMA6 GREQ#/LMD27 GGNT# PIPE#/LMD24 ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB# ST0/LMD28 ST1/LDQM3 ST2/LMD29 RBF#/LMD30 WBF# AGPREF GRCOMP OCLOCK RCLOCK 82815 GMCH
GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB#
Place resistor as close as possible to GMCH. VCC1_8 R120 HUBREF 7,12,39 HLSTB 12,39 40 HLSTB# 12,39 2
B
GHCOMP SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 1 1 R86 174 2 C239 0.1uF 2 2 1
SBA[7:0]
1 9 C196 Do not stuff C196 Place Site within 0.5" 18pF of clock ball (AA21).
9 RBF# 9 WBF# CONN_AGPREF 1 R116 40 1% C190 0.1uF 1
GRCOMP_PD 1 2 R115 15
AD26 AB24 J24 J26 OCLK R22 RCLK P22 C233 22pF NPO
Place resistor as close as possible to GMCH and via straight to plane.
REV.
82815 GMCH: GRAPHICS
1.0
3-26-01
intel
5 4 3 2

R

1
of
40
AGP CONNECTOR
D
VCC5 19 19 VDDQ 12,16,17,36 PIRQ#B VCC3_3 5 AGPCLK_CONN 8 GREQ# 1 2 3 4 8.2K 8 ST[2:0] 8 SBSTB SBA4 SBA6 VCC3SBY 8 ST0 ST2 8 RBF# SBA0 SBA2 AGP_OC# AGPUSBP B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 OVRCNT# 5V_A 5V_B USB+ GND_K INTB# CLK REQ# VCC3_3_F ST0 ST2 RBF# GND_L RESV_H SBA0 VCC3_3_G SBA2 SB_STB GND_M SBA4 SBA6 RESV GND_N 3_3VAUX1 VCC3_3_H AD31 AD29 VCC3_3_I AD27 AD25 GND_O AD_STB1 AD23 VDDQ_F AD21 AD19 GND_P AD17 C/BE2# VDDQ_G IRDY# 3_3VAUX2 GND_Q RESV_K VCC3_3_J DEVSEL# VDDQ_H PERR# GND_R SERR# C/BE1# VDDQ_I AD14 AD12 GND_S AD10 AD8 VDDQ_J AD_STB0 AD7 GND_T AD5 AD3 VDDQ_K AD1 VREF_CG
J14 12V TYPEDET# RESV_A USBGND_A INTA# RST# GNT# VCC3_3_A ST1 RESV_B PIPE# GND_B WBF# SBA1 VCC3_3_B SBA3 SB_STB# GND_C SBA5 SBA7 RESV_C GND_D RESV_D VCC3_3_C AD30 AD28 VCC3_3_D AD26 AD24 GND_E AD_STB1# C/BE3# VDDQ_A AD22 AD20 GND_F AD18 AD16 VDDQ_B FRAME# RESV_E GND_G RESV_F VCC3_3_E TRDY# STOP# PME# GND_H PAR AD15 VDDQ_C AD13 AD11 GND_I AD9 C/BE0# VDDQ_D AD_STB0# AD6 GND_J AD4 AD2 VDDQ_E AD0 VREF_GC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
VCC12
VCC3_3 VDDQ TYPEDET# AGPUSBN 8 7 6 5 12,16,17,29,36 19 32 RP50 8.2k 1 2 3 4 GIRDY# 8 GDEVSEL# 8 GPERR# GSERR#
RP69 8 7 6 5
ST1
SBA[7:0]
SBA1 SBA3
PIRQ#A PCIRST# 6,12,14,15,16,17,18,19,24,29 GGNT# 8 RP49 8.2k 8 1 7 2 6 3 PIPE# 8 5 4 WBF# 8 SBA[7:0] 8 RP48 8.2k SBSTB# 8 8 7 6 5 R163 8.2k2 1 R119 8.2k2 1 R154 8.2k2 1 1 2 3 4
GFRAME# 8 GTRDY# 8 GSTOP# 8 GPAR 8
SBA5 SBA7
GREQ# 8 GGNT# 8 PIPE# 8 WBF# 8 ADSTB0 8 ADSTB1 8 RBF# 8 SBSTB 8

C
GAD[31:0]
Universal AGP Connector
GAD31 GAD29 GAD27 GAD25
GAD30 GAD28 GAD26 GAD24
GAD[31:0]
R160 8.2k2 1
R122 8.2k2 1 ADSTB1# 8 GCBE#3 8 GAD22 GAD20 GAD18 GAD16 GFRAME# 8 1 GTRDY# 8 GSTOP# 8 PCI_PME# 12,16,17,29 GAD15 GAD13 GAD11 GAD9 GCBE#0 GAD6 GAD4 GAD2 GAD0 ADSTB0# 8 CONN_AGPREF 8 GPAR 8 3 Q10 2N7002LT1 2 3 VDDQ R159 8.2k2 1 R117 8.2k2 1
VDDQ
ADSTB1 GAD23 GAD21 GAD19 GAD17
ADSTB0# 8 ADSTB1# 8 SBSTB# 8
8 8
GCBE#2 GIRDY#
VDDQ
8
B
GDEVSEL# GPERR# 8 GSERR# GCBE#1 GAD14 GAD12 GAD10 GAD8 8 ADSTB0 GAD7 GAD5 GAD3 GAD1
R114 301 1%
B
CON_AGPREF
1 R57 200 1% TYPEDET# 1 1 2 2 8
32
GMCH_AGPREF
REV.
AGP CONNECTOR
1.0
3-26-01
intel
5 4 3 2

R

1
of
40
SYSTEM MEMORY
7,11 4,7,11 MEMCLK[7:0] SM_MAA[12:0] SM_BS[1:0] SM_BS[1:0] 168 157 143 133 84 73 59 49 124 110 102 90 41 40 26 18 6 MEMCLK[7:0] SM_MAA[12:0] VCC3SBY SM_DQM[7:0] SM_DQM[7:0]
7,11
5,11 7,11 SM_MD[63:0]
VCC17 VCC16 VCC15 VCC14 VCC13 VCC12 VCC11 VCC10 VCC9 VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1
MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3 42 CLK0 125 CLK1 79 CLK2 163 CLK3
SM_MD[63:0]
DIMM0
SLAVE ADDRESS = 1010000B
SM_CSA#[3:0] SM_CSB#[3:0] 7,11 SM_WE# 7,11 SM_CAS# 7,11 SM_RAS# 7,11 SM_CKE[3:0] 11,12,13,25,30,36 SMBDATA 11,12,13,25,30,36 SMBCLK 7,11 7,11 SM_BS0 SM_BS1 SM_CSA#[3:0] SM_CSB#[3:0] SM_WE# SM_CAS# SM_RAS# SM_CKE[3:0] SMBDATA SMBCLK SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 SM_CSA#0 SM_CSA#1 SM_CSB#0 SM_CSB#1 28 29 46 47 112 113 130 131 30 114 45 129 27 111 115 SM_CKE0 SM_CKE1 122 BA0 39 BA1 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 S0# S1# S2# S3# WE# CAS# RAS# 128 CKE0 63 CKE1 82 83
SM_MAA0 SM_MAA1 SM_MAA2 SM_MAA3 SM_MAA4 SM_MAA5 SM_MAA6 SM_MAA7 SM_MAA8 SM_MAA9 SM_MAA10 SM_MAA11 SM_MAA12 33 117 34 118 35 119 36 120 37 121 38 123 126 132 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
DIMM SOCKET 168 PIN
SMBDATA SMBCLK 147 REGE 165 SA0 166 SA1 167 SA2 81 SAO_PU WP
System Memory DIMM0
intel
2 1
SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63 SAO_PU
R
11
24 25 31 44 48 50 51 61 62 80 108 109 134 135 145 146 164
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 162 152 148 138 127 116 107 96 85 78 68 64 54 43 32 23 12 1
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 21 22 52 53 105 106 136 137

Sheet:

Last Revision Date:
SYSTEM MEMORY: DIMM0

10 3-26-01 of 40
REV.
1.0
SYSTEM MEMORY
7,10 7 MEMCLK[7:0] 4,7,10 SM_MAB[7:4]# SM_MAA[12:0] SM_BS[1:0] 168 157 143 133 84 73 59 49 124 110 102 90 41 40 26 18 6 SM_DQM[7:0]
7,10
5,10 7,10 SM_MD[63:0] VCC3SBY SM_MD[63:0]
VCC17 VCC16 VCC15 VCC14 VCC13 VCC12 VCC11 VCC10 VCC9 VCC8 VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1
MEMCLK4 MEMCLK5 MEMCLK6 MEMCLK7 42 CLK0 125 CLK1 79 CLK2 163 CLK3 SM_MAA0 SM_MAA1 SM_MAA2 SM_MAA3 SM_MAB4 SM_MAB5 SM_MAB6 SM_MAB7 SM_MAA8 SM_MAA9 SM_MAA10 SM_MAA11 SM_MAA12 33 117 34 118 35 119 36 120 37 121 38 123 126 132 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 122 BA0 39 BA1 SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 SM_CSA#2 SM_CSA#3 SM_CSB#2 SM_CSB#3 28 29 46 47 112 113 130 131 30 114 45 129 27 111 115 SM_CKE2 SM_CKE3 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 S0# S1# S2# S3# WE# CAS# RAS# 128 CKE0 63 CKE1 82 83 SMBDATA SMBCLK 147 REGE 165 SA0 166 SA1 167 SA2 81 SAO_PU WP SM_BS0 SM_BS1
7,10 7,10 7,10 7,10 7,10 7,10 10,12,13,25,30,36 10,12,13,25,30,36 SM_CSA#[3:0] SM_CSB#[3:0] SM_WE# SM_CAS# SM_RAS# SM_CKE[3:0] SMBDATA SMBCLK SM_CSA#[3:0] SM_CSB#[3:0] SM_WE# SM_CAS# SM_RAS# SM_CKE[3:0] SMBDATA SMBCLK
DIMM1
SLAVE ADDRESS = 1010001B
DIMM SOCKET 168 PIN
SAO_PU
System Memory: DIMM1
intel
2 1
SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63
R
10 1 R30 2 2.2k
24 25 31 44 48 50 51 61 62 80 108 109 134 135 145 146 164
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 162 152 148 138 127 116 107 96 85 78 68 64 54 43 32 23 12 1
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 21 22 52 53 105 106 136 137

Sheet:
VCC3SBY

Last Revision Date:
SYSTEM MEMORY: DIMM1

11 3-26-01 of 40
REV.
1.0
ICH, PART 1
VCC3_3 VCC1_8 SMBCLK SMBDATA THERM# 10,11,13,25,30,36 13,36 E3 G5 P6 T7 U10 R13 T16 M14 C11 C8 A5 E6 E5 D16 N5 N13 E13 10,11,13,25,30,36 G13 H14 K14 G15 L15 H16 J16
D D
U21-1
VCC3_3_1 VCC3_3_2 VCC3_3_3 VCC3_3_4 VCC3_3_5 VCC3_3_6 VCC3_3_7 VCC3_3_8 VCC3_3_9 VCC3_3_10 VCC3_3_11 VCC3_3_12 VCC3_3_13 VCC3_3_14 VCC3_3_15 VCC3_3_16 VCC3_3_17
16,17,29
AD[31:0]
AD[31:0] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 G2 G4 F2 F3 F4 F5 E1 E2 D1 D3 E4 C2 C1 B1 D4 C3 A4 B4 C5 C6 B5 E7 A6 B6 D7 B8 A7 A8 B7 C9 D8 C7 D2 B2 A3 D6 C14 B3 D9 A2 C4 D5 J5 B9 A9 A1 K1 N6 P5 P4 R5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C_BE#0 C_BE#1 C_BE#2 C_BE#3 PCICLK FRAME# DEVSEL# IRDY# TRDY# STOP# PCIRST# PLOCK# PAR SERR# PME# REQ#A/GPIO0 GNT#A/GPIO16 REQ#B/GPIO1/REQ5# GNT#B/GPIO17/GNT5#
VCC1_8_1 VCC1_8_2 VCC1_8_3 VCC1_8_4 VCC1_8_5 VCC1_8_6 VCC1_8_7
SCLK# 1 SDATA 2 ALERT 3 4
VCC3_3
RP10
CPU
A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HLSTB HLSTB# HCOMP HUBREF PIRQ#A PIRQ#B PIRQ#C PIRQ#D
F13 E12 F15 B17 E15 E14 B16 F14 A17 A15 B15 D17 E17 F17 G16 J15 K16 K17 L17 H15 J17 J14 G17 H17 M17 J13 D10 A10 B10 C10 P11 N14 C16 C17 E16 R4 A14 B13 B12 D12 A13 C13 A12 C12 RESV0PU A11 RESV1PU 1 B11 F16 RESV2RD 1 2 R173 0K
Don't Stuff R173 For Test/Debug
VDD STBY# SCLK# SDATA ALERT ADD0 ADD1 VSS1
INTEL 82801AA PART 1

HUB I/F PCI
A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE HL[10:0] HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HLSTB HLSTB# IHCOMP_PU HUBREF PIRQ#A PIRQ#B PIRQ#C PIRQ#D IRQ14 IRQ15 APICCLK_ICH APICD1 APICD0 SERIRQ PREQ#0 PREQ#1 PREQ#2 PREQ#3 PGNT#0 PGNT#1 PGNT#2 PGNT#3 R213 1 2 R212 8.2K
A20M# 4,36 CPUSLP# 4,36 FERR# 4,36 IGNNE# 4,36 INIT# 4,14,36 INTR 4,36 NMI 4,36 SMI# 4,36 STPCLK# 4,36 RCIN# 15,36 A20GATE 15,36 HL[10:0] 8,39 VCC1_8
C
8 7 6 5
2 15 14 12 11 10 6 8
0K
1 R178 40 1% HLSTB 8,39 possible to HLSTB# 8,39ICH 2

Place R178 as close as
ADM1023
D+ DNC TEST0 TEST1 NC0 NC1 VSS0 U1
3 4 13 1 16 5 9 7
HUBREF PIRQ#A PIRQ#B PIRQ#C PIRQ#D 1 9,16,17,29,36 C291 0.1UF 9,16,17,36 16,17,36 Place C291 16,17,36
as close as possible to
7,8,39
16,17,29 4 4
C_BE#[3:0]
C_BE#[3:0] C_BE#0 C_BE#1 C_BE#2 C_BE#3
IRQ
THERMDN
THERMDP
5 16,17,29,36 16,17,29,36 16,17,29,36 16,17,29,36 16,17,29,36 6,9,14,15,16,17,18,19,24,29 16,17,36 16,17,29 16,17,29,36 9,16,17,29 17,36 17 36 36
PCLK_0/ICH FRAME# DEVSEL# IRDY# TRDY# STOP# PCIRST# PLOCK# PAR SERR# PCI_PME#
PCLK_0/ICH FRAME# DEVSEL# IRDY# TRDY# STOP# PCIRST# PLOCK# PAR SERR# PCI_PME# PCPCI_REQ#A PCPCI_GNT#A REQ#B/GPIO1 GNT#B/GPIO17
IRQ14 IRQ15 APICCLK APICD1 APICD0 SERIRQ REQ#0 REQ#1 REQ#2 REQ#3
IRQ14 18,36 ICH IRQ15 18,36 APICCLK_ICH 5 APICD1 4,36 APICD0 4,36 SERIRQ 15,17,36
B
PREQ#0 PREQ#1 PREQ#2 PREQ#3 PGNT#0 PGNT#1 PGNT#2 PGNT#3 8.2K 2
PCI
GNT#0 GNT#1 GNT#2 GNT#3 GNT4# REQ4# HL11
PCPCI_REQ#A PCPCI_GNT#A REQ#B/GPIO1 GNT#B/GPIO17
PC/PCI
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13
C312 10PF 82815 ICH

No Pop
R2 G3 H8 J8 K8 H9 J9 K9 H10 J10 K10 G14 K15
36 16,36 17,36 29,36 36 16,36 VCC3_3 17,36 29,36
REV.
ICH, PART 1
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
12
of
40
ICH, PART 2
VCC3SBY 1 BAT17 1 1
D
VCCRTC CR10 2 VCC3SBY VRTC VCC3SBY VCC3_3 ICH5VREF 1 1 1 BAT17 C285 1.0UF
R85 and R203 for Test/Debug
VCC5 1
R258 1K
C284 .1UF
CR6
C15
G1
N1
VBATC
VCCSUS2
VCCSUS1
VCCRTC
1 2 CR9 BAT17 1 1
8.2K
C385
R257 1K
ICH_PWROK PWRBTN# ICH_RI# RSMRST# SUS_STAT# SMBDATA SMBCLK SMBALERT#
D14 K3 SLP_S5# K2 J3 PWRBTN# M2 ICH_RI# L3 RSMRST# F1 SUS_STAT# L4 SMBDATA SMBCLK SMBALERT# INTRUDER# ICH_CLK14 USBCLK ICH_3V66 J1 J2 M1 J4 U6 U2 A16 H2 H3 H4 H1 T1 T3 R3 T2 U1 P3 U3 D11 E11 F9 N4 L2 B14 D13 D15 K4 M5 L5 R6 U5 T5 T4 U4 T6 N3 R1 P2 P1 N2 M4 M3 1
R252
JP20 12,36 2 31,35 3 JP24_PD 2.2UF 34,40 R253 21 1K 30,35 30 R_VBIAS C384 10,11,12,25,30,36 10,11,12,25,30,36 .047UF 36 VBATC_DLY1 THERM# SLP_S3# THERM# SLP_S3# THRM# SLP_S3/GPIO24 SLP_S5 PWROK PWRBTN# RI# RSMRST# SUSSTAT#/GPIO25 SMBDATA SMBCLK SMBALERT#/GPIO11 INTRUDER#/GPIO10 CLK14 CLK48 CLK66 VBIAS RTCX1 RTCX2 RTCRST# AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1/GPIO9 SPKR GPIO5 GPIO6 GPIO7/PERR# GPIO12 GPIO13 GPIO21 GPIO22 GPIO23 GPIO26/SUSCLK GPIO27 GPIO28 LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME#/FWH4 LDRQ#0 LDRQ#1/GPIO8 USBP1P USBP1N USBP0P USBP0N OC#1 OC#0
5VREF
R260 10K
R255 10K
U21
L1
C422 1.0UF
R250 2 2 18 18 18 18 18 18
1K
PDCS#1 SDCS#1 PDCS#3 SDCS#3 PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
N12 L14 U13 L16 R12 T12 P12 M16 M15 L13 U11 P17 U12 M13 R11 N16 T11 N15 N11 N17 R10 N9 R9 U9 R8 U8 R7 U7 P7 N7 T8 P8 T9 P9 T10 P10 P15 R16 T17 U16 U15 R14 P13 T13 U14 T14 P14 T15 U17 R15 R17 P16
PDCS#1 SDCS#1 PDCS#3 SDCS#3 PDA[2:0] PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 SDA[2:0]
PDCS#1 SDCS#1 PDCS#3 SDCS#3 PDA[2:0] SDA[2:0]
SYSTEM
VBAT 2 1
R251 10M X2
36 INTRUDER# 5 ICH_CLK14 5 USBCLK 5 ICH_3V66
Socketed
CR2032 3
R259 1 10M Y4A 2 26 26,27 26,27 26,27 26,27,36 26,36 C386 34
VBIAS RTCX1 RTCX2 RTCRST# AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 ICH_SPKR AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 ICH_SPKR LPC_SMI# LPC_PME# GPIO7 GPIO12 GPIO13 GPIO21 GPIO22 GPIO23_FPLED GPIO26_FPLED GPIO27 GPIO28 LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME#/FWH4 LDRQ#0 LDRQ#1 USBP1P USBP1N USBP0P USBP0N OC#0
INTEL 82801AA PART 2

AC97 IDE
1 C380 18PF 2 1 32.768KHZ
18PF 15,36 15,36 17,36 36 36 17,36 36 34 34 VCC3_3 30 30 2 1 14,15 R271 14,15 1K 14,15 14,15 14,15 15 36
LPC_SMI# LPC_PME# GPIO7 GPIO12 GPIO13 GPIO21 GPIO22 GPIO23_FPLED GPIO26_FPLED GPIO27 GPIO28 LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME#/FWH4 LDRQ#0 LDRQ#1 19 19 19 19 USBP1P USBP1N USBP0P USBP0N OC#0
GPIO
LPC
2 1
1 2
A B
VCC
34
ICH_SPKR
JP21
JP24 Minimize Stub Length to Jumpers
USB
19 1
R264 1K
PDREQ SDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY PDD[15:0] PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 SDD[15:0] SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
PDREQ 18 SDREQ 18 PDDACK# 18 SDDACK# 18 PDIOR# 18 SDIOR# 18 PDIOW# 18 SDIOW# 18 PIORDY 18 SIORDY 18 PDD[15:0] 18
VCC3_3 D2 3 VCC3_3
B
VCC_CLK R341 1 43k
U74 2 1
SDD[15:0]
18
BAT54C
JP14_PU 2
C457 1.0uF 2
GND
ICH_PWROK
1 JP13_PD 1
30,31,35
PWROK
R342
AC_SDOUT 2
26,27 2
C289 18PF 82815 ICH Note: Depending on the version of ICH being used, an external crystal may be required. Contact Intel for implementation.
0 Empty Debug Only
741G08 AND
REV.
ICH, PART 2
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
13
of
40
FIRMWARE HUB (FWH) SOCKET

NOTE: This is a TSOP Implementation
D D
VCC3_3 VCC3_3 VCC3_3
C387 0.1UF
C425 0.1UF
C401 0.1UF
C424 0.1UF
C395 0.1UF 2 13,15

C
0.1UF 2
40 PIN_TSOP_SKT
X3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC1 IC NC3 NC4 NC5 NC6 FGPI4 NC8 CLK VCC10 VPP RST# NC13 NC14 FGPI3 FGPI2 FGPI1 FGPI0 WP# TBL# FWH Socket GNDA VCCA FHW4 INIT# RFU36 RFU35 RFU34 RFU33 RFU32 VCC31 GND30 GND29 FWH3 FWH2 FWH1 FWH0 ID0 ID1 ID2 ID3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 LFRAME#/FWH4 INIT#
Distribute close to each power pin
LFRAME#/FWH4 INIT# 4,12,36
VCC3_3
VCC3_3 5 PCLK_6 PCLK_6 R_VPP PCIRST#
R288 4.7K 2
2 0K 6,9,12,15,16,17,18,19,24,29 PCIRST#
1 R273
R274 1
FGPI1_PD FGPI0_PD
JP26
4 3 2 1
4 3 2 1
IC_PD FGPI4_PD FGPI3_PD FGPI2_PD
2 4.7K
WPROT TBLK_LCK
LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0 FWH_ID0 FWH_ID1 FWH_ID2 FWH_ID3
LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0
13,15 13,15 13,15 13,15
PR65
B
RP64 0K 8.2K
4 3 2 1
RP68
B
8.2K
RP68 for Test/Debug
5 6 7 8
5 6 7 8
5 6 7 8
C423
REV.
FIRMWARE HUB (FWH)
1.0
3-26-01 14
1
intel
5 4 3 2

R
of
40
SUPER I/O
D
VCC5
VCC3_3
44 18
U22 13,14 LFRAME#/FWH4 13,14 LAD3/FWH3 13,14 LAD2/FWH2 13,14 LAD1/FWH1 13,14 LAD0/FWH0 13 LDRQ#0 6,9,12,14,16,17,18,19,24,29 PCIRST# 13,36 LPC_PME# 12,17,36 SERIRQ 5 PCLK_1 22 KDAT 22 KCLK 22 MDAT 22 MCLK 12,36 RCIN# 12,36 A20GATE
C
53 65 93
VREF VTR
VCC3_3 R93 8.2k
LFRAME#/FWH4 LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0 LDRQ#0 PCIRST# LRESET# LPC_PME# SERIRQ PCLK_1 KDAT KCLK MDAT MCLK RCIN# A20GATE
24 23 22 21 20 25 26 27 17 30 29 56 57 58 59 63 64 61 62
VCC1 VCC2 VCC3
LFRAME# LAD3 LAD2 LAD1 LAD0 LDRQ# LRESET# LPCPD# PME# SERIRQ PCI_CLK KDAT KCLK MDAT MCLK KBDRST A20GATE IRRX2/GP34 IRTX2/GP35 RXD1 TXD1 DSR1# RTS1# CTS1# DTR1# RI1# DCD1# RXD2_IRRX TXD2_IRTX DSR2# RTS2# CTS2# DTR2# RI2# DCD2# DRVDEN1 DRVDEN0 MTR0# DS0# DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK0# WRTPRT# RDATA# DSKCHG# CLKI32 CLOCKI
LPC I/F
PARALLEL PORT I/F
KYBD/MSE I/F
INIT# SLCTIN# PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 SLCT# PE BUSY ACK# ERROR# ALF# STROBE# FAN2/GP32 FAN1/GP33
66 67 75 74 73 72 71 70 69 68 77 78 79 80 81 82 83 54 55 28
PAR_INIT# SLCTIN# PDR7 PDR6 PDR5 PDR4 PDR3 PDR2 PDR1 PDR0 SLCT# PE BUSY ACK# ERROR# ALF# STROBE# PWM2 PWM1 SIO_GP43
PAR_INIT# 20 SLCTIN# 20 PDR[7:0] 20
SLCT# 20 PE 20 BUSY 20 ACK# 20 ERROR# 20 ALF# 20 STROBE# 20 PWM2 PWM1 34 34

C
34 34
IRRX IRTX
IRRX IRTX 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 22 22 22 22 22 22 5 RXD#0 TXD0 DSR#0 RTS#0 CTS#0 DTR#0 RI#0 DCD#0 RXD#1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 RXD#0 TXD0 DSR#0 RTS#0 CTS#0 DTR#0 RI#0 DCD#0 RXD#1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 DRVDEN#1 DRVDEN#0 MTR#0 DS#0 DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK#0 WRTPRT# RDATA# DSKCHG# SIO_CLK14
INFRARED I/F
C389 470PF
C397 470PF
84 85 86 87 88 89 90 91 95 96 97 98 99 100 92 94 2 1 3 5 8 9 10 11 12 13 14 15 16 4 6 19
FDC_PP/DDRC/GP43
Test/Debug Header Unused GPIOs
SERIAL PORT 1
J25 1 3 5 2 4 6
SIO LPC47B27X
SERIAL PORT 2
GP60/LED1 GP61/LED2 GP27/IO_SMI# GP30/FAN_TACH2 GP31/FAN_TACH1 GP25/MIDI_IN GP26/MIDI_OUT GP10/J1B1 GP11/J1B2 GP12/J2B1 GP13/J2B2 GP14/J1X GP15/J1Y GP16/J2X GP17/J2Y GP20/P17 GP21/P16 GP22/P12 GP24/SYSOPT AVSS 48 49 50 51 52 46 47 32 33 34 35 36 37 38 39 41 42 43 45 SIO_GP60 SIO_GP61 LPC_SMI# TACH2 TACH1 MIDI_IN MIDI_OUT J1BUTTON1 J1BUTTON2 J2BUTTON1 J2BUTTON2 JOY1X JOY1Y JOY2X JOY2Y KEYLOCK# SIO_GP21 SIO_GP22
VCC3_3
Decoupling
Place near VREF pin VCC5
C340 0.1UF
C390 0.1UF
C388 0.1UF
C345 0.1UF
C341 + 2.2UF
C336 0.1UF
Place 1 0.1UF cap near each power pin
DRVDEN#1 DRVDEN#0 MTR#0 DS#0 DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK#0 WRTPRT# RDATA# DSKCHG# SIO_CLK14
LPC_SMI# 13,36 TACH2 34 TACH1 34 MIDI_IN 23 MIDI_OUT 23 J1BUTTON1 23 J1BUTTON2 23 J2BUTTON1 23 J2BUTTON2 23 JOY1X 23 JOY1Y 23 JOY2X 23 JOY2Y 23 KEYLOCK# 34
FDC I/F
CLOCKS
GND1 GND2 GND3 GND4
SYSOPT Pulldown on SYSOPT for IO address of 0x02E 1 R224 4.7K 2
7 31 60 76
40
SIO LPC47B27X
REV.
SUPER I/O
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
15
of
40
PCI CONNECTOR 0 (DEV Ah)

D
VCC3SBY VCC12M VCC5 VCC3_3 17 PTCK PTCK B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 key AD8 AD7 AD5 AD3 AD1 36 PU2_ACK64# PU2_ACK64# B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 PCI3_CON A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 C_BE#0 AD6 AD4 AD2 AD0 PU2_REQ64# PU2_REQ64# 36 C_BE#0 12,17,29 J19 VCC12 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 PTRST# PTMS PTDI PIRQ#B PIRQ#D PTRST# 17 VCC3_3 VCC5
D
PTMS 17,36 PTDI 17,36 PIRQ#B PIRQ#D 9,12,17,36 12,17,36
12,17,36 9,12,17,29,36 17 17
PIRQ#C PIRQ#A PRSNT#21 PRSNT#22
PIRQ#C PIRQ#A PRSNT#21 PRSNT#22
PCIRST# PGNT#1 PCI_PME# AD[31:0] AD30 AD28 AD26 AD24 R_AD16 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# SDONEP2 SBOP2 PAR AD15
PCIRST#
6,9,12,14,15,17,18,19,24,29
5 12,36 12,17,29
C
PCLK_3 PREQ#1 AD[31:0] AD[31:0]
PCLK_3 PREQ#1 AD31 AD29
PGNT#1 12,36 PCI_PME# 9,12,17,29 AD[31:0] 12,17,29

C
12,17,29
C_BE#[3:0]
C_BE#[3:0]
AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2
1 R207 2 100
AD16
12,17,29
FRAME# TRDY# STOP#
12,17,29,36 12,17,29,36 12,17,29,36
12,17,29,36 12,17,29,36 12,17,36 17,29 12,17,29,36
IRDY# DEVSEL# PLOCK# PERR# SERR#
IRDY# DEVSEL# PLOCK# PERR# SERR# C_BE#1 AD14 AD12 AD10
SDONEP2 36 SBOP2 36 PAR 12,17,29
AD13 AD11 AD9
REV.
PCI CONNECTOR 0
1.0
3-26-01
intel
5 4 3 2

R

1
16
of
40
PCI CONNECTOR 1 (DEV Bh)

D
VCC12M VCC5 VCC3_3 J24 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 key AD8 AD7 AD5 AD3 AD1 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 PCI3_CON A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 VCC12 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
VCC3_3 VCC5
D
PTRST# PTMS PTDI PIRQ#C PIRQ#A R261 R_GNT#A 1
PTRST#
16
16
PTCK
PTCK
PTMS 16,36 PTDI 16,36 PIRQ#C PIRQ#A 12,16,36 9,12,16,29,36 VCC3SBY 16 PTRST# PTCK 1 R247 5.6K 1 R284 5.6K
12,16,36 9,12,16,36
For Debug Only
PIRQ#D PIRQ#B PRSNT#31 GPIO21 PRSNT#32 SERIRQ
13,36 12,15,36
GPIO21 SERIRQ 5 12,36 12,16,29
PIRQ#D PIRQ#B PRSNT#31 R_GPO21 R285 0K 2 1 R286 0K 2 1 PCLK_4 PREQ#2 R_SERIRQ
2 2
2 PCPCI_GNT#A
For Debug Only
PCPCI_GNT#A
12 R248 16
For Debug Only
0K VAUX3 PCIRST# PGNT#2 PCI_PME# AD[31:0] AD30 AD28 AD26 AD24 R_AD17 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# SDONEP3 SBOP3 PAR AD15
PCIRST#
1 2 6,9,12,14,15,16,18,19,24,29 0K R249 2 0K
For Debug Only
PCLK_4 PREQ#2 AD[31:0] AD[31:0]
PGNT#2 12,36 PCI_PME# 9,12,16,291 AD[31:0] 12,16,29
PCPCI_REQ#A
12,36
C
AD31 AD29 12,16,29 C_BE#[3:0] C_BE#[3:0] AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 12,16,29,36 12,16,29,36 12,16,36 16,29 12,16,29,36 IRDY# DEVSEL# PLOCK# PERR# SERR# IRDY# DEVSEL# PLOCK# PERR# SERR# C_BE#1 AD14 AD12 AD10
Do Not Stuff R192
R287 1 100 2 AD17 12,16,29 16 16
PRSNT#32 PRSNT#31 PRSNT#22 PRSNT#21 1 1 1 C363 0.1UF 2 C368 0.1UF 2 C414 0.1UF 2 1 2 C415 0.1UF
FRAME# TRDY# STOP#
12,16,29,36 12,16,29,36 12,16,29,36
SDONEP3 36 SBOP3 36 PAR 12,16,29
AD13 AD11 AD9 C_BE#0 AD6 AD4 AD2 AD0 PU3_REQ64# PU3_REQ64# 36 C_BE#0 12,16,29 16,29 PERR#
JP25 1 2 3 GPIO7 13,36 PERR#_PU 36
36
PU3_ACK64#
PU3_ACK64#
REV.
PCI CONNECTOR 1
1.0
3-26-01
intel
5 4 3 2

R

1
17
of
40
IDE CONNECTORS
D
VCC5 PRIMARY IDE CONNECTOR 13 PDD[15:0] PDD[15:0] 1 R102 1K PCIRST_BUF# 1 R190 33 2 R_RSTP# PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J16 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 13 13 13 13 13 12,36 J16_C206 PDCS#3 PDCS#3 13 13 34 SDCS#1 IDEACTS# SDA2 1 1 SDA[2:0] SDA[2:0] 1 1 SDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 SDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 SDA1 SDA0 PCIRST_BUF# 1 R182 33 2 13 SDD[15:0]
VCC5 SECONDARY IDE CONNECTOR SDD[15:0] 1 R100 1K J15 R_RSTS# SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
13 13 13 13 13 12,36
PDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14
PDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0
PRI_PD1
PRI_SD1 J15_C205 SDCS#3 SDCS#3 13
13 34
PDCS#1 IDEACTP# PDA2 PDA[2:0] PDA[2:0] 1 1
13
13 C206 0.047UF
R101 470 2
R98 470
R129 R133 5.6K 2 2 10K
R130 R132 5.6K 2 2 10K 2
C205 0.047UF
VCC3_3
VCC3_3 1 R191 8.2K
14
6,9,12,14,15,16,17,19,24,29
PCIRST#
PCIRST#
U11C 6 SN74LVC07A 7
PCIRST_BUF#
PCIRST_BUF#
REV.
ULTRA DMA/66 CONNECTOR
1.0
3-26-01
intel
5 4 3 2

R

1
18
of
40
VCC3SBY VCC3SBY VCC3_3 VCC3_3
VCC5DUAL Do Not Stuff
USB HUB
D
R214 R181 R228 R188 330K 330K 330K 330K NPO
26 POLYSWITCH_RUSB250 26
AC97_USBAC97_USB+
1 R153 2 0K 1 R151 2 0K
AC_USB_N AC_USB_P
D
F3 2.5A
NPO 9 26 AGP_OC# AC97_OC#
L21 USB_V5 1 R179 1 C294 68UF 1 C295 0.1UF 2 9 9 AGPUSBN AGPUSBP Do Not Stuff 1 R157 2 0K 1 R150 2 0K 470K 2 2 1 2 USB_PO_A 1
R180 0K
1 2
R187 0K
13
OC#0 1 R186 560K 2 U18 8 6 1 R189 1.5K U16 1 2 3 25 DP0 DM0 VCC1 VCC2 DM1 DP1 11 12 15 16 19 20 23 24 DM41 R184 15K DP41 R183 15K PW 1 PW 2 PW 3 PW 4 OC1 OC2 OC3 2 2 3 4 7 8 16 13 12 OC4 9 USB_D2_N USB_D2_P USB_D3_N USB_D3_P U17 DM3 DP3 DM4 DP4 EECLK SUSPND PWRON1# PWRON2# PWRON3# PWRON4# OVRCUR1# OVRCUR2# OVRCUR3# OVRCUR4# BUSPWR EEDATA/GANGED TUSB2043 9 13 17 21 10 14 18 22 8 6 1 1 VCC3SBY C331 C330 47PF 2 6 8 B D A C 4 2 1 FB2 2 USB_GND_B 13 13 USBP0N USBP0P R216 1 15 1 R215 2 15 2 1 R25 0K 1 R24 2 USB_D1_N 0K USB_D1_P 2 FB1 1 2 USB_PO_B 1 2 3 4 5 6 7 8 Ja2 VCC1 DATA1DATA1+ GND1 VCC2 DATA2DATA2+ GND2 RJMAG_USB A C B D 2 4
VCC3_3 1
VCC3_3 0.001UF 1 2 0K 2
R233 0K NO POP
C
R232
C297
SN75240
C
13 13
USBP1P USBP1N
USBP1P USBP1N
5 17,18,24,29
USB_CLK PCIRST#
USB_CLK PCIRST# MODESLCT EXTMEM#
27 4 31 26
USB HUB
TUSB2043
CLKIN RESET# MODESLCT EXTMEM#
DM2 DP2
R296 1K 2
SN75240 USB_D4_N USB_D4_P U15 EN1# EN2# EN3# EN4# OC1# OC2# OC3# OC4# TP2044 OUT1 OUT2 OUT3 OUT4 IN1 IN2 GND1 GND2 15 14 11 10 2 6 1 5 C7 1 OUT1 OUT2 OUT3
1 1 FB8 1 1 FB11 2 2
C296 0.1UF
5 32
USB_PO_C1 2 2 3 USB_GND_C 4 FB10
FB9
J17
29 30
TESTOUT TESTIN
USB_PO_D1 J21 2 2 3 USB_GND_D 4
7 28
GND1 GND2
USB_GND_A 1 C342 100UF 2 1 C343 100UF 2 1 C26 L10 47PF 2 2 1
100UF 2 R193 1 R196 1 R194 1 1 1 1 15K 2 R192 R195 2 2 R197 2 R152 2 R158 15K 15K 1 1 15K
47PF 1 1 1 R301 R300 R299 R298 1K 1K 1K 1K 1 2 2 2 2
REV.
15K 2 2
15K 2
15K
15K
USB HUB
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
19
of
40
PARALLEL PORT
VCC5
D D
CR3 1 2 1N4148 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 RP42 2.2K RP46 2.2K 1 2 3 4 VCC5_DB25_CR
RP40 R84 2.2K 2.2K
RP39 2.2K
1 2 3 4
1 2 3 4
1 2 3 4
J8A DB25 15
C
SLCT# PE
SLCT# PE BUSY ACK# J8_9 RP63 33 1 2 3 4 1 2 3 4 RP41
15 15 15 15
BUSY ACK#
PDR[7:0] PDR7 PDR6 PDR5 PDR4 PDR3 PDR2 SLCTIN# PAR_INIT# ERROR#
8 7 6 5 8 7 6 5 33
J8_8 J8_7 J8_6 J8_5 J8_17 J8_4 J8_16 J8_3 J8_2 J8_14 J8_1
15 SLCTIN# 15 PAR_INIT# 15 ERROR#
RP38 PDR1 PDR0 ALF# STROBE# 1 2 3 4 33 8 7 6 5 1 C172 1 C170 1 C177 1 C176 1 C175 1 C166 1 C168 1 C207 1 C215
13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
15
15 ALF# STROBE#
2 180PF
2 180PF
2 180PF
2 180PF
2 180PF
2 180PF
2 180PF
2 180PF
2 180PF 1 C171 2 180PF 1 C163 2 180PF 1 C178 2 180PF 1 C164 2 180PF 1 C165 2 180PF 1 C167 2 180PF 1 C187 2 180PF 1 C214 2 180PF
REV.
PARALLEL PORT
1.0
3-26-01
intel
5 4 3 2

R

1
20
of
40
Serial Port and Header

VCC12
D
VCC5
VCC12-
U5 15 15 15 15 15 15 15 15 VCC3SBY GD75232 1 1 1 C174 100PF RI#_CR_C 1 2 2 1 1 C173 100PF 2 C189 100PF 2 1 C186 100PF 2 C184 100PF 2 1 C181 100PF 2 1 100PF 2 2 1 C179 100PF 2
PLACE CLOSE TO HEADER
J7A VCC12 RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 VCC-12 1 2 3 4 5 6 7 8 9 10 DB9 DCD0_C DSR0_C RXD0_C RTS0_C TXD0_C CTS0_C DTR0_C RI0_C 1 6 2 7 3 8 4 9 5
DCD#0 RXD#0 DSR#0 DTR#0 TXD0 CTS#0 RTS#0 RI#0
20 19 18 17 16 15 14 13 12 11
VCC RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND
BAT54C
CRa8 1 C118
R276 10K
13
ICH_RI# 3 Q16 1 2 1 ICHRI#_C 2N7002LT1
R277 47K
VCC12 VCC5 VCC12-
2ND COM Header Option

If not populated at all, remove CR14 and short RI#0_C to RI#CR
R278 47K
C398 1.0UF
U23 DCD#1 RXD#1 DSR#1 DTR#1 TXD1 CTS#1 RTS#1 RI#1 20 19 18 17 16 15 14 13 12 11 VCC RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND VCC12 RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 VCC-12 1 2 3 4 5 6 7 8 9 10 DCD#1_C RXD#1_C DSR#1_C DTR#1_C TXD#1_C CTS#1_C RTS#1_C RI#1_C
NOTE: If Wake from S3 on Serial Modem is not supported do not stuff CR15 and Q10.
15 15 15 15 15 15 15 15
J22 1 3 5 7 9 2 4 6 8 10
C353 100PF
C352 100PF
C348 100PF
GD75232
C346 100PF
PLACE CLOSE TO HEADER
C351 100PF
C347 100PF
C350 100PF
C344 100PF
REV.
SERIAL PORTS
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
21
of
40
Keyboard/Mouse Port
VCC5DUAL 1 VCC5 1
Floppy Disk Header

VCC5
R177 0K 2
R185 0K 2 F1 L4 PS2V5_F 2 1 1.25A 2 PS2V5 1 2 3 4 1K RP45 8 7 6 5
R177_F1
8 7 6 5 RP1 4.7K
STACKED PS2 CONNECTOR L3 J1 2 L5 L_KDAT PS2_PD 1 2 3 4 5 6 7 8 9 10 11 12 1 C2 2 0.1UF 470PF 2 1 C4 470PF 2 470PF 2 1 C5 470PF L2 1 2 1 2 17 16 15 14 13 PS2GND 15 DRVDEN#0
1 2 3 4
1 R131 1K
J13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
15
KDAT
15 15
KCLK MDAT
1 L7 1 L6
2 2
L_KCLK L_MDAT
15 DRVDEN#1 15 INDEX# 15 MTR#0 15 DS#0
15
MCLK
L_MCLK
C1
C3
15 DIR# 15 STEP# 15 WDATA# 15 WGATE# 15 TRK#0 15 WRTPRT# 15 RDATA# 15 HDSEL# 15 DSKCHG#
L1
REV.
KEYBOARD/MOUSE/FLOPPY
1.0
3-26-01
intel
5 4 3 2

R

1
22
of
40
Game Port
D D
VCC5
R223 1K
R225 1K
R230 1K
R218 1K
R229 1K
1 2
R217 1K
VCC5
J6-1 DB15 31 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 32
15 15
J1BUTTON1 J2BUTTON1 15 JOY1X 15 JOY2X MIDI_OUT
1 R219 2.2K 2 5% 1 R221 2.2K 2 5% 1 R227 2 47 1 R222 2.2K 2 5% 1 R220 2.2K 2 5% 1 R226 2 47
JOY1X_R JOY2X_R MIDI_OUT_R JOY2Y_R JOY1Y_R MIDI_IN_R
15
15 15
15 JOY2Y 15 JOY1Y J2BUTTON2 J1BUTTON2 15 MIDI_IN
25V 10%
B
C333 0.01UF
25V 10%
C30 470PF
C337 470PF 2
B
0.01UF 2
C112
C29
C67
C80
25V 10%
C335 0.01UF
25V 10%
C334 0.01UF
50V 47PF 50V 47PF 2 2
50V 47PF 50V 47PF 2 2
The game port capacitors together and to SIO AVSS. Tie to system ground at only a single point.
C68
REV.
GAME PORT
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
23
of
40
Digital Video Out Connector (FOR DEBUG PURPOSES ONLY)

D D
J10 8 FTD[11:0] FTD11 FTD10 FTD9 FTD8

C
FTD7 FTD6
1 3 G1 5 7 G2 9 11 G3 13 15 G4 17 19 21 23 G5 25 27 G6 29 31 G7 33 35 G8 37 39 41 43 G9 45 47 G10 49 51 G11 53 55 G12 57 59
D11
Y C
2 4 6 8
VCC5
VCC3_3
D10 G1 CVBS D9 G2 SP0 SP1 D8 G3 SP2 SP3 D7 G4 5V1 5V2 D6 3V1 3V2 ST# G5 3V3 3V4 STB G6 VDD1 VDD2 D5 G7 VDD3 VDD4 D4 G8 VREF D3 PD# RST# D2 G9 SDA5 SCL5 D1 G10 SDA SCL D0 G11 I/C D/B G12 HS VS
VCC1_8 1 1 C261 2.2UF 2 C263 1.0UF 2 1 10 12 14 16 18 20 VCC1_8 22 24 26 28 30 32 34 36 38 40 42 44 PCIRST# 46 48 50 52 54 56 58 60 5VFTSDA 5VFTSCL 6,9,12,14,15,16,17,18,19,29 25 25
B
C260 1.0UF
C262 1.0UF 1 R145 1K 2

C
C257 2.2UF
C258 1.0UF
C259 1K 1.0UF
C266 0.01UF
FTD5 FTD4 FTD3 FTD2

B
2 Place this capacitor near pin 40.
FTVREF
FTD1 FTD0 8 8 8 FTCLK0 FTCLK1 FTBLNK#
3VFTSDA 8,25 3VFTSCL 8,25 SL_STALL FTHSYNC FTVSYNC 8 8 8
DVO CONNECTOR
R144
C265 100PF
REV.
DIGITAL VIDEO OUT CONNECTOR
1.0
3-26-01
intel
5 4 3 2

R

1
24
of
40
VCC5
VGA CONNECTOR
F2
D
2 2.5A
D
R103 1K
2 CRT5V_F 1
1 R104 1K 2 L20 1 1 R107 75 1% CR5 QS4_3V 2 1 L_RED MONOPU L_GREEN 1 C209 3.3PF 2 L_BLUE L_HSYNC FUSE_5 MON2PU L_VSYNC 3 13 9 4 14 10 5 15 1 R105 2 0K C212 3.3PF 2 15 pin VGA CONNECTOR C195 3.3PF 2 VCC5 3.3PF 2 1 J9 2 6 1 11 7 2 12 8 1 C210
BLM11B750S is rated an 75 Ohms an 100MHz
L18 8 VID_RED 1 2 2
RP47
C
Place R66, R67, & R69 close to VGA Connector L17 1 8 4.7K 0.1UF 75 1% 2 3.3PF 2 VID_GREEN 1 R106 1 1 C216 2 R139
8 7 6 5 5V to 3.3V TRANSLATION/ISOLATION 2.2K 1 C256
1 2 3 4
U13 8 3VDDCDA 8 3VDDCCL 8 CRT_HSYNC 8 CRT_VSYNC 8,24 3VFTSDA 8,24 3VFTSCL 5 CK_SMBDATA 5 CK_SMBCLK 3 4 7 8 11 14 17 18 21 22 1 13 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 BEA# BEB# VCC 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 GND 24 2 5 6 9 10 15 16 19 20 23 12
5VDDCDA 5VDDCCL 5VHSYNC 5VVSYNC
5VDDCDA
QSSDA QSSCL R141 1 0K
1 R142 2 0K 2
5VFTSDA 24 5VHSYNC 5VFTSCL 24 SMBDATA 10,11,12,13,30,36 SMBCLK 10,11,12,13,30,36
VGA QST3384
B
5VDDCCL
DO NOT STUFF C119 and C122

B
5VVSYNC 1 R143 2 2.2K 1 R140 2 2.2K 1 Do Not Populate
1 R85 0K C213 3.3PF 2
2 1 2 C188 3.3PF 1 C185 10PF 2 1 1 2 C180 10PF
DO NOT STUFF C100 and C102 L19 8 VID_BLUE 1 1 R109 75 1% 3.3PF 2

A
C250 3.3PF
C249 10PF
1 C219
2 10PF 2 1 C211 3.3PF 2

A
C208
REV.
VIDEO CONNECTOR
1.0
3-26-01
intel
5 4 3 2

R

1
25
of
40
Audio/Modem Riser
D D
VCC3SBY
R206 4.7K
VCC12 VCC5 VCC12VCC5 VCC3_3 J20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 AUDIO_MUTE# GND[0] (ISOLATED) MONO_OUT/PC_BEEP RESV[1] RESV[2] PRIMARY_DN# -12V GND[1] +12V GND[2] +5VD KEY KEY GND[3] RESV[3] RESV[4] +3.3VD GND[4] AC97_SDATA_OUT AC97_RESET# AC97_SDATA_IN3 GND[5] AC97_SDATA_IN2 GND[6] AC97_MSTRCLK AC'97 RISER AUDIO_PWRDWIN MONO_PHONE RESV[5] RESV[6] RESV[7] GND[7] +5VDUAL/5VSBY USB_OC GND[8] USB+ USBKEY KEY GND[9] S/P_DIF_IN GND[10] +3VDUAL/3VSBY GND[11] AC97_SYNC GND[12] AC97_SDATA_IN1 GND[13] AC97_SDATA_IN0 GND[14] AC97_BITCLK A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23
VCC3SBY
VCC3SBY
27,34 U10A 27 PRI_DWN_RST# 3 2 SN74LVC08A 7 14
AC97SPKR PWR_DWN_U PWR_DWN#
MONO_PHONE
27
AC97_OC#
19
AC'97 RISER
AMR_CONNECTOR
AC97_USB+ 19 AC97_USB- 19
JP17 2 13,27 AC_SDOUT 13 AC_RST#
AC_SYNC AC_SDIN1 AC_SDIN0 AC_BITCLK
13,27 13,36 13,27,36 13,27

B
REV.
AUDIO/MODEM RISER
1.0
3-26-01
intel
5 4 3 2

R

1
26
of
40
AC'97 Audio Codec

D
VCC3_3
VCC5_AUDIO
C358 0.1UF
C354
0.1UF 2
C308 0.1UF
D
VCC3_3 VCC12 VCC5_AUDIO VR7 1 VIN GND 1 C403 10UF 2 1 C360 0.1UF 2 1 L22 38 42 25 26 4 1 7 9 2 U24 40 44 43 1 DVSS1 DVDD1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 NC40 NC44 NC43
C
MC78M05CDT +5V 3 1 C406 10UF 2 1 2 C405 0.1UF 2
C359 0.1UF VCC3_3
R244 100K
28 LINE_IN_R 28 LINE_IN_L 28 MIC_IN 28 CD_R 28 CD_L 28 CD_REF 26 MONO_PHONE AC97SPKR 28 28 LNLVL_OUT_R LNLVL_OUT_L
26,34
12 24 23 21 22 20 18 19 C402 17 2 1 16 1UF-TANT 14 2 1 15 C412 MONO_PHONE_C 13 1UF-TANT MONO_OUT_C 37 36 35 41 39
PC_BEEP LINE_IN_R LINE_IN_L MIC1 MIC2 CD_R CD_L CD_GND VIDEO_R VIDEO_L AUX_L AUX_R PHONE MONO_OUT LINE_OUT_R LINE_OUT_L LNLVL_OUT_R LNLVL_OUT_L
RESET# SDATA_OUT SDATA_IN SYNC BIT_CLK CS1 CS0 CHAIN_CLK CHAIN_IN
11 5 8 10 6 46 45 48 47
ORU_DWN_RST#_R 1 R241 AC_SDATAOUT_R 0K 1 AC_SDATAIN_R1 R239 AC_SYNC_R 0K 1 AC_BITCLK_R 1 R243 0K
2 R240 2 0K 2 R242 2 0K 2
PRI_DWN_RST# 26 AC_SDOUT 13,26 AC_SDIN0 13,26,36 AC_SYNC 13,26 AC_BITCLK 13,26
AC'97 CODEC
EAPD
28
VREF VREFOUT
XTL_OUT XTL_IN
AFILT1 AFLIT2 FILT_L FILT_R RX3D CX3D
29 30 32 31 33 34
27 28
CX3D RX3D 1 C411 0.1UF
AC_XTAL_OUT
AFILT1 AFLIT2 FILT_L FILT_R
3 2
AD1819
JP18
B
1 2 28
R237 100K
AUD_VREFOUT AC_XTAL_IN Y3 1 2 1 C356 22PF 2
270PF-NPO
270PF-NPO
1UF-TANT
1UF-TANT
VREF
C410
C367 C404 0.1UF 10UF-TANT
0.1UF 2
C407 2 0.1UF
C408
C409
C307
C361
XTAL C355 22PF
REV.
AC'97 AUDIO CODEC
1.0
3-26-01
intel
5 4 3 2

R

1
27
of
40
Audio Connectors
D
STEREO HP/SPEAKER OUT C226 1 1 C237 R112 FB6 HP_OUTA_C1 HP_OUTA_FB 2 1 2 1 100UF 20 R118 FB7 HP_OUTB_FB 2HP_OUTB_C1 1 2 1 20 100UF J6-4 HP_OUTA_C2 HP30 HP29 HP_OUTB_C2 HP28 HP27 HP26 DB15 AUD_STK
2 2
27
MIC_IN
C217 MIC_IN_C 1 R110 1 2 1K 1UF-TANT 1 C222 0.01UF 2
FB4 2 MIC_IN_R 1 2
MIC_IN_FB M20 M19 M18 M17 M16 DB15 AUD_STK
R297
C36 100PF
20K 2
C218 100PF-NPO
U20 27 LNLVL_OUT_R C224 LNLVL_R_C R111 1 2 1 1UF-TANT 20K C225 LNLVL_L_C R113 2 1 1UF-TANT 20K 2 LNLVL_R_R BYPASS 1 2 3 4 OUTA INA BYPASS GND VDD OUTB INB SHUTDN 8 7 6 5
VCC5_AUDIO HP_OUTB LNLVL_L_R 1 R172 20K EAPD 2 1 C282 100PF 2

C
LINE_IN ANALOG INPUT 27 27 LINE_IN_R LINE_IN_L C221 LINE_IN_R_C 2 1UF-TANT C183 LINE_IN_L_C 1 2 1UF-TANT 1 FB5 1 FB3 1 LINE_IN_L_FB 2 2 LINE_IN_R_FB LI25 LI24 LI23 LI22 LI21 DB15 AUD_STK 1 C220 100PF-NPO 1 C182 100PF-NPO J6-3
27
LNLVL_OUT_L
C321 1UF
LM4880 27
C283 0.1UF
100UF-NPO
J6-2 1
100UF-NPO 2
HP_OUTA
27
AUD_VREFOUT
1 R108 2 2.2K
MICROPHONE INPUT
C235 C236
CD ANALOG INPUT C304 1 R234 2 4.7K JP27 1 2 3 4 CD_L_J CD_REF_J CD_R_J 1 R246 2 4.7K CD_R_C 1 R235 2 4.7K CD_REF_C 2 CD_L_C 2 1 1UF C309 1 1UF C357 2 1 1UF 1 1 R245 4.7K R236 4.7K 1 R238 4.7K
A
CD_L
27
CD_REF
27
CD_R
27

2 2 2
REV.
AUDIO CONNECTORS
1.0
3-26-01
intel
5 4 3 2

R

1
28
of
40
LAN
D
VCC5 VCC3SBY VCC3SBY 1 R149 4.7K 5% G13 K13 N8 P12 A11 LAN Decoupling 12,16,17 Distribute around Power Pins Close to 82559. VCC3SBY AD[31:0] AD[31:0] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C_BE#[3:0] C_BE#0 C_BE#1 C_BE#2 C_BE#3 FRAME# IRDY# TRDY# DEVSEL# STOP# PAR PIRQ#A PERR# SERR# AD20 PREQ#3 PGNT#3 PCIRST# PCLK_5 M4 L3 F3 C4 F2 F1 G3 H3 H1 J1 H2 J2 A2 A4 C3 J3 C2 G1 B9 A9 A10 C9 VIO G2 LAN_XTAL1 LAN_XTAL2 2 Y2 25MHZ N11 P11 U19 N7 M7 P6 P5 N5 M5 P4 N4 P3 N3 N2 M1 M2 M3 L1 L2 K1 E3 D1 D2 D3 C1 B1 B2 B4 A5 B5 B6 C6 C7 A8 B8 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# FRAME# IRDY# TRDY# DEVSEL# STOP# PAR INTA# PERR# SERR# IDSEL REQ# GNT# RST# CLK ISOLATE# ALTRST# SMBCLK SMBD G14 VSSPL[0] K12 VSSPL[1] P8 VSSPL[2] N12 VSSPL[3] VSSPP[0] VSSPP[1] VSSPP[2] VSSPP[3] VSSPP[4] VSSPP[5] VIO X1 X2 VSSPT LAN 82559 E12 G5 G6 H5 H6 H7 H8 J5 J6 J7 J8 J9 J10 J11 K4 K5 K6 K7 K8 K9 K10 K11 L4 L5 L9 L10 A3 A7 E1 K3 N6 P2
D
VCC3SBY
VCC3SBY
VCC3SBY
VCCPT
VCCPP[0] VCCPP[1] VCCPP[2] VCCPP[3] VCCPP[4] VCCPP[5]
VCCPL[0] VCCPL[1] VCCPL[2] VCCPL[3]
VCC[0] VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25]
C300 0.1UF
C303 0.1UF
C301 0.1UF
VCC3SBY
C299 0.1UF
C302 0.1UF
C298 0.1UF
VCC3SBY
C306 4.7UF
C305 4.7UF
82559
12,16,17 Place C305/C306 Close to Ball A10
C_BE#[3:0]
12,16,17,36 12,16,17,36 12,16,17,36 12,16,17,36 12,16,17,36 12,16,17 9,12,16,17,36 16,17 12,16,17,36 12,16,17 12,36 12,36 6,9,12,14,15,16,17,18,19,24 5 30
R204 1 100
2 R_LANIDS
LAN_ISOLATE# 30 LAN_RST# 30 L_SMBCLK 30 L_SMBD
C254 22PF
C251 22PF
C255 0.1UF
D4 D5 D6 D7 D8 D11 E4 E5 E6 E7 E8 E9 E10 E11 F4 F5 F6 F7 F8 F9 F10 F11 G7 G8 G9 G10 G11 H9 H10 H11 L6 L11
C10
B3 B7 E2 K2 M6 N1
VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31]
LILED ACTLED SPEEDLED TDP TDN RDP RDN SMBALRT# CSTSCHG PME# FLA0/PCIMODE# FLA1/AUXPWR FLA2 FLA3 FLA4 FLA5 FLA6 FLA7 FLA8/IOCHRDY FLA9/MRST FLA10/MRING# FLA11/MINT FLA12/MCNTSM# FLA13/EEDI FLA15/EEDO FLA15/EESK FLA16 FLD0 FLD1 FLD2 FLD3 FLD4 FLD5 FLD6 FLD7 EECS FLCS# FLOE# FLWE# CLKRUN# TEST TEXEC TCK TI TO RBIAS10 RBIAS100 VREF NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1
A12 C11 B11 C13 C14 E13 E14 B10 C5 A6 J13 J12 K14 L14 L13 L12 M14 M13 N14 P13 N13 M12 M11 P10 N10 M10 P9 F14 F13 F12 G12 H14 H13 H12 J14 P7 N9 M8 M9 C8 A13 D13 D14 D12 B12 B14 B13 C12 D10 G4 A14 J4 L7 P1 D9 L8 P14 H4 A1
LILED 30 ACTLED 30 SPEEDLED 30 TDP 30 TDN 30 RDP 30 RDN 30
PCI_PME# LANAPWR 1 R198 2 3K
9,12,16,17
VCC3SBY
U14 EEDI EEDO EESK 3 4 2 1 EEDI EEDO EESK EECS
VCC
LAN 93C46 DO NOT STUFF 619 FLD5_PD 1 R199 2 FLD6_PD 1 2 R200 619 EECS 62K LANCLKRUN 1 R203 2 LAN_TEST 1 R205 549 RBIAS10 1 R201 2 RBIAS100 1 R202 619 5
2 4.7K
B
GND
NC2 NC1
7 6
REV.
LAN
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
29
of
40
LAN
VCC3SBY VCC3SBY
D
R146 330
R148 330
29
TDP 1 R294 100 J2 LAN RJMAG/USB 13 14 16 17 121 18 15 20 19 TD+ TDRD+ RDNC RDC P20 P19 1 2 3 4 10 9 12 11 LI_CR
330 330
ACT_CR 2
JP18_PU
29 29
TDN RDP
330 LILED 29
R295
SPEEDLED
29
JP14
JP16
JP15
29
RDN
Place R294 and R295 near 82559

C
CASE0 CASE1 CASE2 CASE3 CASE4 CASE5 CASE6 CASE7
NO POP R295
29 29 29
LILED
C
21 22 23 24 25 26 27 28
ACTLED
SPEEDLED
NOTE: Chassis Ground, use plane for this signal
VCC3SBY
R267 4.7K JP22 1 2 JP8_SMBC 3 1 R266 2 0K L_SMBCLK 29

B
10,11,12,13,25,36 13
B
SMBCLK GPIO27
13 13,31,35
SUS_STAT# PWROK
1 R256 2 0K 1 R254 2 0K DO NOT STUFF R198
LAN_ISOLATE#
29 VCC3SBY
R268 4.7K
JP19 13,35 RSMRST# 1 2 3 13 NOTE: This circuit is for debug purpose only. GPIO28 3 LAN_RST# 29 10,11,12,13,25,36 SMBDATA JP23 1 2 JP9_SMBD 1 R265 2 0K L_SMBD 29 2
JP23_PU
JP7_PU
1 R23
ACTLED
29
R138
R147
REV.
LAN
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
30
of
40
Voltage Regulators
VCC 3.3V Standby VOLTAGE SWITCH
1 This generates 3.3V Standby Power which is on in S0, S1, S3, S4 & S5. It passes 3.3V from the ATX supply in S0/S1, and 3.3VSB (generated by VR2 below) in S3/S4/S5.
D
VCC3_3
V3SB CR1
VCC3SBY
VCC5
VCC5DUAL
1 C56 47UF 2 1 C57 47UF 2 S
2 1 R176 2 0K NPOP D 1 C63 1200UF 2 1
NDS356AP S Q1 G D
VCC 3.3VSB REGULATOR

VCC5SBY V3SB
VCC12 VCC5SBY
C65 1200UF
DO NOT POPULATE
R31 S 4.7K
NDS356AP S G Q2 D D VR2 3 G 1 C62 22UF-TANT 2 IN LT1117-3_3 OUT 2 1 2 C61 100UF-TANT
VCC5SBY
VCC3SBY 10K 2
SN74LVC07A HAS 5V INPUT AND OUTPUT TOLERANCE
R92
PLANE_CTL0 2
PLANE_CTL1
U9A 13,35 13,30,35

C
SLP_S3# PWROK
1 3 2 74LS132 7 7 PCTL_IN 1
U8A 2
4 3 2 1 SI4410DY Q5 4 3 2 1 SI4410DY VCC5 VCC5SBY CR2 1 2 1N5822 NDS356AP S Q4 S G D D
5 6 7 8 VCC5DUAL
14
14
MMBT3904LT1
1 R89
SN74LVC07A
2 V_GQ6 0K Q3
Q7
GND
VCC 1.8 VOLTAGE REGULATOR

5 6 7 8 1 R175 VCC3_3 VR3 2 3 R175_D 100UF-TANT 2 1 1 C98 C103 220 1% 1.0UF 2 2 VOUT VIN ADJ 1 VR1_ADJ 1 2 2 1 0K R32 470 1%
VCC1_8
C
VCC5
2 PLACE C99 AT THE REGULATOR
BAT54C VCC5 2 VR1

B
VCC5 R314 20k
VTT 1.5V VOLTAGE REGULATOR
D1
47UF
47UF
U72A 2 1 V1_8SB LM393A S VCC5 U72B 8 LM393A 7 2 VCC5 1 Q6
VCC3_3
VTT
C64 1200UF
DO NOT POPULATE
3 C14 10uF 2 1
VOUT VIN
2 R315 49.9 1% 1 C16 22uF-Tant
3 2
+ 4
C105 1200UF
NDS356AP S G D D
VCC 2.5 VOLTAGE REGULATOR

VCC5
C110
C104
LT1587ADJ
R33
C99 100UF-TANT
VCC2_5
R316 1k 4 3 2 1
ADJ 1 LT1587-ADJ C437 0.1UF 1
VR5 5 6 7 8 3 1 C111 0.1UF VOUT VIN ADJ 1 VR5_ADJ 2
U2
R83 243 1%
4,5,7
Q21 MOSFET N TUAL5
R318 732 1% 2
C438 0.1UF 2.0 ms delay nominal
1 243 1% 2
R317 10 1%
V1_8SB
C162 22UF-TANT
SI4410DY VCC12 1
LT1587ADJ 2
R82
R320 1k 1% MOSFET N Q22 2
R319 2.2k
VTTPW RGD12 VTT 1 R321 1k
5 4 3 2 1
U3 5 6 7 8 SI4410DY
REV.
VTTPW RGD5#
33
VOLTAGE REGULATORS
VTTPWRGD 4
1.0
3-26-01
Q23 MOSFET N
intel
2

R

1
31
of
40
AGP, VCMOS Voltage Regulator

D
VCC3_3 VCC12
C322 47UF
D
C315 10UF
VDDQ C317 1 2 220UF
NO STUFF R210
R210 VR6 2 C316 1UF 2 1 R121 1 C267 10PF 2 1 VDDQ_COMP 3 R162 LT1575 3 1 2 3 4 SHDN VIN GND FB IPOS INEG GATE COMP 8 7 6 5 R155 VDDQ_G 1 2 VDDQ_G2 1 5.1-5% 1
VCC3_3
0K 2 1
Q13 IRL2203NS
VCC1_8
R209 1K
R211 1K
2.2K 2
VR_SHUTDOWN
C268 C268_R156 1 R156 2 1 2 7.5K-1% 0.001UF
C271 1UF-X7R
C269 1UF-X7R
C270 1UF-X7R
C242 1UF-X7R
C278
C
1UF-X7R 2
301-1% 2
9 VR_SDB Q14
TYPEDET# 1 R208 2 R208_Q15 10K Q15 MMBT3904LT1
VDDQ_FB 1 R161 1.21K-1%
MMBT3904LT1 1 R174 1K 2
Route VR6 GND to VDDQ output caps and then via to ground.
VCC3_3 Q32 3 + C484 10UF 49.9 1% Q32_Feedback R355 10 1% ADJ VIN VOUT LT1117ADJ 2
VCMOS
+ C483 R354 10UF
REV.
AGP, VCMOS VOLTAGE REGULATOR
1.0
3-26-01
intel
5 4 3 2

R

1
32
of
40
Processor Voltage Regulator

VCC5 1 1 1
D
L9 2 1 1 1 1 1 1.7uH C78 3300uF 2 2 C115 C439 C440 C76 1 C441

D
C117 10uF
C66 0.1UF
VCC12 2 2
3300uF 0.1UF 0.1UF 4.7uF 4.7uF 2 2 2 2
1 R37 2 10
VCC3_3 1 C27 1.0UF 2 1 C456 1.0UF 2 2 R343 1k 1 VRM_PWRGD 35
C442
C
1 2
2 2 VCCVID R325 220 1
U73 3 VID[4:0] VID3 VID2 VID1 VID0 VID4 31 VCC5 1 1 R332 38k 1% 2 1 R333 0 C448 0.001uF 2 1 1 2 2 R334 80K 1% VTTPW RGD5# 16 1 2 3 4 5 8 7 13 12 20 C446 100pF 2 VCC VID3 VID2 VID1 VID0 VID25 SD REF COMP CT GND ADP3170 CS+ CSPGND DRVH DRVL FB PWRGD LRDRV LRFB 11 10 19 18 17 9 6 14 15 1 Q24 MOSFET N L13 1 2 1.2uH R330 2.2 11 2
0.001uF R324 220 R326 4.7 1
2 2
R328 ?? R329 ??
1 1 1 1 2 C443 820uF C444 820uF 1 1 2 2 C450 820uF C451 1000uF

B
R331 2.2
C447 4700pF 1 C449 820uF 1
VCC3SBY 2 1 0.004 R335 C453 0.1uF R336 22 1% V1_8SB 1 2 1
R337 28 1%
Q25 MOSFET N
C445 1000uF
Stuff only one
Refer to VR Supplier for Layout Guidelines
REV.
VRM 8.5
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
33
of
40
System
D
VCC3_3 VCC3SBY NO STUFF. FOR TEST ONLY
VCC5
R280 1M
1 C264 C399 + 0.1UF 2 10UF 16V 1
R272 100K
13
PWRBTN# 1 VCC5 1 R124 10K VCC5 1 R99 10K VCC3_3 1 R283 10K VCC3_3
1 R279 2 0K C396 1.0UF 2
NO STUFF. FOR TEST ONLY
SW2 15 15 IRRX IRTX 1 R269 1 R270 2 4.7K PBTN_IN 1 R281 2 470 2 R_IRTX 82
J18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
INFRARED
VCC3_3 PBSWITCH
POWER SW.
14 U11B 3 4 SN74LVC07A 1 7 14 18 18
C
IDEACTP# IDEACTS#
IDE_ACTIVE FP_PD U11A 2 SN74LVC07A 1 R282 2 220 PWRLED VCC5
H.D. LED
POWER LED
15
KEYLOCK#
KEY LOCK SPEAKER VCC5
26,27 VCC3_3 13
AC97SPKR JP28 1 ICH_SPKR 2 3 SPKR 1 R291 2 2.2K SPKR_Q1G
SPKR_IN
1 R289 2 68 1 R290 2 68
R_SPKRIN
FNT_PNL_CONN Q17 2N3904 1 1 C426 0.1UF C400 470PF 2 1 C247
SP1 470PF SPKR_NEG SPEAKER 2 2
SPEAKER CIRCUIT
RP62 4.7K
5 6 7 8
FAN HEADERS
B
VCC3SBY VCC3SBY VCC3SBY
VCC3SBY
B
4 3 2 1
R96 330
R97 330
VCC3SBY
VCC12
VCC12
14
14 U8B LED 4 GP23LED CRb4 7 GP26LED 6
C392 0.1UF J4 1 2 3
R275 330
C394 0.1UF 13 V3SBLED 2 GPIO23_FPLED 1 R90 4.7K
CRa4
U8C 5 SN74LVC07A GPIO26_FPLED 13
J27 1 2 3 15 TACH1 15
SN74LVC07A 7
TACH2 VCC12 VCC12
On-Board LED indicates th Standby Well is on to prevent Hot-Swapping Memory
LED 2
CR7 LED 1 C393 0.1UF 2 1 2 3 15 PWM1 15 J26 1 2 3 1 C391 0.1UF 2
J28
REV.
PWM2
SYSTEM, PART 1
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
34
of
40
System
Power Connector and Reset Control
VCC12
D
ITP RESET CIRCUIT - FOR DEBUG ONLY VCC3SBY VCC3SBY VCC5SBY 1 R123 243 VCC5SBY VCC3_3 VCC5 APOK_ST 5 SN74LVC08A 7 0K VCC5SBY 2 14 SN74LVC06A has 5V input tolerance 1 7 2 7 VCC_51 VCC12R302 R 4 DBRESET# 2 4 6 14 14 DBRST 1 R94 VCC3SBY 1 R62 330 U7A 2 1 SN74LVC06A 7 DBRPOK 3_3V1 3_3V2 GND3 5V4 GND5 5V6 GND7 PW_OK 5VB 12V 1 2 3 4 5 6 7 8 9 10 1 R95 2 0K 1 R91 2 0K DBRPOK_DLY 1 C148 1.0UF 2 ATX_PWOK 3 4 6 5 74LS132 7 14 4.7K U7B 4 1 SN74LVC06A 7 R87 20k 33 SW 1 VRM_PWRGD 1k Ohm Pull-up to 3.3V is on VRM Sheet 2
C
14
U10B
VCC2_5
U12A 1 2 74LVC14A ST23 3
U12B 4
VCC3SBY
74LVC14A
PWRGOOD 4 R344 1.8k 2 1
U9B
14
13,31
SLP_S3# 5
U7C 6 SN74LVC06A 7 5VPSON
SN74LVC06A has 5V input tolerance
11 12 13 14 15 16 17 18 19 20
3_3V11 -12V GND13 PS_ON GND15 GND16 GND17 -5V 5V19 5V20
14
J5
VCC3SBY PWROK# VCC3SBY R88
DO NOT POPULATE R95
ATX
PWROK
13,30,31
RST_PD PBSWITCH 1 2
1 R81
C160 0.01UF
JP13 Place JP13 Near Front Panel Header (J20)
2 22
RESUME RESET CIRCUITRY

C161 + 10UF VCC3SBY VCC3SBY
B
Schmitt Trigger Logic using a 22msec delay
VCC3SBY
14
U12C 13,31 SLP_S3# VCC3SBY 1.0UF 14 2 7 7 R125 1 1 2 8.2K 1 R127 2 22K V3RSMRST C248 5 6 74LVC14A ST69 9
14
U12D 8 74LVC14A 1 R128 8.2k 2 RSMRST# 13,30
U10C DBRPOK 9 10
8 SN74LVC08A
A
CK_PWRD
1 R126
2 0K
CK_PWRDN#
Do Not Stuff R126 - For Test Only: If R125 is Populated, R126 Must Be DE-Populated.
REV.
SYSTEM, PART 2
1.0
Last Revision Date:
intel
5 4 3 2

R
3-26-01
Sheet:
1
35
of
40
VCC5 RP67 17 PERR#_PU 12,16,17,29 SERR# 12,16,17 PLOCK# 12,16,17,29 STOP# 12,16,17,29 DEVSEL# 12,16,17,29 TRDY# 12,16,17,29 IRDY# 12,16,17,29 FRAME# 1 2 3 4 5 6 7 8 2.7K RP66 12,16,17 12,16,17 9,12,16,17 9,12,16,17,29 12,29 12,17 12,16 12 PIRQ#D PIRQ#C PIRQ#B PIRQ#A PREQ#3 PREQ#2 PREQ#1 PREQ#0 1 2 3 4 5 6 7 8 2.7K VCC3_3 RP53 12 12,16 12,17 12,29 PGNT#0 PGNT#1 PGNT#2 PGNT#3 1 2 3 4 8.2K
C
16 15 14 13 12 11 10 9 16 VCC5 16 16 15 14 13 12 11 10 9
PCI Bus
VCC5 RP57 SDONEP2 SBOP2 1 2 3 4 5.6K RP58 17 SDONEP3 17 SBOP3 16,17 PTDI 16,17 PTMS 1 2 3 4 5.6K VCC5 RP59 PU3_ACK64# PU2_ACK64# PU3_REQ64# PU2_REQ64# 1 2 3 4 2.7K 8 7 6 5 8 7 6 5 10,11,12,13,25,30 10,11,12,13,25,30 SMBDATA SMBCLK 8 7 6 5 VCC5 13 SMBALERT# 13 LDRQ#1 13 GPIO12 13 GPIO13
ICH
VCC3SBY RP61 1 2 3 4 4.7K RP60 1 2 3 4 4.7K VCC3_3 RP56 12 REQ#B/GPIO1 1 2 3 4 8.2K 8 7 6 5 8 7 6 5 4,12 APICD1 8 7 6 5
CPU
4,12 APICD0 1 R13 150 1 R11 150 4,12 FERR# 1 R14 2 150 2 2
VCMOS
8 7 6 5
17 16 17 16
12 GNT#B/GPIO17 12,15,17 SERIRQ
VCC3SBY 12,17 PCPCI_REQ#A 12,13 THERM# 12,15 RCIN# 12,15 A20GATE U12E 11 VCC3_3 VCC3SBY 7 10 74LVC14A 13,15 LPC_SMI# 13,17 GPIO7 1 2 3 4 1 2 3 4
RP51 8 7 6 5 8.2K RP54 8 7 6 5 4 8.2K For Future Compatability Upgrade RTTCTRL SLEWCTRL R28 110
B
14
Unused Gates
1 1 2
R12 56
14
14
U11D 9 8 SN74LVC07A
B
U8D 9 8 SN74LVC07A 7 7 13
14 U12F 12 74LVC14A VCC5SBY 13 GPIO22 13,15 LPC_PME# 13,17 GPIO21 1 2 3 4
RP55 8 7 6 5 8.2K RP52 13 INTRUDER# IRQ14 IRQ15 VCCRTC VCC5
VCC3SBY 14 14
11
11
14
U11E 10 SN74LVC07A 7
U8E 10 SN74LVC07A 11 7
U9C 9 U7E 10 SN74LVC06A 10 74LS132 8
12,18 12,18
1 2 3 4 8.2K
8 7 6 5
14
13,26,27 13,26
AC_SDIN0 AC_SDIN1
1 R263 2 10K 1 R262 2 10K
14
U11F 13 12 SN74LVC07A 7 7
A
14
U8F 13 12 14 SN74LVC07A 13 U9D U7F 12 13 SN74LVC06A 74LS132 7 7 12 11 14
REV.
PULLUP/PULLDOWN RESISTORS
1.0
3-26-01
intel
5 4 3 2

R

1
36
of
40
370-pin Socket Decoupling

D D
VCCVID DECOUPLING
Place in 370 PGA Socket Cavity VCCVID
C82 4.7UF
C88 4.7UF
C44 4.7UF
C39 4.7UF
C35 4.7UF
C37 4.7UF
C89 4.7UF
C55 4.7UF
C86 4.7UF
C48 4.7UF
C91 4.7UF
C49 4.7UF
C50 4.7UF
C51 4.7UF
C52 4.7UF
C53 4.7UF
VTT DECOUPLING
B B
0603 Package placed within 200mils of VTT Termination R-packs. One Capacitor for every 2 R-packs
VTT
C6 + 4.7 uF
C458 + 4.7 uF
C93 0.1UF
C459 0.1UF
C460 0.1UF
C461 0.1UF
C462 0.1UF
C463 0.1UF
C464 0.1UF
C465 0.1UF
C466 0.1UF
C467 0.1UF
C468 0.1UF
C469 0.1UF
C470 0.1UF
C471 0.1UF
1 2
C472 0.1UF
REV.
DRAM, ICH, & GMCH DECOUPLING
1.0
3-26-01
intel
5 4 3 2

R

1
37
of
40
GMCH DECOUPLING
DISPLAY CACHE DECOUPLING
ICH DECOUPLING
ICH 3.3V Plane Decoupling: Place 1 .uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit. 1 1 1 1 1 1 1 1 1 Distribute near the 1.8V power pins of the ICH VCC1_8 Distribute near the VCCSUS power pins of the ICH VCC3SBY
VCC1_8
VDDQ
Display Cache: Near the power pins.
VCC3_3
C192 + C193 C131 C197 C127 C428 C135 1 1 1 1 1 1 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
1 2
C383 C332 C290 C293 C339 C329 C327 C328 C326 C324 C325 C338 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF
C287 C292 C286 C477 0.1UF 0.1UF 0.1UF 0.1UF
4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 2 2 2 2 2 2 2 2 2 2 2
2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 2 2 2 2 2
GMCH Core Plane Decoupling: Place 1 .1uF/.01uF pair in each corner and 2 on opposite sides close to component if they fit. VCC1_8
SYSTEM MEMORY DECOUPLING

VCC3SBY DIMM Decoupling: Distribute near DIMM0 Power pins. C70 C69 C54 1 C97 +
C223 C194 C429 C227 C240 C430 C191 C132 0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF 2 2 2 2 2 2 2
C141 C202 C204 C96 2 2 2
C246 C58 2
4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 2 2 2 2 2
C
BULK POWER DECOUPLING

VCC12VDDQ GMCH 3.3V IO Decoupling: Place near GMCH Display Cache Quadrant. VCC3_3 VCC5 VCC_5VCC12
C231 C234 C229 C228 C232 C230 C432 C431 C433 0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF
C24 +
C59
C23
C421 + C379 1 22UF 0.1UF
C378 0.1UF
C60 22UF
C22
C21
C241 + C365 C311 C349 C19 1 1 1 1 22UF 0.1UF 0.1UF 0.1UF 0.1UF
C366 C362 C413 C310 C364 0.1UF 0.1UF 0.1UF 0.1UF 22UF 2 2 2 2
22UF 0.1UF 0.1UF 2 2 2
0.1UF 0.1UF 2 2
.1F on back side. Do not populate. VCC3SBY Distribute as close as possible to GMCH System Memory Quadrant. VCC3SBY DIMM1 Decoupling: Distribute near DIMM1 Power Pins. C28 C31 C95 C142 C203 1 VCC3_3
3 VOLT DECOUPLING
C42
C34
C238 C288 + + C275 C276 C243 C277 C273 C272 C274 C281
1 + +
C382 C473 C474 C475 C476 + C381
C137 C139 C199 C136 C198 C133 C138 C200 C201 C435 C434 C427 0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF0.01UF
C20 +
1 2
C375 C373 C376 C416 C417 C374 C371 C370 C420 C313 C418 C314 C318 C319 C419 C377 C323 C372 C369 C320 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 01.UF 0.1UF 0.1UF 0.1UF 2 2 2 2 2 2 2 2 2 2
.01F on back side. Do not populate.
C169 C245 C252 C32
REV.
VRM DECOUPLING
1.0
3-26-01
intel
5 4 3 2

R

1
38
of
40
Hub Interface Connector

D D
J29 5 HUBPRB_3V66 8,12 HL[10:0] HL0 HL1

C
PROBE_CONNECTOR HUBREF 7,8,12
HL2 HL3 HL9 8,12 8,12 HLSTB HLSTB# HL10 HL8 HL4 HL5 HL6 HL7
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 P08-050-SL-A-G
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
VCC1_8
REV.
HUB INTERFACE CONNECTOR
1.0
3-26-01
intel
5 4 3 2

R

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39
of
40
V1_8SB R349 1K
VCC1_8 R350 1K
V3SB R351 22K
PWRBTN# 13,34
C
R352
1K Q30 NPN
R353 4 THERMTRIP# 1.6K Q31 NPN

A
REV.
A
THERMTRIP
1.0
Last Revision Date:
intel
5 4 3

R

2
3-26-01
Sheet:
40
of
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29834901

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Intel 815 Chipset Platform

Document Number: 298349-001

Intel 815 Chipset Platform Design Guide

System Bus Design Guidelines .........................................................................................43 5.1

Intel 815 Chipset Platform Design Guide

5.4 5.5 5.6 5.7 5.8 5.9

5.12 5.13 6 6.1 6.2

System Memory Design Guidelines...................................................................................69

6.4 6.5 7 7.1

AGP/Display Cache Design Guidelines.............................................................................79

Intel 815 Chipset Platform Design Guide

Integrated Graphics Display Output.................................................................................101

Intel 815 Chipset Platform Design Guide

10.4 10.5 10.6 10.7 10.8

Clocking ...........................................................................................................................131 11.1 11.2 11.3 11.4 11.5 11.6 11.7

Power Delivery.................................................................................................................141 12.1 12.2 12.3 12.4

System Design Checklist.................................................................................................155 13.1 13.2

Intel 815 Chipset Platform Design Guide

13.5 13.6 13.7 13.8 13.9 13.10 14

Third-Party Vendor Information .......................................................................................171

Appendix A: Customer Reference Board (CRB) .....................................................................................173

Intel 815 Chipset Platform Design Guide

Intel 815 Chipset Platform Design Guide

Intel 815 Chipset Platform Design Guide

Intel 815 Chipset Platform Design Guide

Intel 815 Chipset Platform Design Guide

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Intel 815 Chipset Platform Design Guide

Intel 815 Chipset Platform Design Guide

Network Length Pad

Intel 815 Chipset Platform Design Guide

Stub System Bus Trunk

Undershoot Universal Socket 370

Intel 815 Chipset Platform Design Guide

Intel 815 Chipset Platform Design Guide

Figure 1. System Block Diagram

100/133 MHz SDRAM

PCI bus PCI slots

Intel 815 Chipset Platform Design Guide

Figure 2. GMCH Block Diagram

System memory I/F

SDRAM 100/133 MHz, 64 bit

Local memory I/F

Graphics Memory Controller Hub (GMCH)

Intel 815 Chipset Platform Design Guide

Intel 815 Chipset Platform Design Guide

Intel 82801AA I/O Controller Hub (ICH)

Firmware Hub (FWH)

Intel 815 Chipset Platform Design Guide

Accelerated Hub Architecture Interface

Internet Streaming SIMD Extensions

Intel 815 Chipset Platform Design Guide

Processor Present Indicator

Intel 815 Chipset Platform Design Guide

Low-Pin-Count (LPC) Interface

Intel 815 Chipset Platform Design Guide

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Intel 815 Chipset Platform Design Guide

General Design Considerations

General Design Considerations

Nominal Board Stackup

Figure 3. Board Construction Example for 60 Nominal Stackup