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The Facts
MicroBlaze
Soft-core Processor Highly Congurable 32-bit Architecture Master Component for Creating a MicroController
Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline
Overview
The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx eld programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core.
Instruction-side bus interface Data-side bus interface
DOPB
Organization
ALU
D-Cache
IOPB
I-Cache
Program Counter
IXCL_M IXCL_S
DXCL_M DXCL_S
Bus IF
ILMB
Bus IF
DLMB
Features
The MicroBlaze embedded soft core is highly congurable, allowing users to select a specic set of features required by their design. The processors xed feature set includes
Major Components
Harvard Architecture Bus Interfaces Registers General Purpose Special Function ALU Instruction Processing
Optional MicroBlaze feature
IOPB
R
ALU
D-Cache
I-Cache
Program Counter
IXCL_M IXCL_S
DXCL_M DXCL_S
Bus IF
ILMB
Bus IF
DLMB
Table 2-1:
Summary of MicroBlaze Core I/O Interface DOPB DOPB DOPB DOPB DOPB DOPB I/O O O O O O O Description Data interface OPB address bus Data interface OPB byte enables Data interface OPB bus lock Data interface OPB write data bus Data interface OPB bus request Data interface OPB read, not write
Harvard Architecture
Princeton Architecture
Separate (Harvard) Unied (Princeton) Only by load/store instructions (RISC) Use load/store instructions (memory-mapped) Any instruction can read/write memory (CISC) Special I/O instructions
See Harvard Architecture See RISC and CISC See Memory Mapped I/O
16-bit Byte-addressable
Overview
The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx eld programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core.
ALU
D-Cache I-Cache
Program Counter
IXCL_M IXCL_S
DXCL_M DXCL_S
Bus IF
ILMB
Bus IF
DLMB
Which of the preceding processor Figure 1-1: MicroBlaze Core Block Diagram attributes may be inferred from this block Features The MicroBlaze embedded soft core is highly congurable, allowing users to select a diagram? 10 specic set of features required by their design. The processors xed feature set includes
croBlaze Architecture
iew
The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx eld programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core.
Instruction-side bus interface Data-side bus interface
DOPB
IOPB
Program Counter
_M
DXCL_M DXCL_S
Harvard Architecture RISC Load/Store Architecture 3 or 5 Stage Pipeline (currently 5) 32-bit Datapaths Byte Addressable Big Endian Two Addressing Modes 2 or 3 Operand Instructions
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I-Cache
_S
Bus IF
ILMB
Bus IF
DLMB
Features
The MicroBlaze embedded soft core is highly congurable, allowing users to select a specic set of features required by their design. The processors xed feature set includes the following: Thirty-two 32-bit general purpose registers 32-bit address bus Single issue pipeline 32-bit instruction word with three operands and two addressing modes
ANSWERS
www.xilinx.com 1-800-255-7778
(4 bytes)
Example: 0x12345678 Viewed as a 32-bit word at address n 0x12 0x34 0x56 0x78
Big-endian
(2 bytes)
Big-endian
(1 byte)
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Type B
1 source register 1 immediate operand
16-bit or 32-bit
constant
1 destination register
Type A Instructions
Opcode Bit: 0 6 Destination reg Source reg A 11 16 Example: Add contents of r24 and r27, and store the sum in register r25 Assembly language: add r25, r24, r27 Machine code: 000000 11001 11000 11011 0 0 0 0 0 0 0 0 0 0 0 Source reg B 21 0 0 0 0 0 0 0 0 0 0 0 31
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6-bit opcode => 64 instructions How are the other 60 instructions distinguished?
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Occurrence
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10
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Questions
1. Why is it important for an embedded processor to deal efciently with constants? 2. How should we optimize using 0? 3. Should we make a special case of n-bit constants, where n < 32? 4. What if we need a 32-bit constant?
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