Cost Effective Reconfigurable Logic

Cost Effective Reconfigurable Logic Final Project Report Presented to The Faculty of the Department of General Engineering San
Jose State University April 23, 2010 By Piyush Patel (005810493) Ipsita Praharaj (003819596) Nagendra Donepudi (005783986)
Committee Members Industrial Advisor Dr. Love Singhal Sr. Member of Technical Staff, Synopsys Inc.
University Reader Professor Morris Jones Electrical Engineering Department
2010 Piyush Patel Ipsita Praharaj Nagendra Donepudi ALL RIGHTS RESERVED
APPROVED FOR THE DEPARTMENT OF GENERAL ENGINEERING
_________________________________________________________ Professor Morris Jones, Department of Electrical Engineering San Jose State University
____________________________________________________________ Dr. Love Singhal Senior Member of Technical Staff, Synopsys, Inc. Mountain View, CA
____________________________________________________________ Dr. Ali Zargar. Graduate Coordinator, Department of Aviation and Technology San Jose State University
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ABSTRACT In the current digital era, the demand for the new electronic device is increasing in a high pace while the designers and manufacturers are trying their best to provide cheaper solutions in order to satisfy the consumers requirement. The main goal of this project is to develop a methodology to replace the high cost FPGA chip by cheaper microcontroller circuit to make it cost effective. The project's objective is to identify the real time low power applications which employs FPGA chip for its operation to replace it by cheaper microcontroller by achieving a frequency of 1 GHz. This report basically explains, how to design the workflow of converting verilog language to 'C' programming language and then design the microcontroller as per the specification in order to achieve the goal. The methodology and the technical specifications are included in the report. Market research, business case analysis, and economic analysis provided very useful feedback about the current market and helped to conclude that this project has plenty of business potential and capability of being milestone in embedded world.
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ACKNOWLEDGEMENT We would like to express our sincere gratitude to Professor. Morris Jones, Part-Time Assistant Professor, Dept. of Electrical Engineering, San Jose State University for his guidance and support for this project.
We would like to sincerely thank Dr. Love Singhal, Senior Member of Technical Staff, Synopsys Inc. for his guidance for this project.
We would like to express our deep gratitude to Dr. Ali Zargar, Graduate Coordinator, Dept. of Aviation and Technology, San Jose State University for giving us an opportunity to enroll in ENGR 281 course under his guidance and recommendations.
Piyush Patel Ipsita Praharaj Nagendra Donepudi
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Table of Contents 1 2 Introduction ............................................................................................................................. 1 Background ............................................................................................................................. 2 2.1 Microcontrollers ............................................................................................................... 3 2.2 FPGA ................................................................................................................................ 5 3 Experimental Procedure .......................................................................................................... 8 4 Resources Utilized .................................................................................................................. 8 4.1 Software requirement ....................................................................................................... 9 4.2 Hardware requirement (If we implement practical design) ............................................. 9 5 Applications ............................................................................................................................ 9 6 Preliminary Literature Review ................................................................................................ 9 6.1 Literature Review of Microcontroller ............................................................................ 10 6.2 Literature Review of FPGA ........................................................................................... 11 7 Technical details of the Project ............................................................................................. 13 7.1 System Design methodology .......................................................................................... 13 7.1.1 Fist phase :( Verilog to 'C' language Conversation process) .................................. 14 7.1.2 ANTLR Workflow .................................................................................................. 15 7.1.3 Architecture of ANTLR compiler ........................................................................... 17 7.2 Second phase: Design and Implementation of Microcontroller ..................................... 21 7.2.1 Microcontroller design flow ................................................................................... 21 7.2.2 System Architecture ................................................................................................ 23 8 Economic Justification .......................................................................................................... 29 8.1 Executive summary ........................................................................................................ 29 8.2 Problem Statement ......................................................................................................... 29 8.3 Solution and Value proposition ...................................................................................... 30 8.4 Market size ..................................................................................................................... 30 8.5 Competitors .................................................................................................................... 31 8.6 Customers ....................................................................................................................... 32 8.7 Cost summary ................................................................................................................. 33 8.7.1 Fixed cost ................................................................................................................ 33 8.7.2 Employee Wages .................................................................................................... 34 8.7.3 Variable cost ........................................................................................................... 34 8.8 Price Point ...................................................................................................................... 35 8.9 SWOT Assessment ......................................................................................................... 36 8.10 Investment Capital Requirement ................................................................................ 37 8.11 Personnel .................................................................................................................... 37 8.12 Business and Revenue Model ..................................................................................... 38 8.13 Strategic Alliance/Partners ......................................................................................... 38 8.14 Profit/Loss .................................................................................................................. 39 8.15 Breakeven Analysis .................................................................................................... 40 8.16 Return on Investment (ROI) ....................................................................................... 41 8.17 Exit Strategy ............................................................................................................... 42
9 10 11 12 13 14 15 16 17 18
Project Schedule.................................................................................................................... 42 Conclusion ............................................................................................................................ 42 Future Work .......................................................................................................................... 43 List Of References: ............................................................................................................... 44 APPENDIX A ....................................................................................................................... 49 APPENDIX B ....................................................................................................................... 50 APPENDIX C ....................................................................................................................... 53 APPENDIX D ....................................................................................................................... 73 APPENDIX E ....................................................................................................................... 76 APPENDIX F........................................................................................................................ 91
List of Figures Figure 1: Microcontroller in FPGA graph ...................................................................................... 2 Figure 2: Basic Architecture of Microcontroller ............................................................................ 4 Figure 3: (a) Basic architecture of FPGA (b) Basic architecture of logic block............................. 6 Figure 4: Evolution of FPGA Architectures ................................................................................... 7 Figure 5: Technology vs. Design cost........................................................................................... 12 Figure 6: High-level process flow of the project design ............................................................... 14 Figure 7: Overall translation data ................................................................................................. 16 Figure 8: Architecture of ANTLR compiler module .................................................................... 18 Figure 9: AST generated by ANTLR............................................................................................ 19 Figure 10: Close up view of AST ................................................................................................. 20 Figure 11: Microcontroller design flow ........................................................................................ 22 Figure 12: Microcontroller Architecture ....................................................................................... 24 Figure 13: Decision box block diagram ........................................................................................ 28 Figure 14: Market Scale forecast for Microcontrollers................................................................. 30 Figure 15: Worldwide Processor Market In 2010......................................................................... 31 Figure 16: Profit/Loss graph ......................................................................................................... 40 Figure 17: Break Even Analysis Graph ........................................................................................ 41 Figure 18: Project Schedule .......................................................................................................... 42
List of Tables Table 1: Instruction Set ................................................................................................................. 25 Table 2: Mode Conditions ............................................................................................................ 25 Table 3: Opcodes .......................................................................................................................... 26 Table 4: Fixed Cost ....................................................................................................................... 33 Table 5: Employee Wages ............................................................................................................ 34 Table 6: Variable Cost .................................................................................................................. 34 Table 7: Estimated cost for 100K units......................................................................................... 35 Table 8: SWOT assessment .......................................................................................................... 36 Table 9: Human Resources ........................................................................................................... 38 Table 10: Profit/Loss..................................................................................................................... 39
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Introduction
In todays technology world, microcontroller is playing an important role which is the most used component in all kinds of digital electronic component. Its applications vary from simple household electronics to complex aerospace systems. Currently, hardware engineers and chip designers are working hard to improve the key areas of microcontroller like functionality, performance, clock speed, shorter time to market, and reduced Bill of Material (BOM). The single chip of microcontroller used for storing and processing of the data and events in the logic block of an integrated circuit. The highly integrated processor can be used as stand alone device. The compact size, low cost, and simplicity of the microcontroller circuit make it extremely famous in the digital market and a significant number of microcontroller applications are designed and developed to satisfy the consumer requirements. The objective of this project is to develop a solution to replicate the operations done by high speed Field Programmable Gate Array (FPGA) chip by low power microcontroller circuit. FPGA is usually being used when high performance computing applications like digital signal processing, image processing, high speed communication and high speed data transfer is involved. The FPGA provides considerably good computational throughput even at a low clock rates because it employs parallelism in its operation (Field Programmable Gate Array, 2009). Many of the applications dont require the high speed performance which FPGA proffers. Those applications are targeted and the FPGA can be replaced by the redesigned microcontroller which can employ the same operations by using assembly code as a programming language. These redesigned microcontrollers can reduce the cost of product with a big architecture of microcontroller using latest fabrications technology and then convert the verilog code to C code and C code to assembly code for existing applications employed by FPGA.
FPGA graph
Fast
Cost
Slow
Microcontroller Features Figure 1: Microcontroller in FPGA graph
Figure 1 shows the graph of the FPGA with respect to cost and Features. From the graph it is clear that as the number of features in the FPGA increase the price also rises. With this modified microcontroller design we will able to develop a microcontroller that provides all the features of the FPGA at lower cost. If the microcontroller is plotted in the FPGA graph it would appear as shown in Figure 1. It provides all the features of the low end FPGA at a lower price.
Background
Microcontrollers and FPGAs are introduced and are being widely used over the past 10-15 years. The project is to develop a methodology to replace the FPGA by microcontroller. Before designing or developing, it is important to first understand the present technology, architecture, and design of the existing microcontroller and the FPGA. An extensive research was performed over a wide range of resources to understand the basic architecture, design, and different
components of microcontroller and FPGA. The background of the basic architecture of microcontroller and FPGA are described below. 2.1 Microcontrollers
Microcontroller is a small computer inside a single chip. It is basically a programmable chip invented in 1970s. This device is most widely used in automotive products. Initially the microcontrollers were developed using TTL (Transistor-Transistor Logic) technology which are having CMOS (Complementary Metal-Oxide-Semiconductor) technology at present. Currently, microcontrollers are very popular due to its functionality, simplicity, low power consumption, easy programmability, and low cost. The basic components of microcontroller are CPU (Central Processing Unit), Data bus, Timers, Interrupts, ROM (Read Only Memory), I/O (Input Output) unit, RAM (Random Access Memory). In the current market, many kinds of microcontrollers are available with other components in them to perform special errands like USB port, Ethernet port, Bluetooth port, external memory slot, Analog to Digital converter etc. The basic architecture of microcontroller is shown in Figure 2. Some basic components of microcontroller are explained below.
CPU (Central Processing Unit): The CPU is the brain of processor which is responsible for controlling all other units inside the controller. All modules inside processors are connected to CPU and it is responsible to manage the functions of other units, input/output data, and various processes on data, computation and logic performance. Data Bus: It is the medium through which the data moves from one module to another module.
Figure 2: Basic Architecture of Microcontroller Source: What is Microcontroller? Retrieved on 27 September, 2009 from http://o.mneina.googlepages.com/what_is_microcontroller.htm
Input/output unit: This unit is responsible to take the data in and give the resultant data out. The input unit collects the data from external environment and makes it available to modules to perform functions. The output unit collects computed data and gives as resultant data. RAM and ROM: RAM (Random access memory) and ROM (Read only memory) are memory units to store the data temporary or permanently. Timers: The timers are responsible to make the processor functions real time. In the processor more than one timer may be also available for specific purpose. Modifications of the basic architecture of microcontrollers can solve many technical problems. Now industries are approaching to change the architecture of microcontrollers as per their requirement and many of researchers and developers prefers to do advancement in the microcontrollers design. 4
2.2
FPGA
FPGA is one of the revolutionary inventions in the field of the semiconductor industry. The first FPGA was XC2064, introduced in 1984 by Ross Freeman, Co-founder of Xilinx Inc. It had 800 gates in it and was manufactured using 2.0u process technology. As the technology continued to become popular, FPGA has undergone a tremendous amount of changes with respect to architecture, process technology, and complexity. Additional components were included in the FPGA to improve the functionality and complexity. Figure 3 shows the basic architecture of FPGA. The basic FPGA architecture include three main components such as programmable interconnect, logic blocks, and configurable I/O blocks. It also contain additional logic components like decoders, ALUs, memory and programmable elements like static RAM and EPROM are included in the FPGA architecture. A clock circuit decides the speed at which the FPGA works. Configurable Logic Blocks (CLBs): All the FPGAs have small logic components which can be programmed called logic blocks. The logic blocks can be programmed and configured to implement complex logic functions.
Figure 3: (a) Basic architecture of FPGA (b) Basic architecture of logic block Source: Ma Xiaojun; Tong Jiarong; Design and Implementation of a New FPGA Architecture, 21 Oct, 2003. 2, 816 819. Retrieved on 1 October, 2009 from http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=127733 5&isnumber=28525
Configurable I/O blocks: The configurable I/O blocks on FPGA are used to get the inputs and send the outputs. Pull up and pull down registers are included and are used to terminate signals. Programmable Interconnect: A set of long wires are used to connect the critical logic blocks which are far from each other. Logic blocks which are nearer to each other are connected with short wires. To turn on and off the connections between the lines transistors are used in the form of switches.
As the technology developed and the speed of the applications increased, the architecture of FPGA experienced some major changes. The graph in Figure 4, published in a press conference by Xilinx Inc. provides a brief overview of the changes made in FPGAs over the past 20 years.
Figure 4: Evolution of FPGA Architectures Source: Revolutionary Architecture for the Next Generation Platform FPGAs, Xilinx. Xilinx press release, December 8, 2003, retrieved on 5 October, 2009 from http://www.xilinx.com/company/press/kits/asmbl/asmbl_arch_pres.pdf
Even though the FPGA has under gone major changes in the past 20 years, the price and the power consumption of the FPGA remained high when compared to ASIC(Application Specific Integrated Circuit)chips.
Experimental Procedure
The FPGA chip is mainly designed and implemented using verilog-HDL (Hardware Description Language). A parser generator is used which is basically a language converter to convert the verilog modules to C programming language. Then C code was compiled by open source complier such as gcc compiler. The compiled C code can be converted to low level assembly language for the target microcontroller.
The entire algorithm was implemented in many phases as per the project schedule. The issues that came up while proceeding with this project is mainly verilog code design, debugging, use of parser, and conversion of high level language to assembly language.
The initial phase of the project was to work on experimental verilog modules; i.e. converting small verilog modules to C modules both manually as well as by using a parser generator. After this, the real time application verilog code selected to convert to C code using parser generator. Then the C code converted to assembly code. Once the C code is converted to assembly code, testing was being done. The further changes will be more depending upon the progress of work. 4 Resources Utilized
The main objective at present is to develop a solution to replace FPGA by 8-bit microcontroller circuit and further focus on implementing the same if time permits. Our custom designed microcontroller may be required with special features to implement our design. The following resources will be used to proceed with the project.
4.1 4.2 5
Software requirement ANTLR Parser generator to convert the verilog code to convert into C code Modelsim Simulator tool for verilog code simulation Linux Open Source as C code compiler (gcc compiler) Hardware requirement (If we implement practical design) FPGA circuit board (Altera or Xilings) Microcontroller IC
Applications
The low power real time applications are identified which uses FPGA chip and can be replaced by microcontroller. Those are mentioned below. Home based portable medical device like Insulin pump Low power mixed-signal FPGAs in employed in Hemodialysis machine LCD panels of digital cameras, personal digital assistants (PDA), and handheld devices, Touch screen controller In storage device such as memory stick which are used for portable devices like digital camera, PDAs, digital music players
Preliminary Literature Review
We have reviewed considerable publication like IEEE journals, white papers, online newsletters, and publications of pertinent organizations to discover current technology trends, market behavior, and significant methodologies about our hypothesis. We have analyzed the IEEE
journals and publications of applicable organizations to know more about the advancement in the architecture of a FPGA chip as well as the microcontroller and regarding the real time operations carried out by a FPGA chip that need to be replaced by microcontroller circuit. We have investigated regarding the current market share of FPGA and microcontrollers for automotive products. We also carried out the economic analysis for FPGA and microcontroller to understand future inclination of automotive world. We have focused on entire premise of our project to get the information for justifications of our project scope during literature survey. 6.1 Literature Review of Microcontroller
We analyzed the fact that, the compiler architecture, multithread programming model, reconfigurable computing by hardware and software hybrid model etc will be the future trends. Performance of processor can be increased using reconfigurable microcontroller array which is applicable for applications like high speed data handling, image processing, and pattern reorganization. An IEEE paper about Survey on microprocessor architecture and development trends was published by Yao Yingbiao; Zhang Jianwu; and Zhao Danying on November, 2008 in 11th IEEE international conference of Communication technology where authors talked about the future requirements of new amendments in microcontroller architecture. These new architectures can resolve the problems of workload parallelism, speed mismatch problems, and overall recital (Survey on microprocessor architecture and development trends, 2008). One of the IEEE paper published by Maslennikov, O.; Shevtshenko, J.; Sergyienko, A.; about Configurable microcontroller array on September 2002 in the international conference on parallel computing in electrical engineering. In this paper authors have suggested a reconfigurable microcontroller array for i8051 processor. In this paper they have suggested 10
implementation of reconfigurable computing. They justified their proposal by showing detailed work about this new methodology. Authors also showed how the performance of processor can be speed up by this technique which can be useful for such applications like high speed data handling, image processing, and pattern reorganization (Configurable microcontroller array , 2002). The authors Golbert A. and Israel I. mentioned about latest trend in microcontrollers architectures by publishing an IEEE paper about Trends in microprocessor cache architectures in the 17th Convention of Electrical and Electronics Engineers in Israel on March, 1991. They explained the initial architecture of processors and then concluded that the cache memory architecture is requirement of future. They also suggested developing the external cache architecture for some designs as per requirements (Trends in microprocessor cache architectures, 1991). According to IEEE paper Design of an 8 bit general purpose microcontroller with sea-of-gates design style published by Nalan Erdas and Mustafa Gunduzalp in the eleventh international conference on 22-24 November, 1999 is discussing about increasing the capabilities and reliability of microcontrollers and the electronic component size should be minimized. The modification in basic execution style of microcontroller is also necessary (Design of an 8 bit general purpose microcontroller with sea-of-gates design style, 1999). 6.2 Literature Review of FPGA
FPGAs are typically less efficient due to the overhead on the device for the configuration circuitry, including I/O and the SRAM cells required to hold the current design. This leads to larger device sizes and larger power consumption. While it is getting easier all the time, it is
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still true that developing any system on an FPGA usually requires some savvy when it comes to digital design. Even though the FPGA has under gone major changes in the past 20 years, the price and the power consumption of the FPGA remained high when compared to other non FPGA chips. A presentation on Low Power FPGAs A New Era was given by Rich Kapusta, Vice President, Marketing & Business Development, Actel Corporation. In this presentation the speaker clearly explains the problems faced by todays semiconductor industries. He explains the increase in the cost of designing as the process technology develops (Low Power FPGAs A New Era, 2009).
Figure 5: Technology vs. Design cost Source: Low Power FPGAs A New Era, Rich Kapusta, Vice President, Marketing & Business Development, Actel Corporation. Retrieved on 1 October, 2009 from http://www.actel.com/company/events/default.aspx In a recent article on FPGA architectural power-saving techniques at 40 nm by Seyi Verma, Altera Corp, the author gives a theoretical description on how the power consumption of FPGA can be reduced using the 40nm process technology. In this article the author describes that the 40nm process technology offers more benefits when compared to 45nm and 65nm process technology (FPGA architectural power-saving techniques at 40 nm, 2008). 12
In an IEEE paper by W. James MacLean on An Evaluation of the Suitability of FPGAs for Embedded Vision Systems presented at 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, the author describes some of the major disadvantages on FPGAs. The author states that FPGAs are typically less efficient due to the overhead on the device for the configuration circuitry, including I/O and the SRAM cells required to hold the current design. This leads to larger device sizes and larger power consumption. The author also describes that the designers of the FPGA need to have a complete knowledge and understanding about clock signals, flip-flops, FIFOs and propagation delay. He states that the software designers need know about the target platform the software is going to be used. He also describes that the designers of the FPGA need to have a good idea about the architecture of the Adders and Multipliers (An Evaluation of the Suitability of FPGAs for Embedded Vision Systems, 2005).
Technical details of the Project
To design and implement the workflow of converting verilog to 'C' code and then design the microcontroller involves the following technical specification. The project is divided into two phases. In the first part, ANTLR parser is used to convert verilog HDL to C language. In the second phase, microcontroller is designed using the required specification in order to mimic the functionality of FPGA chip.
7.1
System Design methodology
The design of this project took place in different phases. The basic flow chart is given in Figure 6 below. This is the high level process flow of the design shown in Figure 6.
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Figure 6: High-level process flow of the project design 7.1.1 Fist phase :( Verilog to 'C' language Conversation process)
ANTLR parser is used for the language conversion purpose. It can generates a program, then by adding codes to the grammar file, the code parser becomes a translator. It converts behavioral verilog code to 'C' code and the resultant code can be compiled using open source gcc compiler. There are several reasons behind choosing ANTLR passer for this purpose which are described below. ANTLR parser is a platform independent parser and can works in Window, Linux, and Mac operating systems. It basically has a Java based IDE(Integrated Development
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Environment) that can support data structure like structure, tree walking, and error recovery Very reliable, automates tasks, supports multiple languages like Java, C#, python, objective C, C etc. ANTLR is easier to understand and use than other parser generators. ANTLR is used to build interpreters for domain specific languages which are high level languages to be used ANTLR has a good user friendly GUI development environment to produce ANTLR version3 grammars and it contains all the jar files are needed for the application ANTLR v3 has many different kinds of run time liberalities to support different kinds of language like Java, C, C++, python,C#, PERL, ActionScripts, and JavaScript The verilog grammar can be parsed in eclipse IDE in order to support the verilog HDL language The tool can generate AST(Abstract Syntax Tree) out of the verilog module when the verilog grammar file is plug in into the IDE 7.1.2 ANTLR Workflow
A translator's job is to map the input of one language to an output of other language. To complete mapping, the translator parses user provided codes. The translator can translates in two phages, first phase is lexical analysis. The second phage is known as parsing that parse symbols. ANTLR tool automatically generate lexer and parser by analyzing the grammar. This is shown in Figure 7.
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character
Lexer
tokens
Parser AST Tree walker
output
symbol, table, flow graph
Figure 7: Overall translation data
The intermediate structure is a tree data structure called AST(Abstract Syntax Tree). The final output provides structure using all the data structure from previous inputs. The lexer's work is to break the input language into tokens. The parser can parse tokens to understand the input structures. ANTLR has a GUI grammar environment to help edit, compile, and, debug grammars. The method of translating verilog HDL to its equivalent 'C' coding is parsing a verilog pattern in a verilog file and substituting the verilog code with a 'C' language. It helps to debug grammar analysis errors. The GUI development environment has following features. 1. Grammar-aware editor 2. Abstract Syntax diagram grammar 3. Dynamic parse tree view 4. Dynamic AST view
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5. Debugger for grammar errors
7.1.3
Architecture of ANTLR compiler
ANTLR parser tool compiles the verilog RTL (Register Transfer language) behavioral model to convert it to 'C' programming language. The architecture of ANTLR is similar to most of the modern day parser generator like Lex, Yacc etc. However, the advantage behind using this tool is, it can create parse tree in the intermediate stage of language conversion which is very easy to visualize and test in the GUI. Below in Figure 8, it is clearly shown the high level design of ANTLR architecture.
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Figure 8: Architecture of ANTLR compiler module
Front End: The front end of parsor consists of the parser, lexical analyzer and, the semantic analyzer. Lexer
The lexer's input accept a verilog code to make small structures. If there is some error in the input, error is reported in the interpreter. It has a particular value with each structures which passed to the parser which is mainly the start of a line, end of a line number and the file name of the source. Parser:
The job of parser is to accept files passed by the tool and match with the particular grammar rules. If syntax error found, it can be compiled at this stage. Each supported verilog code is modeled as Java class. The verilog constructs are converted into objects in Java classes. The classes together form an internal tree known as Abstract syntax tree or parse tree. Semantic Analyzer
Semantic analyzer's work is to make parse tree an AST(Abstract Syntax Tree). It does error checking which was skipped the lexer. The AST is basically an intermediate form between the front end and back end of language compiler. Optimizer: These mainly implemented in order to increase the capacity and reliability of the code. Back end (Code generator) The backend is code generator which gives the output code from a standard input. It use the 'C' codes for behavioral codes in verilog language. The codes can be mapped into equivalent code
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structure. The code generator takes the AST and outputs the targeted 'C' code. The 'C' program can be compiled using standard gcc complier.
Abstract Syntax Tree (AST) generated by ANTLR: Below there is a verilog test case which was run in the interpreter and it created the AST clearly. The AST is shown in Figure 9 and a close-up view is shown in Figure 10. Verilog test case: module TOP(in, out); input [7:0] in; output [7:0]out; assign out=~in; endmodule
Figure 9: AST generated by ANTLR
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Figure 10: Close up view of AST
Verilog RTL to 'C' code generation After the intermediate phase, i.e. after creating the AST, the next phage is the conversion of Verilog to C code. A class hierarchy is needed to be implemented in JAVA object oriented programming language and the actions were embedded in the codes in order to do the conversion process. A main driver program is written in Java to test the language conversion process. Below is the example of a verilog test case which is used to test. Verilog code for 2:1 MUX module simple_mux(a, b,sel,out); input [31:0] a, b; input sel; output [31:0] out; assign out = (sel)? b : a; endmodule
Equivalent 'C' code for 2:1 MUX The C code out of the above verilog module looks like below. 20
static void simple_mux(int *pa, int *pb, int *psel, int *pout) { if (*psel == 1) { *pout = *pb; } else { *pout = *pa; } } 7.2 Second phase: Design and Implementation of Microcontroller
The existing microcontrollers are not fast enough to replace the FPGAs. The decision making capability of the microcontroller is limited and slow. On the other hand the FPGAs are fast and can take multiple decisions in one step. We are focusing on increasing the speed of the microcontroller and improve the decision making capability of the microcontroller by adding additional memory and giving the ability for the microcontroller to take multiple decisions. Few bits of the instruction are dedicated to help the microcontroller in making decisions.
7.2.1
Microcontroller design flow
The flow of the microcontroller design is as shown in Figure 11. The complete flow is divided into two major parts, Front End and the Back End. The Front End design starts with defining the design specifications followed by the behavioral description. The designing of the microcontroller is done using Verilog HDL. Functional verification and testing is performed on the microcontroller design. Depending on the verification, the design is altered or modified. Once the design is verified functionally it is then synthesized. Synthesizing the design helps to determine the area of the microcontroller. It also helps to determine the timing closures, and delays. Synthesizing the design generates a gate level netlist. Logical verification is the last step in the Front End. Logical verification is performed on the gate level netlist and based on the results the verilog design is modified to incorporate the timing and area specifications.
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The second part of the design flow is the Back End. Back End includes floor planning and automatic place and route, physical layout and layout verification and implementation. All the Back End work will be outsourced to different companies. Once the Back End is completed the chip will be taped for manufacturing.
Figure 11: Microcontroller design flow Source: Magma Design Flow, V. Kamakoti and Shankar Balachandran http://nptel.iitm.ac.in/courses/IITMADRAS/CAD_for_VLSI_Design_II/magma_tutorial/magma_tutorial.html
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7.2.2
System Architecture
The microcontroller is designed using Harvard Architecture and uses separate buses to access program and data. This helps the microcontroller to fetch program data with one bus and read/write to the memory with data bus at the same time. With the help of Harvard architecture it is easy to implement pipelining and allows the fetch and execution cycles to overlap each other. The microcontroller has a 32 bit wide instruction set and 8-bit wide data path.
The architecture of the microcontroller is shown in Figure 12. The microcontroller has an 8-bit Arithmetic Logic Unit (ALU). The microcontroller has 256 byte data memory and 256 byte program memory. The databank is divided into register bank and special function register bank. The special function registers are used for assigning the port inputs, timer, status word, etc. An additional memory of 256 bytes is used by the decision box. Currently in our design we are supporting only 32 I/O inputs. In addition to the regular microcontroller architecture, an additional block known as decision box is implemented which helps the microcontroller to take decisions faster.
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Figure 12: Microcontroller Architecture The instruction is fetched from the program memory and is decoded by the instruction decoder. Depending on the decoded bits the respective bits are enabled for ALU operation, branch operation and decision box operations. A new instruction is fetched at every clock cycle. After the operation is performed according to the instruction the result is sent back to the CPU and it is written into the memory at the destination address specified in the instruction. For the decision box instructions the 5 decision box bits along with the destination address are sent as inputs to the decision box. The last 5 bits of the destination address are replaced with the output of the decision box and a new destination address is calculated to fetch the instruction from.
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No interrupts are supported in the design. The microcontroller has 32 I/O inputs connected in the form of four 8-bit ports. This I/O signals are used in the decision making of the microcontroller. The different components of the microcontroller are described below.
Instruction Set The instruction set for the microcontroller is 32-bit wide. Bits 7-0 are signed for the source address and bit 15-8 are assigned to address the destination address. Bits 20-18 are used as mod bits which decide the nature of the source and destination. Bits 25-21 are used by the selection box to make decisions. Table 1 shows the distribution of the instruction set. 31-26 opcode 25-21 decisionbox_sel 20-18 mod_bits 15-8 destination_address 7-0 source_address
Table 1: Instruction Set Mod bits Mod bits are used to define the source of inputs. These bits define whether the operation is between a register and a register, register and immediate data, port and register etc. Table 2 describes Mode options. Case 000 001 010 011 100 Table 2: Mode Conditions Operation Reg (S) & Reg (D) -----> Reg (S) Immediate(S) & Reg(D) ------> Reg(D) Port(S) & Reg(D) ------> Reg(D) Reg(S) & Port(D) ------> Port(D) Extension ports
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Opcode The microcontroller design supports arithmetic, logic and branch operations. Each opcode represents a different operation, so it is easy for the programmer to choose specific operation. Our design supports 64 different operations, but right now we are implementing only 16 operations. Table 3 describes the opcodes and their respective operations. Opcode 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Operation MOV Clear Carry Set carry ADD SUB ADD with carry NOT AND OR XOR Shift Right Shift Left Shift rotate right Shift rotate left Swap Jump
Table 3: Opcodes 26
CPU The CPU is the brain of the microcontroller. The CPU fetches the instruction from the program memory, decodes and executes the instruction. The CPU fetches the instruction form the program memory using a 32 bit program bus. It also writes the data into the memory using an 8bit bus. The main components of CPU are Arithmetic Logic Unit (ALU), Instruction Register (IR), and Program Counter (PC).
Arithmetic Logic Unit (ALU) ALU has two 8-bit inputs, 1-bit carryin and the opcode. Depending on the opcode the ALU performs the respective operation on the two inputs. The ALU has an 8-bit output which is the result of the operation performed on the two inputs. It also has a single bit carryout output. The alu_enable input acts as the enable signal for the ALU. The operations are performed by the ALU only when the enable signal is 1.
Program Counter (PC) A register known as program counter holds the address of the next instruction. The program counter is incremented after every fetch operation unless any operation is performed on the program counter.
Instruction Register (IR) The instruction pointed by the program counter is fetched and stored in the instruction register. The instruction is then decoded from the instruction register and the type of operation to be performed is determined.
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Decision Box Decision box is the additional mechanism that is being incorporated into the architecture of the microcontroller. The design of the decision box is shown in Figure 13. The decision box helps the microcontroller to make decisions faster. The decision box allows the microcontroller to take decisions from multiple options.
Figure 13: Decision box block diagram There are 32 I/O inputs connected to the decision box. The decision box has a 35X256 bit memory. The memory consists of 35bit words. The 5 bits of the instruction are used as address bits of the memory. The decision box has 5 multiplexers. The 32 I/O are connected as inputs to all the 5 multiplexers. The selected 35 bit data from the memory is then divided into 7 parts. 5 bits of each part is used as select lines for the multiplexer and other 2 bits are used as AND and XOR bits. These bits allow the output of each multiplexer to be set or reset depending on the requirement of the programmer. All the outputs of the multiplexers are then combined and are
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sent as the output. The 5 bit output is then replaced on the last 5 bits of the destination address used to fetch the next instruction.
Economic Justification
8.1
Executive summary
Three engineers from San Jose State University had developed a methodology to replace the high power, high cost FPGA application by low cost custom designed microcontroller. The project was completed in two phases. In the first phage, an open source parser generator, ANTLR is used to convert verilog HDL to C code and then the design of microcontroller was completed in the second phase.
The targeted customers are mainly the manufactures who are using low power FPGAs and have their logic and functionality already developed in HDL which is compatible with FPGAs. It will cost more for these customers to switch completely from FPGA to microcontroller and design their applications in assembly code. Hence, the company is going to provide a solution to convert the HDL logic to assembly level, by using the algorithm that the company is generating.
8.2
Problem Statement
Many of the applications dont require that high speed for the performance which FPGA offers. These FPGAs can be replaced with redesigned less expensive microcontrollers.
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8.3 Solution and Value proposition

Present microcontrollers are not fast enough to replace the FPGAs. Redesigning and adding some decision making capabilities to the microcontroller will increase the speed and functionality to be able to replace the low speed FPGAs.
8.4
Market size
The worldwide microcontroller market is increasing day by day. The market of 8-bit microcontrollers is expected be reach $6000 million by 2016. The graph in Figure 14 shows the expected growth of the microcontroller market.
Figure 14: Market Scale forecast for Microcontrollers Source: Development of the RX Family, Renesas. Retrieved on 16 October, 2009 from http://america.renesas.com/fmwk.jsp?cnt=backgroud.htm&fp=/products/mpumcu /rx_family/child_folder/&title=Development%20of%20the%20RX%20Family Microcontrollers are used in most of the electronic appliances in our daily life. The graph in Figure 15 shows the distribution of microcontrollers in various applications.
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Computers 34%
PDA 0% Cellphones 60% Handhelds 3%
Smartphone 3%
Figure 15: Worldwide Processor Market In 2010 Source: Retrieved on October 24, 2009 from http://www.etforecasts.com/products 8.5 Competitors
The company identified its potential competitors and their product specification while doing the market analysis. Here is the list of some of the key players of microcontroller and FPGA.
Key Players of Microcontroller Microchip technology Atmel STMicroelectonics Renesas Technology Corporation MIPS computer system Intel Inc. NEC Electronics Corporation Cypress semiconductor Rabbit semiconductor 31
Texas Instruments
Key players of FPGA 8.6 Altera Inc. Xilinx Inc. Actel Inc Siliconblue chip Lattice Semiconductor Quick logic Inc. Customers
There are many manufactures who are using low speed FPGAs and have their logic and functionality already developed in HDL which is compatible with FPGAs, it may cost more for these customers to switch completely from FPGA to microcontroller and design their applications in assembly code. So for these types of customers the company is going to provide a solution to convert the HDL logic to assembly level, by using the algorithm that the company is generating. Some of the customers are Diabetes network (e.g. Insulin pump) Abbott lab (e.g. Insulin pump) Casio (e.g. Calculators, PDA) Handspring Inc (e.g. PDA) Sinucircuit Inc (e.g. Memory stick) Automobile companies
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8.7
Cost summary
The cost summary includes fixed cost, variable cost and employee wages. Manufacturing of the microcontrollers will be outsourced to other companies. 8.7.1 Fixed cost
Fixed costs of the company include office building lease and maintenance, wages of the employees, electricity and internet, licensing cost for hardware tools, furniture costs, etc.
Category/Year Licensing cost for Hardware Tools Licensing cost for Software Tools Building Rent Maintenance PG & E bills Furniture Cost Computer Equipment and Stationary Internet and Telephone Employee wages Third party IP's Miscellaneous Patent cost TOTAL
2010 $100,000 $50,000 $80,000 $15,000 $10,000 $15,000
2011 $100,000 $50,000 $100,000 $17,000 $14,000 $5,000
2012 $100,000 $50,000 $100,000 $20,000 $19,000 $5,000
2013 $100,000 $50,000 $110,000 $25,000 $21,000 $8,000
2014 $100,000 $50,000 $110,000 $25,000 $21,000 $8,000
2015 $100,000 $50,000 $140,000 $27,000 $25,000 $10,000
2016 $100,000 $50,000 $140,000 $27,000 $25,000 $10,000
$21,000 $5,000 $500,000 $400,000 $60,000 $2,000
$25,000 $6,600 $760,000 $550,000 $30,000 $2,000
$30,000 $7,200 $980,000 $600,000 $30,000 $3,500
$33,000 $8,400
$33,000 $8,400
$50,000 $12,000
$50,000 $12,000
$1,200,000 $1,600,000 $1,980,000 $2,280,000 $700,000 $30,000 $3,500 $900,000 $30,000 $3,500 $1,000,000 $1,400,000 $30,000 $4,500 $30,000 $4,500
$1,258,000 $1,659,600 $1,944,700 $2,288,900 $2,888,900 $3,428,500 $4,128,500 Table 4: Fixed Cost
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8.7.2
Employee Wages
The wages of the employees are decided depending on their role and experience. Department Design and development Executives Marketing and Sales Administrati on Operations Management 2010 2011 2012 2013 2014 2015 2016 $1,080,000(9) $520,000(3) $1,100,000(10 ) $300,000(3) $360,000(4) $400,000(4)
$100,000(1) $360,000(3) $480,000(4) $720,000(6) $780,000(6) $1,000,000(8) 0 $140,000(1) $140,000(1) $260,000(2) $270,000(2) $520,000(3) $900,000(8) $300,000(3) $360,000(4) $300,000(3)
$180,000(2) $330,000(3) $880,000(4) $660,000(6) $800,000(7) $90,000(1) 0 0 $100,000(1) $100,000(1) $200,000(2) $200,000(2) 0 $90,000(1) $90,000(1) $90,000(1) $270,000(3) $270,000(3) $200,000(2) $200,000(2)
Table 5: Employee Wages 8.7.3 Variable cost
Variable cost includes advertising costs, wages of contract employees, outsourcing, manufacturing cost and customer service cost. Category/Year Advertisement Contract employee Outsourcing Manufacturing Customer service TOTAL 2010 $100,000 $130,000 $300,000 $900,000 $100,000 2011 $190,000 $600,000 2012 $220,000 $1,000,000 2013 $250,000 $1,300,000 $2,100,000 $6,800,000 $200,000 2014 $330,000 $1,400,000 $2,500,000 $8,400,000 $220,000 2015 $400,000 $2,500,000 $3,300,000 2016 $600,000 $2,300,000 $4,500,000
$1,100,000 $1,500,000 $2,600,000 $4,040,000 $150,000 $180,000
$13,000,000 $16,500,000 $250,000 $300,000
$1,530,000 $4,640,000 $6,940,000 $10,650,000 $12,850,000 $19,450,000 $24,200,000 Table 6: Variable Cost
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8.8
Price Point
As the company is focusing on taking over the market of low speed FPGAs, the price of our product will be less than the price of the FPGAs. This will help to approach the market easily. We have decided to produce 100K units initially. An assumption of all the values used to derive the initial price of the product is shown below. Department Building lease and Maintenances Insurance and Taxes Manufacturing Cost Hardware design and development Software design and development Outsourcing Marketing and Sales Miscellaneous costs Total Table 7: Estimated cost for 100K units The value was derived after considering the cost of all the issues involved like product design, maintenance, software, manufacturing of the microcontroller, salaries, etc. We have decided our initial price of our microcontroller to be $15. The initial price of the product is less than the amount obtained by dividing the estimated cost with the number of units. To enter into the market and to sustain and takeover the low speed FPGA market; the price of the microcontroller has to be less than the FPGA. Assumed Cost for 100K units (Millions of dollars) .3 .2 .4 .5 .2 .4 .5 .3 2.7
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8.9
SWOT Assessment
SWOT assessment was done after doing the market analysis and business case analysis. FPGA market is already popular in the market and this project is proposing a methodology to penetrating into the FPGA market to replace some of the application by microcontroller. The company realizes that this project is a big challenge to enter into an already established competitive market. The biggest challenge is to satisfy the customer need by providing the cheaper solution with all kinds of features in it. Any kind of start up company has to face lots of completion in order to make profit in this recession. There is a brief overview of the SWOT analysis is given below.
STRENGTH Low cost Faster than present microcontrollers Frontend design implemented successfully
WEEKNESS Not enough resources Startup company in the current recession period.
OPPERTUNITY The market of 8-bit microcontrollers is expected be reach $6000 million by 2016 The custom designed controller can provide a better solution in the current controller market.
THREATS Competitors are always trying their best to come up with new technologies. Recession period is really a risk for the small start ups.
Table 8: SWOT assessment
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8.10 Investment Capital Requirement The company will break even by the end of 2012. The company requires around 2.7 million dollars before it breaks even. We will be raising part of this money from the investors and the rest will be taken from the banks as a long term loan. Once the company has reached the breakeven point, the profits will be reinvested on the company. 8.11 Personnel Since the company is focusing on a newly emerging technology, it is stared with only three employees initially. The tasks will be distributed equally among the three employees. One employee will take care of the product design and development; the second employee will concentrate on development and testing, i.e. converting Verilog HDL to C codes and testing it. The third employee will be in charge of the non-technical part like marketing, resources, and administration. The product needs to be done in two phases. The first phase will be the front end, where the product will be designed, developed and tested using simulators. The second phase is the backend where the product will be manufactured and the actual testing of the real product will be done. The company will be working with third party vendors for manufacturing the product.
As it is small company, the plan is to outsource the backend work to other companies have less time to market. Table- shows the expected human resources of our company in the next 5 years. Most of the employees will not be full time, but will be hired as contractors, based on the requirement of the projects.
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Department/Year Design and development Executives Marketing and Sales Administration Operations Management
2010 1 0 2 1 0 0
2011 3 1 3 1 0 1
2012 4 1 4 1 1 1
2013 6 2 6 2 3 2
2014 7 2 7 2 3 2
2015 8 3 8 3 4 3
2016 9 3 10 3 4 4
Table 9: Human Resources
8.12 Business and Revenue Model From the market survey we have learned that there is a big growth for microcontroller market. Introducing microcontrollers that can replace low speed FPGAs will be ideal for present and future market. The microcontrollers will be directly sold to the Original Equipment Manufacturer (OEMs) companies who manufacture low speed equipment and applications. The initial price of the microcontroller will be $15. The company's target is to sell 3 million microcontrollers by the end of 2016. 8.13 Strategic Alliance/Partners Our company will be partnered with the leading foundries like Fujitsu for manufacturing the microcontrollers. Our company is also planning to form alliance with Synopsys for the development of the software tool used to convert Verilog HDL to assembly code. These
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partnerships and alliances will help us to approach the present and future market with cheaper microcontrollers. 8.14 Profit/Loss The expenses for developing and manufacturing the microcontroller and estimated and the price of the microcontroller is decided. Once the price of the microcontroller is decided, the revenues are calculated for each year depending on the estimated number of microcontrollers sold each year. With the numbers for the estimated expenses and revenues the profit/loss is derived. The company is expecting loss for the first two years and will start gaining profits from the last quarter of third year. Below the table and graph which show the estimated profit/loss for the next 7 years. Year Expected Revenue (Millions of dollars) 1.6 5.4 8.54 13.2 17.7 28.6 37.8 Fixed Cost Variable (Millions cost/unit of dollars) (dollars) 1.2 1.2 1.5 1.9 2.2 2.8 3.5 4 13.9 13.9 13 11.4 11.1 9.8 8.8 8.1 Variable Cost (Millions of dollars) 1.5 1.5 4.6 6.9 10.7 12.8 19.4 24.3 Total Cost Loss/Profit (Millions (Millions of of dollars) dollars) 2.7 2.7 6.2 8.8 12.9 15.5 12.9 28.3 - 2.73 -1.08 -0.89 -0.38 0.39 2.17 5.74 9.53
2010 2011 2012 2013 2014 2015 2016 2017
Table 10: Profit/Loss
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Figure 16: Profit/Loss graph 8.15 Breakeven Analysis Breakeven point is the point where the revenue of a product is equal to the cost of making the product. To calculate this point we use a financial tool known as Breakeven Analysis. Our company is expected to reach the breakeven point by the end of 2012. The breakeven point graph is shown in Figure 17.
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Figure 17: Break Even Analysis Graph 8.16 Return on Investment (ROI)
Return on investment is the ratio of the investment and the profit.
ROI =
Pr ofit ( Loss)
Investment
* 100
Our initial investment was 2.7 million and cumulative benefit ~12.75 million by the end of 2016 12.75 Return on Investment = ----------------- X 100 2.7 = 471.8%
The company is expecting to breakeven by the end of 2012. By the end of 2016, the company will gain about 464.8% of the investment over a period of 7 years. Which means, for every dollar spent, the investor will receive $4.64 in return over a period of 7 years.
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8.17 Exit Strategy
Our company is open for either going public or acquisition depending on the market growth and economy. We also have plans to merge into other microcontroller manufacturing companies.
Project Schedule
The gantt chart for the schedule of the project is shown below.
Figure 18: Project Schedule 10 Conclusion
The project developed a methodology in order to penetrate into the popular FPGA market to replace it by a cheaper custom designed microcontroller. The several steps of the project used many kinds of open source software. The conversion of verilog HDL to C language and designing the multiway branch switching microcontroller has been completed. The custom designed microcontroller is simulated and tested using open source ModelSim. After the
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verification of a working design, the startup will be ready for the marketing its first design. The break even analysis shows, profit will be stated from the third quarter of year 2012. From the market analysis, it can be concluded that the low cost microcontroller with improved performance can be a key player in the world of automotive products for low power applications.
11 Future Work
The company has planed to add and implement new features in the workflow of this project. Right now, the verilog to C conversion is supporting only the synthesizable verilog constructs and the future plan is to support the simulation constructs. There is also plan to enhance the features of the custom designed microcontroller in order to make it more powerful, cost effective and customer centric.
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12 List Of References:
Actel Corporation. System Solutions. Retrieved October 2, 2009 from http://actel.com/company/default.aspx Altera Inc. End Markets. Retrieved October 2, 2009 from http://www.altera.com/end-markets/end-index.html Amy Leong (August, 2008). Dataquest Insight: Microcontrollers Are Key Enablers for Green Vehicles. Gartner, Inc. Retrieved on 1 October, 2009 from http://www.gartner.com/DisplayDocument?ref=g_search&id=737912&subref=simplesea rch ANTLR v3, retrieved on October 2, 2009 from http://www.antlr.org/ Arnold, Henri(2007). EETimes. Wireless microcontrollers achieve new performance and price points. Retrieved October 2, 2009 from http://eetimes.eu/showArticle.jhtml?articleID=196801875&queryText=price Bringing ARM7(TM) to the Masses design-reuse. Retrieved October 12, 2009 from http://www.design-reuse.com/articles/11767/bringing-arm7-tm-to-the-masses.html Budd, Graham, & Milne, George (1996) ARM7100 - A High-Integration, LowPower Microcontroller for PDA Applications [Electronic version]. Retrieved on October 3, 2009 from http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=501766 &isnumber=10694
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Cadden, Cheryl & Worchel, Jerry (May, 2006). Semiconductor Logic Markets . FPGA Market Will Reach $2.75 Billion by Decades End. Retrieved on 30 September, 2009 from http://www.instat.com/press.asp?Sku=IN0603187SI&ID=1674 Christoph,Hammerschmidt (2007). EETimes. Automotive applications to drive microcontroller market. Retrieved on October, 15 2009 from http://www.eetimes.eu/germany/202101848 Development of the RX Family - Driven by key embedded-system design issues. Renesas Inc. Retrieved October 12, 2009 from http://america.renesas.com/fmwk.jsp?cnt=backgroud.htm&fp=/products/mpumcu /rx_family/child_folder/&title=Development%20of%20the%20RX%20Family Directory listing for /grammar/verilog, retrieved on January 12, 2010 from http://www.antlr.org/grammar/verilog Ed, Sperling (2005). Bottom of the Market, Top of the Game. Retrieved on October, 15 2009 from http://www.edn.com/article/CA6250222.html Erdas, Nalan ,& Gunduzalp, Mustafa (1999) Design of an 8 bit general purpose microcontroller with sea-of-gates design style [Electronic version]. Retrieved on September 30, 2009 from http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=884834&isnumber=19105 Field Programmable Gate Array, retrieved on 2 October, 2009 from http://en.wikipedia.org/wiki/Field-programmable_gate_array FPGA projects dominate by a 30 to 1 margin. GateRocket, Inc. Retrieved on October 12, 2009 from http://www.gaterocket.com/device-nativeverification/?Tag=FPGA+Market
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Gartner Says Green Vehicles to Drive Automotive Microcontroller Market to Reach $6.3 Billion in 2012. Gartner Inc. Retrieved on 1 October, 2009 from http://www.gartner.com/it/page.jsp?id=744612 Golbert A. & Israel I. (1991) Trends in microprocessor cache architectures [Electronic version]. Retrieved on October 3, 2009 from http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=217645&isnumber=5704 Hammerschmidt, Christoph (September, 2009). EE Times Europe. Automotive applications to drive microcontroller market. Retrieved on 27 September,2009 from http://www.eetimes.eu/germany/202101848 In 2009 to shrink China's MCU market will reach double-digit rate. Toeney Electronics Corp. Retrieved October 10,2009 from http://www.toeny.com/en/news13.html?id=79 Le, Meghan (June, 2004). EE Times. 8-bit microcontrollers: still going. Retrieved on 1 October, 2009 from http://www.eetimes.com/showArticle.jhtml?articleID=54202120 MacLean, W.J. (2005). An Evaluation of the Suitability of FPGAs for Embedded Vision Systems, IEEE Computer Society Conference on Computer Vision and Pattern Recognition. 131. Retrieved on 1 October, 2009 from http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=1565446&isnu mber=33215?tag=1 Ma Xiaojun; Tong Jiarong; Design and Implementation of a New FPGA Architecture, 21 Oct, 2003. 2, 816 819. Retrieved on 1 October, 2009 from http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=127733 5&isnumber=28525
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Maslennikov, O.; Shevtshenko, J.; & Sergyienko, A. (2002). Configurable microcontroller array [Electronic Version]. Retrieved on October 2, 2009 from http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=1115196&isnu mber=24596 McGrath, Dylan (May, 2006) EE Times Asia. FPGA/PLD market to grow 14% in '06. Retrieved on 26 September, 2009 from http://www.eetasia.com/login.do?fromWhere=/ART_8800419580_499485_NT_07a6c7d3.HTM Mentor Graphics. Modelsim PE- Simulation and Debug. Retrieved October 3,2009 from http://www.model.com/content/modelsim-pe-simulation-and-debug Microcontroller, retrieved on September 30, 2009 from http://en.wikipedia.org/wiki/Microcontroller Microprocessor - Market statistics, retrieved on October 10 2009 from http://www.experiencefestival.com/microprocessor_-_market_statistics Morsi, Iman (2007) A Microcontroller Based on Multi Sensors Data Fusion and Artificial Intelligent Technique for Gas Identification [Electronics version]. Retrieved on October 1, 2009 from http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460098&isnumber=4459874 ?tag=1 Plungy, Mark (February, 2009). Business Wire. Altera Announces Stratix IV GT and Arria II GX Parr, Terence, ANTLR reference, retrieved on 12 February, 2010 from "The definitive ANTLR reference" FPGAs: Expands. Retrieved on 3 October, 2009 from
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http://www.bloomberg.com/apps/news?pid=conewsstory&refer=conews&tkr=ALTR%3 AUS&sid=aPyV1AmGEEBk Revolutionary Architecture for the Next Generation Platform FPGAs, Xilinx. Xilinx press release, December 8, 2003, retrieved on 5 October, 2009 from http://www.xilinx.com/company/press/kits/asmbl/asmbl_arch_pres.pdf Rich Kapusta, Low Power FPGAs A New Era, Actel Corporation. retieved on 1 October, 2009 from http://www.actel.com/company/events/default.aspx Robert Jania (2009). PRODUCT HOW-TO: Make the transition from 8- to 32-bit MCU design as painless as possible Retrieved on October, 15 2009 from http://www.embedded.com/products/220301132;jsessionid=CZL2IIBXUIWZVQE1GHR SKHWATMY32JVN?pgno=2 Verilog to C compiler simulator generator, retrieved on 12 February, 2010 from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf http://www.antlr.org/grammar/verilogXilinx Inc. Market Solutions. Retrieved October 3, 2009 from http://www.xilinx.com/esp/index.htm Yingbiao, Yao; Jianwu, Zhang; & Danying , Zhao (2008). Survey on microprocessor architecture and development trends [Electronic Version]. Retrieved on October 3, 2009 from http://ieeexplore.ieee.org.libaccess.sjlibrary.org/stamp/stamp.jsp?tp=&arnumber=471624 7&isnumber=4716080?tag=1
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13 APPENDIX A
Set up ANTLR environment:
Set up eclipse by downloading Eclipse Classic 3.5.1(162MB) distribution from www.eclispe.org.
Go to www.antlr.org to download ANTLR v3 Click on the "Download" button and download Complete ANTLR 3.2jar, all tools, runtime, etc.
To add the ANTLR IDE in to the eclipse, go to www.antlr.org/wiki and under the wiki contents, click on the "Integration with Development Environment" link.
After the ANTLR IDE and Eclipse integration is done, load the verilog grammar file into the environment.
Load the verilog test case modules into the eclipse in order to check how ANTLR is generating lexer and parser automatically.
Integrate the ANTLR generated lexer, parser, verilog grammar and test case in the eclipse environment.
Run the test case to check the AST formation
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14 APPENDIX B
Supported Verilog Constructs
List of verilog keywords always and assign automatic begin buf posedge negedge case casex casez signed while wire xnor xor endmodule localparam deassign endprimitive macromodule default endspecify medium defparam endtable module disable endtask nand edge event negedge else for nor end forever not endcase force notif0 endfunction fork notif1 highz0 function or highz1 deassign else if default join initial defparam large inout disable output input edge parameter integer
(Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors) Lexical Constructs Operators White Spaces Comments Numbers Identifiers Single line, multiple line comments Decimal, binary, hexadecimal & octal Simple, Escaped & system names
(Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors)
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Supported Verilog Operators UnaryOperators BinaryArithmeticOperators BinaryLogicalOperators BinaryBitwiseOperators ShiftOperators ComparisonOperators TernaryOperator +,, !,&, |, &, |, , +,, /,%, &&, || &, |, ,, , &,| <<,<<<,>>,>>> <,>,<=,>=,==, !=,===, !== ?,:
Data types Resisters width registers Nets Wire type nets are supported Parameters Parameter, localparam (Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors) Behavioral Modeling Continuous assignments Case statement Conditional statement Procedural assignments Loops Blocks Timing controls Tasks Functions Initial Always for, while, repeat loop
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Unsupported Verilog Constructs
Data types
Behavioral modeling Specify blocks
Time Real numbers Events parameter(defparam) Loops(forever) Ignored by parser
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15 APPENDIX C
//****************SJSU_298_VERILOG_GRAMMER***************************//
grammar verilog; options { language = Java; } @header { package com.javadude.antlr3x; } @lexer::header { package com.javadude.antlr3x; } //PARSER source_text : ( description )* EOF ; description : module | directive ;
module scope { String modName; } : 'module' name_of_module { //System.out.println("Found a module "+$name_of_module.text); TopHandler.CreateModule($name_of_module.text); $module::modName = $name_of_module.text; } (list_of_ports)? SEMI (module_item)* 'endmodule' ; list_of_ports : LPAREN port (COMMA port)* RPAREN ; port : name_of_variable { //System.out.println("Found a port "+$name_of_variable.text); TopHandler.CreatePort($module::modName, $name_of_variable.text); } ; module_item : // ambiguity between net_declaration and continuous_assign, // but parser gets it right: keyword chosen over IDENTIFIER. input_declaration | output_declaration | inout_declaration|
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net_declaration directive | parameter_declaration gate_declaration | parameter_override initial_statement function ;
| reg_declaration
| time_declaration |
| integer_declaration | real_declaration | instantiation | | continuous_assign | | always_statement | task |
instantiation: module_instantiation ; task : 'task' name_of_task SEMI (tf_declaration)* statement_or_null 'endtask' ; function : 'function' (range_or_type)? name_of_function SEMI (tf_declaration)+ statement 'endfunction' ; range_or_type : range | 'integer' | 'real' ; tf_declaration : parameter_declaration | output_declaration | input_declaration | inout_declaration | reg_declaration | time_declaration | integer_declaration | real_declaration ; parameter_declaration : 'parameter' (range)? list_of_param_assignments SEMI ; list_of_param_assignments : param_assignment (COMMA param_assignment )* ; param_assignment : identifier ASSIGN expression ; input_declaration : 'input' (r=range)? lov=list_of_variables SEMI { TopHandler.SetPortDir($module::modName, $lov.text, "input"); if ($r.value != null) { TopHandler.SetRange($module::modName, $r.value, $lov.text,"port"); } } ; output_declaration : 'output' (r=range)? lov=list_of_variables SEMI { TopHandler.SetPortDir($module::modName, $lov.text, "output"); if ($r.value != null) { TopHandler.SetRange($module::modName,$r.value, $lov.text, "port"); } } ;
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inout_declaration : 'inout' (r=range)? lov=list_of_variables SEMI { TopHandler.SetPortDir($module::modName, $lov.text, "inout"); if ($r.value != null) { TopHandler.SetRange($module::modName,$r.value, $lov.text, "port"); } } ; net_declaration : 'wire' (r=range)? lov=list_of_variables SEMI // wire [9:0] w1,w2; { TopHandler.CreateWire($module::modName,$list_of_variables.text); if ($r.value != null) { TopHandler.SetRange($module::modName,$r.value, $list_of_variables.text, "wire"); } } ; net_type : 'wire'|'tri'|'tri1'|'supply0'|'wand'|'triand'|'tri0'|'supply1'| 'wor' | 'trior' | 'trireg' ; reg_declaration : 'reg' (r=range)? lov =list_of_variables SEMI // reg [5:0] ra,rb; { TopHandler.CreateReg($module::modName, $list_of_variables.text); if ($r.value != null) { TopHandler.SetRange($module::modName,$r.value, $list_of_variables.text,"reg"); } } ; time_declaration : 'time' list_of_register_variables SEMI ; // time t1,t2;
integer_declaration : 'integer' list_of_register_variables SEMI count, diff; ; real_declaration : 'real' list_of_variables SEMI ; // real r1,r2;
// integer
continuous_assign : 'assign' (delay)? list_of_assignments SEMI // assign #5 w1=a&b; { } ; parameter_override : 'defparam' list_of_param_assignments SEMI g1.width=8, g2.width=4; // defparam
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; list_of_variables : name_of_variable ( COMMA name_of_variable )* ; list_of_register_variables : register_variable ( COMMA register_variable )* // ra,rb,rc ; register_variable : name_of_register // ra | name_of_memory LBRACK expression COLON expression RBRACK i.e. reg [3:0] ram [7:0]; ;
//ram [7:0]
//range : LBRACK expression COLON expression RBRACK // [7:0] , [a+b:a-b] range returns [String value]: LBRACK DIGIT+ COLON DIGIT+ RBRACK { System.out.println("Found Range "+$range.text); $value = $range.text; } ; list_of_assignments : assignment ( COMMA assignment )* ; // Primitive Instances //--------------------------------------------------------------------------gate_declaration : gate_type (delay)? SEMI // not n1(o1,i1), n2(o2,i2); ; gate_instance ( COMMA gate_instance )*
gate_type : 'and'|'nand'|'or'|'nor'|'xor'|'xnor'|'buf'|'not' ; delay : POUND NUMBER | POUND identifier | // #5 or #d1 POUND LPAREN mintypmax_expression ( COMMA mintypmax_expression ( COMMA mintypmax_expression )?)? RPAREN // #(5) , #(5,6), #(5,6,7) ; gate_instance : (name_of_gate_instance)? RPAREN ; terminal : expression ; // Module Instantiations //--------------------------------------------------------------------------module_instantiation : name_of_module module_instance(COMMA module_instance )* SEMI ; LPAREN terminal ( COMMA terminal )*
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module_instance : name_of_instance LPAREN list_of_module_connections RPAREN // g1(a,b,c), g2(.A(a),.B(b) ; list_of_module_connections : module_port_connection ( COMMA module_port_connection )* | named_port_connection ( COMMA named_port_connection )* ; module_port_connection : expression ; // expression below isn't optional according to Palnitkar, but // several examples generated by Cadence use this syntax. named_port_connection : DOT IDENTIFIER LPAREN (expression)? RPAREN // .A(), .B(b) ; // Behavioral Statements //--------------------------------------------------------------------------initial_statement : 'initial' statement ; always_statement : 'always' statement ; statement_or_null : (statement) => statement | SEMI ; statement : (lvalue ASSIGN) => blocking_assignment SEMI | (lvalue LE) => non_blocking_assignment SEMI | conditional_statement | case_statement | loop_statement | procedural_timing_control_statement | wait_statement | event_trigger | seq_block | par_block | task_enable | system_task_enable | disable_statement | procedural_continuous_assignment ;
// a = b&c ; // a <= b&c;
assignment : lvalue ASSIGN expression // a = b+c { TopHandler.CreateAssignStmt($module::modName, $lvalue.text, $expression.text); } ; blocking_assignment : lvalue ASSIGN ( delay_or_event_control )? ; expression
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non_blocking_assignment : lvalue LE ( delay_or_event_control )? ; // "else" clause is inherently ambiguous; ANTLR gets it right, // so suppress warning. conditional_statement : 'if' LPAREN expression RPAREN statement_or_null ('else' statement_or_null)? ;
expression
case_statement : case_keyword LPAREN expression RPAREN (case_item)+ 'endcase' ; case_keyword : 'case' | 'casez' | 'casex' ; case_item : expression (COMMA expression )* COLON statement_or_null | 'default' (COLON)? statement_or_null ; loop_statement : 'forever' statement | 'repeat' LPAREN expression RPAREN statement | // repeat(6) begin ... end 'while' LPAREN expression RPAREN statement | // while(cond) begin... end 'for' LPAREN assignment SEMI expression SEMI assignment RPAREN statement ; procedural_timing_control_statement : delay_or_event_control statement_or_null ; wait_statement : 'wait' LPAREN expression RPAREN statement_or_null ; event_trigger : TRIGGER name_of_event SEMI ; disable_statement : 'disable' IDENTIFIER SEMI ; seq_block : 'begin' ( COLON name_of_block (block_declaration)* )? ; par_block : 'fork' ( COLON name_of_block (block_declaration)* )? (statement)* 'join' ;
(statement)* 'end'
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block_declaration : parameter_declaration | reg_declaration | integer_declaration | real_declaration | time_declaration ; task_enable : name_of_task ( LPAREN expression (COMMA (expression)?)* RPAREN )? SEMI ; system_task_enable : SYSTEM_TASK_NAME (LPAREN expression (COMMA (expression)?)* RPAREN )? SEMI ; procedural_continuous_assignment : 'assign' assignment SEMI | 'deassign' lvalue SEMI | 'force' assignment SEMI | 'release' lvalue SEMI ; delay_or_event_control : delay_control | event_control ;
// Expressions //--------------------------------------------------------------------------lvalue : (identifier range) => identifier range | identifier | concatenation ; // x[3:0] = ... OR x = .. OR {x,y} = .. concatenation : // {x, {y,z[5]}, x[6]} (LCURLY expression LCURLY) => LCURLY expression LCURLY expression ( COMMA expression )* RCURLY RCURLY | LCURLY expression ( COMMA expression )* RCURLY ; mintypmax_expression : expression ( COLON expression COLON expression )? ; exp11 : STRING | NUMBER | (function_call) => function_call | lvalue | DEFINE ; exp12 : exp11 | LPAREN expression RPAREN ; exp9 : exp12 | unary_operator exp9 ; // &a // (a+c)
exp8 : exp9 ( binary_operator exp9 )* ;
// a+b+c&d
exp7 : exp8 ( QUESTION exp7 COLON exp7 )? ;
// (a<b) ? y : z;
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expression : exp7 ; function_call : name_of_function LPAREN expression_list RPAREN | // myfunc(a,b) SYSTEM_TASK_NAME ( LPAREN expression_list RPAREN )? // $monitor(a,b) ; expression_list : expression ( COMMA expression )* ; unary_operator : PLUS | MINUS BXOR | RXNOR ;
| LNOT
| BNOT
| BAND
| RNAND
| BOR
| RNOR
binary_operator : PLUS | MINUS EQUAL | NOT_EQ LOR | LT_ BAND | BOR SL ;
| | | |
STAR EQ_CASE LE BXOR
| | | |
DIV NOT_EQ_CASE GT BXNOR
| | | |
MOD LAND GE SR
| | | |
//--------------------------------------------------------------------------// Identifiers //--------------------------------------------------------------------------name_of_module : name_of_port : name_of_variable : name_of_UDP : name_of_UDP_instance : name_of_event : name_of_task : real_identifier : name_of_memory : net_identifier : name_of_function : specparam_identifier : udp_name_of_port : name_of_register : name_of_gate_instance : name_of_instance : name_of_block : output_terminal_name : local_identifier local_identifier local_identifier local_identifier local_identifier local_identifier local_identifier identifier ; local_identifier identifier ; local_identifier identifier ; identifier ; local_identifier local_identifier local_identifier local_identifier local_identifier ; ; ; ; ; ; ; ; ;
; ; ; ; ;
identifier : identifier_path ; identifier_path : local_identifier ( DOT local_identifier )* ;
//a.b.c
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local_identifier : IDENTIFIER ; delay_control : POUND NUMBER | POUND identifier | POUND LPAREN mintypmax_expression RPAREN ; event_control : AT identifier | // @clk AT LPAREN event_expression RPAREN ;
// @(posedge clk)
event_expression : sub_event_expression ( 'or' sub_event_expression )* or negedge reset) ;
// @(posedge clk
sub_event_expression : expression | 'posedge' expression | 'negedge' expression ; //--------------------------------------------------------------------------// Compiler directives //--------------------------------------------------------------------------directive: define_directive | include_directive ; define_directive : '`define' IDENTIFIER expression ; include_directive : '`include' ( identifier | STRING ) ;
////// SCANNER////// // Operators AT : '@' COLON : ':' COMMA : ',' DOT : '.' ASSIGN : MINUS : '-' LBRACK : RBRACK : LCURLY : RCURLY : LPAREN : RPAREN : POUND : '#' QUESTION : '?'
; ; ; ; '=' ; '[' ']' '{' '}' '(' ')' ; ;
; ; ; ; ; ; ;
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SEMI : PLUS LNOT BNOT BAND RNAND BOR RNOR BXOR BXNOR RXNOR STAR DIV MOD EQUAL NOT_EQ NOT_EQ_CASE EQ_CASE LAND LOR LT_ LE GT GE SR SL TRIGGER PPATH FPATH
';' ; : '+' ; : '!' ; : '~' ; : '&' ; : '~&' ; : '|' ; : '~|' ; : '^' ; : '~^' ; : '~^' | '^~' ; : '*' ; : '/' ; : '%' ; : '==' ; : '!=' ; : '!==' ; : '===' ; : '&&' ; : '||' ; : '<' ; : '<=' ; : '>' ; : '>=' ; : '>>' ; : '<<' ; : '->' ; : '=>' ; : '*>' ;
SYSTEM_TASK_NAME : '$' IDENTIFIER ; DEFINE : '`' IDENTIFIER ; DIGIT : ('0'..'9') ; HEX_DIGIT : ('a'..'f'|'A'..'F') ; protected SIZE : (DIGIT)+ ; fragment SIZED_NUMBER : (SIZE)? BASE SIZED_DIGIT (SIZED_DIGIT | '_')* ; fragment UNSIZED_NUMBER : DIGIT (DIGIT | '_')* ( '.' (DIGIT | '_')* )? (EXPONENT)? NUMBER : ( (SIZE)? BASE SIZED_DIGIT ) => SIZED_NUMBER | UNSIZED_NUMBER ;
protected BASE : '\'' ( 'd' | 'D' | 'h' | 'H' | 'o' | 'O' | 'b' | 'B' ) ; protected SIZED_DIGIT : DIGIT | HEX_DIGIT | 'x' | 'X' | 'z' | 'Z' | '?' ; protected EXPONENT : ('e'|'E') ('+'|'-')? ('0'..'9')+ ;
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IDENTIFIER : ('a'..'z'|'A'..'Z'|'_') ('a'..'z'|'A'..'Z'|'_'|'$'|'0'..'9')* ; COMMENT : '//' ~('\n'|'\r')* '\r'? '\n' {$channel=HIDDEN;} | '/*' ( options {greedy=false;} : . )* '*/' {$channel=HIDDEN;} ; WS : ( | | | ) ' ' '\t' '\r' '\n' {$channel=HIDDEN;}
; STRING : '"' ( ESC_SEQ | ~('\\'|'"') )* '"' ; fragment ESC_SEQ : '\\' ('b'|'t'|'n'|'f'|'r'|'\"'|'\''|'\\') | UNICODE_ESC | OCTAL_ESC ; fragment OCTAL_ESC : '\\' ('0'..'3') ('0'..'7') ('0'..'7') | '\\' ('0'..'7') ('0'..'7') | '\\' ('0'..'7') ; fragment UNICODE_ESC : '\\' 'u' HEX_DIGIT HEX_DIGIT HEX_DIGIT HEX_DIGIT ;
(Retrieved from http://www.antlr.org/grammar/verilog/verilog.g)
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//*********************TEST.JAVA*************************************// package com.javadude.antlr3x; import java.io.IOException; import java.util.List; import import import import import org.antlr.runtime.ANTLRStringStream; org.antlr.runtime.CharStream; org.antlr.runtime.CommonTokenStream; org.antlr.runtime.TokenStream; org.antlr.runtime.RecognitionException;
public class Test { public static void main(String[] args) throws IOException { CharStream charStream = new ANTLRStringStream("module TOP(in1,in2,bidir1,out);" + "input [7:0] in1,in2;"+ "inout [3:0] bidir1;"+ "output [3:0] out;"+ "reg [5:0] ra,rb;"+ "wire [9:0] w1,w2;"+ "assign out = ~in1;"+ "assign ra = ~in1;"+ "assign in1 = ~in2;"+ "endmodule" + "\n"+ //"module CHILD(clk, ena,out);" + //"input clk,ena;"+ //"output out;"+ //"assign out = ~clk&ena;"+ //"endmodule" + "\n"); verilogLexer lexer = new verilogLexer(charStream); TokenStream tokenStream = new CommonTokenStream(lexer); verilogParser parser = new verilogParser(tokenStream); try { // Generate netlist parser.source_text(); //Start Parsing //Elaborate & Translate TopHandler.PrintModules(); TopHandler.DumpCPP(); } catch(RecognitionException ex){ System.out.println("Exception caught"); } } }
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//***********************NETLIST.JAVA********************************//
package com.javadude.antlr3x; import java.io.BufferedWriter; import java.io.FileNotFoundException; import java.io.FileOutputStream; import java.io.FileWriter; import java.io.IOException; import java.io.OutputStream; import java.util.*; class VRange { // To Model 7:0 VRange(int left , int right){ if (left > right) { dir = new String("down"); lower = right; upper = left; } else { dir = new String("up"); upper = left; lower = right; } System.out.println("Created Range ["+left+":"+right+"]"); } int lower; int upper; String dir; // UP or Down } class VVar { // Register, Wire etc. String name; VRange range; } class VRegVar extends VVar { public VRegVar(String n) { name = n; } } class VWireVar extends VVar { public VWireVar(String n){ name=n; } } class VPort extends VVar{ // Port public VPort(String n) { name =n; } String direction; // input/output/inout }
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class VExpr { String operator; VExpr op1; VExpr op2; } class VStmt { } // assign a = b+c class VAssignStmt extends VStmt { VVar dest; VExpr src; } class VCondAssignStmt extends VAssignStmt { }
class VModule { String name; List portList; // Portlist List regList; List wireList; List concurStmt; public VPort FindPort(String pname) { ListIterator piter = portList.listIterator(); for(; piter.hasNext();){ VPort port = (VPort)piter.next(); if (port.name.equals(pname)){ return port; } } return null; } public VRegVar FindReg(String rname) { ListIterator riter = regList.listIterator(); for(; riter.hasNext();){ VRegVar reg = (VRegVar)riter.next(); if (reg.name.equals(rname)){ return reg; } } return null; } public VWireVar FindWire(String wname) { ListIterator witer = wireList.listIterator(); for(; witer.hasNext();){ VWireVar wire = (VWireVar)witer.next(); if (wire.name.equals(wname)){ return wire; }
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} return null; } }
class TopHandler { static List modList = new LinkedList(); static boolean debug= false; static VModule FindModule(String modName) { VModule mod=null; ListIterator miter = modList.listIterator(); boolean found = false; for(; miter.hasNext();){ mod = (VModule)miter.next(); if (mod.name.equals(modName)){ found = true; break; } } if (found){ return mod; } else { System.out.println("No such module "+ modName+" found"); } return null; }
static void CreatePort(String modName, String name) { if (debug) { System.out.println("Creating Port "+name+" In module " + modName); } VPort port = new VPort(name); VModule mod = FindModule(modName); if (mod.portList == null) { mod.portList = new LinkedList(); } mod.portList.add(port); } static void CreateReg(String modName, String names) { // names is list of registers separated by comma. i.e ra,rb.. String [] name_array = names.split(","); // ra,rb => ra rb VModule mod = FindModule(modName); if (mod.regList == null) { mod.regList = new LinkedList(); } for (int i=0; i<name_array.length; i++) { VRegVar rv = new VRegVar(name_array[i]); mod.regList.add(rv); } }
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// Returns Last wire static VWireVar CreateWire(String modName, String names) { // names is list of registers separated by comma. i.e wa,wb.. String [] name_array = names.split(","); // wa,wb => wa wb VModule mod = FindModule(modName); VWireVar wv=null; if (mod.wireList == null) { mod.wireList = new LinkedList(); } for (int i=0; i<name_array.length; i++) { wv = new VWireVar(name_array[i]); mod.wireList.add(wv); } return wv; }
static VRange CreateRange(String rangeVal) { //[7:0] String [] values = rangeVal.split(":"); // values[0] == [7, values [1] == 0] String sv0 = values[0].replace('[','0'); // [7 => 7 String sv1 = values[1].replace(']','0'); // 0] => 0 int v0 = Integer.parseInt(sv0); int v1 = (Integer.parseInt(sv1))/10; VRange rangeObj = new VRange(v0, v1); return rangeObj; } static void SetPortDir(String modName, String pname, String dir) { VPort port = null; boolean found = false; VModule mod = FindModule(modName); String [] names = pname.split(","); // clk,ena => clk ena for (int i=0; i<names.length; i++) { port = mod.FindPort(names[i]); if (port != null) { port.direction = dir; } else { System.out.println("@ERROR : No such port "+names[i]+" exists in port list"); } } } static void SetPortRange(String modName, String pname, VRange range) { VModule mod = FindModule(modName); if (mod == null) { System.out.println("@ERROR : No such module"); return; }
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String [] names = pname.split(","); // clk,ena => clk ena for (int i=0; i<names.length; i++) { VPort port = mod.FindPort(names[i]); if (port != null) { port.range = range; } } } static void SetRegRange(String modName, String pname, VRange range) { VModule mod = FindModule(modName); if (mod == null) { System.out.println("@ERROR : No such module"); return; } String [] names = pname.split(","); // clk,ena => clk ena for (int i=0; i<names.length; i++) { VRegVar reg = mod.FindReg(names[i]); if (reg != null) { reg.range = range; } } } static void SetWireRange(String modName, String pname, VRange range) { VModule mod = FindModule(modName); if (mod == null) { System.out.println("@ERROR : No such module"); return; } String [] names = pname.split(","); // clk,ena => clk ena for (int i=0; i<names.length; i++) { VWireVar wire = mod.FindWire(names[i]); if (wire != null) { wire.range = range; } } } // Object Type will contain either port/wire/reg static void SetRange(String modName, String range, String objname, String objtype){ VRange rangeObj = CreateRange(range); if (objtype.equals("port")) { SetPortRange(modName, objname, rangeObj); } else if (objtype.equals("reg")) { SetRegRange(modName, objname, rangeObj); } else if (objtype.equals("wire")){ SetWireRange(modName, objname, rangeObj); } } static void CreateModule(String name){ if (debug) { System.out.println("Creating Module "+name);
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} VModule mod = new VModule(); mod.name = name; modList.add(mod); } static VExpr CreateExpr(String exprStr){ VExpr expr = new VExpr(); // TODO return expr; } static void CreateAssignStmt(String modName, String dest, String srcExpr){ VModule mod = FindModule(modName); VWireVar wire = mod.FindWire(dest); VVar destVar = null; boolean foundDest = false; if (wire != null){ destVar = wire; foundDest = true; } else { VPort port = mod.FindPort(dest); if (port != null){ if (port.direction.equals("input")){ System.out.println("ERROR: Target of assign stmt "+dest+" cannot be input port"); return; } destVar = port; foundDest = true; } else { VRegVar reg = mod.FindReg(dest); if (reg != null) { System.out.println("ERROR: Target of assign stmt "+dest+" has to be wire type"); return; } } } if (!foundDest) { wire = CreateWire(modName, dest); destVar = wire; } VAssignStmt stmt = new VAssignStmt(); stmt.dest = destVar; stmt.src = CreateExpr(srcExpr); System.out.println("Creating assign "+dest+"="+srcExpr); } static void PrintModules(){ ListIterator iter = modList.listIterator();
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for(; iter.hasNext();){ VModule mod = (VModule) iter.next(); System.out.println("MODULE = "+mod.name); ListIterator piter = mod.portList.listIterator(); System.out.print("PORTS = "); for(; piter.hasNext();){ VPort port = (VPort)piter.next(); System.out.print(port.direction ); if (port.range != null) { System.out.print("[" +port.range.upper+":"+port.range.lower+"] "); } System.out.print(" " +port.name+","); } System.out.print("\n"); ListIterator riter = mod.regList.listIterator(); System.out.print("REGISTERS = "); for(; riter.hasNext();){ VRegVar reg = (VRegVar)riter.next(); if (reg.range != null) { System.out.print("[" +reg.range.upper+":"+reg.range.lower+"] "); } System.out.print(" " +reg.name+","); } System.out.print("\n"); ListIterator witer = mod.wireList.listIterator(); System.out.print("WIRES = "); for(; witer.hasNext();){ VWireVar wire = (VWireVar)witer.next(); if (wire.range != null) { System.out.print("[" +wire.range.upper+":"+wire.range.lower+"] "); } System.out.print(" " +wire.name+","); } System.out.print("\n"); } } static void DumpCPP() throws IOException{ try { BufferedWriter out = new BufferedWriter(new FileWriter("test2.c")); ListIterator miter = modList.listIterator(); for(; miter.hasNext();){ VModule mod = (VModule) miter.next(); out.write("void "+mod.name+"("); ListIterator piter = mod.portList.listIterator(); boolean first=true;
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for(; piter.hasNext();){ *out){
// void top(int *in, int
VPort port = (VPort)piter.next(); if (first){ out.write("int *"+port.name); first = false; }else { out.write(",int *"+port.name); } } out.write(") {\n"); ListIterator witer = mod.wireList.listIterator(); for(; witer.hasNext();){ VWireVar wire = (VWireVar)witer.next(); out.write("int *"+wire.name+";\n"); // int w1; } // // // // // // // // ListIterator citer = mod.concurStmt.listIterator(); for(; citer.hasNext();){ VAssignStmt stmt = (VAssignStmt)citer.next(); String dst = stmt.dest.name; String src="Hi"; String src= stmt.src.toString(); out.write(dst+"="+src+";\n"); } out.write("}"); } out.close(); } catch (FileNotFoundException e) { // TODO Auto-generated catch block e.printStackTrace(); } } }
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16 APPENDIX D
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17 APPENDIX E
Verilog code // This is ENG-R298 project // This is design of a microcontroller which can run at speed of 1GHz speed // The objective for this project is to equire the market of lower end FPGA //--------------------------------------------------------------------------// // This is the module of CPU // most of control signals are controlled by CPU // // Creater: Team # 3 (Piyush, Nagendra, Ipsita) module CPU (clk, mcu_reset, mcu_enable, IO_port0, IO_port1, IO_port2, IO_port3, mcu_inst ); // Below are the parameters to be used parameter mcu_data_width = 8; parameter rom_adrs_width = 8; parameter mcu_inst_width = 32; parameter rom_depth = 256; parameter reg_bank_adrs_width = 8; parameter reg_bank_adrs_depth = 256; parameter SFR_reg_depth = 16; // Following are the parameters for decoding phase parameter opcode_lenght = 6; parameter decisionbox_sel_lenght = 5; parameter mod_bits_lenght = 3; parameter desti_adrs_length = 8; parameter source_adrs_lenght = 8; ////////////////////////////////////////////////////// input clk; input mcu_reset; input mcu_enable; //inout [mcu_data_width-1:0] mcu_IO[0:3]; input [mcu_data_width-1:0] IO_port0; input [mcu_data_width-1:0] IO_port1; input [mcu_data_width-1:0] IO_port2; input [mcu_data_width-1:0] IO_port3; output [mcu_inst_width-1:0] mcu_inst; // Defining output register wire [mcu_data_width-1:0] IO_port0; wire [mcu_data_width-1:0] IO_port1; wire [mcu_data_width-1:0] IO_port2; wire [mcu_data_width-1:0] IO_port3; reg [mcu_inst_width-1:0] mcu_inst; // Definnig a register bank and special registers
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reg [mcu_inst_width-1:0] rom [0:rom_depth-1]; // This is inbuilt ROM reg [reg_bank_adrs_width-1:0] reg_bank [0:reg_bank_adrs_depth-1]; // This is inbuilt register bank reg [reg_bank_adrs_width-1:0] SFR_reg [0:SFR_reg_depth-1]; `define SFR_reg[0] ALU_status_reg; reg [reg_bank_adrs_width-1:0] ALU_status_reg; // For ALU operation {black_box_op_flag, branch_op_flag, ALU_op_flag, Sign_flag, Overflow_flag, Zero_flag, borrow_flag, Carry_flag} reg [reg_bank_adrs_width-1:0] Branch_status_reg; // For Branch operation {reserve, reserve, reserve, jump_flag, less_than_flag, greater_than_flag, not_equal_flag, equal_flag} reg [mcu_data_width-1:0] branch_operation_result; // Storing branch operation result in this reg reg [31:0] IO_for_mux; // Defining general purpose registers reg [rom_adrs_width-1:0]prog_counter; // Program code starts here
initial begin prog_counter = 8'b00000000; mcu_inst = 32'hxxxxxxxx; // fetch_done = 1'b1; end initial begin $readmemh("inst.txt",rom);
// Reading text file to use as data of ROM // This data is the instructions for controller
$readmemh("reg_bank.txt",reg_bank); end // The following block is fetch phase // In this phase instruction is being loaded to ROM register from inst.text using "$readmemh" always @(posedge clk) begin if(mcu_reset == 1'b1) begin prog_counter = 8'b00000000; mcu_inst = 32'hxxxxxxxx; ALU_status_reg = 8'b00000000; branch_operation_result = 8'b00000000; end else if(mcu_enable == 1'b1 && mcu_reset == 1'b0) begin mcu_inst = rom [prog_counter]; prog_counter = prog_counter + 1; ALU_status_reg[5] = 1'b0; // Set ALU enable flag ALU_status_reg[6] = 1'b0; // Reset branch operation flag ALU_status_reg[7] = 1'b0; // Reset decisionbox operation flag IO_for_mux = {IO_port3,IO_port2,IO_port1,IO_port0}; end else begin
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prog_counter = 8'b00000000; mcu_inst = 32'hxxxxxxxx; end end // Defining registers for decoding phase reg [opcode_lenght-1:0] opcode; reg [decisionbox_sel_lenght-1:0] decisionbox_sel; reg [mod_bits_lenght-1:0] mod_bits; reg [desti_adrs_length-1:0] destination_address; reg [source_adrs_lenght-1:0] source_address; reg [mcu_data_width-1:0] source_data; reg [mcu_data_width-1:0] destination_data; // The following block is decode the instruction phase always@(mcu_inst) begin opcode = mcu_inst[31:26]; decisionbox_sel = mcu_inst[25:21]; mod_bits = mcu_inst[20:18]; destination_address = mcu_inst[15:8]; source_address = mcu_inst[7:0]; // Decoding MOD bits and taking data for R1 and R2 case(mod_bits) 3'b000: begin // Reg (S) & Reg (D) -----> Reg (S) source_data = reg_bank[source_address]; destination_data = reg_bank[destination_address]; end 3'b001: begin // Immediate(S) & Reg(D) ------> Reg(D) source_data = source_address; destination_data = reg_bank[destination_address]; end /* ////
Following MOD are for future expantion 3'b010: begin // Port(S) & Reg(D) ------> Reg(D) source_data = IO_port[source_address]; destination_data = reg_bank[destination_address]; end 3'b011: begin // Reg(S) & Port(D) ------> Port(D) source_data = reg_bank[source_address]; destination_data = reg_bank[destination_address]; end 3'b100: begin // Rom (S) & Reg (D) -----> Reg (D) source_data = rom[source_address]; destination_data = reg_bank[destination_address]; end
*/ default : $display("Error in MOD bits"); endcase
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case(opcode[5:4]) 2'b00: begin ALU_status_reg[5] = 1'b1; ALU_status_reg[6] = 1'b0; flag ALU_status_reg[7] = 1'b0; operation flag end 2'b10: begin ALU_status_reg[6] = 1'b1; ALU_status_reg[5] = 1'b0; ALU_status_reg[7] = 1'b0;
// Set ALU enable flag // Reset branch operation // Reset decisionbox
// Set branch operation flag // Reset ALU enable flag // Reset decisionbox
operation flag end 2'b11: flag
begin ALU_status_reg[7] = 1'b1; ALU_status_reg[5] = 1'b0; ALU_status_reg[6] = 1'b0;
// Set decisionbox operation // Reset ALU enable flag // Reset branch operation
flag end default : begin ALU_status_reg[5] = 1'b0; ALU_status_reg[6] = 1'b0; ALU_status_reg[7] = 1'b0; $display("No opcode available"); end endcase end ///////////////////////////////////////////////////////////////////////////// ////// // Following is calling ALU module to perform ALU operations according to opcode wire alu_op_done; wire [mcu_data_width-1:0] alu_result_data; wire c_out; ALU ALU(.opcode(opcode), .alu_in1(source_data), .alu_in2(destination_data), .alu_enable(ALU_status_reg[5]), .c_in(ALU_status_reg[0]), .alu_op_done(alu_op_done), .alu_result_data(alu_result_data), .c_out(c_out) ); // ALU module ending here ////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////// //////////// Write back the result of ALU operation ////////////// ///////////////////////////////////////////////////////////////////// always@(alu_result_data && ALU_status_reg[5]) //always@(alu_op_done) begin // if(ALU_status_reg[5]) begin if(opcode == 6'b001111) begin // This is for go to instruction prog_counter = destination_address; end else begin case(mod_bits) 3'b000: begin // Reg (S) & Reg (D) -----> Reg (S) reg_bank[destination_address] = alu_result_data; ALU_status_reg[0] = c_out; end 3'b001: begin // Immediate(S) & Reg(D) ------> Reg(D) reg_bank[destination_address] = alu_result_data; ALU_status_reg[0] = c_out; end /* /////
Following MOD are for future expantion 3'b010: begin // Port(S) & Reg(D) ------> Reg(D) source_data = IO_port[source_address]; destination_data = reg_bank[destination_address]; end 3'b011: begin // Reg(S) & Port(D) ------> Port(D) source_data = reg_bank[source_address]; destination_data = reg_bank[destination_address]; end 3'b100: begin // Rom (S) & Reg (D) -----> Reg (D) source_data = rom[source_address]; destination_data = reg_bank[destination_address]; end
*/ endcase end end //////////////////////////////////////////////////////////////////////////// Branch instruction operation without using decisionbox ///// ///////////////////////////////////////////////////////////////////////// wire [mcu_data_width-1:0] branch_operation_flag; ////////////////////////////////////////////////////////// // branch_operation_flag[0] = equal flag // branch_operation_flag[1] = not equal flag // branch_operation_flag[2] = greater than flag
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// branch_operation_flag[3] = less than flag // branch_operation_flag[4] = jump flag (if set then jump o destination address) /////////////////////////////////////////////////////////// branch_operation branch_op(.opcode(opcode), .branch_data1(source_data), .branch_data2(destination_data), .branch_op_enable(ALU_status_reg[6]), .branch_result_data(branch_operation_flag) ); ///////////////////////////////////////////////////////////////////////// always@(branch_operation_flag or destination_address) begin Branch_status_reg = branch_operation_flag; if(branch_operation_flag[4] == 1'b1) begin prog_counter = destination_address; end end //////////////////// Decision_box module calling ////////////////// wire [source_adrs_lenght-1:0] new_destination_address; decisionbox decisionbox(.decisionbox_enable(ALU_status_reg[7]), .opcode(opcode), .decisionbox_sel(decisionbox_sel), .IO_data(IO_for_mux), .destination_address(destination_address), .new_destination_address(new_destination_address) ); always @(new_destination_address && ALU_status_reg[7]) begin if(ALU_status_reg[7] == 1'b1) begin prog_counter = new_destination_address; end end ////////////////////////////////////////////////////// endmodule
// In this file ALU module is created which will perform operation after // decoding instruction // Implementation left : // Have to implement c_out, borrow_in, borrow_out module ALU(opcode, alu_in1, alu_in2, alu_enable, c_in, alu_op_done, alu_result_data, c_out ); parameter mcu_data_width = 8; parameter opcode_lenght = 6;
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input [opcode_lenght-1:0] opcode; input [mcu_data_width-1:0] alu_in1; input [mcu_data_width-1:0] alu_in2; input alu_enable; input c_in; output alu_op_done; output [mcu_data_width-1:0] alu_result_data; output c_out; reg alu_op_done; reg [mcu_data_width-1:0] alu_result_data; reg c_out; always@(alu_enable) begin alu_result_data = 8'bxxxxxxxx; // Following opcode are only for ALU operation case(opcode) 6'b000000: begin // 0) MOV (mov data from source address to destination address) {c_out, alu_result_data} = {1'b0, alu_in1}; end 6'b000011: begin // 3) ADD (Add souce data and destination data and store to destination address) {c_out, alu_result_data} = alu_in1 + alu_in2; end 6'b000100: begin // 4) SUB (Sub source data- destination data and store to destination address) {c_out, alu_result_data} = alu_in1 - alu_in2; end // 6'b000101: begin // 5) ADD with carry (Add two data and also ad carry to the result and store result at destination address) // end
6'b000110: begin // 6) NOT (Invert source data and store to destination address) {c_out, alu_result_data} = {1'b0, ~alu_in1}; end 6'b000111: begin // 7) AND (Logical ANDing between source data and destination data aand storing to destination address ) {c_out, alu_result_data} = {1'b0, alu_in1 & alu_in2}; end 6'b001000: begin // 8) OR (Logical OR between source data & destination data)
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{c_out, alu_result_data} = {1'b0, alu_in1 | alu_in2}; end 6'b001001: begin // 9) XOR (Logical XOR between source data & destination data) {c_out, alu_result_data} = {1'b0, alu_in1 ^ alu_in2}; end 6'b001010: begin // 10) SR (Shift right source data and store to destination address) {c_out, alu_result_data} = {1'b0, 1'b0, alu_in1[7:1]}; // Tested end 6'b001011: begin // 11) SL (Shift left source data and store in destination address) {c_out, alu_result_data} = {1'b0, alu_in1[6:0], 1'b0}; // Tested end 6'b001100: begin // 12) SRR (Shift rotate right source data and store to destinatino address) {c_out, alu_result_data} = {alu_in1[0], c_in, alu_in1[7:1]}; end 6'b001101: begin // 13) SRL (Shift rotate left source data and store to destination adddress) {c_out, alu_result_data} = {alu_in1[7], alu_in1[6:0], end // This opcode is temporary
c_in};
6'b001111: begin // 14) Jump Will have to chage it to 011111
alu_result_data = 8'b00000000; end default : $display("Error in Opcode"); endcase assign alu_op_done = 1'b1; end endmodule
// Tested
///////// This is module for branch instruction operation without using // decisionbox //////////// ///////// The output result will executed by setting the status flags ///////// In this code the instruction for comparing equal,less than, greater than will be executed ///////
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///////// ////////
The result of it will be in the form of flags of status register
module branch_operation(opcode, branch_data1, branch_data2, branch_op_enable, branch_result_data ); parameter mcu_data_width = 8; parameter opcode_lenght = 6; input [opcode_lenght-1:0] opcode; input [mcu_data_width-1:0] branch_data1; input [mcu_data_width-1:0] branch_data2; input branch_op_enable; output [mcu_data_width-1:0] branch_result_data; reg [mcu_data_width-1:0] branch_result_data; /////////////////////////////////////////////////////////////// // branch_result_data[0] = equal flag // branch_result_data[1] = not equal flag // branch_result_data[2] = greater than flag // branch_result_data[3] = less than flag // branch_result_data[4] = jump in next instruction flag ///////////////////////////////////////////////////////////////////////////// //// always@(branch_op_enable) begin case(opcode) // Following are branch instructions 6'b100000: begin // compare Rs(Source reg) with zero if(branch_data1 == 8'b00000000) begin branch_result_data = 8'b00000001; end else begin branch_result_data = 8'b00000010; end end 6'b100001: begin // compare Rd(Destination reg) with zero if(branch_data2 == 8'b00000000) begin branch_result_data = 8'b00000001; end else begin branch_result_data = 8'b00000010; end
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end 6'b100010: begin // compare Rs(source reg) with Rd(Destination reg) if(branch_data1 == branch_data2) begin
branch_result_data = 8'b00000001; end else if(branch_data1 != branch_data2 && branch_data1 > begin branch_result_data = 8'b00000110; end else begin//if(branch_data1 != branch_data2 && branch_data1 > branch_data2) begin branch_result_data = 8'b00001010; end /* else begin branch_result_data = 8'b00000010; end
branch_data2)
if(branch_result_data[1] == 1'b1) if(branch_data1 > branch_data2)
begin begin
branch_result_data[3:2] = 2'b01; end else begin branch_result_data[3:2] = 2'b10; end end */ end
6'b100011: begin // set jump bit if Rs > Rd ; Jump adress must be given in next instruction if(branch_data1 == branch_data2) begin
branch_result_data = 8'b00000001; end else if(branch_data1 != branch_data2 && branch_data1 > begin branch_result_data = 8'b00010110; end
branch_data2)
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else begin//if(branch_data1 != branch_data2 && branch_data1 > branch_data2) begin branch_result_data = 8'b00001010; end end 6'b100100: begin // set jump bit if Rs < Rd ; Jump adress must be given in next instruction if(branch_data1 == branch_data2) begin branch_result_data = 8'b00000001; end else if(branch_data1 != branch_data2 && branch_data1 < begin branch_result_data = 8'b00011010; end else begin
branch_data2)
branch_result_data = 8'b00000110; end
end 6'b100101: begin // set jump bit if Rs = Rd ; Jump adress must be given in next instruction if(branch_data1 == branch_data2) begin
branch_result_data = 8'b00010001; end else begin branch_result_data = 8'b00000010; end begin //if(branch_data1 != branch_data2)
end 6'b100111: begin // set jump bit if Rs != Rd ; Jump adress must be given in next instruction if(branch_data1 != branch_data2) begin
branch_result_data = 8'b00010010; end else && branch_data1 < branch_data2) begin //if(branch_data1 != branch_data2 begin
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branch_result_data = 8'b00000001; end
end
/// The opcode with format of 10XXXX can be used for this module for future expantion
default : $display("Error in Opcode");
endcase end endmodule
// This is the module for decisionbox // Have to read data from external text file for reg "decisionbox_memory" //and change value for new address module decisionbox(decisionbox_enable, opcode, decisionbox_sel, IO_data, destination_address, new_destination_address ); parameter decisionbox_sel_lenght = 5; parameter source_adrs_lenght = 8; parameter opcode_lenght = 6; input decisionbox_enable; input [opcode_lenght-1:0] opcode; input [decisionbox_sel_lenght-1:0] decisionbox_sel; input [31:0]IO_data; input [source_adrs_lenght-1:0] destination_address; output [source_adrs_lenght-1:0] new_destination_address; reg [source_adrs_lenght-1:0] new_destination_address; wire [4:0]temp_new_address_bits; wire [4:0]new_address_bits; reg [34:0] decisionbox_memory[0:127]; reg [34:0] decisionbox_memory_reg; initial begin $readmemh("decisionbox_memory.txt",decisionbox_memory); end always@(decisionbox_enable == 1'b1) begin if(opcode == 6'b111111) begin
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// new_destination_address = 32'h00000000; decisionbox_memory_reg = decisionbox_memory[decisionbox_sel]; end end always@(new_address_bits) begin
new_destination_address = {destination_address[7:5], new_address_bits[4], new_address_bits[3], new_address_bits[2], new_address_bits[1], new_address_bits[0]};
end /* always@(new_address_bits[0] & new_address_bits[1] & new_address_bits[2] & new_address_bits[3] & new_address_bits[4]) begin new_source_address = {source_address[7:5], new_address_bits[4], new_address_bits[3], new_address_bits[2], new_address_bits[1], new_address_bits[0]}; end */ mux m0(.mux_ip(IO_data), .mux_sel(decisionbox_memory_reg[4:0]), .mux_op(temp_new_address_bits[0]) ); mux m1(.mux_ip(IO_data), .mux_sel(decisionbox_memory_reg[11:7]), .mux_op(temp_new_address_bits[1]) ); mux m2(.mux_ip(IO_data), .mux_sel(decisionbox_memory_reg[18:14]), .mux_op(temp_new_address_bits[2]) ); mux m3(.mux_ip(IO_data), .mux_sel(decisionbox_memory_reg[25:21]), .mux_op(temp_new_address_bits[3]) ); mux m4(.mux_ip(IO_data), .mux_sel(decisionbox_memory_reg[32:28]), .mux_op(temp_new_address_bits[4]) );
set_reset s0(.ip_bit(temp_new_address_bits[0]),
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.anding_bit(decisionbox_memory_reg[5]), .exor_bit(decisionbox_memory_reg[6]), .result_bit(new_address_bits[0]) ); set_reset s1(.ip_bit(temp_new_address_bits[1]), .anding_bit(decisionbox_memory_reg[12]), .exor_bit(decisionbox_memory_reg[13]), .result_bit(new_address_bits[1]) ); set_reset s2(.ip_bit(temp_new_address_bits[2]), .anding_bit(decisionbox_memory_reg[19]), .exor_bit(decisionbox_memory_reg[20]), .result_bit(new_address_bits[2]) ); set_reset s3(.ip_bit(temp_new_address_bits[3]), .anding_bit(decisionbox_memory_reg[26]), .exor_bit(decisionbox_memory_reg[27]), .result_bit(new_address_bits[3]) ); set_reset s4(.ip_bit(temp_new_address_bits[4]), .anding_bit(decisionbox_memory_reg[33]), .exor_bit(decisionbox_memory_reg[34]), .result_bit(new_address_bits[4]) ); endmodule /// This module is used for decision box /// This module return bit value
module set_reset(ip_bit, anding_bit, exor_bit, result_bit );
input ip_bit; input anding_bit; input exor_bit; output result_bit; reg result_bit; always@(ip_bit or anding_bit or exor_bit) begin result_bit = (ip_bit & anding_bit) ^ exor_bit; end endmodule
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module mux(mux_ip, mux_sel, mux_op );
input [31:0]mux_ip; input [4:0]mux_sel; output mux_op; reg mux_op; always@(mux_ip or mux_sel) //always@(mux_sel) begin mux_op = mux_ip[mux_sel];
end endmodule
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18 APPENDIX F
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Cost Effective Reconfigurable Logic

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Cost Effective Reconfigurable Logic Final Project Report Presented to The Faculty of the Department of General Engineering San

University Reader Professor Morris Jones Electrical Engineering Department

APPROVED FOR THE DEPARTMENT OF GENERAL ENGINEERING

Piyush Patel Ipsita Praharaj Nagendra Donepudi

Microcontroller Features Figure 1: Microcontroller in FPGA graph

Preliminary Literature Review

Technical details of the Project

System Design methodology

Parser AST Tree walker

symbol, table, flow graph

Figure 7: Overall translation data

5. Debugger for grammar errors

Architecture of ANTLR compiler

Figure 8: Architecture of ANTLR compiler module

Figure 9: AST generated by ANTLR

Figure 10: Close up view of AST

Microcontroller design flow

8.3 Solution and Value proposition

PDA 0% Cellphones 60% Handhelds 3%

2010 $100,000 $50,000 $80,000 $15,000 $10,000 $15,000

2011 $100,000 $50,000 $100,000 $17,000 $14,000 $5,000

2012 $100,000 $50,000 $100,000 $20,000 $19,000 $5,000

2013 $100,000 $50,000 $110,000 $25,000 $21,000 $8,000

2014 $100,000 $50,000 $110,000 $25,000 $21,000 $8,000

2015 $100,000 $50,000 $140,000 $27,000 $25,000 $10,000

2016 $100,000 $50,000 $140,000 $27,000 $25,000 $10,000

$21,000 $5,000 $500,000 $400,000 $60,000 $2,000

$25,000 $6,600 $760,000 $550,000 $30,000 $2,000

$30,000 $7,200 $980,000 $600,000 $30,000 $3,500

Table 5: Employee Wages 8.7.3 Variable cost

$1,100,000 $1,500,000 $2,600,000 $4,040,000 $150,000 $180,000

$13,000,000 $16,500,000 $250,000 $300,000

Table 8: SWOT assessment

Table 9: Human Resources

2010 2011 2012 2013 2014 2015 2016 2017

Table 10: Profit/Loss

Return on investment is the ratio of the investment and the profit.

8.17 Exit Strategy

Figure 18: Project Schedule 10 Conclusion

Set up ANTLR environment:

Set up eclipse by downloading Eclipse Classic 3.5.1(162MB) distribution from www.eclispe.org.

Run the test case to check the AST formation

Supported Verilog Constructs

(Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors)

(Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors)

(Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors)

Unsupported Verilog Constructs

Behavioral modeling Specify blocks

Time Real numbers Events parameter(defparam) Loops(forever) Ignored by parser

(Retrieved from http://www.cse.iitk.ac.in/~moona/students/Y1147043.pdf, redrawn by authors)

net_declaration directive | parameter_declaration gate_declaration | parameter_override initial_statement function ;

| integer_declaration | real_declaration | instantiation | | continuous_assign | | always_statement | task |

// a = b&c ; // a <= b&c;

exp8 : exp9 ( binary_operator exp9 )* ;

exp7 : exp8 ( QUESTION exp7 COLON exp7 )? ;

binary_operator : PLUS | MINUS EQUAL | NOT_EQ LOR | LT_ BAND | BOR SL ;

STAR EQ_CASE LE BXOR

DIV NOT_EQ_CASE GT BXNOR

identifier : identifier_path ; identifier_path : local_identifier ( DOT local_identifier )* ;

event_expression : sub_event_expression ( 'or' sub_event_expression )* or negedge reset) ;

; ; ; ; '=' ; '[' ']' '{' '}' '(' ')' ; ;

(Retrieved from http://www.antlr.org/grammar/verilog/verilog.g)

for(; piter.hasNext();){ *out){