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Introduction Background Work Memory : A Yield Limiter Component Proposed Cache-based Memory Repair Architecture Repair Analysis Overheads Conclusion
References
Introduction
Escalate 90% of the die by 2014 Problems to be addressed asap Susceptible to spot defects than logic Moores law
Background Work
Repair Processes
Automated test equipment (ATE) Captures response Applied externally or via bist circuitry Processes data Allocates spare resources
Background Work
Characterizing Memory Repair Architecture
Allocation scheme
Remaps process and the associated routing circuitry that redirects the read/write requests from the faulty parts to the spare resources.
Spares usage ratio It concerns how much of the redundant resources could potentially be expended on repairing a faulty part i.e. the efficiency
Variability Common denominator of continuous scaling beyond 90 nm era and processing complexity required to attend this trend within given specifications Eg :- 6T SRAM cell Symmetrical back-to-back inverter structure Functional errors (e.g., the cell flips on word line activation during a read access or over time, inability to write)
Parametric errors (e.g., unable to develop the required bitline differential voltage in given wordline activation time)
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Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,, vol. 20, no. 12, Dec 2012 8
Repair Analysis
Random Faults- mathematical analysis
Repair Analysis
Probability of fault free 64 Mbit cell array with random fault spread, a) without any repair features, and b) with the proposed scheme. a) no redundancy (Pnr) b) with PR(64) P7
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,, vol. 20, no. 12, Dec 2012
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Repair process using (a) 6LSBs from A, failing to repair most faults and (b) the proposed index but allocation scheme ( 3LSBs from Ar and 3LSBs from Ac) repairing the majority of faults
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,, vol. 20, no. 12, Dec 2012 11
7 Probability of fault free 64 Mbit cell array assuming three fault clustering probabilities (top cp=0.1, middle cp=0.5, bottom cp=0.9) and (a) without repair features, (b) with the proposed scheme and the MURs address LSBs and (c) with the proposed index bit allocation and repair procedure
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr. 13 (VLSI) Syst.,, vol. 20, no. 12, Dec 2012
Overheads The cache banks and the MURs have been modeled at 32 nm process using CACTI BIST circuitry_ March C- algorithm to support ABS circuitry
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Penalty of 1 MUX delay find the faulty rows repair faulty rows March c- test requires 10N time to run
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Fault-tolerant memories utilizes A spare row/columns scheme with a BIRA algorithm (optimizes spare allocation) CAM memory (replace the faulty words/bits of the MUR array)
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Conclusion
Set of small cache banks for repairing faulty words on memory cores Optimized statistical and mathematical probability analysis to increase Reparability and reduce overheads Fault clustering and index bit allocation scheme_immune to clustering effect Very high repair coverage for high defect densities at low area and Static power dissipation overhead
References
Nicholas Axelos, Kiamal Pekmestzi, and Dimitris Gizopoulos Efficient Memory Repair Using Cache-Based Redundancy IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,, vol. 20, no. 12, Dec 2012
S.-K. Lu, C.-L. Yang, Y.-C. Hsiao, and C.-W. Wu, Efficient BISR techniques for embedded memories considering cluster faults, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 184193, Feb. 2010
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