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DESCRIPTION FEATURES
The ES4008 home theater digital audio processor is a • Single-chip digital audio processor.
single-chip digital audio decoder for audio stream data • 6.1-channel audio outputs.
processing to provide 6.1 channel high-quality analog
audio output and digital audio output for A/V receiver and
• Integrated high-speed I2S serial bitstream interface.
other audio-decoder applications. • Dolby Digital (AC-3).
The ES4008 is built on the ESS proprietary dual CPU • Dolby Pro Logic.
Programmable Multimedia Processor (PMP) core • Dolby Pro Logic II.
consisting of 32-bit RISC and 64-bit DSP processors that
• Dolby Digital Surround EX.
enable simultaneous parallel execution of system
commands and data processing to perform specialized • DTS Surround.
audio decoding tasks. • DTS ES.
The ES4008 performs audio processing to provide • SRS TruSurround.
consumers with rich audio decode features, such as Dolby • High Definition Compatible Digital (HDCD) decoding.
Digital (AC-3), Dolby Pro Logic, Dolby Pro Logic-II,
Dolby Digital Surround EX, DTS Surround, DTS ES, • S/PDIF digital audio output.
SRS TruSurround, as well as bass management. • TDM interface for direct connection to external devices.
The ES4008 integrates an industry-standard serial • On-Screen-Display controller with 3-bit blending to
interface for audio input and output, using either the provide 256 colors display.
normal format or I2S format, to interface to audio DACs • Direct interface to SDRAM.
and ADCs. The ES4008 implements a high-speed,
bidirectional time-division-multiplexed (TDM) serial bus • Direct interface to EEPROM or flash memory.
interface that supports high-speed serial protocols. The • Bass management.
ES4008 also includes a S/PDIF interface to output high-
quality digital audio. LICENSING REQUIREMENTS
The ES4008 also includes an On-Screen-Display (OSD) • Dolby Laboratories, Inc.
controller to provide a user-friendly setup menu to enable
or modify the various audio decoding features. • Digital Theater Systems, Inc.
The ES4008 is available in an industry-standard 208-pin
• SRS Labs, Inc.
Plastic Quad Flat Pack (PQFP) device package.
CONTENTS
ES4008 PINOUT DIAGRAM .................................................. 3 System SRAM Interface .............................................15
ES4008 Pin DESCRIPTION ................................................... 4 SDRAM Interface ........................................................15
ES4008 DEVICE INTERFACES ............................................ 7 SDRAM Address Mapping ........................................16
LICENSING REQUIREMENTS ............................................ 10 SDRAM Configuration Requirements ........................16
FUNCTIONAL DESCRIPTION............................................. 11 TDM Interface ............................................................. 16
Device Architecture ....................................................... 11 Vacuum Fluorescent Display Controller Interface ......16
DMA Controller........................................................... 11 REGISTERS ......................................................................... 18
ESS RISC Processor ................................................. 11 Host Interface Host Side Registers ............................... 18
Instruction Cache ...................................................... 12 On-Screen Display Controller Registers ........................19
Data Cache ............................................................... 12 Host Interface RISC Side Registers .............................. 21
Cache Line Operation ............................................... 12 Host Interface RISC-SRAM Interface Registers ............21
RISC Interrupts ......................................................... 12 Bus Controller Registers ................................................22
STALL# Flag Operation ............................................ 13 Bus Controller (Memory Controller) Registers ............22
Gateway ..................................................................... 13 Audio Interface Registers ..............................................23
Huffman Decoder ....................................................... 13 S/PDIF Interface Registers ......................................... 25
On-Screen Display Controller .................................... 13 AUDIO INTERFACE TIMING ................................................26
Transport Stream Parser ............................................ 13 SDRAM INTERFACE TIMING .............................................. 28
Device Interfaces .......................................................... 13 SRAM INTERFACE TIMING ................................................33
Audio Interface ........................................................... 13 TDM INTERFACE TIMING ...................................................35
Audio Decoding Features........................................... 14 ELECTRICAL SPECIFICATIONS..........................................36
Dolby Digital (AC-3) Audio Decoding........................ 14 Absolute Maximum Ratings ...........................................36
Dolby ProLogic and Pro Logic II ............................... 14 Recommended Operating Conditions ...........................36
DTS Multi-Channel Decoding ................................... 14 DC Electrical Characteristics .........................................36
DTS Surround ........................................................... 15 AC Electrical Characteristics .........................................37
DTS Extended Surround (DTS-ES) .......................... 15 Device Clock Characteristics .........................................37
HDCD Decoding ....................................................... 15 MECHANICAL DIMENSIONS ..............................................38
SRS TruSurround ..................................................... 15 ORDERING INFORMATION ................................................40
Private DMA Bus Interface......................................... 15
FIGURES
Figure 1 ES4008 Device Pinout ....................................... 3 Figure 9 Left Justified Mode / 32-Bit Cycle Frame /
Figure 2 ES4008 System Block Diagram ......................... 9 24-Bit Data Frame / MSB First .......................27
Figure 3 ES4008 Block Diagram .................................... 11 Figure 10 I2S Mode ..........................................................27
Figure 4 STALL# Flag Operation ................................... 13 Figure 11 SDRAM Random Column Read Timing ...........28
Figure 5 Typical Dolby Digital AC-3 Sync Figure 12 SDRAM Random Column Write Timing ............29
Audio Framing ............................................... 14 Figure 13 SDRAM Random Row Read Timing .................30
Figure 6 Right Justified Mode / 16-Bit Cycle Frame / Figure 14 SDRAM Random Row Write Timing .................31
16-Bit Data Frame / MSB First ...................... 26 Figure 15 SRAM Read Timing ..........................................33
Figure 7 Right Justified Mode / 24-Bit Cycle Frame / Figure 16 SRAM Write Timing ..........................................34
16-Bit Data Frame / MSB First ...................... 26 Figure 17 TDM Interface Timing .......................................35
Figure 8 Right Justified Mode / 32-Bit Cycle Frame / Figure 18 Audio Master Clock and TDM Interface
24-Bit Data Frame / LSB First ....................... 26 Clock Timing ..................................................37
Figure 19 208-pin Plastic Quad Flat Package (PQFP) ..... 38
TABLES
Table 1 ES4008 Pin Description ..................................... 4 Table 7 Hex Values for Wait States ...............................21
Table 2 ES4008 Device Interfaces ................................. 7 Table 8 SDRAM Interface Timing ..................................32
Table 3 ESS RISC Interrupts ........................................ 12 Table 9 Operating AC Characteristics ...........................32
Table 4 Typical SDRAM Configurations ....................... 15 Table 10 DC Electrical Characteristics ............................36
Table 5 SDRAM Configurations and Signal Pins .......... 16 Table 11 VFD Interface Characteristics ...........................37
Table 6 ROM Width Selection Options ......................... 21
AUX1[6]/VFD_DOUT
AUX2[0]/VFD_CLK
AUX1[7]/VFD_DIN
RESERVED
RESERVED
RESERVED
AUX2[7]/IR
AUX4[3]
AUX4[2]
AUX3[6]
AUX3[7]
AUX3[4]
AUX4[6]
AUX4[5]
AUX3[3]
AUX3[5]
AUX4[7]
AUX4[0]
AUX4[1]
AUX2[6]
AUX2[5]
AUX2[4]
AUX2[3]
AUX2[2]
AUX2[1]
AUX1[5]
AUX1[4]
AUX1[3]
AUX1[2]
AUX1[1]
AUX1[0]
AUX3[0]
AUX3[1]
AUX3[2]
ADVSS
ADVEE
COMP
VDAC
RSET
DCLK
VREF
VCC
VCC
VSS
VEE
VSS
VSS
VEE
VSS
VSS
NC
NC
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VEE 157 104 VEE
AUX4[4] 158 103 VSS
VEE 159 102 DSCK
I2CDATA/AUX[0] 160 101 DQM
I2C_CLK/AUX[1] 161 100 DCS0#
AUX[2] 162 99 VEE
VSS 163 98 VSS
VEE 164 97 DCS1#
AUX[3] 165 96 DB15
AUX[4] 166 95 DB14
AUX[5] 167 94 DB13
AUX[6] 168 93 DB12
AUX[7] 169 92 VEE
LOE# 170 91 VSS
VSS 171 90 DB11
VCC 172 89 DB10
LCS0# 173 88 DB9
LCS1# 174 87 DB8
LCS2# 175 86 DB7
LCS3# 176 85 DB6
VSS 177 84 VSS
LD0 178 83 VCC
LD1 179 82 DB5
LD2 180 81 DB4
LD3
LD4
181
182
ES4008F 80
79
DB3
DB2
VEE 183 78 DB1
VSS 184 77 DB0
LD5 185 76 VSS
LD6 186 75 VEE
LD7 187 74 DMBS1
LD8 188 73 DMBS0
LD9 189 72 DRAS#
LD10 190 71 DWE#
LD11 191 70 DOE#/DSCK_EN
VSS 192 69 DCAS#
VEE 193 68 VEE
LD12 194 67 VSS
LD13 195 66 DMA11
LD14 196 65 DMA10
LD15 197 64 DMA9
LWRLL# 198 63 DMA8
LWRHL# 199 62 DMA7
VSS 200 61 DMA6
VEE 201 60 VSS
NC 202 59 VEE
NC 203 58 DMA5
LA0 204 57 DMA4
LA1 205 56 DMA3
LA2 206 55 DMA2
LA3 207 54 DMA1
VSS 208 53 DMA0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
9
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
VSS
VEE
TDMDX/RSEL
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
NC
VSS
VCC
RSD
RWS
RBCK
NC
XIN
XOUT
AVEE
AVSS
SPDIF/SEL_PLL3
1 8-bit ROM
OSD
Audio
4/16 MB ES4008 Speakers
DAC
SDRAM Digital Audio
S/PDIF-Out A/V Receiver
EEPROM
VFD VFD Panel
Driver IR Remote
LICENSING REQUIREMENTS
Dolby Digital Licensing SRS Labs, Inc. TruSurround Licensing
Dolby Digital audio enabling software is provided with the SRS TruSurround provides 5.1 virtual surround sound
ES4008 series of DVD processors. Dolby is a trademark from two speakers or headphones and is supported in
of the Dolby Laboratories. Supply of this implementation of ESS DVD processors to let users take advantage of multi-
Dolby Technology does not convey a license or imply a channel formats without needing to have a home theater
right under any patent, or any other Industrial or system. Companies planning to implement TruSurround in
Intellectual Property Right of Dolby Laboratories, to use their products must obtain a separate license agreement
this implementation in any end-user or ready-to-use final from SRS Labs. Details of license agreement with SRS
product. Labs may be obtained by contacting:
Companies planning to use this implementation in SRS Labs, Inc.
products must obtain a license from Dolby Laboratories 2909 Daimler Street
Licensing Corporation before designing such products. Santa Ana, CA 92705
Additional per-chip royalties may be required and are to be (949) 442-1070
paid by the purchaser to Dolby Laboratories, Inc. Details http://www.srslabs.com
of the OEM Dolby Digital license may be obtained by
writing to:
Dolby Laboratories Inc.
Dolby Laboratories Licensing Corporation
Attn.: Intellectual Property Manager
100 Potrero Avenue
San Francisco, CA 94103-4813
FUNCTIONAL DESCRIPTION
Figure 3 shows the internal block diagram for the ES4008
home theater digital audio processor.
GPIO VDAC
TV-Encoder
LA[21:0]
LCS#[3:0]
LD[15:0] 32-Bit
SRAM/ROM
LWRHL# RISC
Interface OSD
LWRLL# Processor
LOE#
Controller
16 K Cache
TDMCLK Gateway
TDMDR
TDMDX TDM Transport +
TDMFS Interface
TDMTSC# DMA
Controller
DSCK_EN
DSCK
DQM
DCS#[1:0]
RSD DRAM DMA[11:0]
RWS Huffman Interface DWE#
RBCK Serial Audio Decoder DOE#
SPDIF DRAS#[2:0]
Interface
TBCK DB[I5:0]
MCLK DCAS#
TSD[3:0]
TWS SIMD
DSP
ROM
RAM
unit, and register file. The program count unit generates an The Programmable Multimedia Processor (PMP) includes
instruction address signal that identifies the location of a the proprietary single instruction, multiple data (SIMD)
32-bit program instruction. DSP, which can handle four 16-bit-wide data streams. Also
included in the device are a screen display controller, a
Program instructions, such as load and store instructions,
digital video encoder, FIFOs and DMA controllers.
include source and destination information, which are
passed on to the instruction decode unit. The instruction RISC Interrupts
decode unit generates specific signals which select their Approximately nine events can cause interrupts to the
targeted registers in the register file. The decoded ESS RISC. Each event has a status bit to indicate the
instruction has its data sent to the program count unit, occurrence of the event and an enable bit to mask it from
where it is incremented to the next data instruction, or, in interrupting the ESS RISC. Table 3 lists the ESS RISC
the case of a branch instruction, changes the data if a interrupts and the conditions that cause them.
branch condition is met.
Table 3 ESS RISC Interrupts
The instruction decode unit generates specific signals Caused By
which select their targeted registers in the register file. The Interrupt Group How To Clear
Condition
decoded instruction has its data sent to the program count
Timer 0 Timer register wraps Writing1 to
unit, where it is incremented to the next data instruction,
from 3FFFFh to ‘clrirq’ register
or, in the case of a branch instruction, changes the data if 00000h bit 3
a branch condition is met.
BCDW 0 DMA Bus Controller Reading the
The execution unit contains a shifter, an arithmetic logic Data is waiting to be ‘rlatch’ register
unit, and a multiplier/divider. The execution unit generates read after DBUS
signal outputs from the respective data signals found in READ command
the register file. These outputs, in turn, are either re-stored H En Idle 1 Huffman Encoder Writing 1 to
in the register file, or asserted as address signals for load state machine goes ‘clrirq’ register
and store operations. idle bit 2
Instruction Cache H De Idle 1 Huffman Decoder Writing 1 to
state machine goes ‘clrirq’ register
The instruction cache of the RISC core is an on-chip
idle bit 1
memory array configured to a size of 8 kB. The cache is
virtually indexed and physically tagged, allowing the Data 1 Either Host-to-RISC TRE cleared
virtual-to-physical address translation to occur in parallel Transfer Data TRE or RISC-to- when RISC
Host DW reads data; DW
with the cache access rather than having to wait for the
(Host can select) cleared when
physical address translation.
RISC writes
Data Cache data
The data cache of the RISC core is an on-chip memory Block 1 After DMA controller Write any data
array configured to a size of 8 kB. Like the instruction Done has read six blocks of to ‘clrhmade’
cache, the data cache is also virtually indexed and RLAs from SIMD register
physically tagged and handles the virtual-to-physical DSP to DRAM
address translation process the same way as the Debug 2 DEBUGIRQ pin goes DEBUGIRQ pin
instruction cache. high goes low
Cache Line Operation FIFO 2 Either Encoder Writing 1 to bit 8
Level Output FIFO or of ‘mipctlreg’
Before cache line operation, the writeback operation may
Decoder Input FIFO register
be performed if the cache content and main memory reach certain fullness.
contents are different. The ESS RISC performs all power
Host to 2 Host sets Host-to- Writing 1 to bit 0
management and system configuration functions.
RISC RISC interrupt bit 7 of of ‘mipctlreg’
‘HostControl0’ register
register (Host
address 2)
The ES4008 audio mode configuration is selectable, The beginning of each frame starts with the Sync
allowing it to interface directly with low-cost audio DACs Information (SI) header. The IS header is followed by the
and ADCs. The audio port provides a standard I 2 S Bit Stream Information (BSI) header and Audio Blocks
interface input and output and S/PDIF (IEC958) audio (AB) 0 through 5.
output.
The audio blocks may be followed by an auxiliary (Aux)
Stereo mode is in I2 S format while 5.1-channel Dolby data field. At the end of each frame is an error check field
Digital and DTS 5.1-channel audio output can be that includes a CRC word for error detection. An optional
channeled through both the I2S interface and the S/PDIF. CRC word may also be added in the SI header, if desired,
The S/PDIF interface consists of a bi-phase mark encoder, for greater accuracy and enhanced error detection in the
which has low skew. decoding process.
The transmit I2S interface supports the 128, 192, 256, 384, During AC-3 decoding, the compressed AC-3 data is input
and 512 Fs sampling frequency formats, where sampling into the ES4008 at 384 kbps, and contains 5.1 channels of
frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, audio data. The five channels represent five full-frequency
or 192 kHz. The audio samples for the I 2 S transmit range channels of stereo audio data, while the.1 channel
interface can be 16, 18, 20, 24, and 32-bit samples. represents one low frequency effects (LFE) channel of
audio data, usually processed as subwoofer-type audio.
For Linear PCM audio stream format, the ES4008
supports 48 kHz and 96 kHz. Dolby Digital and DTS audio Once the audio is decompressed into its native 5.1
only supports 48 kHz. The ES4008 incorporates a built-in channel format, the audio data can be sent directly to the
programmable analog PLL in the device architecture in speakers only if the required number of speakers for each
order to generate a master audio clock. channel are available. If the required number of speakers,
The MCLK pin is for the audio DAC clock and can either the ES4008 will downmix the six channels of audio data
be an output from or an input to the ES4008. Audio data into fewer channels automatically.
out (TSD) and audio frame sync (TWS) are clocked out of Dolby ProLogic and Pro Logic II
the ES4008 based on the audio transmit bit clock (TBCK). Dolby ProLogic is actually four channels of sound,
Audio receive bit clock (RBCK) is used to clock in audio typically 2-channel Dolby Surround-encoded analog
data in (RSD) and audio receive frame sync (RWS). soundtracks, that are decoded and reproduced through
five speakers. The four channels are: left, center, right and
Audio Decoding Features
the left/right surround channels.
The ES4008 incorporates software support for rich audio
decode features, such as Dolby Digital (AC-3), Dolby Pro While both Dolby Digital and DTS require 5.1-channel
Logic, Dolby Pro Logic II, DTS Surround and SRS encoded software in order to produce 5.1-channel
TruSurround. surround sound, Dolby Pro Logic II can create a 5.1-
channel sound effect from any 2-channel software. Dolby
Dolby Digital (AC-3) Audio Decoding Pro Logic II also has a phantom mode that simulates the
Dolby Digital uses proprietary AC-3 data compression to center speaker so that a quasi 5.1-channel soundscape
deliver up to 6 independent soundtrack channels. An AC- can be reproduced from the standard speakers of an audio
3 serial coded audio bitstream is comprised of a sequence system.
of sync frames. Each frame represents 256 new audio
DTS Multi-Channel Decoding
samples.
The ES4008 supports DTS multi-channel decoding and
Figure 5 shows a typical AC-3 sync audio data frame. audio post-processing, including bass management.
Separate downloads can be used to support stereo to 5.1
SI BSI
SI BSI channel effects processing. The DTS 6-channel decoder
C
operates in real time and allows the channels to be
AB 0 AB 1 AB 2 AB 3 AB 4 AB 5 Aux R
C monitored through the decoding cycle. The compressed
data output is on a single AES-EBU channel and is
Sync Frame clocked synchronously by the digital audio inputs.
The decoding algorithm does not involve calculations that
Figure 5 Typical Dolby Digital AC-3 Sync Audio Framing
are of importance to the quality of the decoded audio. After
synchronization, the decoder unpacks the compressed
audio bitstream, detects and corrects any transmission-
induced errors and demultiplexes the data into individual
audio channels.
Table 4 lists the typical SDRAM configurations used by the Table 5 SDRAM Configurations and Signal Pins
ES4008. Size Memory
SDRAM 0 SDRAM 1 SDRAM2 SDRAM3
Table 4 Typical SDRAM Configurations (MB) Type
DCAS# DCAS# DCAS# DCAS#
Bit Order DRAS0# DRAS0# DRAS0# DRAS0# 1Mx8x2
Size 8.0
Memory Configuration DCS0# DCS0# DCS1# DCS1# (16 Mb)
(MB)
SD64M SD8BIT SDCFG1 SDCFG0
DB[0:7] DB[8:15] DB[0:7] DB[8:15]
2.0 0 0 0 1 1 pc: 512Kx16x2 (16 Mb) DCAS#
DRAS0# 1Mx16x4
4.0 0 0 0 0 2 pcs: 512Kx16x2 (16 Mb) 8.0 — — —
DCS0# (64 Mb)
DB[0:15]
4.0 0 1 0 1 2 pcs: 1Mx8x2 (16 Mb)
DCAS# DCAS#
8.0 0 1 0 0 4 pcs: 1Mx8x2 (16 Mb) DRAS0# DRAS0# 1Mx16x4
16.0 — —
DCS0# DCS1# (64 Mb)
8.0 1 0 X X 1 pc: 1Mx16x4 (64 Mb) DB[0:15] DB[0:15]
The TDM interface can transfer data at a maximum rate of by the software for supporting the control and format
16 Mbps, with a more typical configuration supporting a functions in the first access, and enables the interface in
data rate of up to 4.096 Mbps with a frame sync frequency the second access.
of 8 kHz. The TDM interface programmability includes
The VFD_DATA register, along with the AUX_MODE
independent receive, transmit, and frame sync clock edge
register, both act as containers for an external VFD device
selection and independent receive and transmit data
to read data from it and write VFD clock and data to it
offsets.
during normal operations. The SYS_STATUS register and
Vacuum Fluorescent Display Controller Interface the IR_DIFF register provide additional hardware support
for remote control operations.
The ES4008 provides hardware support for the vacuum
fluorescent display (VFD) controller interface in DVD
player designs. The VFD_CTRL register is programmed
REGISTERS
Host Interface Host Side Registers Bits Name Description
This section describes the host interface (host side) 3:1 ISEL Select which TRE and DW bits are sent to the
registers of the ES4008. HWRREQ (write request) pins.
7:0 7 6 5 4 3 2 1 0
The Host Side Command Port register contains control The Host Side Interrupt Mask register initializes to 0x00
and status data transferred to and from the RISC. After after reset.
reset, this register initializes to 0x00. Bit Definitions:
Bits Name Description
H_HOSTDBGPORT (0x2, R/W)
7 ENDN_ Host Side Endian Select. When set, this bit
HOST INTERFACE (DEBUG PORT) DATA SEL switches the upper and lower bytes of data sent
7:0 as writes to the Host Interface DMA Port
register.
The Host Side Debug Port register transfers data to and
from the RISC during debugging. After reset, this register 1 = switch upper/lower bytes.
initializes to 0x00. 6 DBG_ Host To RISC Debug Transmit Register Empty
TRE Flag.
H_HOSTCTL (0x3, R/W) 5 DBG_ RISC To Host Debug Data Waiting Flag.
DW
H2R_IRQ OSEL ISEL CLR_RIRQ
1 = Host ready to read debug data from ESS
7 6:4 3:1 0 RISC.
4 DMA_ Host To RISC DMA Transmit Register Empty
The Host Side Control register enables and disables the TRE Flag.
host-to-RISC and RISC-to-host interrupt capabilities of the
ES4008. After reset, this register initializes to 0x00. 1 = Host ready to send DMA data to ESS RISC.
Bit Definitions: 3 DMA_ DMA data waiting.
Bits Name Description DW
1 = Host waiting to read data from ESS RISC.
7 H2R_IRQ Host to RISC IRQ Enable.
2 VCXI_ VCXI transmit register empty.
Writing a 1 to this bit sets the host to RISC TRE
IRQ flag. 1 =Host ready to send data to ESS RISC.
6:4 OSEL Select which TRE and DW bits are sent to the 1 VCXI_ VCXI data waiting.
HRDREQ read request pins. DW
1 = Host waiting to read data from ESS RISC.
HRDREQ = 0 R2R_ Interrupt flag.
(DMA_DW and OSEL_0) or IRQ
(VCX_DW and OSEL_1) or 1 = Set by ESS RISC as Ready To Receive
(DBG_DW and OSEL_2). signal to the host.
The OSD Video Screen Horizontal Start Address register VID_SCN_OSD_MISC (0x20001124h, R/W)
contains the horizontal starting address value for the OSD, LAT_INT RESET_OVERLAY PAL_INDEX INTEN LDMD MODE
as referenced from the active display window. 7 6 5:4 3 2 1:0
Bit Definitions:
The OSD Video Screen Miscellaneous register contains
Bits Name Description the control logic and status bits for the OSD controller.
15:13 — Reserved.
Bit Definitions:
12:0 OSD_ OSD horizontal starting address value.
HSTART Bits Name Description
7 LAT_INT Latched interrupt. Read-only.
VID_SCN_OSD_HEND (0x20001114h, R/W) 6 RESET_ Reset overlay section (set to 1 at reset).
OVERLAY
— OSD_HEND
5:4 PAL_ Upper 2 bits of palette address when in
15:13 12:0
INDEX 2-bit/pixel mode.
The OSD Video Screen Horizontal End Address register 3 INTEN Interrupt enable.
contains the 13-bit horizontal ending address value for the 2 LDMD Enable palette load.
OSD, as referenced from the active video display.
3 VFDDATA VFD Data Output Select. 4 IR_DET Interrupt edge detect for IR
_OUT 1 = VFD data output selected. 1 = Falling edge.
0 = AUX1[6] selected. 0 = Rising edge.
3 — Reserved.
S/PDIF Interface Registers The S/PDIF Channel Status 1:6 registers initialize to
This section describes the S/PDIF audio interface 0x0000 0000 after reset.
registers. Bit Definitions:
Bits Name Description
31:0 CDS1:6 SPDIF channel status data.
SPDIF_CTL (0x2000D01Ch, R/W)
SPDIF_ AUDIOIMASK (0x2000D038h, R/W)
— SPDIF_RST SPDIF_CLK SFRMDB — SOE
SFRMV
MSSE MSCSE MSTRE MSUE MACS MAUE MATRE MADW
7 6 5:4 3 2 1 0
7 6 5 4 3 2 1 0
TBCK/RBCK
TWS
TSD[3:0]/RSD
Figure 6 Right Justified Mode / 16-Bit Cycle Frame / 16-Bit Data Frame / MSB First
TBCK/RBCK
TWS
TSD[3:0]/RSD
Figure 7 Right Justified Mode / 24-Bit Cycle Frame / 16-Bit Data Frame / MSB First
TBCK/RBCK
TWS
TSD[3:0]/RSD
Figure 8 Right Justified Mode / 32-Bit Cycle Frame / 24-Bit Data Frame / LSB First
TBCK/RBCK
TWS
TSD[3:0]/RSD
Figure 9 Left Justified Mode / 32-Bit Cycle Frame / 24-Bit Data Frame / MSB First
TBCK/RBCK
TWS
TSD[3:0]/RSD
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
DSCK
tCK3
DSC[1:0]#
DRAS#
DCAS#
DWE#
DMA[11]
DQM
Hi-Z
DB[15:0] Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
DSCK
tCK3
DSC[1:0]#
DRAS#
DCAS#
DWE#
DMA[11]
DQM
Hi-Z
DB[15:0] DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
DSCK
tCK3
DSC[1:0]#
DRAS#
DCAS#
DWE#
DMA[11]
tRP
tAC3
tRCD
DQM
Hi-Z
DB[15:0] Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Axy By0
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
DSCK
tCK3
DSC[1:0]#
DRAS#
DCAS#
DWE#
DMA[11]
DMA[10]
DQM
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
DB[15:0]
tRAS (min) 54 —
Row active time
tRAS (max) — 100 µs —
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time,
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1 ns, (tR/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tR & tF) = 1ns. If tR and tF are both longer than 1 ns, transient time
compensation should be considered, that is, [(tR + tF)/2 - 1] ns should be added to the parameter.
LCS[3:0]#
LWRxx#
LCS[3:0]#
tA_STWS Address setup time to write strobe 0.5 — 0.5 Internal CPU clock cycle
tTDMCLK_P
tTDM_RD Recv Channel 0 Recv Channel 1
TDMCLK
tTDMFS_HT
TDMFS
tTDMDR_ST
tTDMFS_ST
TDMDR 0 1 2 3 4 5 6 7
tTDMDR_HT
TDMTSC#
tTDM#_COD
TDMDX 0 1 2 3 4 5 6 7
tTDMDX_DOD
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings WARNING: Stress beyond those listed under the Absolute
Maximum Ratings may cause permanent damage to the device.
Storage temperature range –65° C to 150° C This is a stress rating only, and functional operation of the device
Operating temperature range 0° C to 70° C at these or any other conditions beyond those indicated in the
Recommended Operating Conditions section of this specification
Voltage range on any pin –0.5 V to + 5.5 V
is not implied. Exposure to the Absolute Maximum Ratings
Power dissipation 1.8 W conditions for extended periods may affect device reliability.
WARNING: Electrostatic Discharge (ESD) can damage this
Recommended Operating Conditions device. Proper procedures must be followed to avoid ESD when
Operating temperature range 0° C to 70° C handling this device.
Supply voltage VCC 2.80V±150 mV; Electrical characteristics for the ES4008 are listed in Table
415 mA nominal 10 through Table 11.
Supply voltage VEE 3.60V±150 mV;
60 mA nominal
Supply voltage AVEE 3.60V±150 mV;
10 mA nominal
Supply voltage ADVEE 3.60V±150 mV;
150 mA nominal
DC Electrical Characteristics
Table 10 DC Electrical Characteristics
Symbol Parameter Minimum Maximum Unit Comments
AC Electrical Characteristics
Table 11 VFD Interface Characteristics
Parameter Minimum Typical Maximum Unit
t1, t6
t2, t7
Clock
t4, t9 t3, t8 t5, t10
MECHANICAL DIMENSIONS
The mechanical dimensions for the ES4008 are shown in
Figure 19.
D1
A2 A1
E E1 ES4008F
208-Pin PQFP e e1
L b L1
Millimeters
Symbol Description
Minimum Nominal Maximum
D Lead to lead, X-axis 30.25 30.60 30.85
D1 Package’s outside, X-axis 27.90 28.0 28.10
E Lead to lead, Y-axis 30.25 30.60 30.85
E1 Package’s outside, Y-axis 27.90 28.00 28.10
A1 Board standoff 0.25 0.33 0.42
A2 Package thickness 3.17 3.37 3.67
b Lead width 0.13 0.17 0.27
e Lead pitch — 0.50 —
e1 Lead gap 0.20 — —
L Foot length 0.35 — 0.75
L1 Lead length — 1.30 —
— Foot angle 0° — 7°
— Coplanarity — — 0.102
— Number of leads in X-axis — 52 —
— Number of leads in Y-axis — 52 —
— Total number of leads — 208 —
— Package type — PQFP —
ORDERING INFORMATION
Part Number Description Package
ES4008F Home Theater Digital Audio Processor 208-pin PQFP
No part of this publication may be reproduced, stored in a retrieval MPEG is the Moving Picture Experts Group of the ISO/IEC. References
system, transmitted, or translated in any form or by any means, to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee
electronic, mechanical, manual, optical, or otherwise, without the prior draft ISO 11172 dated January 9, 1992.
written permission of ESS Technology, Inc. Dolby is a trademark of Dolby Laboratories, Inc. TruSurround is a
ESS Technology, Inc. makes no representations or warranties trademark of SRS Labs, Inc. All other trademarks are trademarks of
ESS Technology, Inc. regarding the content of this document. their respective companies and are used for identification purposes
only.
All specifications are subject to change without prior notice.
48401 Fremont Blvd. ESS Technology, Inc. assumes no responsibility for any errors H.261 refers to the International Standard described in
recommendation H.261 of the CCITT Working Party 15-1.
Fremont, CA 94538 contained herein.
U.S. patents pending.
Tel: (510) 492-1088
Fax: (510) 492-1898