Modulation Strategies For Three Level PWM Converter - Fed Induction Machine Drives

WARSAW UNIVERSITY
OF TECHNOLOGY

Faculty of Electrical Engineering

Ph.D. THESIS

Wojciech Koomyjski M. Sc.

Modulation Strategies for Three-level PWM
Converter-fed Induction Machine Drives

Supervisor
Professor Marian P. Kazmierkowski, Ph.D., D.Sc.

Warsaw, 2009

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0

The research work presented in this thesis has been carried out during my Ph.D. study
at the Institute of Control and Industrial Electronics, Warsaw University of Technology in the
period 2004-2008.
Some part of the work was performed in cooperation with the Electronics Engineering
Department, University of Seville, Spain (Prof. Leopoldo Garcia Franquelo and Dr. Jose
Ignacio Leon) during my stay in Sevilla (December 2005)
First of all, I would like to thank Prof. Marian P. Kamierkowski for support and help.
His precious advice and numerous discussions enhanced my knowledge and scientific
inspiration.
Furthermore, I thank my colleagues from the Intelligent Control Group of the
Industrial Electronics Division for their support and friendly atmosphere. Especially, to Dr.
Mariusz Malinowski, and Sebastian Styski, MSc.
Finally, I would like to thank to my whole family for patience and faith over the years.
Especially, to my wife Agnieszka.

Preface

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1
Contents
1. Introduction ........................................................................................................................ 6
2. Basic Topologies of Multilevel Converter ....................................................................... 10
2.1. Introduction .............................................................................................................. 10
2.2. H-Bridge Converter .................................................................................................. 11
2.3. Floating Capacitor Converters (FLC) ...................................................................... 13
2.4. Diode Clamped Converters (DCC) .......................................................................... 15
2.5. Summary .................................................................................................................. 16
3. Pulse Width Modulation (PWM) Methods for NPC Multilevel Converters .................... 18
3.1. Introduction .............................................................................................................. 18
3.2. Sinusoidal Pulse Width Modulation ......................................................................... 19
3.3. Space Vector Representation of Output Voltage ..................................................... 24
3.4. SVM in Natural (abc) Coordinates........................................................................... 28
3.5. SVM in Coordinates ............................................................................................ 38
3.6. Modulation With Simplified Duty Cycle Calculations ............................................ 45
3.7. Summary .................................................................................................................. 46
4. DC Capacitors Voltage Balancing Methods in NPC Converters ..................................... 47
4.1. Introduction .............................................................................................................. 47
4.2. Hardware Solution for DC Link Capacitor Voltages Balancing .............................. 49
4.3. Virtual Vectors Based DC Capacitors Voltage Balancing Method ......................... 49
4.4. DC Link Balance With Additional Controller ......................................................... 51
4.5. DC Capacitors Voltages Balancing With Carrier Based SPWM ............................. 52
4.6. Summary .................................................................................................................. 52
5. Modified Space Vector Modulation Algorithm for NPC Converters. ............................. 53
5.1. Introduction .............................................................................................................. 53
Contents

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2
5.2. DC-Link Capacitors Voltage Balancing .................................................................. 53
5.3. Switching Number Minimization ............................................................................. 56
5.4. Overmodulation ........................................................................................................ 58
5.5. Summary .................................................................................................................. 62
6. Three Level NPC Converter-Fed Induction Motor Drive ................................................ 65
6.1. Introduction .............................................................................................................. 65
6.2. Mathematical Description of Induction Machine ..................................................... 65
6.3. Control Strategy of Induction Machine .................................................................... 66
6.4. Stator Flux and Torque Estimation .......................................................................... 67
6.5. PI Controllers Design ............................................................................................... 68
6.6. Summary .................................................................................................................. 70
7. Experimental Results ........................................................................................................ 71
7.1. Introduction .............................................................................................................. 71
7.2. Laboratory Setup ...................................................................................................... 71
7.3. Experimental Results ................................................................................................ 75
7.4. Summary .................................................................................................................. 85
8. Summary and Closing Conclusions ................................................................................. 86
REFERENCES: ........................................................................................................................ 88
Appendices ............................................................................................................................... 95
Contents

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3
List of symbols
A, B ,C ,D - regions in modulation with virtual vectors
C
1
, C
2
DC link capacitors
D_R_up, D_S_up, D_T_up, D_R, D_S, D_T, - transistors duty cycles
d
1
, d
2
, d
3
, d
4
reference voltage vector distances to base vectors in 3D-SVM
f
N
fundamental frequency
f
s
sampling frequency
f
C
switching (commutating) frequency
F
T
choice indicator between SD1 and SD45 sub-cube division in 3D-SVM
F
SD1
distance indicator for SD1 cube division in 3D SVM
F
SD45
distance indicator for SD145 cube division in 3D SVM
i
A
, i
B
, i
C
, i
A
(t), i
B
(t), i
C
(t) instantaneous phase current values
i
s
, i
s
- instantaneous stator currents values in - stationary reference frame
I
S
stator current vector
I
SK
stator current vector in rotating reference frame with
K
angular speed
I
rK
rotor current vector in rotating reference frame with
K
angular speed
I
sd
, I
sq
- stator current components in d-q rotating reference frame
J moment of inertia
k
0
maximum instantaneous current indicator
k
1
DC-link capacitor voltage unbalance indicator
L
M
mutual inductance
L
r
rotor inductance
L
s
stator inductance
m
1
m
2
small modulation indexes
M modulation index
m
e
electromagnetic torque
m
L
load torque
m
ec
commanded electromagnetic torque
p instantaneous active power
p
b
number of pole pairs
R
s
stator resistance
R
r
rotor resistance
List of symbols
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4
T
0
, T
1
, T
2
, T
3
, T
4
, T
5
,T
V
switching intervals of voltage vectors
T
S
sampling time
u
A
, u
B
, u
C
, u
A
(t), u
B
(t), u
C
(t) phase voltage, instantaneous value
U
C1
, U
C2
DC link capacitors voltages
U
DC
DC link voltage
U
i_ref
instantaneous value of reference phase voltages (i = a, b, c)
U
N
nominal voltage
U
N_phase_m
phase voltage nominal magnitude
U
OUT
output voltage
U_ref converter commanded voltage
U
sx
, U
sy
stator voltage components in stator flux x-y rotating frame
U
SK
- stator voltage vector in rotating frame with
K
angular speed
U
, U
voltage components in - stationary reference frame

U
0
, U
1
, U
2
, U
3
, U
4
, U
5
basic output voltage vectors
U
V
virtual vector
commanded voltage angle
1
modified commanded angle in overmodulation mode
h
hold angle in overmodulation mode
p
hexagon crossing angle in overmodulation mode
m
rotor position angle
m
rotor angular speed
K
- angular speed of coordinate system K
torque angle (between stator flux and current vectors)
phase angle (between voltage and current vectors)
leakage factor
sN
nominal value of stator flux magnitude
s
- stator flux magnitude
r
rotor flux vector
s
stator flux vector
sK
stator flux vector in rotating frame with
K
angular speed
rK
rotor flux vector in rotating frame with
K
angular speed
sc
commanded value of stator flux magnitude
rd
,
rq
rotor flux components in d-q rotating reference frame
sd
,
sq
stator flux components in d-q rotating reference frame
List of symbols
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5
Abbreviations
3D-SVM Three Dimensional Space Vector Modulation
APOD Alternative Phase Opposite Disposition
ASD Adjustable Speed Drive
CB-PWM Carrier Based Pulse Width Modulation
DCC Diode Clamped Converter
FLC Flying Capacitor Converter
IGBT Insulated Gate Bipolar Transistor
IM Induction Motor
LSC Level Shifted Carriers
NPC Neutral Point Clamped Converter
OVPWM - Overmodulation
PD Phase Disposition
PI Proportional Integral (controller)
POD Phase Opposite Disposition
PSC Phase Shifted Carriers
PWM - Pulse Width Modulation
SVM Space Vector Modulation
VSI Voltage Source Inverter

Abbreviations
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6
1. Introduction
Demands for various appliances satisfied by small power, highly specialized, vector
controlled Adjustable Speed Drives (ASD) brought about great interest in similar solutions for
higher power drives. Constant development of power electronics devices such like IGBT and
IGCT technology made possible construction more powerful converters. Increased nominal
voltage and current of those devices allowed to satisfy the market for some time. However,
the new, high voltage semiconductors have higher switching losses and cannot be switched
with the same frequency as low voltage components. Decreased switching frequency causes
the output current performance degradation and requires larger filters. It also can create
problems for control strategy implementation.
To avoid these problems several solutions have been developed. One of them is
introducing additional output filter. This method is questionable for high current drives
because of voltage drops on filter passive components and additional losses.
Nowadays most widespread system for medium power ASD are multilevel converters.
As first, Neutral Point Clamped (NPC) inverter topology has been proposed by Nabae and
Takahashi in 1981 [N3]. Later, in 1991, Flying Capacitor (FLC) topology has been introduced
by Meynard and Foch [M11].
The idea of those converters bases on voltage spreading on series connection of
semiconductors. This guarantee lower voltage on diodes and transistors followed by smaller
switching stress for semiconductors. Thus, in multilevel converters is possible to use
semiconductors dedicated for smaller voltage than in two level converters with the same DC
link voltage. This feature allows increasing the switching frequency of the semiconductors
followed by improvement of drives output parameters.
Multilevel converters use more than one DC voltage source, usually capacitors, to
generate more than one level of output voltage. There are three main groups of multilevel
converters differentiated by those sources connection method. Diode Clamped Converters
(DCC) use one common DC-link built from series connection of capacitors. Each capacitors
connection is connected to all phase legs of converter by diodes and can be connected to the
output giving part of the whole voltage. Three level DCC is called Neutral Point Clamped
(NPC) because of DC-link middle (neutral) point diode clamped. Flying Capacitor
Introduction
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7
Converters (FLC) use one common DC-link capacitor and separated by semiconductors from
other phases capacitors. Higher number of levels requires higher number of flying capacitors
in each phase. Last group are Series Connected H-Bridge converters (SCHB). This group does
not share one DC-link, but each H-Bridge converter have separated DC circuit. Thus for three
phase converter minimum three separated circuits are required. This feature requires special
transformers with separated and divided secondary windings.
Wide comparison of ASDs presented in [K6] takes up a subject of efficiency of
different inverters devoted for drives. Comparison takes into account maximum switching
frequency for five types of applied converters. Fig. 1.1 presents total losses in the system for
two level Voltage Source Inverter (2L-VSI), three level Neutral Point Clamped VSI (3L-
NPC), three level Floating Capacitor VSI (3L-FLC), four level FLC-VSI (4L-FLC) and five
level Series Connected H-bridge VSI (5L-SCHB)

Fig. 1.1. Comparison of loss distribution and converter efficiency (I
Arms
= 600 A, U
Arms
=2.3kV
f
C
:2L-VSI = 450 Hz, 3L-NPC VSI = 1.9 kHz, 3L-FLC VSI =1.8 kHz, 4L-FLC VSI = 1.5 kHz, 5L-
SCHB VSI = 4.58 kHz,
f
o
=50 Hz, cos = 0.9). [K6]
Highest efficiency is guarantied by NPC-VSI using quite high switching frequency
what is followed by minimization of output LC filter. Two level converters cannot compete
with multilevel solution, even though high efficiency, because of low quality of output
parameters [K6].
Among development of multilevel topologies, new modulation techniques have been
elaborated. Historically, the first approach was adaptation of analog carrier modulation types.
Multilevel topologies created new possibilities for multicarrier Pulse Width Modulation
(PWM). Several techniques, depending on mutual placement of carrier signals, have been
elaborated [H6, M5, N1, O1, R1, T1]. Parallel to carrier based PWM development, the
voltage Space Vector Modulation (SVM) was constantly improved [B3, M2, F2, P4, P6, P7].
Introduction
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8
Use of many voltage sources, especially in DCC and FLC converters brings out
problem of capacitors utilization. Not equal use of those sources can introduce voltage
unbalance and output parameters distortion. Proper modulation technique, among transistor
control signals generation, can be an active tool for bringing DC link voltage differences to
zero [A1, B1, C3, D1, H4, M8, P5, T1]. Some solutions for voltage balancing, such as
hardware solutions or introduction of additional virtual vectors can have negative influence on
system efficiency [P2, P5]. None the less some algorithms can improve converter efficiency.
Those techniques usually base on proper choice of redundant states of the converter (states
which are generating the same output voltage using different sources from DC-link) causing
charging and discharging chosen capacitors. In authors opinion there is possibility for further
losses reduction by introduction of new Space Vector Modulation algorithm.
For demanding ASDs is important to maximally utilize operating range of the
converter. Modulation algorithms called Overmodulation (OVPWM) make possible operation
in nonlinear control range of the converter. Those features distort output voltage and current
however make possible to maximize stator flux in high speed range.
Thus author has formulated the following thesis Application of proper Pulse Width
Modulation (PWM) technique in multilevel converter guaranties losses minimization as
well as DC link capacitors voltage unbalance elimination in linear operation range of the
converter.
To proof the above thesis, author has performed analysis based on Space Vector
method using an advanced geometrical approach. For verification of the proposed modulation
algorithm several simulation studies based on model in professional SABER Designer
software package have been performed. Finally, the experimental results measured on 15kVA
NPC three-level inverter supplying 3kW induction machine verifies the thesis.
In authors opinion following parts of the thesis are his original achievements:
Development of new cube division for 3D-SVM in orthogonal abc
coordinates eliminating unwanted distortions,
Elaboration of Modified SVM for NPC inverter-fed induction machine
increasing converter efficiency with active DC link capacitors voltage
balancing algorithm,
Development of NPC-inverter-fed induction motor simulation model in
Saber Designer simulation software,
Simulation study of SVM and proposed modulation method,
Introduction
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9
Adaptation of overmodulation algorithm for NPC converter,
Development of experimental setup containing dSpace dS1104 control
board with peripheral hardware modulator enclosed in Altera CycloneII
FPGA device.
The thesis consist of eight chapters. Chapter 1 is an introduction. In Chapter 2 basic
topologies of multilevel converters are presented. Chapter 3 contains description of PWM
methods devoted to multilevel converters. Chapter 4 presents selected DC link capacitors
voltage balancing algorithms. SVM method developed by author is revealed in Chapter 5.
Chapter 6 is devoted to Direct Torque Control of Induction Machine and contains motor
mathematical model and control algorithm description. In Chapter 7 experimental results are
presented and discussed. Final conclusions are enclosed in Chapter 8.

Introduction
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10
2. Basic Topologies of Multilevel Converter
2.1. Introduction
In last few years there is growing interest in multilevel topologies, because of many
possibilities of expanding areas of power electronics use. It can also extend the application of
power converters to higher voltage and power ratio. Introducing multilevel converters to
power conditioning, drives, power generation and power distribution small and medium
voltage (2 to 15kV) applications is very promising idea.
Multilevel converters synthesize output voltage from more than two voltage levels.
Thus, the output signals spectrum is significantly improved in comparison to classical two-
level converter.
The main drawback of multiphase multilevel converters is number of switches which
is growing when number of levels is increasing. In early stages of multilevel converters
development control for such amount of power switches was a significant problem, but
continuous evolution of DSP and FPGA/CPLD devices easily solved this inconvenience.
Other drawback of those converters is requirement of multiple DC voltage sources, mainly
provided by capacitors. Balancing voltage sources during operation under different load
conditions is an important challenge.
In spite of these drawbacks, introducing multilevel converters will decrease switching
losses (smaller voltage on the power device) in comparison with two level appliance, allowing
to increase switching frequency and as consequence decrease requirements for reactive
components. This, in turn, results in converter weight, dimension and cost reduction.
So far development of multilevel converters concentrated on three topologies:
cascaded H-bridge converters,
Floating capacitors converters,
Diode clamped converters.
Other terminology is also used to define these topologies. For example, when referring
to the three-level diode-clamped converter, it is also called the NPC converter. This name
cannot be extended to topologies with a higher number of levels because of the multi-clamped
points available.
Basic Topologies of Multilevel Converters
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11
2.2. H-Bridge Converter
One of the simplest topology of multilevel converters is cascaded connection of IGBT
H-Bridges as shown in Fig. 2.1.
U
OUT
U
C1
U
C2

Fig. 2.1. H-Bridge cascaded converter.
This topology allows to achieve 5 different levels of output voltage: 2U
C1
, U
C1
, 0, -
U
C1
, -2U
C1
when U
C1
equals U
C2
. Changing the U
C2
to double value of U
C1
can expand the
output to seven voltage levels: 3U
C1
, 2U
C1
, U
C1
, 0, -U
C1
, -2U
C1
, -3U
C1
[M1] Fig. 2.2.
One of the most important matters in building cascaded converters is separation of
each DC circuits. Most of states generating output voltage would cause short-circuits and
damage to the IGBTs if DC links are non-separated. Therefore, separation transformers must
be used to obtain proper operating conditions for cascaded converters. Although for one phase
and low power applications (few kVA) such solution is possible, for higher power (mostly
multiphase applications) building huge transformers with many separated output voltages is
more expensive than the whole converter and the dedicated load makes this idea less
appropriate then other converter topologies for ASD.
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12

a) b)

c) d)

Fig. 2.2. Generation of different output voltages in cascaded H-bridge multilevel converters.
Interesting idea presented in [G1, G2, G3] partly solves the problem of use of
additional transformer with many separated outputs by eliminating states which are
generating common mode voltage at the output of multiphase converters. Fig. 2.3 presents
one of such states which normally (with separated DC links for all phases) would generate
u
A
=-U
C1
and u
B
=0, after connecting DC sources for each cascade, short-circuit occurs in
upper DC link. Eliminating dangerous states causes limitation of output voltages (less output
voltage levels) and reduces the maximum output voltage from
i
Ci
U
to
i
Ci
U /2 3 [G1,
G2, G3]. Thus this topology is more appropriate for small power and mostly single phase
applications such as: DC/AC converters for photovoltaic power generation systems connected
directly to the low voltage grid (transformerless).
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13

Fig. 2.3. One of forbidden states in cascaded multilevel converters with one DC link per cascade.
2.3. Floating Capacitor Converters (FLC)
More suitable for multi phase, medium power systems operating with medium voltage
grid is Floating Capacitor Multilevel Converter (FLC). Fig. 2.4. presents three level FLC
inverter. Operating principle of this type of converter bases on generating output voltage from
U
DC
and C
1
, C
2
, C
3
capacitors voltages. It is a critical matter to keep constant capacitors
voltages (floating capacitors), in case of three level converter 0.5U
DC
. It is an independent
process for each phase which take place when 0.5U
DC
potential is demanded at the output of
the phase. It is possible to realize this potential in two ways: apply capacitor voltage e.g. U
C1

or U
DC
-U
C1
. Choosing one of this states, depending on output current direction, makes
possible charging and discharging the flying capacitor in each phase. This mechanism allows
easy voltage balancing but makes modulation technique more complicated and time
consuming as in Diode Clamped Converters (DCC).
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14

Fig. 2.4. Three level Floating Capacitor Converter.

a) b)

c) d)
Fig. 2.5. Generating of the output voltage in FLC converter. a) U
DC
output potential ,
b) 0 output potential, c) and d) U
DC
/2 output potential.
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15
Keeping constant voltage on all capacitors requires additional measurement circuits
for each capacitor. Moreover, for higher number of output voltage levels more voltage
measurements are required and capacitors which will survive higher voltage. Three level FLC
converter has two capacitor voltages U
DC
and 1/2U
DC
, five level converter has 4 voltages U
DC
,
3/4U
DC
,1/2U
DC
and 1/4U
DC
.
Minding that during generation voltage different from 0 and full U
DC
, DC-link
capacitors and flying capacitors are connected in series and they should have the same voltage
it is obvious that the capacitors should have the same capacitance. Moreover, each flying
capacitor voltage have to be measured. Taking into consideration prices of voltage
measurement and high voltage capacitors, building high power, high voltage multilevel FLC
converter is very expensive. This topology is used in traction for 3 kV DC grid [R1].
2.4. Diode Clamped Converters (DCC)
Third kind of multilevel converters is Diode Clamped Converter (DCC) or also for
three level called Neutral Point Clamped (NPC) converter. In this type of converters, DC link
is built from batteries of capacitors connected in series, each connection point divides voltage
and can be switched to the output point. Fig. 2.5. presents three level, three phase NPC
inverter.
A
B
C
C2
C1
U
DC

Fig. 2.5. Three level NPC converter.
As in other types of multilevel converters, keeping capacitor voltages equal is
necessary for proper operation of the converter. For low commanded output voltage it is easy
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16
to balance voltages even in more than three level converters. In such cases energy can be
taken directly from one capacitor which voltage is highest. When reference voltage is bigger
only groups of capacitors can be controlled. For commanded voltage near to the limit of linear
operation range of the converter, upper and lower capacitors are used alternatively, but
capacitors in the middle are used all the time. Thats why voltage balancing is very difficult
for more than three level DCC converters where are only two capacitors.

a) b) c)

Fig. 2.6. Voltage generation in NPC converter. a) U
DC
output potential, b) U
DC
/2output potential,
c) 0 output potential.
2.5. Summary
Presented converters are designated for different applications. Table 1. contains typical
parameters of multilevel converters. Note, that all topologies use equal number of IGBTs.
Diode Clamped Converters use additionally clamping diodes, presented number takes into
account series connections of diodes in more than 3 level converters with the object to equal
voltage drops on all diodes and use only one type of them. It is important that cascaded
multilevel converters use separated DC sources for each bridge and usually require complex
transformers with multiple separated outputs. This feature in authors opinion excludes H-
Bridge converters from Variable Speed Drives. FLC topology is suitable for Adjustable Speed
Drives (ASD), but their drawbacks, high number of voltage measurements and capacitors
make these converters expensive. Table 2 presents number of possible states of the converter,
and it is significant that for NPC converters this number is respectively low what makes
modulation much easier than for other topologies.
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17
TABLE 1 MULTILEVEL CONVERTER PARAMETERS
Topology
Number of
levels
Number of
IGBTs
Number of
diodes
Number of
capacitors
*
Number of
DC voltage
measurements
DCC
3 12 6 4 2
4 18 18 9 3
5 24 24 16 4
n 6 (n-1) 3(n-1)(n-2) (n-1)
2
n-1
FLC
3 12 0 7 4
4 18 0 24 7
5 24 0 58 10
n 6 (n-1) 0

= == =
+ ++ +
2
0
2 2
3 ) 1 (
n
i
i n
3(n-2)+1
H-Bridge
3 12 0 3 3
4 18 0 4 4
5 24 0 6 6
n 6 (n-1) 0 )
2
3 3
(
n
Int )
2
3 3
(
n
Int
*-referred to two level DC link capacitor in same power converter.
TABLE 2 NUMBER OF STATES IN DIFFERENT TOPOLOGIES OF MULTILEVEL CONVERTERS.
Topology
Number of
levels
Number of
possible states
Number of
different states
NPC
3 27 19
4 64 37
5 125 61
n n
3
n
3
-(n-1)
3
FLC
3 64 19
4 512 37
5 4096 61
n 2
3(n-1)
n
3
-(n-1)
3
H-Bridge
3 64 19
4 512 37
5 4096 61
n 2
3(n-1)
n
3
-(n-1)
3

In authors opinion NPC converter is the best compromise for ASD up to 3kV.
Additional clamping diodes are less problematic than disadvantages of other topologies.
Therefore, three level DCC converter was chosen for further research.

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18
3. Pulse Width Modulation (PWM) Methods for NPC Multilevel
Converters
3.1. Introduction
In previous chapter several multilevel converter topologies have been presented. Each
topology has different switching configuration to achieve commanded output voltage.
Modulation strategies are responsible for synthesizing reference control signals and for
keeping all voltage sources balanced. For Power Converters with DC voltage sources output
voltage is represented by short voltage pulses of different width. Average voltage in sampling
time should be equal to commanded voltage. In literature many different approaches have
been presented [A1, B3, B7, B8, C5, D2, F1, F2, H3, H6, K3, L1, M11, P1, P4, P6-P9, T1].
Among them, most important are: Carrier Based Pulse Width Modulation (CB-PWM), also
called Sinusoidal PWM (SPWM), and Space Vector Modulation (SVM). For understanding
SVM space vector definition and explanation is presented.

Fig. 3.1. Modulation techniques classification [R1].

Pulse Width Modulation Methods for NPC Multilevel Converters
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19
3.2. Sinusoidal Pulse Width Modulation
Historically, first analog PWM methods were developed. The most advanced of those
is Carrier Based or also called Sinusoidal Pulse Width Modulation (CB-PWM or SPWM)
[B3, H3, H6, M5, T1]. The operation principle of this method bases on comparison of
commanded voltage signal with the triangular carrier signal. Result of this operation is
rectangular signal. Width of the rectangle is proportional to average value of the commanded
signal. Output signal of this operation can be directly delivered to the semiconductors driver,
see Fig. 3.2. Operating with constant frequency of carrier signal concentrate voltage
harmonics around switching frequency (which is doubled carrier frequency) and multiple of
switching frequency.
U
U
t
t
U
ref
Carrier

Fig. 3.2. Principle of CB-PWM for two level converter.
Carrier based modulation for more then two level converters requires more carrier
signals. For n-level converter minimum n-1 carrier signals are needed. Each carrier signal is
responsible for a pair of switches. One switch is controlled directly by the rectangular signal
and second one is controlled by negative sequence. Multiple carrier signals in multilevel
converters creates various possibilities of mutual locations of those signals.
Typical combinations for multi-carrier systems are :
Phase Shifted Carriers (PSC)
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20
Level Shifted Carriers (LSC)
o Phase Disposition (PD)
o Phase Opposite Disposition (POD)
o Alternative Phase Opposite Disposition (APOD)
Phase Shifted Carriers
This method of carrier signals placement is usually used in H-bridge and FLC
converters, but can also be applied in all kinds of multilevel converters. As in other types of
sinusoidal modulation, PSC modulation requires n-1 carriers shifted in phase by 360/n-1,
where n is number of levels.

Fig. 3.3. Phase shifted carrier (PSC) based nodulation for 3 level converter.
Fig. 3.3. presents carrier placement for 3 level converter and one of the commanded
voltages. Each carrier is responsible for a pair of switches in all legs of the converter. In three
phase system two other phase voltages by comparison with the carriers are generating four
more rectangular sequences for the remaining switches.
It is significant in this type of carrier placement that phase to phase voltage reaches
three values : 0, 1/3 and 2/3 of DC link voltage in each sampling (Fig.3.4.). In other
modulation techniques and carrier signal placement it is possible to avoid non necessary
switching of the output voltage, e.g. Fig. 3.6. PSC based modulation is widely used in FLC
converters because it automatically balances the capacitor voltages [C2, H6].
___________________________________________________________________________
21

Fig. 3.4. Phase and phase to phase voltage generation in PSC based modulation.
Level Shifted Carriers
Second type of sinusoidal modulation is PWM with level shifted carriers. Variants of
this type of modulation take the names from mutual locations of the carrier signals as it is
shown in Fig 3.5. Differences between those methods are rather small and gathered around
the output voltage spectrum [H6, M2].

___________________________________________________________________________
22
b ) Phase opposite disposition (POD)
0
0
a) Phase disposition (PD)
c) Alternative phase opposite disposition ( APOD)
0

Fig. 3.5. Variants of Level Shifted CB-PWM.

Fig. 3.6. Phase and phase to phase voltage generation in LSC CB-PWM
U
ref

U
carrier

U
an

U
bn

U
ab
t

t

t

t

___________________________________________________________________________
23
Extending linear range of sinusoidal modulation
Maximum instantaneous value of output phase voltage is 2/3U
DC
. In this work all
values of the modulation depth index M are referred to operation without modulation called
six step mode, when phase to phase voltage is square wave. This operation utilizes whole DC-
link voltage and for that state of operation M = n-1 is adopted (where n- number of levels in
the converter). For analog modulation with sinusoidal reference signal, linear operation range
is for M<0.785(n-1) [B8, C4, H7, K7, M9]. If the loads neutral point is not connected, three
phase - three wire system, phase currents depend only on phase to phase voltage. Therefore, it
is possible to insert an additional Zero Sequence Signal (ZSS) of 3rd harmonic frequency to
commanded voltage which does not influence output phase voltages. However, it influences
current ripples, extends linear region up to M
max
= 907 . 0 3 2 / = and allows reduction of
average switching frequency. The most known modulation is method with sinusoidal ZSS
with 1/4 and 1/6 amplitude of the first harmonic. First of those methods corresponds to
minimal output current harmonics, and the second maximally extends the linear working
range [H3, K5].

Fig. 3.7. Block scheme of modulator with Zero Sequence Signal (ZSS) injection.
___________________________________________________________________________
24
Most known ZSS is sinusoidal but it is possible to add other kinds of waves. Inserting
triangular wave of amplitude of reference voltage results the same output voltage as Space
Vector Modulation.
3.3. Space Vector Representation of Output Voltage
Typical three phase systems are rather considered in orthogonal coordinates then
in natural abc coordinates. Usually the Clarke transformation for symmetric is used, three
wire systems. In such cases three dimensional space is projected on plane, component is
equal to 0 and axis follows axis by 90, see Fig. 3.9. This transformation of three phase
quantity gives one complex vector on plane. For more complicated systems containing
neutral wire and usually not symmetric, this transformation brings out new possibilities of
Space Vector Modulation and Neutral Point voltage generation.
In three dimensional space abc, versors generate cube and their projection on plane
creates hexagon which is the basic area for space vector modulation. Graphic interpretation
shown in Fig. 3.8. and Fig. 3.9. under assumption that edge length is equal to 1 leads to
simple determination of plane vectors notation. On the plane vectors 111 and 000 are situated
in the same point. For this system Clarke transformation is defined :
(
(
(
(
(
(
=
(
(
(
C
B
A
x
x
x
2 1/ 2 / 1 2 1/
2 3 - /2 3 0
1/2 - 1/2 - 1
3
2
x
x
x
/ (3.1)

Clarke transformation is useful only for symmetric systems because in asymmetric
systems it only moves axes and introduces scaling of the versors. For those systems omitting
the Clarke transformation does not complicate the calculations.
___________________________________________________________________________
25

Fig. 3.8. Typical coordinates considered in three phase systems.
C
A ,
B
100
110 010
011
001 101
000
111

Fig. 3.9. ABC cube projection on plane, transformation in symmetrical three phase systems.
___________________________________________________________________________
26
This notation can be naturally adopted to represent switching states in PWM
converters. Fig. 3.10. presents three phase, two level inverter switching states and their
equivalents on plane.
1 0 0
0 1 1
0 0 1 1 0 1
1 1 0
0 1 0
0 0 0 1 1 1
a)
c)
e)
g)
b)
d)
f)
h)

Fig. 3.10. Possible states in two level converter. a-f) active vectors, g, h) zero vectors.
In multilevel converters it is possible to generate as many output levels of voltage as
many levels the converters are (Fig. 3.11.). In this case following notation is introduced: each
vector has three numbers from 0 to n-1 for three phases (where n is number of converter
levels). Numbers divided by n-1 and multiplied by U
DC
represent output potential for each
phase, Fig. 3.11.
___________________________________________________________________________
27

Fig. 3.11. Output voltage generation for n-level converter.
Using this notation and extending two level converter vector representation to n level
converters leads to simple representation of Voltage Space Vector where the number
represents potential attached to output in each phase multiplied by U
DC
/n-1 (where n-number
of levels).

Fig. 3.12. Vector representation on plane for three level converter.

___________________________________________________________________________
28
3.4. SVM in Natural (abc) Coordinates
One of the most natural and universal approaches to generate output voltage vector is
3D-SVM (3 dimensional SVM) [F1, F2, P6, P9]. This type of modulation can be adopted to n
level converters with neutral wire and neutral leg in the converter (Fig. 3.13).

Fig. 3.13. Three level four leg NPC converter.
If component in the reference signal is not equal to zero, three dimensional (3D)
modulation algorithms must be taken into account in order to generate the desired signal. The
component can not be equal to zero in systems with neutral connection (four-leg converters
or converters connecting the neutral point of the load with the middle point of DC-Link). As
an example, the control region for a four-leg three level diode-clamped converter is shown in
Fig. 3.14.
___________________________________________________________________________
29

Fig. 3.14. Generalized 3D space for a four-leg three level diode clamped converter
The multilevel control region is divided in several sub-cubes and the first step of the
modulation algorithm is to find the sub-cube where the reference vector is pointing to.
Considering this sub-cube using abc coordinates and changing the origin coordinates to the
nearest to (0,0,0) sub-cube vertex, the problem is reduced to a two level case because the two
level control region is one sub-cube. This is shown in Fig. 3.15.

Fig. 3.15. Sub-cube reference coordinates in generalized 3D modulation algorithms.
___________________________________________________________________________
30
In [F1, P6], the 3D modulation algorithm divides each sub-cube of the control region
in six tetrahedrons using 45 degree planes in order to simplify the calculations in the
tetrahedron determination where the reference vector is located. Therefore, the reference
vector is generated using the state vectors defined by the tetrahedron vertexes. The six
tetrahedrons by these 45 degree planes are shown in Fig. 3.16. This three dimensional space
division is named SD45. The modulation algorithm looks for the better tetrahedron to
generate the reference signal. The better solution is the tetrahedron where all the distances
between the reference vector and the four state vectors are minimum. In fact, the ideal
solution would be to increase infinitely the number of levels of the converter doing that the
reference vector is always perfectly generated using only one state vectors. So, minimizing
the distances between the reference vector and the state vectors, the ripple of the resultant
output signals will be minimized. Four new planes are used to divide the sub-cube volume
and resulting tetrahedrons are shown in Fig. 3.17. In this case, five tetrahedrons compose the
sub-cube volume where there is one central tetrahedron and four external ones. Five is the
minimum number of tetrahedrons to compose the sub-cube. This space division is named
SD1.
010
110
011
101
100
111
000
001
a
b
c
Case 1
a
b
c
Case 2
010
110
011
101
100
111
001
000
a
b
c
Case 3
010
110
011
101
100
111
001
000
a
b
c
Case 4
010
110
011
101
100
001
000
111
a
b
c
Case 5
010
110
011
101
100
001
111
000
a
b
c
Case 6
010
110
011
101
100
001
000
111

Fig. 3.16. Sub-cube division using 45 planes (named SD45 space division). Six tetrahedrons compose
the total sub-cube volume.
___________________________________________________________________________
31

Fig. 3.17. Sub-cube division using new planes (named SD1). Five tetrahedrons compose the total sub-
cube volume.
The flow diagram to find out the tetrahedron where the reference vector is pointing to
using SD1 is shown in Fig. 3.18. Once the tetrahedron is found, the state vectors to be used
and their duty cycles can be determined using Table 3.

Fig. 3.18. Flow diagram to find the tetrahedron where the reference vector is pointing to using space
division SD1

___________________________________________________________________________
32
TABLE 3 SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON TETRAHEDRON CASE
USING SPACE DIVISION SD1
Tetrahedron Space vectors sequence Switching times
Case 1
U
1
= (a,b,c+1)
U
2
= (a+1,b,c+1)
U
3
= (a,b+1,c+1)
U
4
= (a,b,c)
T
1
= -r
a
r
b
+ r
c

T
2
= 1 - T
1
- T
3
- T
4

T
3
= r
b

T
4
= 1 - r
c

Case 2
U
1
= (a+1,b,c)
U
2
= (a+1,b+1,c)
U
3
= (a+1,b,c+1)
U
4
= (a,b,c)
T
1
= r
a
r
b
- r
c

T
2
= 1 - T
1
- T
3
- T
4

T
3
= r
c

T
4
= 1 - r
a

Case 3
U
1
= (a+1,b+1,c+1)
U
2
= (a+1,b+1,c)
U
3
= (a+1,b,c+1)
U
4
= (a,b+1,c+1)
T
1
= r
a
+ r
b
+ r
c
-2
T
2
= 1 - r
c

T
3
= 1 - T
1
T
2
- T
4

T
4
= 1 - r
a

Case 4
U
1
= (a,b+1,c)
U
2
= (a+1,b+1,c)
U
3
= (a,b+1,c+1)
U
4
= (a,b,c)
T
1
= -r
a
+ r
b
- r
c

T
2
= 1 - T
1
- T
3
- T
4

T
3
= r
c

T
4
= 1 - r
b

Case 5
U
1
= (a+1,b+1,c)
U
2
= (a+1,b,c+1)
U
3
= (a,b+1,c+1)
U
4
= (a,b,c)
T
1
= (r
a
+ r
b
- r
c
)
T
2
= (r
a
- r
b
+ r
c
)
T
3
= 1 - T
1
T
2
- T
4

T
4
= 1 - (r
a
+ r
b
+ r
c
)

In order to compare SD45 and SD1 space divisions, the distances between the
reference vector and the four state vectors that form the tetrahedron where the reference
vector is pointing to can be determined. In this work these distances are denoted d
1
,d
2
,d
3
,d
4
. In
Fig. 3.19, the distances d
i
using SD45 and SD1 are shown.
Depending on the used space division (SD45 or SD1), the reference vector is
generated using different state vectors. Mathematically, the reference vector is correctly
generated using both tetrahedrons but the distances d
i
change and consequently the ripple of
the output signals also changes. The output current ripple is related to the value of the
distances d
i
. If these distances decrease, it means that the reference vector is generated with
nearer state vectors and therefore the instantaneous error due to each state vector is lower. A
merit figure can be defined in order to show what are the distances d
i
in each case and what is
the better solution depending on the reference vector coordinates. This merit figure is defined
as:
___________________________________________________________________________
33
4 3 2 1
1 1 1 1
d d d d
F + + + =
(3.2)

Fig. 3.19. Generation of the reference voltage using the four nearest state vectors with SD45 (a) and
SD1 (b). The distances between the state vectors and the reference vector are different
In order to pick out which sub-cube division depending on the reference vector
coordinates inside the sub-cube is better, F functions for both space divisions are calculated
(F
SD45
and F
SD1
). Finally the function F
T
is defined as the difference of F
SD1
and F
SD45
:
45 1 SD SD T
F F F =
(3.3)
F
T
can be determined for all possible locations of the reference vector in the sub-cube.
In the control regions where F
T
is lower than zero, SD45 appears as the better solution. On the
other hand, in the control regions where F
T
is greater than zero, SD1 improves the ripple
behavior.
In Fig. 3.20, simulation results using SD45 (3.20.a) and SD1 (3.20.b) are shown. It can
be seen that undesired ripples in the output phase currents using SD1 appear.

a) b)
Fig. 3.20. Output phase currents using SD45 (a) and SD1 (b) for a three level four-leg four-wire diode
clamped converter.
___________________________________________________________________________
34
Using SD1, the distortion in the output phase currents occurs when the reference
vector moves from a sub-cube (sub-cube 1) to an adjacent sub-cube (sub-cube 2). Adjacent
tetrahedrons from both sub-cubes have only two common state vectors. In the transition
between adjacent tetrahedrons, there is only one not-common state vector with non zero duty
cycle that generates the reference vector. This is shown in Fig. 3.21, where the not-common
state vector between adjacent tetrahedrons in adjacent sub-cubes is emphasized using a circle.
The contribution of this state vector to the output currents is completely different and
therefore, undesired ripples appear (Fig. 3.20b).

Fig. 3.21. Transition between adjacent sub-cubes using space division SD1. State vectors with non
zero duty cycle create output current distortion.
The problem of ripple distortion can be solved defining other new planes to divide the
control region sub-cubes. New tetrahedrons are obtained using SD1 but rotating them 90
over b axis. The obtained tetrahedrons (named space division SD2) are represented in Fig.
3.22. In the same way that using previous 3D space divisions, other flow diagram can be
defined to find out the tetrahedron where the reference vector is pointing to. The flow diagram
for space division SD2 is shown in Fig. 3.23. In Table 4, the state vectors sequence and the
corresponding duty cycles using this space division are shown.
___________________________________________________________________________
35

Fig. 3.22. Sub-cube division SD2. Five tetrahedrons compose the total sub-cube volume.

Normalized
reference vector
(U , U , U )
an bn cn
a = integer (U )
b = integer (U )
c = integer (U )
r = U - a
r = U - b
r = U - c
an
bn
cn
a
b
c
an
bn
cn
-r + r + r >1
a b c
r - r - r <0
a b c
r + r - r >1
a b c
r + r + r >2
a b c
Yes No
Case 6 No Yes
Case 7
Case 8
Yes No
No Yes
Case 9 Case 10

Fig. 3.23. Flow diagram to find the tetrahedron where the reference vector is pointing to using space
division SD2.

___________________________________________________________________________
36
TABLE 4 SPACE VECTORS SEQUENCE AND DUTY CYCLES DEPENDING ON TETRAHEDRON CASE
USING SPACE DIVISION SD2
Tetrahedron Space vectors sequence Switching times
Case 6
U
1
= (a+1, b, c+1)
U
2
= (a+1, b+1, c+1)
U
3
= (a, b, c+1)
U
4
= (a+1, b, c)
T
1
= -r
a
r
b
+ r
c
- 1
T
2
= 1 - T
1
- T
3
- T
4

T
3
= 1 r
a

T
4
= 1 - r
c

Case 7
U
1
= (a, b, c)
U
2
= (a, b+1, c)
U
3
= (a, b, c+1)
U
4
= (a+1, b, c)
T
1
=1 - r
a
r
b
- r
c

T
2
= 1 - T
1
- T
3
- T
4

T
3
= r
c

T
4
= r
a

Case 8
U
1
= (a, b+1, c+1)
U
2
= (a+1, b+1, c)
U
3
= (a, b+1, c)
U
4
= (a, b, c+1)
T
1
= -1 - r
a
+ r
b
+ r
c

T
2
= 1 - T
1
T
3
- T
4

T
3
= 1 - r
c

T
4
= 1 - r
b

Case 9
U
1
= (a+1, b+1, c)
U
2
= (a+1, b+1, c+1)
U
3
= (a, b+1, c)
U
4
= (a+1, b, c)
T
1
= -1 + r
a
+ r
b
- r
c

T
2
= r
c

T
3
= 1 r
a

T
4
= 1 - T
1
T
2
T
3

Case 10
U
1
= (a+1, b+1, c+1)
U
2
= (a, b+1, c)
U
3
= (a, b, c+1)
U
4
= (a+1, b, c)
T
1
= (-1 + r
a
+ r
b
- r
c
)
T
2
= (1 - r
a
+ r
b
- r
c
)
T
3
= (1 - r
a
- r
b
+ r
c
)
T
4
= 1 - T
1
T
2
- T
4

In order to avoid the presence of not-common state vectors, adjacent sub-cubes in the
total control region are divided using SD1 and SD2 alternately. Using this configuration in the
control region, adjacent tetrahedrons from adjacent sub-cubes have three common state
vectors and in the transition instant, the fourth state vector has zero duty cycle. So, the
movement between adjacent sub-cubes is performed avoiding the presence of state vectors
with non negligible duty cycles. This space division is named SD12 and is represented in Fig.
3.24.
___________________________________________________________________________
37

Fig. 3.24. Adjacent sub-cubes in the total control region divided using SD1 and SD2 alternately
(named SD12 space division)
Considering the combination of the SD1 and SD2 control region division, the same
simulations can be carried out. In Fig. 3.25, simulation output phase currents using SD12
space division are shown. It can be seen that the obtained results are very similarto those
presented in Fig. 3.20a.

Fig. 3.25.Output phase currents using simultaneously the two new planes division generating a pure
sinusoidal reference for a three level four-leg four-wire diode clamped converter.
In spite of its advantages the 3D-SVM is not commonly used method of modulation. It
usually is used in 4 leg 4 wire systems (for example in active filters), but in symmetric
systems without neutral wire more suitable are methods operating only on the plane.

___________________________________________________________________________
38
3.5. SVM in Coordinates
Most popular method of two dimensional Space Vector Modulation bases on nodes
projection, of cube constructed by abc versors, on plane (shown previously in Fig. 3.8 and
3.9).
For such modulation most convenient is polar representation of reference voltage
vector. By two simple equations (Eq.3.1) it is possible to calculate length of the reference
vector and its angle as follows:
) (
_
2 2

=
+ =
U
U
arctg
U U ref U
(3.4)
A three-phase three-level converter provides twenty seven vectors, (Fig. 3.26):
3 zero (000, 111, 222),
12 internal (100, 211, 110, 221, 010, 121, 011, 122, 001, 112, 101, 212),
6 middle (210, 120, 021, 012, 102, 201)
6 external (200, 220, 020, 022, 002, 202).
External vectors divide plane into six sectors (Fig. 3.26.). Voltage angle can also be
used to determine the sector, since each section encloses in 60
o
. In each sector calculations
carried out to achieve vectors duration times are the same and the difference is only in power
switch selection for the gating signal. Thus, the reference vector is normalized to the first
sector and after evaluation of vectors switching times a proper transistors switching sequence,
for reference position, is created.
___________________________________________________________________________
39

Fig. 3.26. Plane division into six sectors by external vectors.
Each sector is divided into four triangular regions by the internal and medium vectors
as shown in Fig. 3.27. Reference vector U_ref is obtained by switching on (for proper time)
three adjacent vectors in each region, but it can be realized by the different on/off sequence,
what have influence on performance of modulator.

Fig. 3.27 Sector division into regions by internal and medium vectors.
___________________________________________________________________________
40
For calculation of duration times for all vectors, a value of modulation index M
(proportion of commanded voltage in respect to DC link voltage) is indispensable. There are a
few different definitions of M factor presented in Table 5
TABLE 5. MODULATION INDEX
No. Modulation index Description
1.
DC
U
ref U
M
_ 3
=
M = 1 when U_ref trajectory lies on inscribed
circle in the hexagon.
2.
DC
U
ref U
M
=
2
_ 3

M=1 when U_ref trajectory lies on circonscrit
circle on the hexagon.
3.
DC
U
ref U
M

=
2
_

M=1 for the block operation (square wave) of the
inverter.

Table 5 presents M factor calculations for two level converters where no additional
division of the sector is performed. For multilevel converters this value is multiplied by n-1
(where n number of levels) to achieve M=1 for U_ref length equal to shortest (internal), non
zero vector on the plane.
To find the region in which the ordered vector lies, two factors m
1
and m
2
called small
modulation indexes are needed. These factors are projection of the modulation index M on to
external vectors limiting the section as it is shown in Fig. 3.28.
3
sin
M 2 m
)
3
sin
(cos M m
2
1
=
(3.5)
After calculation of small modulation indexes m
1
and m
2
, time durations for all vectors
in the region are calculated according to Table 6.
___________________________________________________________________________
41

Fig. 3.28. Small Modulation indexes m
1
and m
2
as a function of commanded voltage vector.
TABLE.6. SELECTION OF REGION DEPENDING ON MODULATION INDEXES.
Region Duration of the switching states
m1>1 1
T1=m1-1
T2=m2
T4=2-m1-m2
T0=T3= T5= 0
m1<1,
m2<1,
m1+m2>1
2
T2=m1+m2-1
T4=1-m2
T5=1-m1
T1= T3= T0=0
m2>1 3
T2=m1
T3=m2-1
T5=2-m1-m2
T0= T1= T4=0
m1<1,
m2<1,
m1+m2<1
4
T4=m1
T5=m2
T0=1-m1-m2
T1=T2=T3=0
___________________________________________________________________________
42
It is significant that for ordered vector placed inside the hexagon the sum of small
modulation indexes is smaller or equal 2, thus it is safe to calculate vectors lifespan from
those factors. Duration of the sum of all vectors will be equal to 1, multiplying this values by
sampling time we achieve switching times for those vectors. Duty cycles for transistors are
calculated by adding time of vectors which are affecting that transistors.
U
DC
A C B
D_R_up
D_S_up D_T_up
D_R D_S D_T
_______
D_T_up
_______
D_S_up
_______
D_R_up
____
D_R
____
D_S
____
D_T

Fig. 3.29. Duty cycles arrangement for NPC three level converter.
Classical modulation for three-level converter uses symmetrical placement of zero and
internal vectors. It means that time T
0
dedicated for zero vector is divided by three and each
of zero vectors (000, 111, 222) is selected for one third of that time. Similarly time devoted to
internal vectors is divided by two and each vector (e.g. 211 and 100) is switched on for half of
the calculated time [P1]. This type of modulation provides good neutral point balance because
of equal selection of small (redundant) vectors, which is followed by equal usage of DC link
capacitors. Although good voltage equalization in DC link and minimization of current and
torque ripples thanks to high number of different voltage states in sampling, this modulation
introduces high switching losses (all possible vectors are used Fig. 3.30 -3.33). In 4
th
region
number of switching reaches twelve and in other regions six or eight in sampling time.
___________________________________________________________________________
43

Fig. 3.30. Vector selection sequence in 4
th
region.

Fig. 3.31. Switching sequence for reference vector lying in the 4
th
region.
U_ref
T
0
T
5
T
3
T
2
T
1
T
4
U_ref
T
0
T
5
T
3
T
2
T
1
T
4

Fig. 3.32. Vector selection sequence in 3
rd
region.
___________________________________________________________________________
44

Fig. 3.33. Switching sequence for reference vector lying in the 3
rd
region.
Very important feature of Space Vector Modulation is expanded linear operation range
of work. Carrier based modulation needs introduction of additional zero sequence signal to
expand the operation range. Because of vectors arrangement in the abc and space, shown
in Fig. 3.34. triangular third harmonic is automatically added. Thus there is no need to modify
reference voltage signal to achieve wider linear operation range of the modulator.

t
2
3
1
4
5
6
1
1
4
5
6
2
3

Fig 3.34. Transformation abc coordinates into space.
___________________________________________________________________________
45
3.6. Modulation With Simplified Duty Cycle Calculations
Development of Digital Signal Processors (DSP) pushed out sinusoidal modulation
with analog carrier signal. However its simplicity was an incentive to develop modulation
algorithms as simple as SPWM and possible to introduce into DSP [B1, H1, M2, M6]. Those
methods base on calculation of the duty cycles from instantaneous reference phase voltages in
respect to DC-link voltage. For each phase the duty cycle is calculated separately from the
equation as below:
1) (n
U
2
U
u
DC
DC
i_ref

+
=
i
duty_cycle (3.6)
where i-phase number (A,B,C); n-number of converter levels
Duty cycle calculated from Eq. 3.6 is between 0 and n-1. Integer part of this value is
number of transistors above output point switched on for whole sampling period and the rest
of duty cycle multiplied by sampling time is switch on time for the transistor (Fig. 3.35).

Fig. 3.35. Simplified calculation of duty cycles for multilevel converters.
___________________________________________________________________________
46
Although, this method seems very simple to implement and has little processor time
consumption it has two main disadvantages:
The zero sequence signal (instantaneous value) has to be added to expand linear
operation region of the converter. Thus, additional calculations are needed,
There is no possibility to control capacitor voltages and therefore, an unbalance may
occur.
3.7. Summary
From presented survey of PWM techniques it can be seen that less convenient for
digital implementation is sinusoidal PWM, because most of control processing schemes
generate DC values for linear regulators instead of sinusoidal signals. The 3D-SVM is used
for 4-wire systems where non symmetrical loads may occur. From presented modulation
methods two dimensional (Classic) Space Vector Modulation is most suitable for symmetrical
loads like 3-phase motors. It also gives largest possibilities to introduce improvements which
guarantee DC link capacitors voltages balancing and additionally minimize number of
switching.

___________________________________________________________________________
47
4. DC Capacitors Voltage Balancing Methods in NPC
Converters
4.1. Introduction
For proper operation of NPC converters DC link capacitor voltages must be equal.
Any deviation from this state will affect output currents and voltages. Reference value of the
output voltage is referred to the DC link voltage, but does not take into account any
discrepancies of neutral point voltage. Unbalance in DC-link induces inequality of redundant-
internal vectors and distortions in medium vectors. In such cases generated voltage is different
than reference. Output voltage influences current which is most important measured value
used for further calculations, The current distortions may cause dysfunction of whole control
system. Fig. 4.1 shows experimentally measured current distortions caused by DC-link
voltages unbalance.

Fig. 4.1. Operation of NPC converter with unbalanced capacitors voltage.
From the top: DC-link capacitors voltages (70V/div), phase current (5A/div), phase voltage
(150V/div).
DC Capacitors Voltage Balancing Methods in NPC Converters
___________________________________________________________________________
48
Most unbalances are caused by use of medium vectors which clamp one phase to
neutral point of DC-circuit and introduce additional current flowing from, or to, neutral point.
As result inequalities occur in charging and discharging of capacitors.

Fig. 4.2. Neutral point current flow caused by use of medium vectors.
From the top: phase voltages, phase currents in idle mode of IM (cos=0),
Phase currents during load mode of IM (cos=0.85)
Fig. 4.2 shows parts of currents in phases connected to the neutral point of the
converter by the medium vectors. Current is symmetrical, thus it do not introduce constant
difference to capacitor voltages but oscillations with third harmonic of fundamental output
frequency.
Other source of imbalances in capacitor voltages are asymmetries in the system. Non
equal delays during transistors switching introduce differences in capacitors usage and
increasing difference between its voltages.
This chapter presents several approaches to avoid any unbalance in DC-link
capacitors.
___________________________________________________________________________
49
4.2. Hardware Solution for DC Link Capacitor Voltages Balancing
Easiest way to balance the voltages on DC link capacitors is introduction of
independent chopper circuit for each capacitor which guaranties the proper value of voltage.
This method has two significant disadvantages:
requires additional components,
causes big energy losses.
Fig. 4.3 presents typical circuit for passive capacitors voltages balancing.

Fig. 4.3. Chopper circuit for balancing DC link capacitors voltage in 3-level NPC converter.
4.3. Virtual Vectors Based DC Capacitors Voltage Balancing Method
Unbalance in DC link caused by internal vectors can be neutralized by equal use of
those vectors, what is made in the symmetric SVM. Additional unbalance is introduced by
medium vectors through connection of one phase to neutral point in DC link. One of the
methods to solve this problem, presented in [P1, P2], introduces to the modulation additional
virtual vector, parallel to the medium vector, which utilizes both capacitors equal and does not
affect voltage balance in DC circuit.
Virtual vector U
V
is summation of medium vector and internal vectors in equal
proportion. Thus, it is shorter than medium vector and divides the sector into five regions
instead of 4 in classical modulation, see Fig. 4.4.
___________________________________________________________________________
50

Fig. 4.4. Illustration of virtual vector U
V
used for capacitor voltages balancing.
Using the same calculation for small modulation indexes, presented in Eq.(3.2) new
dependencies for vectors usage can be calculated as shown in Table 7.
TABLE 7. VECTOR SWITCHING TIMES CALCULATION FOR VIRTUAL VECTOR METHOD
Region Duration of the switching states
A
T
V
=3(m
1
+m
2
-1)
T
4
=2-2m
1
-m
2
T
5
=2-2m
2
-m
1
B
T
V
=1.5m
2
T
1
=m
1
+0.5m
2
-1
T
4
=2-2m
2
-m
1

C
T
V
=1.5m
1
T
2
=0.5m
1
+m
2
-1
T
5
=2-2m
1
-m
2

D
T
V
=3(m
1
+m
2
-1)
T
4
=2-2m
1
-m
2
T
5
=2-2m
2
-m
1

In this type of modulation, external vectors are used more often and medium vector
usage is brought to minimum. In regions B and C both internal vectors are used because
virtual vector consists of them. Region D, in comparison to classic SVM technique, has been
changed mostly. In this part of plane all active vectors are used (internal, medium and
external) which means five vectors, instead of three, are used in each sampling time.
New division in sector requires additional orthogonal (instead 60 degrees) projection
of modulation index for A, B, C, D regions determination.
___________________________________________________________________________
51
This method guaranties better DC link capacitor voltages balancing than classical
SVM modulation, but introduces additional switching per sampling time and causes higher
switching losses. Also, calculation of duty cycles is more complicated because of different
angles and regions division.
4.4. DC Link Balance With Additional Controller
Neutral Point (NP) balance algorithm which introduces least changes to the
modulation algorithm and does not increase number of switching is based on additional
controller [H4, M8, P2, P3, P5]. Additional control loop chooses redundant vectors according
to power flow direction and difference of the capacitor voltages to achieve best NP voltage
balance. Fig. 4.5 presents an example of circuit for NP balance control. This example uses
hysteresis controller for voltage balance, but it is possible to use other kind of controllers.
{
{
Sign(P)
LOAD
Compare
U
C2
U
C1
Modulator with
redundant
vector selection
Control
Algorithm

Fig. 4.5. NP voltage balancing algorithm with additional controller.
This method is simple to implement in digital system, does not increase losses and can
efficiently bring NP voltage error to minimum.
___________________________________________________________________________
52
4.5. DC Capacitors Voltages Balancing With Carrier Based SPWM
In the SPWM one of the easiest approaches to balance capacitors voltages in
multilevel converters is introduction of additional offset and amplitude correction of carrier
signals. Each carrier signal (in level shifted carriers method) is responsible for one capacitor
voltage. Changing its amplitude, to match the actual value of capacitor voltage, avoids output
voltage distortion. This adaption changes utilization of DC-link. Fig. 4.6 shows carriers
placement during unbalanced operation. Modified carriers automatically increases use of
capacitor with the higher value of the voltage, what is followed by decreasing of the
unbalance.

t
U
NP

Fig. 4.6. Carrier signals modification during unbalance operation.
This method is called natural balancing in CB-PWM.
4.6. Summary
Methods presented in this Chapter are mostly based on hardware solution and
introduce additional losses, and cannot guarantee proper operation of the converter. Therefor,
for further consideration a combination of additional controller with redundant vector has
been chosen because it gives also possibilities to minimize losses.

___________________________________________________________________________
53
5. Modified Space Vector Modulation Algorithm for NPC
Converters.
5.1. Introduction
Nowadays, most of Adjustable Speed Drives use closed loop vector control [K1, Z2,
Z3, Z4]. All those methods use at least current and DC link voltage sensors, as well as flux
and torque estimators. As the modulator is part of the control algorithm, it can use estimated
and measured variables. Proper use of those quantities also helps to improve the performance
of modulator. In this Chapter an improved modulation algorithm based on the SVM principles
with switching number minimization and DC-link capacitor voltage balancing is presented.
Additionally, the operation range of presented method is extended by overmodulation
algorithm.
5.2. DC-Link Capacitors Voltage Balancing
In Chapter 4 several methods for DC link capacitor voltages balancing were presented.
Most of them have disadvantages like requirement of additional sensor or increased switching
frequency. Algorithm presented below uses only variables and sensors applied in control
algorithm. For proper DC link voltages balancing, energy flow direction and difference
between capacitor voltages is sufficient. Depending on those two attributes and choosing
proper redundant vector, charging or discharging of DC link capacitors is possible.

a) b)
Fig. 5.1. Example of redundant states with the same output voltage.
Modified Space Vector Modulation Algorithm for NPC converters
___________________________________________________________________________
54
Fig. 5.1a and 5.1b present two redundant short vectors which produce identical output
voltage, but use different capacitors to deliver the energy.
Determination of the energy flow direction in Adjustable Speed Drives can be done by
determination one of the quantities: instantaneous power p , electromagnetic torque m
e
, torque
angle or current vector to voltage vector angle .

Fig. 5.2. Vector diagram of basic Induction Motor quantities.
Fig 5.2 presents basic relationships between induction motor (IM) quantities which are
helpful for determination of the IM operation mode. Choosing the proper quantity to use in
the modulation algorithm depends on the purpose of the converter and availability in the
control. Also, the complexity of calculation can be the reason to use one quantity from among
all.
Calculating the instantaneous power delivered to the motor requires only the
knowledge about voltage and current, all kind of converters have current sensors and
converter voltage sensor or calculation block. From those parameters active power p is
obtained:

+ = i u i u p
(5.1)
Sign of the power will define the converter operating mode inverter or rectifier, i.e. if
the energy is flowing from the capacitors to the motor or inversely.
Similar procedure of calculation is for electromagnetic torque m
e
which is the
result of vector product of stator flux
S
and stator current I
S
:
___________________________________________________________________________
55
( )
pairs pole of number is p where
2
3
p m
b
b e S S
I =
*
(5.2)
In this case also the sign of the torque multiplied by mechanical speed shows the
direction of energy flow. This method strongly depends on accuracy of flux estimation.
Calculation of torque angle is not needed, only the sign of the matters. Thus, current
transformation to d-q stator flux rotating frame and sign of i
d
current determines the direction
of energy flow.
TABLE 8. DIRECTION OF ENERGY FLOW DETERMINATION FOR ASD-IM
Parameter
Inverter mode -
Motoring
Rectifier mode -
Regenerating
P P > 0 P < 0
m
e
,
m
m
e

m
>0 m
e

m
< 0
(i
d
) > 0 (i
d
>0) < 0 (i
d
<0)
< /2 > /2

Most reliable parameter is power p because depends only on measured current and
output voltage, which is calculated from duty cycles of proper transistors. According to
assigned power proper short vector can be used. In contrast to the symmetrical SVM, only one
of the redundant vectors is applied in one sampling time and as consequence reduction of
switching in all Regions. Fig. 5.3 and Fig. 5.4 present vectors selection and transistors gating
signals. Table 9 presents internal vectors selection according to power P and capacitors
voltage difference.
TABLE 9. INTERNAL VECTORS SELECTION FOR DC LINK CAPACITORS BALANCING
Sector
P>0 (motoring mode) P<0 (regenerative mode)
C1<C2 C1>C2 C1<C2 C1>C2
I 211 and 221 100 and 110 100 and 110 211 and 221
II 221 and 121 110 and 010 110 and 010 221 and 121
III 121 and 122 010 and 011 010 and 011 121 and 122
IV 122 and 112 011 and 001 011 and 001 122 and 112
V 112 and 212 001 and 101 001 and 101 112 and 212
VI 212 and 211 101 and 100 101 and 100 212 and 211

___________________________________________________________________________
56

Fig. 5.3. Choice of proper short vector for capacitor voltage balancing. Region 2.

Fig. 5.4. Redundant vectors waveforms per sampling time. Sector 1; region 2

5.3. Switching Number Minimization
The method presented in the previous Subchapter guaranties reduction of number of
switching related with DC link capacitors voltage equalization. It is possible to make further
reduction of switching number in low output voltage operation mode by proper use of zero
vectors in the 4
th
region. For two level converters Discontinues PWM methods are well
known [B7, H6, M9, M10], In this method of one leg of converter is clamped to upper or
lower DC link and two other phases modulated [H8, M9, M10]. Introducing further
improvements it is possible to reduce switching losses up to 50% in two level converter. The
same method presented in [M9] can be adopted for multilevel converters in closest to - grid
origin regions.
___________________________________________________________________________
57
It bases on assumption one phase is clamped to NP, lower or upper DC bus. It gives
only one zero vector per sampling time. However, switching losses strongly depend on load
power factor angle. Therefore, the maximal reduction can be obtained, when peak of the
phase current is located in the centre of clamped (non modulated) regions. It is necessary to
observe the peak current position and select proper zero vector for this purpose. It can be
implemented by simple relation describing positive or negative peak of current polarity in
each phase (Fig. 5.5):

If 0 k 0 i i i
0 C B A
= < (5.3)
If 1 k 0 i i i
0 C B A
= >

Fig. 5.5. Determination of k
0
factor from waveform of currents.
If the peak of current is positive (k
0
= 1) upper zero vector should be selected eg. (222)
but if the peak of current is negative (k
0
= 0) lower zero vector should be selected eg. (111).
Choice of zero vector is strongly connected with internal vectors selection. If in sampling time
the converter is fed from lower capacitor, it is recommended to use 111 vector instead of 222
vector to minimize switching. Proper use of zero vectors must be connected with redundant
vectors selection. To simplify the calculation and combine two features of modulator, an
additional variable k
1
was introduced to keep in conformity with voltage balancing procedure.
0 ) 0 ( ) 0 (
1 ) 0 ( ) 0 (
1 2 1 2 1
1 2 1 2 1
= < > > <
= < < > >
k p U U p U U if
k p U U p U U if
C C C C
C C C C
(5.4)
Taking into account capacitors voltage unbalance and peak of current, following
formula for use of zero vectors can be written as presented in Table 10.

___________________________________________________________________________
58
TABLE 10. ZERO VECTOR SELECTION
k
0

k
1

0
(negative peak current)
1
(positive peak current)
0 111 222
1 000 111

This method reduces the number of applied vectors per sampling time to three vectors
independently of the region in the sector. For the 4
th
region in comparison to symmetrical
SVM presented on Fig. 3.30 and 3.31, benefit shown in Fig.5.6 is significant.
D_R_up
D_R
D_S_up
D_S
D_T_up
D_T
T5 T4 T0 T5 T4 T0
1 1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0

D_R_up
D_R
D_S_up
D_S
D_T_up
D_T
T5 T4 T0 T5 T4 T0
1
1
1
1
1 1
2 2
2
1
1
1
1
1 1
2 2
2

a) b)
Fig. 5.6. Generation of output voltage for negative peak of current (k
0
=0)
a) in 4th region at U
C1
<U
C2
(k
1
=0), b) in 4th region at U
C1
>U
C2
(k
1
=1)

5.4. Overmodulation
Methods presented in Subchapters 3.2, 3.4, 3.5 and 3.6 are applied for linear range of
the modulation (M<1.814) [H5]. Attempt to use normal modulation in non-linear range will
generate smaller output voltage than reference. For vector controlled ASD it is important to
obtain reference voltage amplitude in the motor, since its responsible for flux and torque,
usually controlled quantities. Control algorithm can not work properly if output voltage is not
corresponding to input (reference) value. Use of nonlinear modulation and adjustment of
control, feedback signals will be strongly distorted, leads to full use of converter properties.
Generation of higher voltage can be achieved by nonlinear algorithm of modulation
called overmodulation (OVPWM). This procedure can not form sinusoidal waveform but
amplitude of first harmonic of output signal is equal to the reference value. It can be achieved
by proper modification of voltage space vector length and angle. Because in OVPWM region
___________________________________________________________________________
59
reference vector trajectory lies partly outside of the working hexagon, there is need to adjust
its length in places where the trajectory is inside the hexagon.
The OVPWM algorithm is divided into two sub-regions [H2, H6, L2]. First region is
for 1.814<M<1.904. In this region is possible to manipulate the length of the vector in some
parts of the trajectory as it is shown in Fig. 5.7.

Fig. 5.7. Voltage trajectories in first region of OVPWM.
red- reference voltage, blue modified voltage.
Angle of the output voltage is not changed. From the value of the modulation index
M a crossing angle
P
is calculated. For reference angle value between
P
and /3-
P
only
two vectors are used, external and middle vector. In this part small modulation indexes are
calculated as follows:
1 2
1
m 2 m
sin cos 3
sin cos 3
2 m
=
+

=
(5.5)
For such calculation summation of small modulation indexes is always equal 2.
When commanded angle is smaller than
P
normal modulation procedure is applied.
Because
P
= f(M) function is strongly nonlinear, it has been divided in three sections and
linearized (Fig. 5.8). Linearized characteristic of cross angle
P
bases on [H1, H6, N2]
following relation:
___________________________________________________________________________
60
>
>
> <
=
904 . 1 896 . 1 ( 0 5 . 5
896 . 1 818 . 1 ( 5 . 5 5 . 24
818 . 1 814 . 1 5 . 24 30
M
M
M
o o
o o
o o
P
(5.6)
p
12
6
0
1.814 1.86 1.904
M

Fig. 5.8. Crossing angle characteristic
P
=f(M) in first OVPWM region and its linearization.
For M=1.904 voltage trajectory is continuous and situated on the hexagon, no internal
vectors are used. For higher modulation index the voltage trajectory is discontinuous up to
M=2 when voltage becomes a square wave and each external vector is clamped for 1/6 of first
harmonic period. This feature is called six-step mode or square wave operation [H1, H6, L2].
In the second OVPWM region additionally output voltage angle is modified. After
entering sector output voltage vector is held until the reference angle crosses the hold angle
value
h
. After that, the modified value speeds up to next vertex of the hexagon and is held
there until crosses the hold angle value
h
in the next sector (Eq. 5.7, Fig. 5.9).
This procedure can be described as follows:
<
<

=
3 / 3 3 /
3 /
6 6 /
0 0
1
h
h h
h
h
h
(5.7)
___________________________________________________________________________
61
U
U
Im
Re
U ( 200)
1
3
h
h
_ref
3
U ( 220)
2
U ( 210)

Fig. 5.9. Reference and modified trajectory of voltage vector in second OVPWM region.
After calculation of modified angle
1
small modulation indexes are evaluated similar
like in the first OVPWM region:
1 2
1 1
1 1
1
m 2 m
sin cos 3
sin cos 3
2 m
=
+

=
(5.8)
Hold angle characteristic
h
=f(M) is nonlinear but can be linearized in three sections
(Fig. 5.10; Eq. 5.9) giving following conditions:

Fig. 5.10.
h
=f(M) characteristic and its linearization.
___________________________________________________________________________
62
>
>
>
=
0 . 2 994 . 1 ( 30 5 . 19
994 . 1 958 . 1 ( 5 . 19 2 . 17
958 . 1 904 . 1 ( 2 . 17 0
M
M
M
o o
o o
o o
h
(5.9)
The overmodulation algorithm is essential for full utilization of DC-link voltage in
ASD. Usually it is used to increase voltage and flux in high speed range of induction
machines. Unfortunately this modulation type distorts the output voltage from flattop
sinusoidal thru trapezoidal up to square wave for maximum modulation index (Fig. 5.11). As
consequence also the output current is strongly distorted.

Fig. 5.11. Overmodulation.
From the top : Phase to phase voltage, Phase voltage, phase current, modulation index.
5.5. Summary
Presented modifications in the SVM modulation, DC capacitors voltages balancing
and minimization of switching number in the 4
th
region of the converter output voltage plane
enables significant reduction of switching number in the whole range of modulation.
Unfortunately, decreasing the number of current forming states per sampling time increases
distortion of current waveform and as consequence higher torque ripples (Fig. 5.12; 5.13.).
___________________________________________________________________________
63
That distortions are highest in low speed operation mode, because in the 4
th
region is the
largest reduction of number of current forming states.
a) b)

Fig. 5.12. Steady state operation of IM in regions 1
st
, 2
nd
, 3
rd

a) classical modulation b) modified modulation
From the top: capacitors voltages U
C1
and U
C2
, phase voltage u
A
, phase current i
A
,

___________________________________________________________________________
64
a) b)

Fig. 5.13. Steady state operation of IM in regions 4
th

a) classical modulation b) modified modulation
From the top: capacitors voltages U
C1
and U
C2
, phase voltage u
A
, phase current i
A
,
a) b)

Fig. 5.14. Step change of the torque from 25% to 100% nominal (without speed control loop)
a) classical modulation b) modified modulation.
From the top: amplitude of stator flux
S
, phase current i
A
and torque m
e
.
___________________________________________________________________________
65
6. Three Level NPC Converter-Fed Induction Motor Drive
6.1. Introduction
This chapter presents mathematical description of induction machine (IM) based on
space vector notation and Direct Torque Control method used in simulations and experimental
setup.
6.2. Mathematical Description of Induction Machine
To describe a three phase IM by system of equations [K1] following assumptions are
made:
Three phase motor is symmetrical,
Only the fundamental harmonic is considered,
Effects of anisotropy, magnetic saturation, iron losses and eddy currents are
neglected,
All resistances and reactances are assumed to be constant,
Taking into consideration above assumptions, following instantaneous stator
phase voltage equations can be written:
dt
d
R i u
dt
d
R i u
dt
d
R i u
C
S C C
B
S B B
A
S A A
+ =
+ =
+ =
(6.1)
This set of equations can be transformed to one space vector equation, where space
vectors are defined as follows:
(t)] k (t) k (t) k [
3
2
C
2
B A
+ + = a a 1 k (6.2a)
0 (t) k (t) k (t) k
C B A
= + + (6.2b)
where (t) k (t), k (t), k
C B A
- instantaneous phase quantities, 1, a, a
2
complex unit vectors.
Three Level NPC Converter-Fed Induction Motor Drive
___________________________________________________________________________
66
General set of equations for three phase squirrel cage IM in reference frame rotating
with the angular speed
K
can be written as [K1]:

SK
SK
SK SK
I U
K S
j R + + =
dt
d
(6.3a)
rK
rK
rK
I ) p j( R 0
m b K r
+ + =
dt
d
(6.3b)
rK SK SK
I I
M S
L L + = (6.3c)
SK rK rK
I I
M S
L L + = (6.3d)
) m (m
J
1
L e
m
=
dt
d
(6.3e)
Above equations can be transformed to stationary - coordinate system to operate on
instantaneous values, which is more proper for modulator.
6.3. Control Strategy of Induction Machine
Control algorithm used in experiment, Direct Torque Control with Space Vector
Modulation (DTC-SVM), was presented in [H5]. Principle of operation bases on PI
controllers for torque and flux closed loops in stator flux oriented x-y rotating coordinates.
The output of controllers are stator voltages U
Sx
, U
Sy
in rotating frame and are DC component
in steady state (Fig.6.1).

Fig. 6.1. Block diagram of DTC-SVM.
___________________________________________________________________________
67
Commanded value of stator flux magnitude
SC
can be easy calculated from nominal
value of machine phase voltage:
N
f
=
2
U
N_phase_m
SN
(6.4)
Reference value of electromagnetic torque is generated in outer mechanical speed
control loop. Mechanical speed is measured by a sensor. Its value is subtracted from
commanded speed defined by user. Speed error is the input of PI controller and its output is
commanded torque.
6.4. Stator Flux and Torque Estimation
For experiment and simulation a Current Model in rotor coordinates has been chosen
for stator flux estimation. It uses rotor position and motor currents for stator flux vector
calculation. Coordinate system rotates with the angular speed of motor shaft
m
defined as:
dt
d
m
m
=
(6.5)
where
m
is the rotor position angle.
Taking into account pole pairs number, the system d-q rotates with angular speed
K
= p
b
m
.
Stator current vector must be transformed to d-q rotating frame to calculate rotor flux
[K1] as follows:
) I (L
L
R
) I (L
L
R
rq' sq' M
r
r
rq'
rd' sd' M
r
r rd'
=
=
dt
d
dt
d
(6.6)
Rotor flux must be transformed to - system for stator flux calculation according to:
s r s
I
s
r
M
L
L
L
+ = (6.7)
Stator flux vector is resolved to - components and calculated from Eq.(6.7)
according to block diagram shown in Fig. 6.2.
___________________________________________________________________________
68

Fig. 6.2. Block diagram of stator flux estimation
This estimator has very good accuracy in high and low speed operation, is resistive to
wrong initial conditions and also behaves good in steady and transient states. However it is
sensitive to motor parameters changes (L
r
, R
r
).
Torque calculation bases on equation [K1] in stationary reference frame -:
) i i (
2
3
p ) (
2
3
p m
s s s s b b e
= =
s
*
s
I Im (6.8)
Equation 6.8 shows that torque calculation depends strongly on current sensing
accuracy and stator flux estimation accuracy.
6.5. PI Controllers Design
According to Fig. 6.1 two PI controllers are used for torque and stator flux magnitude
regulation. Fig. 6.3 shows block diagram of PI controller.

Fig. 6.3. Block diagram of PI controller.
K
p
controller gain T
i
integration time of controller.

___________________________________________________________________________
69
Flux controller design
The block diagram of the flux control loop is shown in Fig. 6.4. The voltage drop on
the stator resistance is neglected. In the stator flux control loop the inverter delay is taken into
consideration.

Fig. 6.4. Stator flux magnitude control loop.
For the flux controller parameter design, the symmetry criterion can by applied [K1].
In accordance with the symmetry criterion the plant transfer function can be written as:
(6.9)
where: K
c
= 1 is the inverter gain,
0
is dead time of the inverter (
0
= 0 ideal
converter), T
2
= 1, and T
1
= T
s
is a sum of small time constants, which includes statistical
delay of the PWM generation and signal processing delay. The optimal controller parameters
can be calculated as:
(6.10)
Torque controller design
The block diagram of the torque control loop is shown in Fig. 6.5. The same like for
flux this control loops is based on the model presented in Fig. 6.2. However, coupling
between torque and flux is omitted. Because of that very simple model is obtained and for this
model any criterion cannot be applied.

Fig. 6.5. Block diagram of the torque control loop.
___________________________________________________________________________
70
In this case the simple (practical) way to design torque controller can be used. Starting
from the initial values e.g. K
pM
=1, T
iM
= 4T
s
the proportional gain K
pM
is increasing
cyclically. From these tests the best value of K
pM
for the fast torque response without
oscillation and small overshoot can be selected. For the sampling frequency, used in
experiment and simulation, 5kHz the best value of proportional gain is K
pM
= 17.
6.6. Summary
Presented Direct Torque and Flux Control with Space Vector Modulation (DTC-SVM)
in spite of simplicity is characterized by very good dynamic performance. It guaranties flux
magnitude and torque control without subordinated current control loops. This considerably
simplify the control scheme, controllers design as well as use advantage of separated SVM
algorithm. Therefore, contrarily to conventional DTC, operates with constant switching
frequency.

___________________________________________________________________________
71
7. Experimental Results
7.1. Introduction
To verify the proposed Modified SVM algorithm and its influence on operation of the
induction motor drive a laboratory model with 18 kVA NPC converter and 3kW Induction
machine.
7.2. Laboratory Setup
Laboratory setup (Fig. 7.1.) consists of:
Two NPC converters;
3kW IM and DC motor as load set;
Measurement and signal conditioning block
PC computer with dSpace 1104 control board;
Altera FPGA MAX II board with fiber optics interface for IGBTs
control signals.

Fig. 7.1. Block scheme of experimental laboratory setup.

Experimental Results
___________________________________________________________________________
72
The converters used for laboratory tests were experimentally constructed by Z.E.
TWERD company. The power circuit has been built using Mitsubishi IPM modules
PM75DSA120, what gives maximum continuous output power ~18kVA. DC circuit consists
of two DC links of two converters with sum of capacitance 9mF (2x4.5mF) and maximum
DC voltage 800V. Fig 7.2. presents view of the converter.

Fig. 7.2. NPC converter used in experiment.
Power transistors are controlled by peripheral modulator implemented in Altera FPGA
MaxII via fiber optics (Fig. 7.3). Modulation algorithm is separated from heart of the
control system enclosed in PC computer on dSpace control board dS1104. Communication
between these two devices is held by Serial Peripheral Interface (SPI) with 1Mb/s speed.
Small modulation indexes m
1
, m
2
, sector number and two additional bits responsible for DC
link voltages balance and zero vector selection were transmitted via SPI. From these values
duty signals for power transistors are.
___________________________________________________________________________
73

Fig. 7.3. Peripheral FPGA Altera Max II circuit used for modulation algorithms.
Control algorithm has been enclosed in dSpace ds1104 control board located in PC
computer (fig. 7.4). This platform includes power PC master processor, TMS320F240 slave
processor, D/A and A/D converters, several serial interfaces, 16 multipurpose I/O channels,
incremental encoder input, 3-phase PWM output and three single-phase PWM outputs.
However PWM channels can not be used for multilevel converters control, thus peripheral
modulator in FPGA device has been developed. Communication between user and dS1104 is
provided by Control Desk software. It is possible to program control board in C language via
this interface and communicate online with special GUI which can be built according to user
needs.

Fig. 7.4. dS1104 board in PCI computer slot.
___________________________________________________________________________
74
All data needed by control algorithm are delivered to A/D converters by measurement
circuit consisting of two LV-25 (LEM) voltage probes for both DC link capacitors voltages
measurement and two LA55P (LEM) current probes for IM stator current measurements.
Setup shown in Fig. 7.5 is prepared to control back to back NPC converter and measurements
are doubled.

Fig. 7.5. Measurement box.
In the experimental investigations 3kW squirrel cage IM has been used. The IM is
mechanically coupled with DC motor working as a load (Fig. 7.6). Table 11 presents IM
parameters.

TABLE 11. MOTOR PARAMETERS.
Number of pole pairs p
b
2
Nominal speed
N

148,2 rad/s
1415 rpm
Nominal torque m
N
20 Nm
Nominal current I
N
6.9 A rms
Nominal voltage U
N
3x380V
Stator and rotor resistance R
s
=R
r
1.84
Stator and rotor inductance L
s
=L
r
0.145 mH
Main inductance L
m
0.135 mH
___________________________________________________________________________
75

Fig. 7.6. Laboratory setup of motors. On the left DC motor, on the right Induction machine.
Lab setup consists two NPC converters but only one, feeding the Induction Motor, is
controlled. The other converter works as classic diode rectifier. This solution can be easily
adopted to buck-to-buck converter by adding second FPGA device for front-end converter
modulation.
7.3. Experimental Results
Comparative Examinations of Modulation Methods
Proposed modulation algorithm guaranties different efficiency improvement for low
and high speed operation mode, thus all tests have been repeated for different modulation
indexes M<1.0 and M>1.0.
For modulation index M<1.0 use of Modified Space Vector Modulation increases
efficiency of the converter significantly (Fig. 7.10.).However, this improvement is occupied
by increased distortion of the motor current resulted from reduction of current forming states
number. Fig. 7.7. presents comparison of proposed modified method with classical Space
Vector Modulation (SVM). Current THD has increased from 2,4% to 3,4% (see Table 12.
Norma LEM D6100).

TABLE 12. COMPARISON OF CURRENT TOTAL HARMONIC DISTORTION.
Operating region
Current THD
Symmetrical SVM Modified SVM
M<1.0 2.4 % 3.4 %
M>1.0 3.0 % 3.8 %

___________________________________________________________________________
76
Symmetrical SVM
Modified SVM

Fig. 7.7. Comparison of modulation techniques. 4
th
region operation M<1.0.
From the top : Stator fluxes
S
,
S
[1Wb/div] Phase voltage U
SA
[100V/div],
Phase current I
SA
[10A/div]
Zoom: Phase voltage U
SA
[100V/div], Phase current I
SA
[2A/div]
For higher modulation index (M>1.0) minimization of switching number is not so
high, thus efficiency improvement is smaller in this region. The highest total efficiency
improvement is for medium output power and reaches 0,8%. In comparison to classical SVM
losses are reduced by 18% (see Fig. 7.11).

___________________________________________________________________________
77
Symmetrical SVM
Modified SVM

Fig. 7.8. Comparison of modulation techniques. 1
st
, 2
nd
, 3
rd
region operation M>1.0.
From the top : Stator fluxes
S
,
S
[1Wb/div]; Phase voltage U
SA
[100V/div],
Phase current I
SA
[10A/div]
Zoom: Phase voltage U
SA
[50V/div], Phase current I
SA
[2A/div]

___________________________________________________________________________
78
Efficiency comparison
For efficiency tests Power Analyzer Norma LEM D6100 was used in configuration
presented in Fig. 7.9.

Fig. 7.9. Block diagram of laboratory setup.
This setup measures efficiency of all system including diode rectifier. Characteristics
presented in Fig .7.10 and 7.11 show influence of Modified SVM algorithm on the whole
system losses (not only switching losses!). For small output voltage (4
th
region operation)
profit from the proposed modulation technique is higher. It increases total efficiency by 2%
which is 25% less losses for nominal operation conditions (Fig. 7.10).
Efficiency comparison in 4th region
80
82
84
86
88
90
92
94
0,15 0,3 0,45 0,6 0,75 0,9 1,05 1,2 1,35
Electrical Power delivered to motor [kW]
E
f
f
i
c
i
e
n
c
y

[
%
]
Symmetric SVM Modified SVM

Fig. 7.10. Efficiency characteristics for classical and modified modulation in the 4
th
region.
___________________________________________________________________________
79
Efficiency comparison in regions 1,2,3
88
89
90
91
92
93
94
95
96
97
0,15 0,6 1,05 1,5 1,95 2,4
Electrical Power delivered to motor [kW]
E
f
f
i
c
i
e
n
c
y

[
%
]
Symmetric SVM Modified SVM

Fig. 7.11. Efficiency characteristics for classical and modified modulation in 1
st
, 2
nd
, 3
rd
region.
Semiconductor losses energy is transformed into heat, thus checking heat emission of
the IGBT modules working with different modulation techniques clearly shows advantages of
the proposed method. Fig. 7.12 shows comparison of heat emission of IGBTs after 30 minute
motor work at 60% nominal load, 60% nominal speed, U
DC
= 500V, f
S
= 5kHz, ambient
temperature = 25
o
C - started from ambient temperature. As it can be seen the surface
temperature of the module was reduced by 0.9
o
C for modified SVM.
Symmetrical SVM
Modified SVM

T
max
=39.3
o
C T
max
=38.4
o
C
Fig. 7.12. Comparison of heat emission in IPM modules.
___________________________________________________________________________
80
DC link capacitors voltage balancing comparison
In NPC multilevel converters balancing of DC capacitors voltages guaranties proper
working conditions of supplied motor drive. Disturbances of neutral point potential affect
output voltage and current (see Chapter 4). All passive methods assume symmetry of the
converter. Symmetrical SVM method does not take into account any parameter differences
between transistors or gating drivers. Figure 7.13. shows comparison of DC voltages during
load step change. Symmetrical SVM balances the capacitor voltages properly during idle
operation of the motor. After change of the load difference between capacitors voltages is
constantly rising. Proposed Modified SVM keeps the difference close to 0 constantly, even
after changing working conditions (Fig. 7.13).
Symmetrical SVM
Modified SVM
Fig. 7.13. Comparison of DC link Capacitors voltage balancing.
Load step change to 75% nominal torque.
From the top : Capacitors voltages U
C1
, U
C2
100V/div],
electromagnetic torque m
e
[12.5 Nm/div], Phase current I
SA
[10A/div].
Voltage unbalance in symmetric SVM is introduced by non equal transistor switching
delays caused by IGBT drivers and transistors themselves. To prove this properties, an
additional simulation was elaborated. Various delays in transistor signals were introduced in
range from 0 to 0.5s, which corresponds to practical delays values. Fig 7.14-7.16 show
obtained results. Note, that switching on Modified SVM bring capacitor voltages difference to
zero in spite of different transistor switching delays.
___________________________________________________________________________
81
Fig. 7.14. Voltage unbalance introduced by transistor signals delays (Symmetrical SVM).
From the top: Capacitor voltages U
C1
, U
C2
, Electromagnetic torque m
e
, stator current i
SA
.

Fig. 7.15. Voltage unbalance introduced by transistor delays (Symmetrical SVM).
Load step change from 0 to 15Nm.
C1
, U
C2
e
, stator current i
SA
.
___________________________________________________________________________
82
Fig.7.16. Modified SVM: switch-on process during voltage unbalance.
C1
, U
C2
e
, stator current i
SA
.
During speed reversal the Modified SVM introduces small error between capacitor
voltages, brought down to zero after the speed sign change.
Symmetrical SVM
Modified SVM
Fig. 7.17. Comparison of DC link Capacitors voltage balancing.
Speed reversal from-100rad/s to 100rad/s.
From the top : Capacitors voltages U
C1
, U
C2
100V/div],
e
SA
[10A/div].
___________________________________________________________________________
83

Fig. 7.18. Speed reversal from-120rad/s to 120rad/s with DC link voltage lack.
From the top : Capacitors voltage U
C1
, U
C2
100V/div],
e
SA
[10A/div].
Control strategy examination
In DTC-SVM Induction Machine control method, torque rising and flux stabilization
have primary meaning. Fig. 7.19. shows speed reversal of IM, most stressed examination of
control. Modified SVM does not have any negative influence on control algorithm, flux is
kept on the same level in both cases, Symmetrical and Modified SVM. Torque rising and its
stabilization is also unchanged.

Symmetrical SVM
Modified SVM

Fig. 7.19. Speed reversal from-100rad/s to 100rad/s.
From the top : Stator flux magnitude
m
[0.6Wb/div],
e
SA
[10A/div].
___________________________________________________________________________
84
Overmodulation tests
Overmodulation extends operation range of the converter up to maximum possible
output voltage. Although its advantages nonlinear algorithm has significant influence on drive
parameters. Use of nonlinear modulation introduces heavy distortions into the motor current
and voltage. Distorted electrical parameters lead to flux and electromagnetic torque
deformation (Fig. 7.20 7. 21.). Therefore, to guarantee proper working conditions for the
drive with vector control DTC-SVM it is necessary to change PI controllers parameters during
operation in overmodulation range.
a b

c d

Fig. 7.20. Overmodulation. a) M= 1.85, b) M=1.94 , c) M = 1.98 , d) M = 2.0
From the top : stator fluxes
S
,
S
[0.5Wb/div];
e
[5Nm/div],Phase current a), b), c) I
SA
[5A/div]; d) I
SA
[10A/div]

___________________________________________________________________________
85

Fig. 7.21.Transition process from linear modulation to six step mode.
From the top : stator fluxes
S
,
S
[0.5Wb/div]; electromagnetic torque m
e
[5Nm/div],
Phase current I
SA
[5A/div]
During OVPWM there is no possibility to balance capacitor voltages, especially when
M > 1.904, because internal vectors are not used. For M = 2.0 (six step mode) problem of
capacitors voltage does not exist, only external vectors are used and neutral point of the
converter is separated from the load.
7.4. Summary
Experimental results presented in this chapter confirm proper operation of proposed
Modified SVM. Introducing two algorithms in 4
th
and 1
st
, 2
nd
, 3
rd
regions improved
performance of the drive in following aspects:
Capacitors voltage balancing in whole linear working range of the
converter,
Increased system efficiency,
Important matter is absence of the new algorithm influence on performance of the
drive.
Additionally, presented method utilizes whole working range of the converter thanks
to nonlinear overmodulation technique with fluent passing from linear modulation mode.
Unfortunately, there is no possibility to control DC-link capacitor voltages during OVPWM
because of internal vectors absence in selection sequence. The other inconvenience of non-
linear algorithm is difference between flux and torque PI controllers gains in compare with
linear range gains.
___________________________________________________________________________
86
8. Summary and Closing Conclusions
This thesis studied basic problems related to topology solutions, investigation and
implementation of the PWM three-level inverter-fed induction machine drive. After review of
the basic three-level inverter topologies (Chapter 2) further considerations have been
concentrated on Neutral Point Clamped (NPC) converter. When implementing multilevel
converter, one of the most important tasks is selection of appropriate modulation strategy. In
the literature several modulation techniques has been presented : SPWM, SVM, 3D-SVM.
These PWM types have been analyzed in Chapter 3. Since 3L-NPC converters are mainly
applied in high power systems (over 100kW), therefore the problem of switching losses
becomes extremely important. Thus, the author of this work, basing on systematical study and
investigation of existing modulation techniques, has proposed Modified SVM algorithm
which minimizes NPC converter losses (Chapter 5).Additionally, the developed algorithm
includes following features:
Guaranties DC-link capacitors voltage balancing in linear operation
range,
Extends operation range to maximum, by non-linear Overmodulation
algorithm,
Reduces switching losses in whole linear working range of the
converter,
Minimal number of vectors used in one sampling time,
Bases on Space Vector approach,
Constant switching frequency,
Sinusoidal stator current waveform,
No additional sensors are required (only DC-link voltage and output
AC current are measured),
All parts of the drive control scheme were verified in simulation and experiment. The
whole scheme apart of the Modified SVM algorithm consist of: flux and torque controllers,
speed controller, flux and torque estimation algorithm.
Summary and Final Conclusions
___________________________________________________________________________
87
This complete structure have been presented in Chapter 6. Laboratory setup and results
of experimental investigation have been described in Chapter 7.

Based on the laboratory and simulation results, the advantage of developed drive can
be summarized as:
Good dynamic control of flux and torque,
Increased total system efficiency up to 2%,
In comparison to classical hysteresis based DTC lower sampling
frequency is required,
Although, the Modified SVM algorithm increases current flux ripples (when compared
with Symmetrical SVM) still the flux and current distortions are considerably lower than in
two level converters [K6]. Finally, in authors opinion proposed modulation algorithm can also
be applied for control 3L-NPC AC/DC converters used in renewable energy systems, active
filters etc. Proper operation of the system with highly demanding control algorithm, in means
of measurement and estimation accuracy, proves high quality of proposed Modified SVM
algorithm.

Summary and Final Conclusions
___________________________________________________________________________
88
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[1]. M. elechowski, M. Malinowski, P. Kaczyski, W. Koomyjski, M. Twerd, J. Zaski, DSP
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Dydaktyce ENID'2004, 20-22 wrzenia 2004, Pozna, Polska, str. 115- 122
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5.04.2005, Wisa, Polska, pp. 87-90.
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for Three-Level NPC PWM Inverter-Fed Induction Motor AMC2006, Istanbul, Turkey,
pp.523-528
[9]. M. Kazmierkowski, M. Jasiski, M. Malinowski, T. Patek, S. Styski, P. Antoniewicz, W.
Koomyjski, D. wierczyski, H. Ch. Soerensen, E. Friis-Madsen, L. Christiansen, W. Knapp,
Z. Zhou, P. Igic, Sea Wave Energy Converter Wave Dragon MW for Few Megawatts
Power Range, Elektrotechnika 2006 Conference, (na CD)
[10]. M. Malinowski, W. Kolomyjski, M. P. Kazmierkowski, S. Stynski Advanced DSP Control
of 3-level DC/AC Converter for Variable-Speed PMSG EPE-PEMC2006, Portoroz,
Slovenia, pp.889-894
[11]. M. Malinowski, W. Kolomyjski, M. P. Kazmierkowski, S. Stynski DSP/FPGA Control for
Variable-Speed Wind Turbines , IECON2006, Paris, France, pp. 5161-5166
[12]. J.I.Leon, R.Portillo, L.G.Franquelo, M.M.Prats W. Kolomyjski, New State Vectors Selection
Using Space Vector Modulation in Three Dimensional Control Regions for Multilevel
Converters , ISIE2006, Montreal, Canada, pp. 1376-1381.
[13]. M. Malinowski, W. Kolomyjski, M. P. Kazmierkowski, S. Stynski Control of Variable-
Speed Type Wind Turbines Using Direct Power Control Space Vector Modulated 3-Level
PWM Converter , ICIT2006, Mumbai, India, pp. 1516-1521
[14]. S. Stynski, W. Koomyjski, M. Malinowski, BADANIA SYMULACYJNE W PROGRAMIE
SABER UKADU STEROWANIA TRJPOZIOMOWYM PRZEKSZTATNIKIEM DC/AC ,
MIS-4, Kocielisko, Polska, pp. 173-180
[15] M. Kamierkowski, M. Jasiski, M. Malinowski, T. Patek, S. Styski, P.
Antoniewicz, W. Koomyjski, D.wierczyski, H. Ch. Soerensen, E. Friis-Madsen, L.
Christiansen, W. Knapp, Z. Zhou, P. Igic, "Sea Wave Energy Converter - Wave Dragon MW
for Few Megawatts Power Range", Elektrotechnika 2006 Conference, (on CD)
___________________________________________________________________________
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[16] Andrzej Sikorski, Marek Korzeniewski, Adam Ruszczyk, Marian P. Kamierkowski, Patryk
Antoniewicz, Wojciech Koomyjski, Marek Jasiski, "A Comparison of Properties of Direct
Torque and Flux Control Methods (DTC-SVM, DTC-d, DTC-2x2, DTFC-3A)" EUROCON
2007 The International Conference on "Computer as a Tool" Warsaw, September 9-12
[17] M. Kamierkowski, M. Jasiski, M. Malinowski, T. Patek, S. Styski, P. Antoniewicz, W.
Koomyjski, D. wierczyski, H. Ch. Soerensen, E. Friis-Madsen, L. Christiansen, W. Knapp,
Z. Zhou, P. Igic, "Sea Wave Energy Converter - Wave Dragon MW for Few Megawatts Power
Range", Proceedings of Electrotechnical Institute, Issue 231, 2007
[18] Malinowski, M.; Stynski, S.; Kolomyjski, W.; Kazmierkowski, M. P.; Control of Three-
Level PWM Converter Applied to Variable-Speed-Type Turbines ; IEEE Transactions on
Industrial Electronics, Volume 56, Issue 1, Jan. 2009 Page(s):69 - 77

___________________________________________________________________________
95
APPENDICES

A1. Total Harmonic Distortion (THD) factor
THD is most commonly used factor to characterize the magnitude of the distorted
signals. It gives the ratio between the geometric sum of the magnitudes or rms of the
harmonics and magnitude (or rms) of fundamental component.
1
2
2
X
X
THD
n
n
=
= (A.1)
A2. Simulation model in Saber Designer
The control algorithm DTC SVM with two modulation methods was implemented in
SABER, which provides analysis of the complete behavior of analog and mixed signals
system, including electrical subsystem. The main parameters are enclosed in table A.1. The
example model is shown in Fig. A.1.

Table A.1. Simulation parameters
Sampling frequency 5kHz
DC-link capacitors 2 x 500uF
DC-link Voltage 600V
Motor parameters:
Rotor resistance R
r
1,84
Stator resistance R
S
1,84
Rotor inductance L
r
0,17 H
Stator inductance L
S
0,17 H
Leakage inductance L
S
0,1 H
Mutual inductance L
M
0,16 H
Motor power P 3 kW
Pole pairs number p 2
Nominal stator current I
S
6,9 A
Nominal Stator Voltage U
S
3 x 400V
Nominal mechanical speed
N
1415 rpm

Appendices
___________________________________________________________________________
96

Fig. A.1. Saber model of DTC-SVM for NPC converter supplying IM.
Example of modulation algorithm written in MAST language is listed below.
#**************************#
#*/*Modulacja falownika */#
#**************************#
#/**** Calculation of modulation index [M_index2] ****/
M_index2= PI * U_motor/ udc
arg2=theta2
sektor2=1

if (PI <= arg2){
#/* 0 <= Theta2 > 180 */

sektor2=sektor2+3
arg2=arg2-PI
}
if (_2pi3<=arg2) {
#/* Theta2 > 120 */

sektor2=sektor2+2
arg2=arg2-_2pi3
}
if (_1pi3 <= arg2) {
#/* Theta2 > 60 */

sektor2=sektor2+1
arg2=arg2-_1pi3
}

cosinus2 = cos(arg2)
sinus2= sin(arg2)
if(M_index2>M_limit) M_index2=M_limit
Appendices
___________________________________________________________________________
97
if(M_index2<0.0) M_index2=0.0
##OVM_arg1, OVM_arg2 angles In OVM
if(M_index2>=1.814 & M_index2 < 1.904){
if(M_index2>=1.814 & M_index2<1.818 ){ #30 -24.5 st.
OVM_arg1=pi/6-((M_index2-1.814)*23.9983)
}
if(M_index2>=1.818 & M_index2<1.896 ){
OVM_arg1=0.4276-((M_index2-1.818)*4.25144305) #24.5-5.5 st.
}
if(M_index2>=1.896 & M_index2<1.904 ){ #5.5 -0 st.
OVM_arg1=0.096-((M_index2-1.896)*12.0)
}

if(arg2>OVM_arg1 & arg2<((pi/3)-OVM_arg1)){
m1_index2=2.0*((sqrt(3.0)*cosinus2-sinus2)/(sqrt(3.0)*cosinus2+sinus2))
m2_index2=2.0-m1_index2
}

if(arg2<=OVM_arg1 | arg2>=((pi/3)-OVM_arg1)){
m1_index2=M_index2*((cosinus2)-(sinus2/sqrt(3.0)))
m2_index2=(2*M_index2*sinus2/sqrt(3.0))
}
}
#OVM first level end
#second level OVM
if(M_index2>=1.904 & M_index2 <= 2.0){

if(M_index2>=1.904 & M_index2<1.958 ){ #0 -17.2 st.
OVM_arg1=((M_index2-1.904)*5.56)
}
if(M_index2>=1.958 & M_index2<1.994 ){
OVM_arg1=0.3+((M_index2-1.958)*1.11507222) #17.2-19.5 st.
}
if(M_index2>=1.994 & M_index2<=2.0 ){ #19.5 -30.0 st.
OVM_arg1= 0.34034+((M_index2-1.994)*30.543262)
}

if(arg2<=OVM_arg1){
cosinus2=1.0
sinus2=0.0
OVM_arg2=0.0
}
if((OVM_arg1<arg2) & (arg2<pi/3.0-OVM_arg1)){
OVM_arg2 = (pi/6.0)*(arg2-OVM_arg1)/(pi/6.0-OVM_arg1)
sinus2=sin(OVM_arg2)
cosinus2=cos(OVM_arg2)
}
if(arg2>=pi/3.0-OVM_arg1){
cosinus2=0.5
sinus2=sqrt(3.0)/2.0
}
m1_index2=2.0*((sqrt(3.0)*cosinus2-sinus2)/(sqrt(3.0)*cosinus2+sinus2))
m2_index2=2.0-m1_index2
}

#OVM end
if(M_index2<1.814){
m1_index2=M_index2*((cosinus2)-(sinus2/sqrt(3.0)))
m2_index2=(2*M_index2*sinus2/sqrt(3.0))
}
Appendices
___________________________________________________________________________
98
#region1 wektory t1,t2,t4
if(m1_index2>1.0){
T_1s=m1_index2-1.0
T_2s=m2_index2
T_3s=0.0
T_4s=2.0-m1_index2-m2_index2
T_5s=0.0
T_0s=0.0
}
if((m1_index2<=1.0) & (m2_index2<=1.0) &(m1_index2+m2_index2>1.0)){
T_1s=0.0
T_2s=m1_index2+m2_index2-1.0
T_3s=0.0
T_4s=1.0-m2_index2
T_5s=1.0-m1_index2
T_0s=0.0
}
if(m2_index2>1.0){
T_1s=0.0
T_2s=m1_index2
T_3s=m2_index2-1.0
T_4s=0.0
T_0s=0.0
}
if((m1_index2<=1.0) & (m2_index2<=1.0) &(m1_index2+m2_index2<=1.0)){
T_1s=0.0
T_2s=0.0
T_3s=0.0
T_4s=m1_index2
T_5s=m2_index2
}
if(((uc1>=uc2) & (moc2>0)) | ((uc1<uc2) & (moc2<0))){
k1=1.0
if(i1s*i2s*i3s>=0.0) kk_0=1.0
if(i1s*i2s*i3s<0.0) kk_0=0.0
kk_1=1.0
}

if(((uc1<uc2) & (moc2>0)) | ((uc1>=uc2) & (moc2<0))){

k1=0.0
kk_0=0.0
if(i1s*i2s*i3s>=0.0) kk_1=1.0
if(i1s*i2s*i3s<0.0) kk_1=0.0
}
}

if (sektor2==1){
D_R2_up = T_1s + T_2s + T_3s + k1*(T_4s + T_5s)+ kk_0*T_0s
D_R2 = T_1s + T_2s + T_3s+ T_4s + T_5s+ kk_1*T_0s
D_S2_up = T_3s + k1*T_5s+ kk_0*T_0s
D_S2 = T_2s + T_3s + k1*T_4s + T_5s+ kk_1*T_0s
D_T2_up = kk_0*T_0s
D_T2 = k1*(T_4s + T_5s)+ kk_1*T_0s
}
Appendices
___________________________________________________________________________
99
if (sektor2==2){
D_R2_up = T_1s + k1*T_4s+ kk_0*T_0s
D_R2 = T_1s + T_2s + T_4s + k1*T_5s+ kk_1*T_0s
D_S2_up = T_1s + T_2s + T_3s + k1*(T_4s + T_5s)+ kk_0*T_0s
D_S2 = T_1s + T_2s + T_3s + T_4s + T_5s+ kk_1*T_0s
D_T2_up = kk_0*T_0s
D_T2 = k1*(T_4s + T_5s)+ kk_1*T_0s
}
if (sektor2==3){
D_R2_up = kk_0*T_0s
D_R2 = k1*(T_4s + T_5s)+ kk_1*T_0s
D_S2_up = T_1s + T_2s + T_3s + k1*(T_4s + T_5s)+ kk_0*T_0s
D_S2 = T_1s + T_2s + T_3s + T_4s + T_5s+ kk_1*T_0s
D_T2_up = T_3s + k1*T_5s+ kk_0*T_0s
D_T2 = T_2s + T_3s + k1*T_4s + T_5s+ kk_1*T_0s
}
if (sektor2==4){
D_R2_up = kk_0*T_0s
D_R2 = k1*(T_4s + T_5s)+ kk_1*T_0s
D_S2_up = T_1s + k1*T_4s + kk_0*T_0s
D_S2 = T_1s + T_2s +T_4s+ k1*T_5s+ kk_1*T_0s
D_T2_up = T_1s + T_2s + T_3s + k1*(T_4s + T_5s)+ kk_0*T_0s
D_T2 = T_1s + T_2s + T_3s + T_4s + T_5s + kk_1*T_0s
}
if (sektor2==5){
D_R2_up = T_3s + k1*T_5s+ kk_0*T_0s
D_R2 = T_2s + T_3s + k1*T_4s + T_5s+ kk_1*T_0s
D_S2_up = kk_0*T_0s
D_S2 = k1*(T_4s + T_5s)+ kk_1*T_0s
D_T2_up = T_1s + T_2s + T_3s + k1*(T_4s + T_5s)+ kk_0*T_0s
D_T2 = T_1s + T_2s + T_3s + T_4s + T_5s+ kk_1*T_0s
}
if (sektor2==6){
D_R2_up = T_1s + T_2s + T_3s + k1*(T_4s + T_5s)+ kk_0*T_0s
D_R2 = T_1s + T_2s + T_3s + T_4s + T_5s+ kk_1*T_0s
D_S2_up = kk_0*T_0s
D_S2 = k1*(T_4s + T_5s)+ kk_1*T_0s
D_T2_up = T_1s + k1*T_4s + kk_0*T_0s
D_T2 = T_1s + T_2s + T_4s + k1*T_5s+ kk_1*T_0s
}
###############################################################################

A3. Equipment
Table A.2. List of Equipment
Instrument Type
Digital oscilloscope Tektronics TDS 3034B
Power Analyzer NORMA LEM D6000
Voltage differential probe Tektronics P5200
Current probe Tektronics TCP A300
Simulation software SABER 2003.6, Synopsys Inc.

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