ECE 301 Digital Electronics

Introduction to and Analysis of Sequential Logic Circuits

(Lecture #21)

The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Combinational vs. Sequential

Combinational Logic Circuit

Output is a function only of the present inputs. Does not have state information. Does not require memory.

Sequential Logic Circuit (aka. Finite State Machine)

Output is a function of the present state. Has state information Requires memory. Uses Flip-Flops to implement memory.
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Synchronous vs. Asynchronous

Synchronous Sequential Logic Circuit

Clocked All Flip-Flops use the same clock and change state on the same triggering edge.

Asynchronous Sequential Logic Circuit

No clock Can change state at any instance in time. Faster but more complex than synchronous sequential circuits.
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Sequential Circuits: General Model

Memory

Stores state information Realized using Flip-Flops

Combinational Logic

Implements Flip-Flop input functions and output functions Realized using logic gates, a ROM or a PLA
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Sequential Circuits: Models

Moore Machine

Outputs are a function of the present state. Outputs are independent of the inputs. State diagram includes an output value for each state.

Mealy Machine

Outputs are a function of the present state and the present input. State diagram includes an input and output value for each transition (between states).
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Sequential Circuits: Models

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Sequential Circuits: Mealy Model

output

Next state

Present state

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Sequential Circuits: Moore Model

Present state output

Next state
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Sequential Circuits: State Diagram

Input

State

Output

Moore Machine
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Each node in the graph represents a state in the sequential circuit.

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Sequential Circuits: State Diagram

Input Output State

Mealy Machine
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Each node in the graph represents a state in the sequential circuit.

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Sequential Circuit Analysis

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Analysis: Signal Tracing

1.Assume an initial state for the sequential circuit.

All Flip-Flops reset to 0 (unless otherwise stated).

2.Determine the sequential circuit output and the flipflop inputs for the first input value in the sequence. 3.Determine the next state of each Flip-Flop

After the next active clock edge.

4.Determine the sequential circuit output and the flipflop inputs for the next value in the sequence. 5.Repeat steps 3 & 4.
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Example: Moore Machine

Flip-Flop inputs

output

State = AB
input
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Example: Moore Machine

0 1 1 0 1

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Example: Mealy Machine

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Example: Mealy Machine

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Analysis: State Tables and Graphs

Although constructing timing charts is satisfactory for small circuits and short input sequences, the construction of state tables and graphs provides a more systematic approach which is useful for the analysis of larger circuits and which leads to a general synthesis procedure for sequential circuits. The state table specifies the next state and output of a sequential circuit in terms of its present state and input.

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Analysis Procedure
1. Determine the Flip-Flop input equations 2. Determine the Sequential Circuit output equations 3. Derive the Next State equation for each Flip-Flop

Using the corresponding input equation And the Flip-Flop characteristic equation

4. Plot the Next State K-map for each Flip-Flop 5. Construct the State Table (aka. Transition Table)

Assign a state label to each binary state assignment

6. Draw the corresponding state diagram (aka. state graph)

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Example: Analyze a sequential circuit using D Flip-Flops

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Example: Analysis (D FF)

Derive the State Table for the following Sequential Logic Circuit:

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Example: Analysis (D FF)

The flip-flop input equations are:
DA = X xor B' DB = X or A

The sequential circuit output equation is:

Z = A xor B

The next-state equations for the flip-flops are:

A+ = DA = X xor B' B+ = DB = X or A

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Example: Analysis (D FF)

The corresponding next-state (K-) maps are:

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Example: Analysis (D FF)

The state table, or transition table, is then:
A+ B+ X=0 X=1 10 01 00 11 01 11 11 01 Present State S0 S1 S2 S3 Next State X=0 X=1 S3 S1 S0 S2 S1 S2 S2 S1

AB 00 01 11 10

Z 0 1 0 1

Output 0 1 0 1

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Example: Analysis (D FF)

The state diagram can then be drawn from the state table:

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Example: Analyze a sequential circuit using JK Flip-Flops

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Example: Analysis (JK FF)

Derive the State Table for the following Sequential Logic Circuit:

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Example: Analysis (JK FF)

The flip-flop input equations are:
JA = X.B KA = X JB = X KB = X.A

The sequential circuit output equation is:

Z = X.B' + X.A + X'.A'.B

The next-state equations for the flip-flops are:

A+ = JA.A' + KA'.A A+ = X.B.A' + X.A
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B+ = JB.B' + KB'.B B+ = X.B' + X.A.B

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Example: Analysis (JK FF)

The corresponding next-state (K-) maps are

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Example: Analysis (JK FF)

The state table, and transition table, is then:

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Example: Analysis (JK FF)

The state diagram can then be drawn from the state table:

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Example: Analyze a serial adder

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Example: Serial Adder

The serial adder adds two n-bit binary numbers.
(serial) output (serial) inputs next state present state

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Example: Serial Adder

Truth Table for the Full Adder:

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Example: Serial Adder

The state table, or transition table, is then:
Ci+1 Ci 0 1 0 0 0 1 0 1 1 1 0 1 1 0 Sum XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = 11 1 0 0 1

Present State S0 S1 S0 S0

Next State S0 S1 S0 S1 S1 S1 0 1 1 0

Output 1 0 0 1

XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = 11

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Example: Serial Adder

State Graph for the Serial Adder:

What type of state machine is this?

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Example: Serial Adder

Timing Diagram for the Serial Adder:

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Example: Analyze a state machine with multiple inputs.

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Example: Multiple Inputs

State Table for a state machine with multiple inputs:

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Example: Multiple Inputs

State Graph for a state machine with multiple inputs:
What type of state machine is this?

How many paths leave each state?

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Questions?

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