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SP0256 Instruction Set

Speech parameter updates are generally f ollowed by a data block whose f ormat depends on the particular instruction issued. Most of these instructions only update a subset of the total speech parameter set, and of ten they update only the most signif icant bits of the registers they modif y. T he data blocks themselves are a variable number of bits, and are not constrained to byte boundaries. T he instruction stream itself is processed as a sequence of bits, not bytes, and so instructions and their data blocks can start on any bit boundary. Ordinarily, there are no gaps between instructions, and so the machine largely behaves as a bit-aligned machine. Control transf er instructions introduce alignment points, as all addresses in the system are byte addresses, and so all branch targets (including the return-branch target f or RTS) are on byte boundaries. It is customary to pad the data stream with 0s at alignment points (eg. af ter JSR instructions). T he instruction ref erence below shows the exact data f ormats that each instruction requires. Note that the data f ormat f or an instruction varies according to the current MODE setting, and so the machine provides a large variety of data f ormats. Other important things to note are: On instructions that accept a repeat count, a repeat count of zero causes the instruction to not execute , which means that no data block follows the instruction in that case. (My disassembler currently does not handle this case.) ( T his part may be in error. Conflicting documentation suggests there's more going on here than we worked out.) As a matter of convention in this document, bits are packed into bytes lef t-to-right, with the lef tmost bit going in the MSB of the f irst byte, and the LSB of the f irst byte being logically adjacent to the MSB of the second byte. T his is likely backwards f rom how the hardware looks at it, but it is the most natural f or a human interpreting the data, as it reads f rom lef t-to-right. Most bit f ields, except those which specif y branch targets, are bit reversed, meaning the lef t-most bit is the LSB. Bit f ields narrower than 8 bits are MSB justified unless specif ied otherwise, meaning that the least signif icant bits are the ones that are missing. T hese LSBs are f illed with zeros. When updating f ilter coef f icients with a delta-update, the microsequencer perf orms plain 2s-complement arithmetic on the 8-bit value in the coef f icient register f ile. No attention is paid to the f ormat of the register. Key for opcode formats below Field AAAAAAAA PPPPPPPP Description Amplitude bits. T he 3 rightmost bits are the exponent. T he exponent determines what power of 2 is applied to the lower 5 bits. Pitch period. When set to 0, the impulse switches to random noise. For timing purposes, noise

and silence have an ef f ective period equivalent to period==64. BBBBBBBS FFFFFFFS RRRR B coef f icient data. T he 'S' is the sign bit, if present. If there is no 'S' on a given f ield, the sign is assumed to be 0. F coef f icient data. Repeat bits. On Opcode 1000 (SETMODE), the repeat bits go to the two MSBs of the repeat count f or the next instruction. On all other instructions, the repeat bits go to the f our LSBs of the repeat count f or the current instruction. Mode bits. T hese are set by Opcode 1000 (SETMODE), and they control the data f ormat f or a number of other instructions. Byte address f or a branch target. Branch targets are 16 bits long. T he JMP/JSR instruction provides the lower 12 bits, and the PAGE register provides the upper 4 bits. T he PAGE register is modif ied via the SETPAGE instruction, Opcode 0000. Amplitude delta. (unsigned) Pitch delta. (unsigned) Amplitude delta. (2s complement) Pitch delta. (2s complement) Filter coef f icient deltas. (2s complement)

MM LLLLLLLL

aaaaa ppppp aaas ppps bbbs fffs

For ref erence, each 2nd order f ilter section looks like so. Note that "1/Z " represents a single unit delay. Altogether, there are 6 such stages, yielding a 12 pole f ilter. T he exact ordering of the stages with respect to the coef f icient data f ormats appears to be straightf orward, with the lowest-numbered coef f icient pair used in the earliest f ilter stage, etc.

Instruction Set Quick Ref erence

Opcode 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 Mnemonic RTS/SETPAGE LOADALL LOAD_2 SETMSB_3 Description Return OR set the PAGE register Load All Parameters Load Pitch, Amplitude, Coef f icient, and Interpolation Regsisters Load Pitch, Amplitude, MSBs of 3 Coef f icients, and Interpolation Registers

0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

LOAD_4 SETMSB_5 SETMSB_6 JMP SETMODE DELTA_9 SETMSB_A JSR LOAD_C DELTA_D LOAD_E PAUSE

Load Pitch, Amplitude, Coef f icients (2 or 3 stages) Load Pitch, Amplitude, and MSBs of 3 Coef f icients Load Amplitude and MSBs of 2 or 3 Coef f icients Jump to 12-bit PAGE-relative Address Set the Mode bits and Repeat MSBs Delta update Amplitude, Pitch and 5 or 6 Coef f icients Load Amplitude and MSBs of 3 Coef f icients Jump to Subroutine (12-bit PAGE-Relative Address) Load Pitch, Amplitude, Coef f icients (5 or 6 stages) Delta update Amplitude, Pitch and 2 or 3 Coef f icients Load Pitch, Amplitude Silent pause

Individual Instruction Descriptions

[Ref ] [Top] OPCODE 0000 Format

RTS / SETPAGE LLLL 0000

Return or set the PAGE register

It slices, it dices, it juliennes! It's a f loor wax! It's a dessert topping! It's two instructions in one! SETPAGE When LLLL is non-zero, this instruction sets the PAGE register to the value in LLLL. T he PAGE register determines which 4K page (eg. the upper f our bits of the address f or) the next JMP or JSR will jump to. (Note that address loads via ALD appear to ignore PAGE, and set the f our MSBs to $1000. T hey do not modif y the PAGE register, so subsequent JMP/JSR instructions will jump relative to the current value in PAGE.) T he PAGE register retains its setting until the next SETPAGE is encountered. Valid values f or PAGE are in the range $1..$F. T he RESROM starts at address $1000, and no code exists below that address. T heref ore, the microsequencer can address speech data over the address range $1000 through $FFFF, f or a total of 60K of speech data. (Up to 64K may be possible by jumping to a location near $FFFF and letting the address wrap around. At this time, the exact behavior of an address wraparound is unknown, and may be dependent on the behavior of both the microsequencer and the attached speech ROMs.) RTS When LLLL is zero, this opcode causes the microsequencer to pop the PC stack into the PC, and resume execution there. T he contents of the stack are replaced with $0000 (or some other f lag which represents an empty stack). If the address that was popped was itself $0000 (eg. an empty stack), execution halts, pending a new address write via ALD.

Action

(Of course, if an address was previously written via ALD and is pending, control transf ers to that address immediately.)

[Ref ] [Top] OPCODE 0001 Format

LOADALL

Load All Parameters

RRRR 0001 [data] AAAAAAAA PPPPPPPP BBBBBBBS FFFFFFFS (coe BBBBBBBS FFFFFFFS (coe BBBBBBBS FFFFFFFS (coe BBBBBBBS FFFFFFFS (coe BBBBBBBS FFFFFFFS (coe BBBBBBBS FFFFFFFS (coe

MODE x0

pair 0) pair 1) pair 2) pair 3) pair 4) pair 5)

Data Formats, by MODE Action

MODE x1

AAAAAAAA PPPPPPPP BBBBBBBS FFFFFFFS (coe pair 0) BBBBBBBS FFFFFFFS (coe pair 1) BBBBBBBS FFFFFFFS (coe pair 2) BBBBBBBS FFFFFFFS (coe pair 3) BBBBBBBS FFFFFFFS (coe pair 4) BBBBBBBS FFFFFFFS (coe pair 5) aaaaaaas ppppppps (pit ch and amplit ude int erpolat ion)

Loads amplitude, pitch, and all coef f icient pairs at f ull 8-bit precision. T he pitch and amplitude deltas that are available in Mode 01 and 11 are applied every pitch period, not just once. Wraparound may occur. If the Pitch goes to zero, the periodic excitation switches to noise.

Notes

[Ref ] [Top] OPCODE 0010 Format

LOAD_2

Load Pitch, Amplitude, Coefficients, and Interpolation registers.

RRRR 0010 [data]

MODE 00

AAAAAA PPPPPPPP BBB FFFFS (coe pair 0) BBB FFFFS (coe pair 1) BBB FFFFS (coe pair 2) BBBB FFFFFS (coe pair 3) BBBBBBS FFFFFS (coe pair 4) aaaaa ppppp (Int erpolat ion regist er LSBs)

MODE 01

AAAAAA PPPPPPPP BBB FFFFS (coe pair 0) BBB FFFFS (coe pair 1) BBB FFFFS (coe pair 2) BBBB FFFFFS (coe pair 3) BBBBBBS FFFFFS (coe pair 4) BBBBBBBS FFFFFFFS (coe pair 5) aaaaa ppppp (Int erpolat ion regist er LSBs)

MODE 10

AAAAAA PPPPPPPP BBBBBB FFFFFS (coe pair 0) BBBBBB FFFFFS (coe pair 1) BBBBBB FFFFFS (coe pair 2) BBBBBB FFFFFFS (coe pair 3) BBBBBBBS FFFFFFFS (coe pair 4) aaaaa ppppp (Int erpolat ion regist er LSBs)

Data Formats, by MODE

MODE 11

AAAAAA PPPPPPPP BBBBBB FFFFFS (coe pair 0) BBBBBB FFFFFS (coe pair 1) BBBBBB FFFFFS (coe pair 2) BBBBBB FFFFFFS (coe pair 3) BBBBBBBS FFFFFFFS (coe pair 4) BBBBBBBS FFFFFFFS (coe pair 5) aaaaa ppppp (Int erpolat ion regist er LSBs)

Action

Loads new amplitude and pitch parameters. Also loads a set of new f ilter coef f icients, setting the unspecif ied coef f icients to zero. T he exact combination and precision of f ilter coef f icients that are loaded is determined by which pref ix is used. Opcode 1000 (SETMODE) provides the pref ix bits. For all Modes, the Sign bit f or B0, B1, B2 and B3 (the B coef f s f or pair 0 thru pair 3) has an implied value of 0. T his opcode is identical to Opcode 1100 (LOAD_C), except that it also loads new values into the Amplitude and Pitch Interpolation Registers.

Notes

[Ref ] [Top] OPCODE

0011 Format

SETMSB_3

Load Pitch, Amplitude, MSBs of 3 Coefficients, and Interpolation Registers.

RRRR 0011 [data] AAAAAA FFFFS (New F0 MSBs) FFFFS (New F1 MSBs) FFFFS (New F2 MSBs) aaaaa ppppp (Int erpolat ion regist er LSBs)

MODE 0x

Data Formats, by MODE

MODE 1x

AAAAAA FFFFFS (New F0 MSBs) FFFFFS (New F1 MSBs) FFFFFS (New F2 MSBs) aaaaa ppppp (Int erpolat ion regist er LSBs)

Action

Loads new amplitude. Also updates the MSBs of a set of new f ilter coef f icients. T he Mode pref ix bits controls the update process as noted below. Opcode 1000 (SETMODE) provides the pref ix bits. When MODE is 00 or 10, the parameter load sets the 5 or 6 MSBs of F0, F1, and F2 f rom the data provided. F5 and B5 are set to all 0s. All other coef f icient bits are unaf f ected. When MODE is 01 or 11, the parameter load sets the 5 or 6 MSBs of F0, F1, and F2 f rom the data provided. F5 and B5 are not modif ied. All other coef f icient bits are unaf f ected. T his opcode is identical to Opcodes 0101 (SETMSB_5) and 1010 (SETMSB_A), except that is also includes the Interpolation Registers, and like Opcode 1010 (SETMSB_A), it does not set the Pitch Registers.

Notes

[Ref ] [Top] OPCODE 0100 Format

LOAD_4

Load Pitch, Amplitude, Coefficients (2 or 3 stages)

RRRR 0100 [data] AAAAAA PPPPPPPP BBBB FFFFFS (coe pair 3) BBBBBBS FFFFFS (coe pair 4)

MODE 00

MODE 01

AAAAAA PPPPPPPP BBBB FFFFFS (coe pair 3) BBBBBBS FFFFFS (coe pair 4) BBBBBBBS FFFFFFFS (coe pair 5)

MODE 10

AAAAAA PPPPPPPP BBBBBB FFFFFFS (coe pair 3) BBBBBBBS FFFFFFFS (coe pair 4)

Data Formats, by MODE

MODE 11

AAAAAA PPPPPPPP BBBBBB FFFFFFS (coe pair 3) BBBBBBBS FFFFFFFS (coe pair 4) BBBBBBBS FFFFFFFS (coe pair 5)

Action

Loads new amplitude and pitch parameters. Also loads a set of new f ilter coef f icients, setting the unspecif ied coef f icients to 0. T he exact combination and precision of f ilter coef f icients that are loaded is determined by which pref ix is used. Opcode 1000 (SETMODE) provides the pref ix bits. For all modes, the Sign bit f or B0 (the B coef f icient f or pair 0) has an implied value of 0.

Notes

[Ref ] [Top] OPCODE 0101 Format

SETMSB_5

Load Pitch, Amplitude, and MSBs of 3 Coefficients

RRRR 0101 [data] AAAAAA PPPPPPPP FFFFS (New F0 MSBs) FFFFS (New F1 MSBs) FFFFS (New F2 MSBs)

MODE 0x

Data Formats, by MODE

MODE 1x

AAAAAA PPPPPPPP FFFFFS (New F0 MSBs) FFFFFS (New F1 MSBs) FFFFFS (New F2 MSBs)

Action

Loads new amplitude and pitch parameters. Also updates the MSBs of a set of new f ilter coef f icients. T he Mode pref ix bits controls the update process as noted below. Opcode 1000 (SETMODE) provides the pref ix bits. When MODE is 00 or 10, the parameter load sets the 5 or 6 MSBs of F0, F1, and F2 f rom the data provided. F5 and B5 are set to all 0s. All other coef f icient bits are unaf f ected. When MODE is 01 or 11, the parameter load sets the 5 or 6 MSBs of F0, F1, and F2 f rom the data provided. F5 and B5 are not modif ied. All other coef f icient bits are unaf f ected. T his opcode is identical to Opcodes 0011 (SETMSB_3) and 1010 (SETMSB_A), only Pitch is modif ied, and unlike Opcode 0011, the interpolation registers are not set.

Notes

modif ied, and unlike Opcode 0011, the interpolation registers are not set.

[Ref ] [Top] OPCODE 0110 Format

SETMSB_6 RRRR 0110 [data]

Load Amplitude and MSBs of 2 or 3 Coeffcients

MODE 00

AAAAAA FFFFFS FFFFFS

(New F3 6 MSBs) (New F4 6 MSBs)

MODE 01

AAAAAA FFFFFS FFFFFS FFFFFFFS

(New F3 6 MSBs) (New F4 6 MSBs) (New F5 8 MSBs)

MODE 10

AAAAAA FFFFFFS FFFFFFFS

(New F3 7 MSBs) (New F4 8 MSBs)

Data Formats, by MODE

MODE 11

AAAAAA FFFFFFS FFFFFFFS FFFFFFFS

(New F3 7 MSBs) (New F4 8 MSBs) (New F5 8 MSBs)

Action

Loads new amplitude and pitch parameters. Also updates the MSBs of a set of new f ilter coef f icients. T he MODE pref ix bits controls the update process as noted below. Opcode 1000 (SETMODE) provides the pref ix bits. For MODE 00 and 10, coef f icients B5 and F5 are set to zero. For MODE 01 and 11, coef f icient F5 is set f rom the last 8 bits of the data provided, and B5 is not modif ied. For MODE 00 and 01, the 6 MSBs of F3 and F4 are set f rom the f irst 12 bits provided. T he other bits of F3 and F4 are not modif ied. For MODE 10 and 11, the 7 MSBs of F3 and the 8 MSBs of F4 are set f rom the f irst 12 bits provided. T he LSB of F3 is not modif ied.

Notes

[Ref ] [Top]

OPCODE 0111 Format

JMP

Jump to 12-bit PAGE-Relative Address

LLLL 0111 LLLLLLLL Perf orms a jump to the specif ied 12-bit address relative to the 4K page number specif ied by the PAGE register. T hat is, the JMP instruction jumps to the location PAGE LLLL LLLLLLLL, where the upper f our bits come f rom the PAGE register and the lower 12 bits come f rom the JMP instruction.

Action

At power-up, the PAGE register def aults to the value 0001 ($1). T he PAGE register may be set using the SETPAGE instruction, Opcode 0000.

[Ref ] [Top] OPCODE 1000 Format

SETMODE RRMM 1000

Set the MODE bits and Repeat MSBs

Serves as a pref ix to many other instructions. T he upper two bits of the immediate constant are loaded into the upper two bits of the 6-bit repeat register. T hese two bits combine with the f our LSBs that are provided by most parameter-load instructions to provide longer repetition periods. T he two MM bits select the data f ormat / coef f icient count f or many of the parameter load instructions. Action T his opcode is known to have no ef f ect on JMP/JSR instructions and JMP/JSR instructions have no ef f ect on it. T he MM mode bits are sticky, meaning that they stay in ef f ect until the next Opcode 1000 (SETMODE) instruction. T he RR repeat bits are not, however.

Notes

[Ref ] [Top] OPCODE 1001 Format

DELTA_9

Delta update Amplitude, Pitch and 5 or 6 Coefficients

RRRR 1001 [data] aaas bbs bbs bbs bbs bbbs pppps s s s fs fs (Amplit ude 6 MSBs, Pit ch LSBs.) (B0 4 MSBs, F0 5 MSBs.) (B1 4 MSBs, F1 5 MSBs.) (B2 4 MSBs, F2 5 MSBs.) (B3 5 MSBs, F3 6 MSBs.) (B4 6 MSBs, F4 6 MSBs.)

MODE 00

MODE 01

aaas bbs bbs bbs bbs bbbs bbbbs

pppps s s s fs fs s

(Amplit ude 6 MSBs, Pit ch LSBs.) (B0 4 MSBs, F0 5 MSBs.) (B1 4 MSBs, F1 5 MSBs.) (B2 4 MSBs, F2 5 MSBs.) (B3 5 MSBs, F3 6 MSBs.) (B4 6 MSBs, F4 6 MSBs.) (B5 8 MSBs, F5 8 MSBs.)

MODE 10

aaas bbbs bbbs bbbs bbbs bbbbs

pppps fs fs fs s s

(Amplit ude 6 MSBs, Pit ch LSBs.) (B0 7 MSBs, F0 6 MSBs.) (B1 7 MSBs, F1 6 MSBs.) (B2 7 MSBs, F2 6 MSBs.) (B3 7 MSBs, F3 7 MSBs.) (B4 8 MSBs, F4 8 MSBs.)

Data Formats, by MODE

MODE 11

aaas bbbs bbbs bbbs bbbs bbbbs bbbbs

pppps fs fs fs s s s

(Amplit ude 6 MSBs, Pit ch LSBs.) (B0 7 MSBs, F0 6 MSBs.) (B1 7 MSBs, F1 6 MSBs.) (B2 7 MSBs, F2 6 MSBs.) (B3 7 MSBs, F3 7 MSBs.) (B4 8 MSBs, F4 8 MSBs.) (B5 8 MSBs, F5 8 MSBs.)

Action

Perf orms a delta update, adding small 2s complement numbers to a series of coef f icients. T he 2s complement updates f or the various f ilter coef f icients only update some of the MSBs -- the LSBs are unaf f ected. T he exact bits which are updated are noted above. T he delta update is applied exactly once, as long as the repeat count is at least 1. If the repeat count is greater than 1, the updated value is held through the repeat period, but the delta update is not reapplied. T he delta updates are applied to the 8-bit encoded f orms of the coef f icients, not the 10bit decoded f orms. Normal 2s complement arithmetic is perf ormed, and no protection is provided against overf low. Adding 1 to the largest value f or a bit f ield wraps around to the smallest value f or that bitf ield. T he update to the amplitude register is a normal 2s complement update to the entire register. T his means that any carry/borrow f rom the mantissa will change the value of the exponent. T he update doesn't know anything about the f ormat of that register.

Notes

[Ref ] [Top] OPCODE 1010 Format

SETMSB_A

Load Amplitude and MSBs of 3 Coefficients

RRRR 1010 [data]

MODE 0x

AAAAAA FFFFS FFFFS FFFFS

(New F0 MSBs) (New F1 MSBs) (New F2 MSBs)

MODE 1x

AAAAAA FFFFFS FFFFFS FFFFFS

(New F0 MSBs) (New F1 MSBs) (New F2 MSBs)

Action

Loads new amplitude. Also updates the MSBs of a set of new f ilter coef f icients. T he MODE pref ix bits controls the update process as noted below. Opcode 1000 (SETMODE) provides the pref ix bits. When MODE is 00 or 10, the parameter load sets the 5 or 6 MSBs of F0, F1, and F2 f rom the data provided. F5 and B5 are set to all 0s. All other coef f icient bits are unaf f ected. When MODE is 01 or 11, the parameter load sets the 5 or 6 MSBs of F0, F1, and F2 f rom the data provided. F5 and B5 are not modif ied. All other coef f icient bits are unaf f ected.

Data Formats, by MODE

Notes

T his opcode is identical to Opcodes 0011 (SETMSB_3) and 0101 (SETMSB_5), except that Pitch is not modif ied, and the Interpolation Registers are not set.

[Ref ] [Top] OPCODE 1011 Format

JSR

Jump to Subroutine (12-bit PAGE-Relative Address)

LLLL 1011 LLLLLLLL Perf orms a jump to the specif ied 12-bit address relative to the 4K page number specif ied by the PAGE register. T hat is, the JMP instruction jumps to the location PAGE LLLL LLLLLLLL, where the upper f our bits come f rom the PAGE register and the lower 12 bits come f rom the JSR instruction. At power-up, the PAGE register def aults to the value 0001 ($1). T he PAGE register may be set using the SETPAGE instruction, Opcode 0000. T his variant pushes the byte-aligned return address onto the PC stack. T he previous contents of the PC stack are lost, as the PC stack is only one entry deep. To return to the next instruction, use Opcode 0000 (RTS).

Action

[Ref ] [Top] OPCODE

1100 Format

LOAD_C

Load Pitch, Amplitude, Coefficients (5 or 6 stages)

RRRR 1100 [data] AAAAAA PPPPPPPP BBB FFFFS (coe pair 0) BBB FFFFS (coe pair 1) BBB FFFFS (coe pair 2) BBBB FFFFFS (coe pair 3) BBBBBBS FFFFFS (coe pair 4)

MODE 00

MODE 01

AAAAAA PPPPPPPP BBB FFFFS (coe pair 0) BBB FFFFS (coe pair 1) BBB FFFFS (coe pair 2) BBBB FFFFFS (coe pair 3) BBBBBBS FFFFFS (coe pair 4) BBBBBBBS FFFFFFFS (coe pair 5)

MODE 10

AAAAAA PPPPPPPP BBBBBB FFFFFS (coe pair 0) BBBBBB FFFFFS (coe pair 1) BBBBBB FFFFFS (coe pair 2) BBBBBB FFFFFFS (coe pair 3) BBBBBBBS FFFFFFFS (coe pair 4)

Data Formats, by MODE

MODE 11

AAAAAA PPPPPPPP BBBBBB FFFFFS (coe pair 0) BBBBBB FFFFFS (coe pair 1) BBBBBB FFFFFS (coe pair 2) BBBBBB FFFFFFS (coe pair 3) BBBBBBBS FFFFFFFS (coe pair 4) BBBBBBBS FFFFFFFS (coe pair 5)

Action

Loads new amplitude and pitch parameters. Also loads a set of new f ilter coef f icients, setting the unspecif ied coef f icients to zero. T he exact combination and precision of f ilter coef f icients that are loaded is determined by which pref ix is used. Opcode 1000 (SETMODE) provides the pref ix bits. For all values of MODE, the Sign bit f or B0, B1, B2 and B3 (the B coef f icients f or pair 0 thru pair 3) has an implied value of 0.

Notes

[Ref ] [Top] OPCODE 1101

DELTA_D

Delta update Amplitude, Pitch and 2 or 3 Coefficients

Format

RRRR 1101 [data] aaas bbs bbbs pppps (Amplit ude 6 MSBs, Pit ch LSBs.) fs (B3 5 MSBs, F3 6 MSBs.) fs (B4 7 MSBs, F4 6 MSBs.)

MODE 00

MODE 01

aaas pppps (Amplit ude 6 MSBs, Pit ch LSBs.) bbs fs (B3 5 MSBs, F3 6 MSBs.) bbbs fs (B4 7 MSBs, F4 6 MSBs.) bbbbs s (B5 8 MSBs, F5 8 MSBs.)

MODE 10

aaas pppps (Amplit ude 6 MSBs, Pit ch LSBs.) bbbs s (B3 7 MSBs, F3 7 MSBs.) bbbbs s (B4 8 MSBs, F4 8 MSBs.)

Data Formats, by MODE

MODE 11

aaas pppps (Amplit ude 6 MSBs, Pit ch LSBs.) bbbs s (B3 7 MSBs, F3 7 MSBs.) bbbbs s (B4 8 MSBs, F4 8 MSBs.) bbbbs s (B5 8 MSBs, F5 8 MSBs.)

Action

Perf orms a delta update, adding small 2s complement numbers to a series of coef f icients. T he 2s complement updates f or the various f ilter coef f icients only update some of the MSBs -- the LSBs are unaf f ected. T he exact bits which are updated are noted above. T he delta update is applied exactly once, as long as the repeat count is at least 1. If the repeat count is greater than 1, the updated value is held through the repeat period, but the delta update is not reapplied. T he delta updates are applied to the 8-bit encoded f orms of the coef f icients, not the 10bit decoded f orms. Normal 2s complement arithmetic is perf ormed, and no protection is provided against overf low. Adding 1 to the largest value f or a bit f ield wraps around to the smallest value f or that bitf ield. T he update to the amplitude register is a normal 2s complement update to the entire register. T his means that any carry/borrow f rom the mantissa will change the value of the exponent. T he update doesn't know anything about the f ormat of that register.

Notes

[Ref ] [Top] OPCODE 1110 Format

LOAD_E

Load Pitch, Amplitude

RRRR 1110 AAAAAA PPPPPPPP Loads new amplitude and pitch parameters. Data f ormat does not seem to be af f ected by the Opcode 1000 (SETMODE) pref ix, although the repeat count may be extended using the Opcode

Action

1000 (SETMODE) pref ix.

[Ref ] [Top] OPCODE 1111 Format RRRR 1111 Provides a silent pause of varying length. T he length of the pause is given by the 4-bit immediate constant RRRR. T he pause duration can be extended with the Opcode 1000 (SETMODE) pref ix. T he pause behaves identially to a pitch with Amplitude == 0 and Period == 64. All coef f icients are cleared, as well.

PAUSE

Silent Pause

Action

Notes

$Id: sp0256_instr_set.html,v 1.1 2000/09/28 00:05:49 im14u2c Exp $