1080

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

Operation of a Medium-Voltage Drive Under Faulty Conditions

Jos Rodrguez, Senior Member, IEEE, Peter W. Hammond, Member, IEEE, Jorge Pontt, Senior Member, IEEE, Rodrigo Musalem, Pablo Lezana, and Mara Jos Escobar

AbstractThis paper presents a method for operating cascaded multilevel inverters when one or more power cells are damaged. The method is based on the use of additional switches in the power circuit to bypass the faulty cell. To control the cells, the angle of phase shifting in the carrier signals is modied according to the number of operating cells, to minimize the load voltage distortion, when the inverter operates in failure mode. The reference signals of the pulsewidth-modulation modulators are also modied to increase the output voltage. Simulation and experimental results show the effectiveness of this method, which signicantly increases the reliability of the drive. Index TermsFault tolerance, multilevel inverters, power electronics.

I. INTRODUCTION

EDIUM-VOLTAGE inverters are, in general, high-power equipment and when they fail they create great losses in production. For this reason, reliability is a very important issue in this family of converters. In addition, medium-voltage inverters use a high number of power semiconductors, and for this reason it may be considered that they are less reliable [1]. However, a different approach is to consider that medium-voltage inverters offer more possibilities in the power circuit to allow for operation even during faulty conditions. This approach has recently been considered for the ying-capacitor topology [2][4]. The design of a sensor to improve the short-circuit tolerance of this topology is reported in [4]. This work is dedicated to a different family of mediumvoltage inverters, the so-called cascaded multicell topology, which uses several cells in series connection to generate higher voltages [5], [6]. Each cell is supplied by an isolated three-phase secondary of the input transformer. This paper proposes a method to increase the reliability of cascaded multicell inverters, permitting the operation even with
Manuscript received February 5, 2004; revised June 1, 2004. Abstract published on the Internet April 28, 2005. This work was supported by the Chilean Research Fund (CONICYT) under Grant 1030368 and by the Universidad Tcnica Federico Santa Mara. J. Rodrguez, J. Pontt, R. Musalem, and P. Lezana are with the Electronics Engineering Department, Universidad Tcnica Federico Santa Mara, 110-V Valparaso, Chile (e-mail: jrp@elo.utfsm.cl; jpo@elo.utfsm.cl; musa@elo.utfsm.cl). P. W. Hammond is with ASIRobicon Corporation, New Kensington, PA 15068 USA (e-mail: pete.hammond@us.asirobicon.com). M. J. Escobar was with the Electronics Engineering Department, Universidad Tcnica Federico Santa Mara, 110-V Valparaso, Chile. She is now with Sixbell Chile, Santiago, Chile (e-mail: mescobar@sixbell.cl). Digital Object Identier 10.1109/TIE.2005.851645

Fig. 1. Topology of an inverter with 15 cells.

some faulty cells. This is achieved by adding small contactors in the power circuit and modifying the modulation strategy, to maintain the generation of balanced voltages. II. MEDIUM-VOLTAGE INVERTER A. Power Circuit Fig. 1 represents the power circuit of an 11-level mediumvoltage inverter, which has ve cells in series connection in each phase. This inverter has 15 modules (cells). Each cell is fed by isolated three-phase voltages to generate a noncontrolled dc link, as shown in Fig. 2. The output part of the cell has a single-phase inverter which delivers three values: V , 0, and V , generating a voltage in the range of 0480 Vac. Five cells in series connection are used to generate a phase voltage of 2400 Vac, which corresponds to a line voltage of 4160 Vac. Table I shows the solutions adopted for voltages 2.34.16 kV.

B. Modulation of the Inverter The modulation of each cell is done using unipolar pulsewidth modulation (PWM) generated by using a triangular carrier signal with a frequency of 600 Hz, as shown in Fig. 3.

0278-0046/$20.00 2005 IEEE

RODRGUEZ et al.: OPERATION OF A MEDIUM-VOLTAGE DRIVE UNDER FAULTY CONDITIONS

1081

Fig. 2.

Power circuit of each cell. TABLE I CASCADED INVERTERS USED IN MEDIUM-VOLTAGE DRIVES

Fig. 4.

The drive of Fig. 1 with three faulty cells bypassed.

Fig. 3. Voltages of a cell. Upper: reference voltages and triangular carrier; lower: output voltage of a cell.

The carrier signals of the different cells in each phase are shifted in order to reduce the distortion in the load voltage [5], [6]. Another advantageous consequence of this phase-shifting technique is that the effective switching frequency of the load times the switching frequency of each cell ( voltage is is the number of cells in series connection in each phase). This property allows for a reduction in the switching frequency of each cell, thus reducing the losses. III. OPERATION UNDER ABNORMAL CONDITIONS A. Some Reliability Considerations The main idea to improve reliability is to bypass the damaged cell by using the bypass contactor shown in Fig. 2, to allow for operation of the inverter with reduced capacity. This solution protects against the failure of all components in the power cir-

Fig. 5.

The drive of Fig. 4 re-balanced by bypassing functional cells.

cuit of each cell, rather than just the damage of some power semiconductors. In the following analysis it is supposed that a cascaded inverter has modules (cells) and cannot tolerate any failure. If the probability that a power cell will function properly during cells will a time interval is , then the probability that all . Consefunction properly during the same time interval is quently, the inverter reliability will be . If the same modular drive can tolerate one failure, the drive . It is clear that reliability will be this drive has a higher reliability than one with no tolerance

1082

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

Fig. 7.

The drive of Fig. 1 with faulted cells and balanced operation.

Fig. 6. General diagram for angles calculation.

for failures. Similar equations can be applied to drives that can tolerate a larger number of faults. For example, if no faults can be tolerated in a 15-module drive and each cell has a 99% reliability during an arbitrary time interval, then the reliability of the drive is 86%. However, if one failure can be tolerated the drive reliability increases to 99.03%, and if two failures can be tolerated the drive reliability increases to 99.9%. B. Simple Solution When cells are bypassed in one of the drive phases, the output voltage will tend to become unbalanced. Fig. 4 shows the voltages delivered by the inverter when one faulty cell in phase and two faulty cells in phase have been bypassed. Due to the modulation scheme, the phase voltages have a phase displacement of 120 with different amplitudes. The simplest solution to avoid the generation of unbalanced load voltages is to additionally bypass three cells in the other two phases, generating the balanced voltages shown in Fig. 5. The price that must be paid for this solution is that the voltage is reduced to 60%, and three operating cells are not used. To reduce the voltage distortion, the phase shifting between the carriers of the cells in each phase must be changed from to . C. Maximizing the Load Voltage 1) Principle: The proposed method takes advantage of the fact that the star-point of the modules is oating, and is not connected to the neutral of the motor. The star-point can be shifted away from the motor neutral, and the phase angles of the module voltages can be adjusted, so that a balanced set of motor voltages is obtained even though the inverter phase voltages are not balanced.

Fig. 8. Simulation results for balanced operation with no faulty cells. Upper: reference voltages; middle: line voltages delivered by inverter; lower: line currents delivered by inverter.

2) Calculation of the References: Fig. 6 shows the general voltage diagram when all inverter phases have a different amount of operating cells. The problem to be solved is to nd the corresponding angles , , and necessary to generate balanced line voltages at the load when the phase voltages of the inverter have different am, plitudes. In this gure, the phase voltages , with . Voltage is located are represented by the vectors in the real axis of the complex plane and, for this reason, its . imaginary part is The equivalence of line voltages magnitude is given by (1) (2)

RODRGUEZ et al.: OPERATION OF A MEDIUM-VOLTAGE DRIVE UNDER FAULTY CONDITIONS

1083

Fig. 9. Simulation results for unbalanced operation with ve faulty cells. Upper: reference voltages; middle: line voltages delivered by inverter; lower: line currents delivered by inverter.

Fig. 11. Simulation results for balanced operation with ve faulty cells. Upper: reference voltages; middle: line voltages delivered by inverter; lower: line currents delivered by inverter.

Fig. 12. Experimental result from a 4.16-kV inverter. Upper: reference voltages.; lower: load currents by inverter. Fig. 10. The simplest solution. Simulation results for balanced operation with one cell in each phase. Upper: reference voltages; middle: line voltages delivered by inverter; lower: line currents delivered by inverter.

These equations can be expressed in terms of the real and imaginary parts of the voltages, as follows: (3) (4) In addition, the following equations are valid: (5) (6) It is important to point out that the effective values (module) , , and are known, since of the phase voltages

these values are obtained directly from the number of cells in operation. The four nonlinear equations (3)(6) have the four unknown , , , and . These equations are solved by variables using the command solve in the software MAPLE. Finally, the angles are obtained from (7) (8) (9) Fig. 7 shows the situation of a 15-module drive (ve cells per phase) under similar conditions of Fig. 4: all ve cells remain in

1084

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

Fig. 13.

Input current spectrum for different number of bypassed cells.

phase , one cell bypassed in phase , and two cells bypassed in phase . In the case of Fig. 7, the angles between the phase voltages , , and , of the inverter are generating balanced line voltages. This solution uses all operating cells and generates a load voltage 30% higher than the simplest solution shown in Fig. 5. The phase displacement of the reference voltages, depending on the number of faulted cells, is calculated previously, in order to reduce processing time during the operation of the inverter. IV. RESULTS Fig. 8 represents the operation of the 15 cells inverter under normal conditions, i.e., with no faulty cells. Fig. 9 shows the operation of the inverter with four cells bypassed in phase , and one cell bypassed in phase . In this result, the reference voltages and the carrier signals maintain the same values and phase displacements of the normal operation. This condition generates unbalanced voltages and currents in the load, which is observed in the middle and lower part of Fig. 9. This condition is not acceptable for the machine. As mentioned above, the simplest solution to avoid the generation of unbalanced load voltages is to bypass four cells in phase and three additional cells in phase , in order to obtain the same number of cells in each phase, generating the balanced voltages shown in Fig. 10. However, the obtained balanced voltages and currents are signicantly reduced with respect to the number of the total operating cells, because with this solution there is only one cell working in each phase. In addition, the load currents are reduced to 20% of the values obtained with all operating cells.

Fig. 11 represents the operation of the inverter with the same ve faulty cells of Fig. 9. In this case, the neutral is shifted to generate balanced voltages at the output, which is achieved with and (see Fig. 6) for the reference voltages. In addition, the voltages and currents in the load have higher values than those obtained in Fig. 10. In this result, the angles of the carriers were modied to minimize the distortion. More precisely, the phase shifting between the carriers of the cells in phase is now of 45 (instead of 36 ) and in phase the displacement of 36 is maintained. In this case, the reduction of the load currents is 55% of the original values (see Fig. 8), but this situation is much better than in the case of Fig. 10. Fig. 12 shows experimental results obtained from a 4.16-kV 15-module inverter operating with one cell bypassed in phase , and four cells bypassed in phase . The top signals are the reference signals to phases and into the PWM modulator, which contain a zero-sequence component to increase the voltages delivered to the load. The bottom signals are two of the motor currents (phases and ). It can be observed that the load currents are balanced. A very important issue in the operation of the inverter under fault conditions with this strategy is the behavior of input current harmonics. In effect, the input transformer of the inverter is designed considering that all cells are operating. Under this condition, the phase displacement of the secondaries allows for the cancellation of current harmonics. If some cells are bypassed, the condition for the cancellation is lost, which will create an increase in the harmonics. Fig. 13 shows the input current spectrum for an 15-module drive, for the cases of 0, 1, 2, and 3 cells bypassed in one phase group.

RODRGUEZ et al.: OPERATION OF A MEDIUM-VOLTAGE DRIVE UNDER FAULTY CONDITIONS

1085

Fig. 13 conrms the increase in the current harmonics as modules are bypassed. However, the harmonics are always under values permitted by IEEE Std. 519 with one cell bypassed, and probably with two or three cells bypassed, depending on the source impedance. V. COMMENTS AND CONCLUSION The reliability of the inverter can be improved drastically using the method presented in this paper, by adding a few simple contactors in the power circuit. In addition, the modication of the reference voltages delivered to the modulator allows for an increase in the voltage available at the load, reaching a high utilization of the operating cells. The operation of the inverter with bypassed cells deteriorates the quality of the input current. However, the increase in the harmonics is not excessive and can be tolerated in an emergency situation. REFERENCES
[1] F. Dewinter, R. Paes, R. Vermaas, and C. Gilks, Maximizing large drive availability, IEEE Ind. Appl. Mag., vol. 8, no. 4, pp. 6675, Jul./Aug. 2002. [2] C. Turpin, P. Baudesson, F. Richardieu, F. Forest, and T. Meynard, Fault management of multicell converters, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 988997, Oct. 2002. [3] P. Baudesson, F. Richardeau, and T. Meynard, Failure-tolerance and remedial strategies for a multilevel ying capacitors inverter, in Proc. IEEE PESC00, Jun. 2000, pp. 649654. [4] F. Richardeau, P. Baudesson, and T. Meynard, Design of a sensor to improve safety and short-circuit tolerance of a ying capacitors multilevel inverter, in Proc. Power Conversion Intelligent Motion 2000, Nuremberg, Germany, 2000, pp. 649654. [5] P. W. Hammond, A new approach to enhance power quality for medium voltage drives, IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202208, Jan./Feb. 1997. [6] J. Rodriguez, J. S. Lai, and F. Z. Peng, Multilevel inverters: a survey of topologies, controls and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724738, August 2002.

Peter W. Hammond (M74) received the B.S.E.E. degree from California Institute of Technology, Pasadena, in 1962, and the M.S.E.E. degree from Case Institute of Technology, Cleveland, OH, in 1966. He has almost 40 years of experience in ac drives. For the last 27 years, he has been an Engineer with ASIRobicon Corporation, Pittsburgh, PA, where he participated in the development of cascaded multilevel inverters.

Jorge Pontt (M00SM04) received the Engineer and Master degrees in electrical engineering from the Universidad Tcnica Federico Santa Mara (UTFSM), Valparaso, Chile, in 1977. Since 1977, he has been with UTFSM, where he is currently a Professor in the Electronics Engineering Department and Director of the Laboratory for Reliability and Power Quality. He is coauthor of the software Harmonix used in harmonic studies in electrical systems. He is the coauthor of patent applications concerning innovative instrumentation systems employed in high-power converters and large grinding mill drives. He has authored more than 90 international refereed journal and conference papers. He is a Consultant to the mining industry, in particular, in the design and application of power electronics, drives, instrumentation systems, and power quality issues, with management of more than 80 consulting and R&D projects. He has had scientic stays at the Technische Hochschule Darmstadt (19791980), University of Wuppertal (1990), and University of Karlsruhe (20002001), all in Germany. He is currently Director of the Centre for Semiautogenous Grinding and Electrical Drives at UTFSM.

Rodrigo Musalem was born in Via del Mar, Chile, in 1978. He received the Engineer and M.Sc. degrees in electronic engineering from the Universidad Tcnica Federico Santa Mara (UTFSM), Valparaso, Chile, in 2004. He recently joined Procter & Gamble Chile, Santiago, Chile. His main research interests are in automatic control and power electronics.

Jos R. Rodrguez (M81SM94) received the Engineer degree from the Universidad Tcnica Federico Santa Maria, Valparaso, Chile, in 1977, and the Dr.-Ing. degree from the University of Erlangen, Erlangen, Germany, in 1985, both in electrical engineering. Since 1977, he has been with the Universidad Tcnica Federico Santa Maria, where he is currently a Professor and Academic Vice-Rector. During his sabbatical leave in 1996, he was responsible for the mining division of Siemens Corporation in Chile. He has several years consulting experience in the mining industry, especially in the application of large drives such as cycloconverter-fed synchronous motors for SAG mills, high-power conveyors, controlled drives for shovels, and power quality issues. His research interests are mainly in the areas of power electronics and electrical drives. In recent years, his main research interests are in multilevel inverters and new converter topologies. He has authored or coauthored more than 130 refereed journal and conference papers and contributed to one chapter in the Power Electronics Handbook (New York: Academic, 2001).

Pablo Lezana was born in Temuco, Chile, in 1977. He is currently working toward the Ph.D. degree in power electronics at the Universidad Tcnica Federico Santa Mara, Valparaso, Chile. His research interests include PWM rectiers and modern digital devices.

Mara Jos Escobar received the M.Sc. degree in electronic engineering, with a major in automatic control, from the Universidad Tcnica Federico Santa Mara, Valparaso, Chile. She has worked in the areas of power systems and digital signals. She is currently with Sixbell Chile, Santiago, Chile, where she works in telephony, developing mobile platforms.