PVT Sensitive Sleep for SRAM Core

Piyush Jain, Jitendra Dasani and Ashish Kumar

STMicroelectronics Pvt Ltd. Greater Noida, India Email: {piyush.jain, jitendra.dasani, ashish.kumar}@st.com
AbstractData retention power gating is a commonly used feature for deep submicron SRAM. However, reducing supply voltage and increasing process variation puts a limitation on such usages. Gain in leakage reduction and stability are inversely proportional. Present scheme proposes a method to enhance stability while applying such data retention power gating to SRAM memory core. Method takes care of stability using a feedback mechanism and provides stability under crosscorner/high-leakage conditions. We could observe increase in noise margin up to 6% of VDD using the proposed methodology, with 5% penalty in leakage gain. The scheme enables the memory usage under low voltage (sub-1V) operation, where we observe data retention failures using normal gating methods.

voltage varies with process corner. RNM depends on this railto-rail voltage. The scheme provides increased rail-to-rail voltage under high-Vt/high-leakage conditions, thus increasing the RNM for a given supply voltage.

II.

SLEEP CIRCUIT IMPLEMENTATION

A. Normal Sleep-Circuit Implementation

I. INTRODUCTION Scaling of CMOS devices has led to an era of high leakage and power density. This is the most prominent challenge to scaling and for the survival of Moores law. Increasing usage of SRAM on SOCs requires leakage suppression methods for them [1], [2]. Power gating with data retention is commonly used method [6], [3]. However, stability issues associated with them at deep-submicron technologies limit their usage [4], [5], [8]. Stability is affected at different corners by different extent. Efforts have also been done for PVT dependent leakage reduction [7]. Fig.1 shows the sub-threshold leakage components of a SRAM cell. Power gating reduces the supply voltage, and increases the source voltage up to certain extent, so as to retain the data stored. This reduces the bitline-leakage, cell-leakage-n and cell-leakage-p, the main components of leakage at high leakage conditions, along with gate-leakage and GIDL. Reduction of rail-to-rail voltage results in the reduced noise margin of the cell, measured as retention noise margin (RNM). Sufficient RNM is needed for the cells in sleep mode so as to ensure data integrity once the memory awakes after sleep [8]. At low voltages and slow process corners although we observe less leakage, high Vt of devices p-diode and n-diode(Fig.2) results in low rail-to rail voltage reducing RNM to unacceptable values. Sleep circuit proposed here uses a bulk bias modulation using feedback from virtual power planes and results in Vt lowering of diode devices used for these conditions, making rail-to-rail voltage higher. To take care of cross-corner instabilities, p-n combination of diode device is used. Data retention voltage for SRAM is directly related to this RNM value. For a particular supply voltage, after application of such schemes, the rail-to-rail

Using data-retention gated power is a widely used feature for deep sub-micron SRAM [6], [3]. Scheme uses header and footer devices for providing lower supply across memory cells while in sleep mode (fig.2). PMOS is used to provide normal mode active current, controlled by ENb and NMOS is used to provide normal mode active sink for the memory columns, controlled by EN. A low EN triggers sleep mode for the memory core. Normal mode current is no more available. Due to leakage current of the memory core, virtual-VDD plane starts falling and virtual-GND plane starts rising. Eventually virtual levels achieve VDD-Vtp and Vtn respectively.

WL(L)
Cell leakage-p

0
Bitline leakage

1
Cell leakage-n

BL

BLb

Figure-1. Sub-threshold leakage in SRAM

ILEAK vs V DD@150C

ENb p-diode Virtual VDD

4 . 00E - 0 6

FF FS SF SS FF_PD
3 . 50E - 0 6

ENb p-diode

FS_PD SF_PD SS_PD

3 . 00E - 0 6

ILEAK (A)

2 . 50E - 0 6

Virtual VDD

SRAM Columns

2 . 00E - 0 6

1 . 50E - 0 6

1 . 00E - 0 6

Virtual GND

SRAM Columns
5 . 00E - 0 7 0 . 00E +0 0 0. 90 1. 0 0

n-diode EN

VD D ( Vo l t s)

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(b) Leakage Variation

Virtual GND

(a)Sleep Circuit
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FF_- 40C

n-diode EN
0.30 0.25 0.20 FF_-40C FS_-40C SF_-40C SS_-40C FF_150C FS_150C SF_150C SS_150C

p-diode in parallel gnd

VRTR vs VDD (Pow er Dow n)

RNM vs VDD (Pow er Dow n)

1.000

FS_-40C SF_-40C SS_-40C

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FF_150C FS_150C SF_150C

R N M ( N o m - 7 s ig m a )

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SS_150C

Figure 3. p-n Diode for Footer cross corner conditions (SF/FS) or at slow (SS) corner, railto-rail voltage and RNM becomes minimum. PN compensated structure takes care of cross-corner conditions. Fig.3 explains the implementation of the scheme. At SF condition, n-diode in footer becomes less effective, and most of the leakage current is siphoned by the p-diode put in parallel. To meet Vt adjustment requirement, bulk of this pdiode is connected to ground. Bulk can be connected to any reference voltage also to meet the appropriate Vt requirement. In another implementation, bulk of this device (footer pdiode) can be connected to virtual VDD also, thus exploiting the advantage of feedback. Increased leakage reduces virtual-VDD level which in turn is fed back to bulk of footer p-diode, reducing the Vt of this device. Overall effect is the reduction in virtual-ground level. The similar advantage can be taken using a n-diode with header, using a triple well and supplying a higher bulk bias or feedback bulk bias from virtual-ground. C. Using Feedback to the Bulk of Header( p-diode) Addition of bulk bias to the p-diode of header from virtualVDD takes care of excessive drop in its value (Fig.4). At SS (slow nmos, slow pmos) corner, or at fast corner with high leakage condition, rail-to-rail voltage drops significantly. This feedback reduces threshold voltage of p-diode (header) and hence prevents virtual-VDD from falling to a certain extent. The similar arrangement can be done at footer (n-diode) with the use a separate p-well, where bulk of n-diode is biased with virtual-ground. In deep submicron technologies, variation of

V R T R ( V o lt s )

0.10

0.700

0.05

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0.00 0.9V 1.0V 1.1V 1.2V 1.3V 1.4V

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VDD

0.400

0.300 0.9V 1.0V 1.1V 1.2V 1.3V 1.4V

VDD

-0.20

(c) VRTR Variation

(d) RNM variation

Figure 2. Normal Sleep Circuit and Performance The rail-to-rail voltage is given by, Vrail-to-rail = VDD Vtn Vtp B. Sleep Circuit Using P-N Compensated Diode With the use of normal circuit explained above, the problem arises at cross corner situations. When NMOS becomes slow and PMOS becomes fast (SF corner condition), virtual ground value rises to higher value, despite of low leakage. Thus rail-to-rail voltage reduces, decreasing the RNM and hence putting a limitation on DRV. Reduction in rail-to-rail voltage can be due to excessive leakage and hence increase in virtual-ground with reduction in virtual-VDD level. In deep submicron processes, due to large process variations, slow device achieves very high threshold value reducing the rail to rail voltage though leakage is very less in this condition. This phenomena creates a situation, when at (1)

VDD/Virtual VDD Virtual VDD ENb p-diode Virtual VDD Virtual VDD ENb p-diode Reference Reference

Noise-sink

SRAM Columns SRAM Columns

Virtual GND Virtual GND n-diode p-diode in parallel n-diode p-diode in parallel EN gnd EN

Figure-5. Using Reference Voltage for the Bulk of Header Figure-4. Using Virtual-VDD feedback to header threshold voltage is large across process corners. At low temperatures threshold voltage increases and stability problem arises due to severe reduction in rail-to-rail-voltage and hence reduced RNM. DRV (external voltage for memory) increases, creating a limitation for the low voltage designs. This is undesirable being such a limitation imposed by a very low leakage condition/corner, where sleep circuit is not required. D. Reference Voltage to the Bulk of Header (p-diode) Fig-5 explains the usage of a reference voltage derived from VDD/Virtual VDD for the bulk of p-diode (header). When the desired lowering for threshold voltage of p-diode is large, the direct feedback from virtual-VDD is not sufficient. Bias voltage is further reduced using N-diode/diodes. Bulk bias voltage should be kept high enough so that the junction diode of MOS device is always in reverse bias. Using this scheme even the bulk of footer n-diode can be optimized for stability. Here we need to mention that we are compromising very less with leakage gain of sleep circuit. Targeted leakage reduction is at fast corner, highest temperature and highest voltage which is the least affected condition. However, low DRV achieved using the scheme results in overall gain in leakage reduction. observed to be least for FS condition. Also at FF and SS corners, VRTR is reduced the most (fig.2c). RNM is least for SS and then for FS corner (fig2.d). Dependence of VDD on RNM is very high at these corners. Due to highest reduction in voltage across memcell at these corners, RNM dependence has taken a sharper slope even at higher supply. We have performed simulations with proposed schemes along with a comparison to the basic scheme. Schemes illustrated in fig.3, fig.4, fig.5 are respectively called as PD1, PD2 and PD3 schemes. Fig.6 illustrates relative performances of various schemes. VRTR is compared for two corners, FS/150C and SS/-40C. We observe that the application of PD2 and PD3 schemes increases VRTR significantly (fig.6a, fig.6c). PD1 has little impact on VRTR, as this scheme is to take care for stability at SF corner. RNM is taken as a measure of stability for memcell sleep/power-down mode. We are using a parameter defined as RNM (Nominal7*Sigma(RNM)) as stability parameter for the memory cell. Sigma(RNM) is the standard deviation of RNM value under statistical simulations. We observe that the parameter is significantly improved with applied methods, PD2 and PD3. For a stable and usable cell, we take the criteria, RNM(Nominal- 7*Sigma(RNM)) >0 (2)

III.

RESULTS AND DISCUSSION

We have discussed three incremental schemes here other than conventional or basic sleep/power-down. Scheme illustrated in fig.2a refers to basic scheme. Leakage is highest at fast corner (fig.2b). However,VRTR (rail-to-rail voltage) is

We observe that the value of VDD for which this parameter crosses x-axis is lower for the schemes applied (fig.6b, fig.6d). This value of VDD is the DRV for the memory unit. We define DRV as the minimum supply voltage applied to memory core including sleep arrangement for which no data-retention failure is observed. We observe from our results that the value of DRV is lower with the applied sleep circuits (PD1, PD2, PD3) compared to the basic

1.0 0 0

VRTR vs VDD (All Schemes )

0.25 0.20

RNM vs V DD (All Schem es)

4.00E-06 3.50E-06

Ile ak vs V DD @FF 150C (All Sche m e s )

0 .9 0 0

SS_-40_basicPD SS_-40_PD 1 SS_-40_PD 2 SS_-40_PD 3

SS_-40_bas ic P D

0.15 0.10 0.05 0.00 0.9V

SS_-40_P D1 SS_-40_P D2 SS_-40_P D3

3.00E-06
Ileak (A)

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2.50E-06 2.00E-06 1.50E-06 1.00E-06 5.00E-07

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R N M ( N o m - 7 S ig m a )

V R T R (V o lt s )

no_scheme basicPD PD1 PD2 PD3

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VDD

1.2 V

1.3V

1.4 V

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(a). RTR Vs VDD (-40C)

(b). RNM Vs VDD (-40)

Figure-7. Leakage with Various Schemes

0.950

VRTR vs VDD (All Sche me s)

FS_150_basicPD

0.15

RNM vs VDD (All Schem es)

IV.

SUMMARY AND CONCLUSION

0.850

FS_150_PD1 FS_150_PD2 FS_150_PD3

0.10

0.750

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R N M ( N o m - 7 S ig m a )

V R T R ( V o lt s )

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1.3V

1.4V

0.550

0.450

FS_150_basicP D

We have analyzed sleep circuits and stability of SRAM. Methods for stability improvement with negligible loss in leakage current are proposed. Proposed methods provide significant improvement in noise margin and hence lower DRV for the memory subsystem. We could reduce the DRV up to 100mv with a penalty of 5% in leakage gain factor.

-0.10
0.350 0.9V 1.0V 1.1V

FS_150_P D1 FS_150_P D2 FS_150_P D3

VDD

1.2V

1.3V

1.4V

-0.15

REFERENCES
[1] Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty, Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design, ISLPED, pp. 214219, 2004. Huifang Qin, Yu Cao, Dejan Markovic, Anderi Vladimirescu and Jan Rabaey, SRAM Leakage Supression by Minimizing Standby Supply VoltageProceedings of 5th International Conference on Quality Electronics Design 2004. J.B.Kuang, H.C. Ngo, K.J. Nowka, J.C. Law, and R.V. Joshi, A LowOverhead Virtual Rail Technique for SRAM Leakage Power Reduction, ICCD2005. Bhaskar Chatterjee, Manoj Sachdev, Stevan Hsu, Ram Krishnamurthy, Shekhar Borkar, Effectiveness and Scaling Trends of Leakage Control Techniques for Sub-130nm CMOS Technologies, ISLPED2003,pp.122-127. Oliver Thomas, Marc Belleville, Francois Jacquet, Philippe Flatresse, Impact of CMOS Technology Scaling on SRAM Standby Leakage Reduction Techniques, ICICDT06. Amit Agarwal, Hai Li, Kaushik Roy, A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron, IEEE Journal of Solid State Circuits, Vol. 38, No. 2, pp.319-328,Feb2003. Chris Hyung-il Kim, Jae-Joon Kim, Ik-Joon Chang and Kaushik Roy, PVT-Aware Leakage Reduction for On-Die Caches With Improved Read Stability,IEEE Journal of Solid State Circuits, Vol. 41, No. 1, pp.170-178, Jan2006. Stephan Henzler, Matthias Eireiner, Georg Georgakos, Joerg Berthold, Doris Schmitt-Landsieldel, Activation Technique for Sleep-Transistor Circuits for Reduced Power Supply Noise,CIRC2006,pp.102

(c). RTR Vs VDD (150C)

(d). RNM Vs VDD (150C)

Figure-6. Rail-to-Rail and RNM Variation sleep/power-down scheme. We have measured leakage with all the schemes discussed. We observe that the impact of various schemes applied for providing stability has negligible impact on leakage (fig.7). We have used the concept of bulk bias for the designing the sleep circuit along with feedback mechanism, which tracks the advantage gained across PVT conditions. Bulk bias effect is formulated as,

[2]

[3]

[4]

[5]

Vt = Vt 0 + ( s + Vsb s )

(3)

[6]

Where, is the body effect co-efficient, s is the surface potential at threshold. Vsb is the source-to-bulk potential. Vt is modulated with bulk bias to adjust virtual power levels and hence improves the stability.

[7]

[8]