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ORIGINAL ARTICLE
frequency division multiplexing the total band is divided into N non-overlapping frequency channels, while on OFDM the band is divided into a number of overlapping frequency channels but with orthogonal frequencies, the consequence is a better use of the available spectrum. Those orthogonal frequencies could be achieved by the IFFT. Each subcarrier has a different frequency. Frequencies chosen so that an integral number of cycles in a symbol period and Signals are mathematically orthogonal. A technique which allows an arbitrary number of symbol shapes to be distinguishable is orthogonal signaling. Orthogonality describes the degree to which a pair of di? erent pulse shapes is independent or unrelated. Functions n(t) and m(t) are orthogonal with respect to each other over the interval a < t < b if,
Note that this is a continuous version of the vector dot product. The idea is that given a certain bandwidth of out pulse shapes there can be entire sequences of functions that are orthogonal. If we have a set of functions {1(t), 2(t), . . , n(t), . .} and each function is orthogonal to each other function. A.OFDM in A Multipath Environment Data is transmitted in parallel without interference.
st nd rd
To generate OFDM successfully the relationship between all the carriers must be carefully controlled to maintain the orthogonality of the carriers. For this reason, OFDM is generated by firstly choosing the spectrum required, based on the input data, and modulation scheme used. Each carrier to be produced is assigned some data to transmit. The required amplitude and phase of the carrier is then calculated based on the modulation scheme (typically differential BPSK, QPSK, or QAM).
Two possible
2
The orthogonal carriers required for the OFDM signal can be easily generated by varying the amplitude and phase of each frequency bin, then performing the IFFT. Since each bin of an IFFT corresponds to the amplitude and phase of a set of orthogonal sinusoids, the reverse process guarantees that the carriers generated are orthogonal. III. SYSTEM DESIGN A basic OFDM system consists of a QAM or PSK modulator/demodulator, a serial to parallel / parallel to serial converter, and an IFFT/FFT module. The iterative nature of the FFT and its computational order makes OFDM ideal for a dedicated architecture outside or parallel to the main processor. Using FPGA instead of an ASIC gives also flexibility for reconfiguration, which is a need for the Software Defined Radio (SDR) concept. The focus of this work is to validate the suitability of reconfigurable devices such as FPGAs toperform Intermediate Frequency (IF) processing to support SDR A. OFDM Transmitter
Cloc k
Input bits In p
S y
Seri al to
IFFT
OFDM signal
1)Input Sampler IQ Gen:This block samples the serial input and generates 2 bit IQ output. The following techniques are used to implement this block 1) Serial input (in data) is assigned to the LSB of one internal Shift Register (sig IQ). 2) Finally sig IQ is assigned to the 2bit Output (IQ data). 2) Symbol Mapper: This block consist of a number of ROMs containingthe constellation mapping for each of the specifiedmodulation schemes (QPSK, 16-QAM and 64-QAM),two multiplexers which select the In Phase andQuadrature data from the desired modulation schemestored on ROMs.
This block maps the input I, Q to the corresponding to the real part and imaginary part of the constellation symbols.
3) Serial to Parallel Conversion: This block is used in OFDM Transmitter, to convert serial input to parallel output. This block's output is given to the input of IFFT.The input serial data stream is formatted into the word size required for transmission, e.g. 2 bits/word for QPSK, and shifted into a parallel format. The data is then transmitted in parallel by assigning each data word to one carrier in the transmission. 4) Inverse Fast Fourier Transform: The following techniques are followed to implement the IFFT using FFT. After the required spectrum is worked out, an inverse Fourier transform is used to find the corresponding time waveform. This act like to Frequency domain to time domain signal translator. Below figure shows internal architecture of IFFT
B.OFDM Receiver
Sy mb ol Dema ppe r
1) Fast Fourier transforms: On the receiver side the FFT is implemented and the signal is translated from time domain to frequency domain.In VHDL implementation the FFT block is used to compute the IFFT by reversing the real & Imaginary at input and output side and further dividing by 8.Above figure shows FFTdecimation in frequency
and the output from this block is given to the Symbol de-mapper. 3) Symbol de-mapper: This block maps, the Real and imaginary parts of the serial out from PISO, to the IQ corresponding to the symbols. It extracts the IQvalues from the serial out of PISO.real part and imaginary part of the constellation 4) Out bit generator: This block takes 2 bit IQ s from Symbol de-mapper and generates output bits. The following techniques are followed to implement this blockfirstly 2 bit input (IQ Data) data is assigned to the one internal Shift Register (sig IQ) and finally sig IQ's msb is assigned to the output bit. 5) Clock distributor: This is the clock distributer block, which generates two enable signals a) en_div_2 and b) en_div_16. Performance in a multipath channel OFDM can provide wideband wireless connectivity even in fading channel, efficiently deals with channel delay spread and gives Enhanced channel capacity.OFDM increases robustness against Frequency Selective Fading or Narrowband Interference.Approximately 50% of bandwidth can be reduced using OFDM technology .Thus spectral efficiency increases.
Conventional multicarrier
S S X ( ( S S [ 0 8 1 X ( ( - 0 ) ) 2 1 S S [ ] X 1 S ) 0 ( ( - 2 1 ( S [ ) 4 1 x -1 S ] X 1 S 1 ( ( ) 2 ` 1 [ This 1 block6 - parallel ( [ input to serial output 2) Parallel to Serial conversion: is used in OFDM RX, 3 1 )to convert
Orthogonal multicarrier
Frequency
IV .TOP MODULE FOR OFDM TRANSMITTER AND RECEIVER SYNTHESIS REPORT A. Advanced HDL Synthesis Report TABLE : Macro Statistics
ROMs 4x2-bit ROM Multipliers 14x14-bit multiplier Adders/Subtractors 14-bit adder Counters 4-bit up counter 6-bit up counter 8-bit up counter Registers Flip-Flops Comparators 14-bit compara tor greater Multiplexers 1-bit 140-to-1 multiplexer XORs 1-bit xor2
RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal
Selected Device : Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs Number of bonded IOBs: Number of MULT18X18SIOs:
3s500efg320-4 3839 out of 4656 241 out of 9312 7026 out of 9312 3 3 out of 232 16 out of 20 1% 80% 82% 2% 75%
V.SIMULATION After architecture of the processor is modeled in VHDL. Modelsim Xilinx Edition will be used for functional simulation and verification of results. Xilinx ISE will be used for synthesis.Spartan 3E FPGA board: synthesis & verifying results on the FPGA hardware. Xilinx Chipscope tool will be used for verifying the results on Spartan 3E FPGA. Hardware architecture for the proposed design wasdeveloped, realized in VHDL. The realized architectures was tested and validated the outputs are generated by a hardware simulation using Modelsim.Simulation results are given in below Figure. 1 And Figure. 2 VI. CONCLUSION In this paper, OFDM has been studied and implemented for transmitter and receiver and Its applications have been extended from high frequency radio communications to telephone networks, digital audio broadcasting and terrestrial broadcasting of digital television. The advantages of
OFDM, especially in the multipath propagation, interference and fading environment, make the technology a promising alternative in digital communications including mobile multimedia. Therefore this design can be applied to real-time signal processing system, which completes the main computing modules in the OFDM for multi services. REFERENCES Lenin Gopal*, Daniel Wong Sing Tze, Nur Zawanah Ishak Design of an FPGA-Based OFDM Transceiver for DVB-T Standard , School of Engineering and Science, Curtin University Sarawak Malaysia Miri, Sarawak, Malysia On the design of an FPGA-Based OFDM modulator for IEEE 802.16-2004, Joaqun Garca, Ren Cumplido, Department of Computer Science, INAOE, Puebla, Mexico,joaquingr@ccc.inaoep.mx, rcumplido@inaoep.mx E.Lawrey, Multiuser OFDM, in Proc. International Symposium on Signal Processing Applications '99 vol2, 1999, pp.761.764. Ahmad sghaier,Shawki Areibi and Bob Dony School of Engineering , Guelph ,Guelph ON Canada N1G2W1 ,A Pipeline Implementation Of OFDM Transmission On Reconfigurable Plateforms Joaqun Garca, Ren CumplidoDepartment of Computer Science, INAOE, Puebla, Mexico On the design of an FPGA-Based OFDM modulator for IEEE 802.16-2004joaquingr@ccc.inaoep.mx, rcumplido@inaoep.mx