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=exp (2n]
N
)
Fig. 4 Butterfly Processor
To avoid using a complete digital multiplier to carry out
multiplication with the twiddle factors, we used CSD
(canonical signed digit multiplication, using shifts and adds).
The results desired multiplication is controlled by 2 stages of
multiplexing feeding into the CSDs. The butterfly processor
has two pipelined stages. The data-path of the butterfly
processor as shown in fig. 5.
Fig. 5 Butterfly Architecture
International Journal of Engineering Trends and Technology- Volume4Issue2- 2013
ISSN: 2231-5381 http://www.internationaljournalssrg.org Page 112
B. Address Generation Unit (AGU): The address
generation unit controls the address bus going to memory. The
FFT processor reads and writes fromand to the 8 dual port
memory banks concurrently (each address is 3 bits). The
address mapping scheme ensures that no memory location is
read fromand written to at the same time [3]. There are 8 read
address buses, and 8 write address buses. The computations
are in place, which simplifies the address generation unit.
C. Micro-coded State Machine: The Micro-coded state
machine stores and generates all the control signals for the
FFT processors operation at every, its progression is
controlled by the clock. A reset signal en_fft resets the state
machine counter and signals the beginning of a new 64-point
FFT calculation. Upon completion the FFT processor asserts a
done_fft signal to communicate the completion of the 64-point
FFT. To performan Inverse Fast Fourier Transform, all we
need to do is swap the real and imaginary parts
VI. RESULTS AND DISCUSSION
The simulated waveforms of Address Generation Unit ,
where the top to signals indicates read data and write data
respectively is shown in fig. 6. It shows no memory location
is read fromand written to at the same time.
Fig. 6 Simulation Results in Address Generation Unit (AGU)
The simulated waveforms of contol unit , where the top to
signals indicates clk ,fft enable and all control signals is
shown in fig. 7.
Fig. 7 Simulation Results in Control Unit
Fig. 8 Simulation Results in Butterfly Unit
Fig 8 Simulation Results in 64 Point FFT using Radix-4
Algorithm
The simulation results of Butterfly Unit is shown in fig. 8
and the simulated waveforms of 64 point FFT using Radix-4
algorithmis shown in fig. 9, where the top to signals indicates
Butterfly operation and address generation and dual port
RAM.
VII. CONCLUSION
This paper presented a new, very high speed FFT
architecture based on the Radix-4
3
algorithm. A fully
pipelined, systolic processing core of a 64-point FFT has been
implemented in both FPGA and standard cell technologies and
validated in the former case. The results demonstrate the very
high operating frequencies and the low latencies of both the
FPGA and VLSI implementations. The proposed FFT
architecture demonstrates a significant latency reduction
compared to existing solutions and at the same time, has
reduced data memory required and improved multiplier
utilization while occupying a smaller silicon area occupation
consuming less power compared to similar solutions. The
modular design of the Radix-4
3
allows them to be easily
incorporated into larger systems for computing large scale
FFTs while a fully registered, systolic architecture assures
maximumoperating frequency. Future research by our group
will focus on the implementation of a reconfigurable FFT
architecture, capable of performing the FFT transformof 64,
4K, 256K or 16M complex points.
REFERENCES
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AUTHORS
K.Sreekanth yadav, Student, is
currently Pursuing his M.Tech VLSI.,
in ECE department of Sree
Vidyanikethan Engineering College,
Tirupati. He has completed B.Tech in
Electronics and Communication
Engineering in J awaharlal Nehru
Technological University, Anantapur.
His research areas are VLSI, Digital IC
Design, and VLSI and Signal
processing.
MS. V.Charishma, Assistant Professor,
Department of ECE, Sree Vidyanikethan
Engineering College (Autonomous),
Tirupati, India. She has completed
M.Tech in VLSI Design, in Satyabhama
University. Her research areas are
,Digital IC Design, VLSI Technology
MS. K. Neelima, Assistant Professor,
Department of ECE, Sree
Vidyanikethan Engineering College
(Autonomous), Tirupati, India. She has
completed M.Tech in VLSI Design, in
Satyabhama University. Her research
areas are RFIC Design ,Digital Design,
VLSI Signal Processing