Sie sind auf Seite 1von 14

www.fairchildsemi.

com

AN- 9038
PDP Panel Drive System Using PDP-SPMTM Module
By S.N. Kim, D.C. Choi, J.E. Yeon, C.K. Kim

Contents 1. Introduction 2. Plasma Display Panel 2.1. 2.2. 2.3. 2.4. 3.1. 3.2. 3.3. 3.4. 4.1. 4.2. 4.3. 5.1. 5.2. 5.3. 5.4. Consist of an AC PDP Panel Commercial Driving Scheme for AC PDPs Driving Methods for AC PDPs Driving Sequence and Waveforms in Sustain Mode Ordering Information Product Selection Internal Circuit and features Package Outline Overview of Application Circuit Bootstrap Circuit Footprint Guide of PDP-SPM for PCB Design Heat Sink Mounting Handling Precaution Marking Specifications Packaging Specifications

3. Product Outline of PDP-SPM

4. Application Outline

5. Package

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com

APP NOTE NUMBER

APPLICATION NOTE

1. Introduction
This PDP-SPMTM module combines an optimized circuit in a buffer IC and a drive that is matched to the IGBTs switching characteristics. System reliability is further enhanced by integrated under-voltage protection and high driving capability. The PDP- SPM module is an advanced module designed to achieve high system reliability. This application note explains how to design the detailed power circuit of PDP-SPM and its applications for users. This document provides a design example with a sustain and ER module, which is a well-known driving method and sequence of PDP panel driving.

2. Plasma Display Panel


2.1 Consist of an AC PDP panel A PDP is a display device with self-emission characteristics. This device used plasma discharge in order to utilizing the light emission. This device has commonly Surface Discharge Structure for long life and high brightness. Fig. 1. is simplified cross sectional structure of Alternating Current (AC) PDP.
Figure 2. Equivalent Circuit for inherent capacitance of PDP cell

2.2 Commercial driving scheme for AC PDPs Most AC PDPs use Address Data Separation(ADS) method for displaying one picture as shown Fig. 3. On every sub-fields consist of reset, address and sustain period. The number of subfield is variable by picture brightness and power consumption. During the reset period, the PDP cell is initiated without any charge for unexpected discharging. During the address period, wall charge accumulated in the PDP cell for sustaining. The gas discharge occurs during sustain period, which is for light emission. Meanwhile, most of the power that is required to drive the PDP is consumed driving the sustaining period. In other words, the power switches in the sustain circuit are primarily responsible for efficiency and size of the overall system.

Figure 1.

Cross Sectional Structure of AC Plasma Display Panel (PDP)

As shown in the figure above, the AC PDP is composed of three electrodes, two bus electrodes, whose role is to make light emissions, one bus and address electrode, whose function is to make a wall charge before plasma discharge during sustain period. Meanwhile, since bus electrodes are covered with the dielectric and MgO, the load characteristics of the AC PDP can be represented by the capacitive load. Fig. 2. is an equivalent circuit for inherent capacitance of PDP cell.
2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

SF : sub-field

Figure 3.

ADS of one TV field

2.3 Driving Methods for AC PDPs This application note deals with Weber driving method that is commonly used.

www.fairchildsemi.com 2

APP NOTE NUMBER

APPLICATION NOTE

Fig.4. is conventional driving pulse at Weber driving method, X and Y are Bus electrodes, A is Address electrode.

resonance frequency. L is series inductor including parasitic inductance and C is an equivalent capacitor of panel. The t2 is sustaining the energy. During the t2, PDP panel is charged positive across Y to X board, and the panel voltage is maintained to Vs. The t3 is recovered the energy which is charged in Panel, and the panel capacitor discharges until the panel voltage drops to zero. The t4 is free-wheel time and the ground potential is supplied to the panel.

Sustain

Reset

Address

Sustain

The t5 is same function like t1, energy flow from X-board to Y-board Next time sequence is alternating as same flow.

Figure 4.

Weber Driving Method

In general, X and Y electrode are operating a fullbridge configuration as shown in Fig.5. This schematic diagram is conventional Weber circuit. This is the leading that is now used by many PDP manufacturers. This application note focus on the sustain period, so there is a focus on sustain and energy recovery block. Power devices in Fig.5. can be grouped as a functional unit : Energy recovery circuit : Q3~4, Q7~8, D3~4, D7~8 Sustain circuit : Q1~2, Q5~6, D1~2, D5~6

The sustain block is operating as full-bridge and the energy recovery block is operating leading and lagging energy for give-and-take charges to the PDP cells with the assistance of sustain operating.

Figure 6.

Driving sequence during sustain period

The waveform in board output is Fig.7. in PDP set.

Figure 5.

Schematic diagram of Y- & X- electrode

2.4 Driving Sequence and Waveform in Sustain Mode Fig.6. is shown t1~t5 which are the timing flows at Yboard at sustain period. The t1 is given the energy through the PDP panel from Yboard to X-board. The panel voltage goes high as rate of LC
2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

Figure 7.

X & Y board voltage waveform at sustain period

www.fairchildsemi.com 3

APP NOTE NUMBER

APPLICATION NOTE

3. Product outline of PDP-SPM module


3.1 Ordering Information

3.2 Product Selection

Part Number FVP18030IM3LSV1 FVP12030IM3LEG1

Rating Current Voltage (A) (V) 180 300 120 300

Main Application Sustain ER

3.3 Internal Circuit and features Use of high speed 300V IGBTs with parallel FRDs Single-grounded power supply by means of built-in HVIC Sufficient current driving capability for IGBTs due to adding buffer ICs.

Low leakage current due to using an insulated metal substrate Metal part IMS is connected with IGND pin for heat-sink ground. Sustain and ER module each consist of a board

(a) Sustain ( FVP18030IMS3LSG1 ) Figure 8.

(b) ER ( FVP12030IMS3LEG1 ) Internal circuit

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com 4

APP NOTE NUMBER

APPLICATION NOTE

3.4 Package Dimensions These two modules are distinguished from IGND(Pin7)

(a) Sustain ( FVP18030IMS3LSG1 ) Figure 9.

(b) ER ( FVP12030IMS3LEG1 ) Package Dimensions

4. Application Outline
4.1 Overview of Application Circuit
Y - Board
+ Vcc
DZSP CSPC CSP SUS_DN RIN DZBS

X- Board

(1) COM L (2) VIN L (3) VCC L (4) VB L (5) G L (6) VS L (7) I GND
CSP

(19) EL
ERC

<Top View>

CBS

(14) CH (18) AL

(13) VS H (12) G H (11) VB H (10) VCC H (9) VIN H (8) COM H (7) I GND

FVP18030IM3LSG1

DBS DZBS

RBS

FVP12030IM3LEG1

C CLAMP CP

(15) EH

CBS

(17) CL
ERL

ER_UP RIN CSP CBS RBS DBS

(16) KH

RIN SUS_UP

(8) COM H (9) VIN H (10) VCC H


DZBS

(16) AH (17) AL
CP

(15) EH
C CLAMP

RBS

DBS CBS

(11) VB H (12) G H (13) VS H

(18) CL

(6) VS L (5) G L (4) VB L (3) VCC L (2) VIN L (1) COM L

DZBS RIN CSP CSPC

(14) CH
<Top View>

ER_DN

(19) EL

Panel
+ Vs
DZSP CSPC CSP ER_DN RIN

+ Vs + Vs + Vs
(1) COM L (2) VIN L (3) VCC L
DZBS DZSP

Cp
(19) EL
<Top View>

CBS

(14) CH (18) CL
CP C CLAMP

DBS RBS RIN ER_UP

CBS CSP

(4) VB L (5) G L (6) VS L (7) I GND (8) COM H (9) VIN H (10) VCC H

(13) VS H (12) G H (11) VB H (10) VCC H (9) VIN H (8) COM H (7) I GND (6) VS L (5) G L (4) VB L (3) VCC L (2) VIN L (1) COM L

FVP12030IM3LEG1

DZBS

DBS RBS

FVP18030IM3LSG1

(15) EH (17) AL (16) AH (16) KH


CP ERL

SUS_UP RIN CSP

(17) CL (15) EH
C CLAMP

CBS DZBS

RBS

DBS

DZBS

CBS

(11) VB H (12) G H (13) VS H

(18) AL (14) CH
<Top View>

RIN SUS_DN CSP CSPC DZSP

ERC

(19) EL

+ Vcc

Figure 10.
2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

Overview of Application circuit


www.fairchildsemi.com 5

APP NOTE NUMBER

APPLICATION NOTE

Figure 4.1 shows a typical application circuit of a sustain and energy recovery block to compose the Webber circuit that is used to drive the PDP. The circuits of X and Yboard are identical and symmetry structure.

+Vs DBS RBS C BS

VB VCC COM I N OUT Vs

VCC IN OUT GND

SUS-UP

ER-UP
RBS

ERL

4.2 Bootstrap Circuit 4.2.1 Operation of Bootstrap Circuit of Sustain part The VBS voltage, which is the voltage difference between VB and VS, provides the supply to the HVICs and the buffer ICs within the PDP-SPM in VPM19. This supply must be in the range of 13.0~20V to ensure that the buffer IC can fully drive the IGBT. The PDP-SPM module includes an under-voltage detection function for the VBS to ensure that the HVIC does not drive the IGBT. If the VBS voltage drops below a specified voltage (refer to the datasheet). This function prevents the IGBT from operating in a high dissipation mode.
There are a number of ways in which the VBS floating supply can be generated. One of them is the bootstrap method described in the following way. This method has the advantage of being simple and inexpensive. However, the duty cycle
ERC
V CC

DBS

VB VCC COM I N OUT Vs

VCC IN OUT GND

C BS

SUS-DN

ER-DN

Figure 12.

ER-UP Bootstrap Circuit

+Vs DBS RBS C BS

VB VCC COM I N OUT Vs

VCC IN OUT GND

SUS-UP

ER-UP
RBS DBS

ERL

and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor. The bootstrap supply is formed by a combination of an external diode, resistor and capacitor as shown in Figure 10. The current flow path of the bootstrap circuit is shown in Figure 11, 12, 13. When the
SUS-DNs switch is on, the SUS-UP and ER-UPs bootstrap capacitor (CBS) is charged through the bootstrap diode (DBS) and the resistor (RBS) from the VCC supply. And when the ER-UPs switch is on, the ER-DNs bootstrap capacitor is charged through the bootstrap diode(DBS), the resister(RBS) and the ER-UPs IGBT in figure 13. ER-DNs bootstrap system uses the ER-UPs bootstrap voltage to power source instead of the VCC supply.

VB

VCC OUT Vs IN OUT GND

ERC

V CC C BS

VCC COM I N

SUS-DN

ER-DN

Figure 13.

ER-DN Bootstrap Circuit

4.2.2 Initial Charging of Bootstrap Capacitor An adequate on-time duration of the IGBT on the current flow path of the bootstrap circuit to fully charge the bootstrap capacitor is required for initial bootstrap charging. The initial charging time (tcharge) can be calculated from the following equation: for SUS-UP
t charg e C BS RBS 1

+Vs

VB

VCC OUT Vs I N OUT GND

DBS RBS

VCC

C BS

COM I N

ln(

VCC ) VCC VBS (min) V f VLS

(4-1)

for ER-UP
t ch arg e C BS ( RBS + RERL )
VB VCC OUT Vs I N OUT GND

V CC

VCC COM I N

ln(

VCC VCC V BS (min) V f V LS

(4-2)

SUS-DN

for ER-DN
t ch arg e C BS RBS ln( 1

V BS _ ER UP )

(4-3)

Figure 11.

SUS-UP Bootstrap Circuit

V BS _ ER UP V BS (min) V f V HS

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com 6

APP NOTE NUMBER

APPLICATION NOTE

Vf = Forward voltage drop across the bootstrap diode VBS(min) = The minimum value of the bootstrap capacitor VHS = Voltage drop across the high-side IGBT in ER VLS = Voltage drop across the low-side IGBT in SUS RERL = The equivalent resistance of ERL inductor = Duty ratio of of the IGBT on the current flow path

The bootstrap capacitor should always be placed as close to the pins of the SPM as possible. At least one low ESR capacitor should be used to provide good local de-coupling. For example, a separate ceramic capacitor close to the SPM is essential, if an electrolytic capacitor is used for the bootstrap capacitor. If the bootstrap capacitor is either a ceramic or tantalum type, it should be adequate for local decoupling. 4.2.3 Selection of a Bootstrap Diode When floating-side IGBT or diode conducts, the bootstrap diode (DBS) supports the entire sustain voltage. Hence the withstand voltage more than 300V is recommended. It is important that this diode should be fast recovery (recovery time < 100ns) device to minimize the amount of charge that is fed back from the bootstrap capacitor into the VCC supply. 4.2.4 Selection of a Bootstrap Resistance A resistor RBS must be added in series with the bootstrap diode to slow down the dVBS/dt and it also determines the time to charge the bootstrap capacitor. That is, if the minimum ON pulse width of the IGBT on the bootstrap charging current flow path or the minimum OFF pulse width of floating-side IGBT is t0, the bootstrap capacitor has to be charged V during this period. Therefore, the value of bootstrap resistance can be calculated by the following equation.
(Vcc VBS ) t O C BS V

VCC

0V

VBS

0V

VIN : SUS-Down

Sustain & Energy Rec overy C irc uits Operation

VIN : ER-Up

Figure 14.

Timing Chart of Initial Bootstrap Charging

4.2.3 Selection of a Bootstrap Capacitor


The bootstrap capacitance can be calculated by:
C BS = I BS (max) t V

(4-4)

RBS =

(4-5)

Where t = maximum ON pulse width of floating-side IGBT V = the allowable discharge voltage of the CBS. IBS(max) = maximum discharge current of the CBS mainly via the following mechanisms: (1) Gate charge for turning the floating-side IGBT on (2) Quiescent current to the high-side circuit in the IC (3) Level-shift charge required by level-shifters in the IC (4) Leakage current in the bootstrap capacitor(CBS) leakage current (ignored for non-electrolytic capacitors) (5) Bootstrap diode reverse recovery charge By taking consideration of dispersion and reliability, the capacitance is generally selected to be 2~3 times of the calculated one. The CBS is only charged when the floatingside IGBT is off and the VS voltage is pulled down to ground. Therefore, the on-time of the SUS-DNs IGBT(ERUPs IGBT for ER-DN) must be sufficient to ensure that the charge drawn from the CBS capacitor can be fully replenished. Hence, inherently there is a minimum on-time of the SUS-DNs IGBT(ER-UPs IGBT for ER-DN) (or off-time of the floating-side IGBT).
2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07 7

In conclusion, RBS is selected to the maximum value between the two values calculated by the equations and its power rating is greater than 1/4W. Note that if the rising dVBS/dt is slowed down significantly, it could temporarily result in a few missing pulses during the start-up phase due to insufficient VBS voltage. 4.2.4 Charging and Discharging of the Bootstrap Capacitor The bootstrap capacitor (CBS) charges through the path as shown Fig. 11, 12 and 13 when the floating-side IGBT is off, and the VS voltage is pulled down to ground. It discharges when the floating-side IGBT is on. Example 1: Selection of the Initial Charging Time An example of the calculation of the minimum value of the initial charging time is given with reference to equation (4.1) to (4.3). Conditions: CBS = 10 F RBS = 5.6 Duty Ratio()= 0.2
www.fairchildsemi.com

APP NOTE NUMBER

APPLICATION NOTE

DBS = 1N4937 (600V/1A rating) VCC = 15V Vf = 0.5V VBS(min) = 13V VHS =VLS= 0.7V VERL=0.01
t ch arg e 1 15V 10uF 5.6 ln( ) 821us 0.2 15V 13V 0.5V 0.7V

Capacitor Conditions : V = 0.8V t = 0.5usec IBS(max) = 5A


(4-6)
C BS 5 A 0.5us = 3.13uF 0.8V

In order to ensure safety, it is recommended that the charging time must be at least three times longer than the calculated value.

The calculated bootstrap capacitance is about 3uF. By taking consideration of dispersion and reliability, the capacitance is generally selected to be 2-3 times of the calculated one. Note that this result is only an example. It is recommended that you design a system by taking consideration of the actual control pattern and lifetime of components.

Example 2: The Minimum Value of the Bootstrap

4.2.5 Recommended Boot Strap Operation Circuit and Parameters


Figure 4.6 is the recommended bootstrap operation circuit and parameters.

+15V line R BS D BS +Vs

+Vs

DBS

RBS

VB VCC

VCC OUT Vs I N OUT GND

5.6 10uF 1uF

5.6
VB VCC COM I N OUT Vs VCC I N OUT GND

10uF 1uF

COM IN

SUS-UP

RBS

5.6

DBS

ERL

VB
VB VCC VCC OUT Vs I N OUT GND

VCC OUT Vs I N OUT GND

ERC
+15V line

VCC COM

10uF 1uF

COM I N

10uF 1uF

IN

SUS-DN

(a) Sustain circuit


Figure 15.

(b) ER circuit
Recommended Bootstrap Circuit and Parameters

4.3 Footprint Guide of PDP-SPM for PCB design Since the lead pins of the PDP- SPM have 7o angle as shown figure 16 (a), the specific footprint guide is needed to design the PCB for assembly between PCB and PDP

SPM and for the distance of electric safety between each pins as shown figure 16 (b) and (c).

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com 8

APP NOTE NUMBER

APPLICATION NOTE

Max. Min.

Max. Min.

Max. Min.

Max. Min.

Unit : mm

Unit : mm

Unit : mm

(a) Pin Pitch of PDP-SPM ( side view )


Figure 16.

(b) Footprint guide of Sustain ( top view )

(c) Footprint guide of ER ( top view )

Recommended Footprint Guide for PCB design.

Silicon Grease

5. Package
5.1 Heat Sink Mounting The following precautions should be observed to maximize the effect of the heat sink and minimize device stress, when mounting an SPM on a heat sink.

Apply silicon grease between the SPM and the heat sink to reduce the contact thermal resistance. Be sure to apply the coating thinly and evenly, do not use too much. A uniform layer of silicon grease (100 ~ 200um thickness) should be applied in this situation.

Screw Tightening Torque

Heat Sink

Please follow the instructions of the manufacturer, when attaching a heat sink to a PDP-SPM module. Be careful not to apply excessive force to the device when attaching the heat sink. Drill holes for screws in the heat sink exactly as specified. Smooth the surface by removing burrs and protrusions of indentations. Refer to Table 1. Heat-sink-equipped devices can become very hot when in operation. Do not touch, as you may sustain a burn injury.

Do not exceed the specified fastening torque. Over tightening the screws may cause ceramic cracks and bolts and AL heat-fin destruction. Tightening the screws beyond a certain torque can cause saturation of the contact thermal resistance. The tightening torques in table 1 is recommended for obtaining the proper contact thermal resistance and avoiding the application of excessive stress to the device. Avoid stress due to tightening on one side only. Figure 17 shows the recommended torque order for mounting screws.

Table 1 Torque Rating

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com 9

APP NOTE NUMBER

APPLICATION NOTE

Figure 17.

Flatness Measurement Position

5.2 Handling Precaution When using semiconductors, the incidence of thermal and/or mechanical stress to the devices due to improper handling may result in significant deterioration of their electrical characteristics and/or reliability.

5) Use storage areas where there is minimal temperature fluctuation. Rapid temperature changes can cause moisture condensation on stored devices, resulting in lead oxidation or corrosion. As a result, lead solder ability will be degraded. 6) When repacking devices, use antistatic containers. Unused devices should be stored no longer than one month. 7) Do not allow external forces or loads to be applied to the devices while they are in storage.

Transportation

Handle the device and packaging material with care. To avoid damage to the device, do not toss or drop. During transport, ensure that the device is not subjected to mechanical vibration or shock. Avoid getting devices wet. Moisture can also adversely affect the packaging (by nullifying the effect of the antistatic agent). Place the devices in special conductive trays. When handling devices, hold the package and avoid touching the leads, especially the gate terminal. Put package boxes in the correct direction. Putting them upside down, leaning them or giving them uneven stress might cause the electrode terminals to be deformed or the resin case to be damaged. Throwing or dropping the packaging boxes might cause the devices to be damaged. Wetting the packaging boxes might cause the breakdown of devices when operating. Pay attention not to wet them when transporting on a rainy or a snowy day. Storage 1) Avoid locations where devices will be exposed to moisture or direct sunlight. (Be especially careful during periods of rain or snow.) 2) Do not place the device cartons upside down. Stack the cartons atop one another in an upright position only.: Do not place cartons on their sides. 3) The storage area temperature should be maintained within a range of 5C to 35C, with humidity kept within the range from 40% to 75%. 4) Do not store devices in the presence of harmful (especially corrosive) gases, or in dusty conditions.
2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

Environment 1) When humidity in the working environment decreases, the human body and other insulators can easily become charged with electrostatic electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment. Be aware of the risk of moisture absorption by the products after unpacking from moistureproof packaging. 2) Be sure that all equipment, jigs and tools in the working area are grounded to earth. 3) Place a conductive mat over the floor of the work area, or take other appropriate measures, so that the floor surface is grounded to earth and is protected against electrostatic electricity. 4) Cover the workbench surface with a conductive mat, grounded to earth, to disperse electrostatic electricity on the surface through resistive components. Workbench surfaces must not be constructed of low-resistance metallic material that allows rapid static discharge when a charged device touches it directly. 5) Ensure that work chairs are protected with an antistatic textile cover and are grounded to the floor surface with a grounding chain. 6) Install antistatic mats on storage shelf surfaces.

www.fairchildsemi.com 10

APP NOTE NUMBER

APPLICATION NOTE

7) For transport and temporary storage of devices, use containers that are made of antistatic materials of materials that dissipate static electricity. 8) Make sure cart surfaces that come into contact with device packaging are made of materials that will conduct static electricity, and are grounded to the floor surface with a grounding chain. 9) Operators must wear antistatic clothing and conductive shoes (or a leg or heel strap). 10) Operators must wear a wrist strap grounded to earth through a resistor of about 1M&. 11) If the tweezers you use are likely to touch the device terminals, use an antistatic type and avoid metallic tweezers. If a charged device touches such a low resistance tool, a rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pad at the tip and connect it to a dedicated ground used expressly for antistatic purposes.

12) When storing device-mounted circuit boards, use a board container or bag that is protected against static charge. Keep them separated from each other, and do not stack them directly on top of one another, to prevent static charge/discharge which occurs due to friction. 13) Ensure that articles (such as clip-boards) that are brought into static electricity control areas are constructed of antistatic materials as far as possible. 14) In cases where the human body comes into direct contact with a device, be sure to wear finger cots or gloves protected against static electricity.

Electrical Shock A device undergoing electrical measurement poses the danger of electrical shock. Do not touch the device unless you are sure that the power to the measuring instrument is off.

5.3 Marking Specifications

(a) Sustain ( FVP18030IMS3LSG1 ) Figure 18.

(b) ER (FVP12030IMS3LEG1 ) Marking Layout (bottom side)

(a) Sustain ( FVP18030IMS3LSG1 )


2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07 11

(b) ER (FVP12030IMS3LEG1 )
www.fairchildsemi.com

APP NOTE NUMBER

APPLICATION NOTE

Figure 19.

Marking Dimension of PDP-SPM

1. F : FAIRCHILD LOGO (STYLE & SIZE : SEE SPEC BD-2249) 2. XXX : Last 3 digits of Lot No (OPTION CODE) 3. YWW : WORK WEEK CODE ("Y" refers to the right alphabet character table) Table 2 Work Week Code

5.4 Packaging Specifications

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com 12

APP NOTE NUMBER

APPLICATION NOTE

Figure 20.

Description of packaging process

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com 13

www.fairchildsemi.com

References
[ 1 ] Sang-Kyoo Han, New High-Performance EnergyRecovery Driver System and High-Efficiency Power Conversion Circuit for Plasma Display Panel

[ 2 ] Motion System Gr, Smart Power Module, Motion SPM in Mini-Dip Users Guide, Fairchild Semiconductor Application Note AN-9035, Rev.B.

DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

2007 Fairchild Semiconductor Corporation Rev. 1.0.0 9/4/07

www.fairchildsemi.com