Computer Architecture

Assignment 1 (Solutions)
UNIT 1: Data Representation
1. Differentiate between parity checker and parity generator. Show with circuit diagram. Parity generator and checker networks are logic circuits constructed with exclusive-OR functions. Consider a 3-bit message to be transmitted with an odd parity bit. At the sending end, the odd parity is generated by a parity generator circuit. The output of the parity checker would be 1 when an error occurs i.e. no. of 1s in the four inputs is even.

Considers original message as well as parity bit

e=1 No. of 1s in pxyz is even. Therefore there is an error in data e=0 No. of 1s in pxyz is odd. Therefore the data is error free Circuit diagram for parity generator and parity checker is given below:

2. Represent decimal number 8620 in BCD, excess-3 code, 2421 code and as a binary number (a) BCD 1000 0110 0010 0000 (b) XS-3 1011 1001 0101 0011 (c) 2421 1110 1100 0010 0000 (d) Binary 10000110101100 (8192 + 256 + 128 + 32 + 8 + 4) 3. List the 10 BCD digits with an even parity in the leftmost position (total of five bits per digit). Repeat with an odd-parity bit. Decimal 0 1 2 3 4 5 6 7 8 9 BCD with even parity 00000 10001 10010 00011 10100 00101 00110 10111 11000 01001 BCD with odd parity 10000 00001 00010 10011 00100 10101 10110 00111 01000 11001

UNIT 2: Microoperations
1. The following transfer statements specify a memory. Explain the memory operation in each case: a. R2 M[AR] b. M[AR] R3 c. R5 M[R5]

(a) Read memory word specified by the address in AR into register R2. (b) Write content of register R3 into the memory word specified by the address in AR. (c) Read memory word specified by the address in R5 and transfer content to R5 (destroys previous value)

2. Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. the circuit generates the following four arithmetic operations in conjunction with the input carry Cin. Draw the logic diagram for the first two stages. S 0 1 Cin = 0 D = A + B (add) D = A - 1 (decrement) Cin = 1 D = A + 1 (increment) D = A + B +1 (subtract)

3. Design a digital circuit that performs the four logic operations of exclusive-OR, exclusive-NOR, NOR, and NAND. Use two selection variables. Show the logic diagram of one typical stage.

4. Register A holds the 8-bit binary 11011001. Determine the B operand and the logic microoperation to be performed in order to change the value in A to a. 01101101 b. 11111101

UNIT 3: Fundamental of Computer Organization and Design

1. Explain interrupt cycle in detail. The interrupt cycle is a hardware implementation of a branch and save return address operation.

Figure: Flowchart for Interrupt Cycle

At the beginning of the instruction cycle, the instruction that is read from memory is in address 1. At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine. The instruction that returns the control to the original program is "indirect BUN 0".

Figure: Demonstration of the Interrupt Cycle 2. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part. a. How many bits are there in the operation code, the register code part, and the address part? b. Draw the instruction word format and indicate the number of bits in each part. c. How many bits are there in the data and address inputs of the memory? Memory 256 K = 28 210 = 218 64 Registers = 26 (a) Address: 18 bits Register code: 6 bits Indirect bit: 1 bit Total = 25 bits Now, 32 25 = 7 bits for opcode (b) 1 7 6 18 = 32 bits

(c) Data = 32 bits; Address = 18 bits.

3. What are the two instructions needed in the basic computer in order to set the E flip-flop to 1? CLE CME Clear E Complement E

UNIT 4: Control Unit

1. What do you mean by field decoding? Explain with block diagram. The 9-bits of the micro-operation field are divided into 3 subfields of 3 bits each. The control memory output of each subfield must be decoded to provide distinct micro-operations. The outputs of the decoders are connected to the appropriate inputs in the processor unit.

Since there are three microoperation fields we need 3 decoders. Each of the three fields of the microinstruction presently available in the output of control memory are decoded with a 3x8 decoder to provide eight outputs. when F1 = 5, transfers the content of DK(0-10) to AR (DRTAR). when F1 = 6 there is a transfer from PC to AR (PCTAR). Outputs 5 and 6 of decoder F1 are connected to the load input of AR so that information is transferred to AR. The multiplexers select the information from DR when output 5 is active and from PC when output 5 is inactive.

2. Explain the Micro program sequence with an example along with a suitable diagram and a truth table. The basic components of a micro programmed control unit are control memory and the circuits that select the next address. This address selection part is called a micro program sequencer. The purpose of micro program sequencer is to load CAR so that microinstruction may be read and executed. Commercial sequencers include within the unit an internal resister stack to store addresses during micro program looping and subroutine calls. Internal structure of a typical micro program sequencer is shown below in the diagram. It consists of input logic circuit having following truth table:

Figure: Input Logic Truth for Micro program Sequencer The figure below represents the micro program sequencer for a control memory in which: MUX1 selects an address from one of four sources of and routes it into CAR. MUX2 tests the value of selected status bit and result is applied to input logic circuit. Output of CAR provides address for the control memory. Input logic circuit has 3 inputs I0, I1 and T and 3 outputs S0, S1 and L. Variables S0 and S1 select one of the source addresses for CAR. L enables load input of SBR. The binary values of the two selection variables determine the path in the multiplexer. Example: When S1S0=10, MUX input number 2 is selected and establishes a transfer path from SBR to CAR.

Figure: Microprogram sequencer for a control memory

3. Using table 7-1 from textbook (Morris Mano), give the 9-bit microoperation field for the following microperations: a. AC AC + 1, DR DR + 1 b. PC PC + 1, DR M[AR] c. DR AC, AC DR F1 011 000 100 F2 110 100 101 F3 000 101 000

(a) (b) (c)

INCAC NOP DRTAC

INCDR READ ACTDR

NOP INCPC NOP

Solutions By: Bijay Mishra