ECE103 Version No.

Prerequisite Objectives

DIGITAL LOGIC DESIGN

3 0 2 4

1.2 ECE101 ELECTRON DEVICES AND CIRCUITS Establish a strong understanding of the principles of Digital Design. Provide Understanding of number systems and Boolean algebra. Represent logical functions in Canonical form and standard forms. Develop the Knowledge of combinational and sequential circuits design. Enable the student to design and implement their circuits
1. An ability to understand the basic number systems used in digital design

Expected Outcome

2. An ability to understand the basic principles of Boolean algebra 3. An ability to design and analyze combinational logic and sequential logic digital circuits 4. Develop state diagrams and algorithmic state machine charts methods of minimization of next state transition tables, and strategies for state assignment. 5. An ability to design and analyze finite state machines. 6. An ability to design and implement Combinational and Sequential circuits using PLAs. Unit I Number systems and Boolean algebra 3 Hrs Brief review of Digital systems, Binary numbers, Number base conversions, Representation of Negative Numbers, Complements, Binary arithmetic, Binary Codes for Decimal Numbers. Basic Definitions, Axiomatic Definition of Boolean Algebra, Basic Theorems and Properties of Boolean Algebra, Boolean Functions, Canonical and Standard Forms, Digital Logic Gates and timing concepts. Unit II Gate-Level Minimization 4 Hrs The Map Method - K-map 4 variable, Product of Sums Simplification, NAND and NOR Implementation, Other Two-Level Implementations. Review of , RTL, DTL, TTL, ECL, CMOS families. Unit III VerilogHDL Coding Style 8 Hrs Lexical Conventions - Ports and Modules Operators - Gate Level Modeling - System Tasks & Compiler Directives - Test Bench - Data Flow Modeling - Behavioral level Modeling -Tasks & Functions Unit IV Design and Modeling of Combinational Logic Circuits 15hrs using Verilog Analysis Procedure, Design Procedure, Binary Adder-Subtractor, Parallel Adder, Carry look Ahead Adder, Binary Multiplier, Code Converters-Binary to Gray, Gray to Binary, BCD to Excess-3 Code Conversion and vice versa, BCD to 7-segment code converter, Magnitude Comparator-4 bit, Decoders, Encoders, Multiplexers, De-multiplexer, Parity generator and checker. Modeling of above combinational circuits using Verilog Unit V Sequential Logic 15 Hrs Latches, Flip-Flops-SR, D, JK & T, realization of FFs, synchronous and asynchronous sequential circuits-State table and state diagrams, State reduction, Shift Registers-SISO, SIPO, PISO,PIPO, Design of counters-Modulo-n, Johnson, Ring, Up/Down, Design of Serial

Adder, Serial Multiplier, FSM, Mealy and Moore state machines - State minimization Sequence detection. Modeling of above sequential circuits using Verilog Text Books
1. M. Morris Mano, "Digital Design", 4th Edition, Prentice Hall of India Pvt.Ltd., 2012. 2. Samir Palnitkar,Verilog HDL: A Guide to Digital Design and Synthesis Prentice Hall, Second Edition, 2009

Reference Books 1. Charles H. Roth, Jr., "Fundamentals of Logic Design", 6th Edition, Brooks/Cole, 2009
2. Thomas L. Floyd & R P Jain, Digital Fundamentals, PHI, 10th Edition, 2009. 3. Ronald J Tocci & Neal S. Widmer, Digital Systems, Principles and Applications,

10th edition, Pearson education, 2009. 4. Ronald J. Tocci & Neal S. Widmer, Digital Systems, Principles and Frank Vahid, Digital Design, John Wiley and Sons, 2007. Mode of Evaluation CAT- I & II, Quizzes, Assignments/ other tests, Term End Examination Date of Approval by the Academic Council: 29th Academic council dated on 26.4.13