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ROM BIST RAM BIST Serial BIST for RAMs

Processor-Based RAM BIST

RAM BISTs in SOCs


Characteristics of todays SOC designs
Typically more than 30 embedded memories on a chip Memories scattered around the device rather than

concentrated in one location Different types and sizes of memories Memories doubly embedded inside embedded cores Test access to these memories from only a few chip I/O pins

Built-in self-test (BIST) is considered the best solution for testing embedded memories within SOCs
It offers a simple and low-cost means without

significantly impacting performance

General BIST Architecture

Test Generator

Circuit Under Test (CUT)

Response Verification

Test Controller

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ROM Functional Block Diagram


Inputs Buffer

NOR/NAND
Decoder

(ROM Array)

Buffer Outputs
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An Example of ROM BIST

Counter

RO M

Controller Go/No-Go Status

MISR

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Typical RAM BIST Architecture


Normal I/Os

Test Controller
Test C ollar

Test Pattern Generator Go/No-Go Comparator

RA M

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RAM BIST

In general, two BIST approaches have been proposed for the RAMs
FSM-based RAM BIST ROM-based RAM BIST

Controller
Generate control signals to the test pattern

generator & the memory under test

Test pattern generator (TPG)


Generate the required test patterns and Read/Write signals

Comparator

Evaluate the response


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ROM-Based RAM BIST

The features of ROM-based BIST scheme


The ROM stores test procedures for generating test patterns Self-test is executed by using BIST circuits controlled by the

microprogram ROM A wide range of test capabilities due to ROM programming flexibility

The BIST circuits consists of the following functional blocks


Microprogram ROM to store the test procedure

Program counter which controls the microprogram ROM TPG Comparator


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ROM-Based RAM BIST Architecture


Normal I/Os

End

Microprogram

ROM

Test Collar

TPG

RA M

Go/No-Go Comparator

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Normal I/Os

End

FSM

Test Collar

TPG

RA M

Go/No-Go Comparator

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FSM-Based RAM BIST

An example of the state diagram of controller


S S
R0 W1 R1 W0 R0
1

W0

NOT last address?

NOT last address?

S
2

S3

S S

NOT last address?

NOT last address?

S
W1 End
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S4
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Programmable RAM BIST

An example of the programmable RAM BIST


Normal I/Os BSI
Co ntroller

CMD &TP G Test TGO ENA DONE a t o r RA M

BSC BRS BGO

Collar

Comp ar

CLK BNS

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FSM State Diagram of the Controller


Idle
BSC=1 DONE=1 BRS=1

Shift_cmd
BSC=0

Get_cmd

Apply
DONE=0

ENA=1

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Serial BIST

Todays telecommunication ICs often have a variety if multiport memories on one chip Typical RAM BISTs evaluate all the bits of a memory word in parallel as it is read We can encounter significant problems when applying these BIST schemes to chips that have multiple embedded RAMs of varying sizes and port configurations
The area cost of these BIST designs would be

unacceptably high

One better solution is a serial BIST technique


To share BIST design among several RAMs
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Benefits of Serial BIST

Only a small amount of additional circuitry is required Only a few lines are needed to connect the RAM to the test controller Several RAM blocks easily share the BIST controller hardware The serial-access mode does not compromise the RAM cycle time
Existing memory designs do not need any modification to use the serial interface

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Serial-Data-Path Connection
dRow

Ci
ecoder Column decoder
Latch

C i+1

Latch

Write Read BIST on


From previous output or serial input To next test input or serial input

I
Ii Oi
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O
i+1 i+1

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Serial Shift Operation

An example of serial shift operations for the match


element (R0W1)
Time Operation Serial Word Serial

in

content

out

0 1 101 00 00 00 2 3 4 010 1 X
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X R0 W1 R0 W1 R0 W1 R0 W1 X 1 1 1 1 1 1 1

0 0 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1

0 0 0 0 0 0 1 1 1

0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
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00

0 0 X

5 6 7 8
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Serial March (SMarch)

Assume that a RAM has W words, and each word contains C bits A Read operation is denoted by R0, R1, or Rx, depending on the expected value at the serial output (x=dot care) For a write operation, the terms W0 or W1 are used and only the serial input is forced to the value indicated The SMarch modified from March C- is as C C C C follcows(RxW 0) ( R0,W 0) ; ( R0,W 1) ( R1,W 1)
( R1,W 0) ( R0,W 0) ; ( R0,W 1) ( R1,W 1)
C C C C C C C C
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( R1,W 0) ( R0,W 0) ; ( R0,W 0) ( R0,W 0)


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Serial BIST Architecture


BIST GO Done
Controller

Counters
Control Data out Data in Address Multiplexer

Timing

SO
lsb

SI
msb

generator

C-1

Multiplexer
C C

Multiplexer

Address

Data in

Data out

Control

RAM (W words of C bits)


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Sharing BIST in Daisy-Chain Style


BIST GO Done

Counters

Controller SO SI

Timing generator

Address

R d/Write

Test Collar RAM1 Serial Interface SI SO


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Test Collar RAM2 Serial Interface SI SO


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Test Collar RAM3 Serial Interface SI SO


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Sharing BIST in Parallel Style


BIST

GO

Done

DeMux

SO Counters
Address

SI

Timing generator

Controller

Test Collar RAM1 Serial Interface SI


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Test Collar RAM2 Serial Interface SI


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Test Collar RAM3 Serial Interface SI SO


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SO

SO

BIST Using Data Decoding/Encoding

n m wire n

n m wire

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Processor-Based RAM BIST


Normal I/Os

Processor
Test Collar

TPG

RA M

Go/No-Go Comparator

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NTHU Processor-Programmable BIST


ADDR_cp u
ADDR_bist DATAO_sy s

ADD R

DATA O
DATAO_bist Mux_sel

Embedded CPU

Clock_cpu

BIST core

On-chip bus

Embedded Memory

Ctrl_cpu

Ctrl_bist

control

DATAI_cpu

DATAI_bist

DATAI_sys

DATAI

Source: Prof. C. W. Wu, NTHU

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NTHU Processor-Programmable BIST

BIST core
DATAO_cpu DATAO_bist

R
B G

R
A

Lowest/highest addr

Address
counter

ADDR_bist

ADDR_cpu

Address

R
EA

decorder

AH

Up/down
Read/Write Control

R
M E

R
FLA G

R
I R

R
ED

Controller

Match/unmatch DATAI_bis t Comparator


DATAI_sy s

Data background

Source: Prof. C. W. Wu, NTHU

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NTHU Processor-Programmable BIST

Data registers
Register

R BG R AL R AH R ME R IR R FLAG R
R
ED
EA

Function Store background data Store lowest address Store highest address Store current March element Instruction register of BIST circuit Status register of BIST circuit Erroneous response of defective cell Address of defective cell
Source: Prof. C. W. Wu, NTHU

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NTHU Processor-Programmable BIST


BIST procedure
Test program write data background to R
BG

Source: Prof. C. W. Wu, NTHU

Test program write lowest/highest address to RAL/RAH


Performed by test program

Test program write March instructions to RME Test program write START to RIR

(Wa)

(Ra,Wa) (Ra,Wa)

(Ra,Wa) (Ra,Wa)

(Ra)

Performed by BIST circuit

Compare Data error

yes

Write ERROR to RFLAG Write error response to RED Write faulty addr to REA

No No
March element complete

yes Write FINISH to RFLAG


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Test program take over 31

SOC Testing

A typical SOC chip


ADC FPGA Wrapper CPU UDL DSP
Sink

Flash Memory

Source

Test Access Mechanism (TAM)

TAM

MPEG

SRAM

SRAM

DRAM

Source: Y. Zorian, et al.-ITC98

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SOC Test Access


ADC FPGA
Wrapper

Flash Memory Sink

Off-chip Source/Sink
1. Pins determine bandwidth 2. More TAM area 3. Requires expensive ATE

CPU

UDL TAM

DSP TAM DRAM

Source MPEG

SRAM SRAM

ADC

FPGA
Wrapper

On-chip Source/Sink
CPU

Flash Memory

UDL
DSP
Sink

1. Close to Core-under-test 2. Less TAM area 3. BIST IP area 4. Requires lightweight ATE
Source
MPEG

Sink

Source
SRA M SRAM

DRAM

Source: Y. Zorian and E.J. Marinissen


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1500 Scalable Test Architecture


Source TAM-in User Defined Parallel TAM TAM-out TAM-in TAM-out Sink

1500 Wrapper Fin

1500 Wrapper Fout Fin

Core1

CoreN

Fout

WSI

WIR

WSO WSI WIP User-Defined Test Controller

WIR

WSO

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1500 Test Wrapper

Test stimuli

WPI
WBR

WPO Test response Core


WBR

Functional data

Functional data

WBY
WSI WIR

WSO
WSC

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Memories in SOCs
ADC FPGA Flash Memory CPU
UDL DSP

DRAM

SRAM

SRAM BIST

SRAM

BIST

MPEG

SRAM BIST

SRAM

DRAM
BIST

Non-BIST memory cores


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BIST-ready memory cores


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RAM BIST in SOCs

Memory cores in an SOC can be categorized into two types in term of testability
BIST-ready memory cores Non-BIST memory cores

An SOC can contain tens or even hundreds of memory cores


Although a BIST usually have only about 8

controlling pins The total BIST controlling pins is huge if each BIST-ready memory cores has its own BIST controlling pins

The BIST controlling pins should be shared


One solution is using memory BIST interface
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Sharing BIST Controlling Pins


ADC FPGA

Flash Memory CPU UDL DSP DRAM

SRAM

SRAM BIST
MBI

SRAM

BIST
MBI MBI

MBI

BIST SRAM

MPEG

BIST SRAM

DRAM

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Memory BIST Interface (MBI)

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Memory BIST Interface (MBI)

Instruction Register
Store the instructions
RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL

Bypass Register
It is selected if the corresponding memory core is not tested

Monitor Register
Monitor the error flag (indicating whether a memory fault is

detected or not)

Status Register
Record the key status values, such as Fail output from the

BIST
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Testing Multiple Memories with MBI

Using RUN_BIST instruction, we can test multiple memory cores concurrently


When one or more BIST circuits detect faults, the primary MSO_N will

be high after N-K clock cycles if the concurrent output of the (K+1) through the N memory cores are fault free
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Sharing BIST Hardware


BIST controlling signals TPG & Comparator

BIST Controller

BIST Collar RAM 1

BIST Collar RAM 2

BIST Collar RAM N

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RAM BIST Compiler

Source: Prof. C. W. Wu, NTHU


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1500-Compilant BIST

T ConAP troller

Wra

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TA
P

BIST

RAM

pper
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Programmable BISD for RAMs in SOCs


General test architecture
ATE SO C
Wrapper Processor + Test Program Memory

TAP controller

TAM

Embedded Memory Core

Source: Appello D., et. al. ITC03

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Programmable BISD for RAMs in SOCs


Test Processor
Processor
Wrapper P1500 Instructions

Control Unit

Test Program

P1500 Output Data

Memory Adapter

Address Bus
Data Bus

Control Signals

Source: Appello D., et. al. ITC03


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Programmable BISD for RAMs in SOCs

Control Unit
Manage the test program execution Include an Instruction Register (IR) and

Program Counter (PC) The control unit allows the correct update of some registers located in Memory Adapter This part simplifies the processor reuse in different applications without the need for any re-design

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Programmable BISD for RAMs in SOCs

Memory Adapter
Control Address registers (Current_address) Control Memory registers
Current_data Received_data

Control Test registers


Dbg_index, Step, Direction flag, and Timer registers

Result registers
Status, Error, and Result registers

Some constant value registers


Add_Max, Add_Min, DataBackGround, Dbg_max

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Programmable BISD for RAMs in SOCs


Processor instruction set
Instruction
SET_ADD RST_ADD

Meaning
Current_address Add_Max Direction flag BACKWARD Current_address Add_Min Direction flag FORWARD Current_data DataBackGround[Dbg_index] Dbg_index Dbg_index+1 Current_data NOT (Current_data) Current_data Memory[Current_address] Memory[Current_address] Current_data
Source: Appello D., et. al. ITC03

STORE_DBG INV_DBG READ WRITE

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Programmable BISD for RAMs in SOCs


Wrapper
WSI

WRCK WRSTN ShiftWR UpdateWR


CaptureWR

W I R W B Y

W D R

W C D R Processor

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TAP controller

W B R

M e mo ry

SelectWIR

Test Program

CORE

WSO

Wrapper Source: Appello D., et. al. ITC03


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Summary

ROM BIST has been presented ROM-based and FSM-based RAM BIST have been introduced Serial BIST methodology for embedded memories has also presented BIST approaches for testing multiple RAMs in an SOC have also been addressed

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