VLSI Implementation of Hybrid Universal Logic on 350 nm Technology

Manoj Kumar1, Ravi Chandra Pratap Singh2

2

Maharaja Agrasen Institute of Technology, Guru Gobind Singh Indraprastha University, Delhi, India Guru Nanak Education Trust Group of Institution, Department of Electronics, Uttarakhand Technical University, Roorkee, India 1 manoj.uiet@gmail.com, 2ravipratapsingh98@gmail.com
ABSTRACT

This paper presents a Hybrid Universal Logic. The designed logic circuit comprise the property of both the NAND and NOR gate as well as the NOT gate. The schematic is designed and simulated using the Tanner EDA 13.0 tool on 350 nm technology. Six MOS transistor used to implement this design, one buffer is used to provide the stability to the output. The design consists of five PMOS transistor and one NMOS transistor. The Hybrid Universal Logic is such designed to overcome the hectic of designing the circuit using the MUX and changing the inputs and the working of the circuit changes from NAND to NOR or viceversa. Keywords Hybrid Universal Logic, 350 nm, Six Transistor.

The final output can be viewed form the equation form: Here S Operation Select. Output = {S (A+B) + S (AB)} For NAND S = 0 NOR S = 1 NOT S = 1, A = GND (Zero) In the output equation if the value of S is zero then the first part of the equation will be executed and the second part will be completely zero it means the circuit will work as the NAND, and if the value of Sis one the first part of the equation will be completely zero and the second will be executed TABLE.1 shows the complete logic of the equations. When one of the input is set to grounded or zero ant the value of S is one and the input is assigned to the other input the circuit will act as the inverter. II. HYBRID UNIVERSAL LOGIC

I.

INTRODUCTION

The universal logic gates available as NAND and NOR are well known [1], both of the gates can designed all the logic circuits and the alternative approach to design these gates is Multiplexer. The universal gates can be designed using the Multiplexer but the data inputs and the select line should change when to change the gate either from NAND to NOR or vice-versa. To compensate this problem without changing the inputs and only altering the operation select line the NAND, NOR and NOT gate operation can be performed using the Hybrid Universal logic. The Hybrid Universal Logic is so designed and implemented that it can perform the NAND gate operation, NOR gate operation as well as Inverter. So using this logic circuit all the logic circuits can also be designed without solving the cumbersome logical equations which are solved to implement the logical equation using multiplexer. The simple structure of the designed Hybrid Universal Logic circuit can be viewed by Fig. 1. The circuit designed can also be represented by the symbolic representation shown in Fig.1. The symbol shows that the inputs are the A and B and the output is dependent on the operation Select when it is zero it will act as NAND and if it is one it will work as NOR.

The truth table shown in TABLE 1. shows basic approach that followed in this design. The inputs are A and B are binary data, the operation select is also the one bit binary input that decides that which operation is desired. If the value of the operation select is zero the Hybrid Universal Logic circuit will perform the NAND operation over the binary input data, or if the value of the operation select is one then Hybrid Universal Logic circuit will work as the NOR gate over the binary input data A and B. To operate the Hybrid Universal Logic circuit as the Inverter connect the one of its input to ground assign the input on the remaining terminal and set the operation select to one, so it will work as the inverter. The schematic diagram of the Hybrid Universal Logic circuit shown in Fig.4. The sizing of the transistor has been adjusted to obtain the desired results. For the PMOS used in the design the width of the PMOS taken 9.5m and for the NOMS the width used is 1.25 m. The channel length for both the NMOS and the PMOS is 0.25 m.
TABLE 1. Truth Table for the input of Hybrid Universal Logic circuit with the Operation select and the outputs.

Fig.1

The TABLE 1. describes the complete detail of the Hybrid Universal Logic circuit. In column first the input A and in column second the input B is shown if the value of the operation select is zero for the value of AB= 00,01,10 and 11 respectively the circuit is working as NAND gate, and if the Operation Select is 1 the circuit is working as the NOR gate. III. A. Simulation result The Hybrid Universal Logic circuit has been designed in two versions one is with output buffer and other without output buffer. The output buffer is used to stabilize the output. Without the buffer the result is approximately desired but with the buffer the results is accurate and clear. Fig.1 shows the output results of the Hybrid Universal Logic circuit with buffer, and Fig. 3 shows the simulated results without buffer. RESULTS

Fig.3 Hybrid Universal Logic circuit output without buffer

TABLE 2. Transistor switching table for the Hybrid Universal Logic circuit

The complete working can be viewed with the help of the truth table designed for the Hybrid Universal Logic circuit. TABLE 2. covers all the condition of the inputs and based on the input conditions the working of the transistor is shown the final output is represented as Z.

B. Schematic

Fig. 2 Hybrid Universal Logic circuit output with buffer

From zero ns to 40 ns the output waveform showing the results of NAND gate and from 40 to onwards it circuit is acting as NOR gate. If we consider that the input A is grounded means zero for 80 ns to 100ns and the value of operation select is one then the output is the invert of input B. The description given is for the result shown in Fig.1.If the output is taken without the output buffer then the output is not being complete one or complete zero.

Fig.4 Schematic of Hybrid Universal Logic circuit

The discussion of the on and off of the transistors is presented in the TABLE.2. The PMOS transistors are assigned as P1, P2, P3, P4, P5 and the NMOS is assigned as the N1.to stablize the output the output buffer has been used.

IV.

CONCLUSION

The Hybrid Universal Logic which gives the working of NAND, NOR and NOT gate successfully designed and implemented on 350 nm MOS technology. The total numbers of MOS transistor used are 6 when the buffer is not being inserted. On inserting the buffer in the circuit the total number of MOS transistor are 10. Due to the less number of the transistor are being used in the design the area of the designs using this circuit can me reduced and the better speed can be achieved.

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