The Inverter

KTH/ESDlab/HT
The Inverter
Prof. Hannu Tenhunen Royal Institute of Technology Department of Electronics Electronic System Design Laboratory Email: hannu@ele.kth.se
KTH/ESDlab/HT
10/4/00
Outline
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Noise margins in logic Delay definitions CMOS inverter characteristics

VTC delay
Power dissipation
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Noise margins
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Noise sources in digital logic
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2
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DC characteristics: Voltage transfer curve
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From analog signals to digital values
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3
3
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Noise margins
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Regenerative property of digital logic
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4
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Simulated inverter chain response
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Delay definitions
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5
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Ring oscillator
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CMOS Inverter Static Behavior
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NMOS transistor characteristics
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PMOS transistor characteristics
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7
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Basic CMOS inverter
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CMOS inverter layout
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Switch model of MOS transistor
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Pull-up/pull-down via NMOS
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9
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CMOS inverter: steady state response
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CMOS inverter: steady state responses
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10
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PMOS load lines
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CMOS inverter load characteristics
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11
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CMOS inverter VTC
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Simulated VTC
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12
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NMOS and PMOS transistor I-V curves in inverter
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CMOS inverter VTC
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13
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CMOS static characteristics
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CMOS inverter VTC vs. transistor sizing
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Gate switching threshold
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Example: VTC of CMOS inverter
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Inverter Dynamic Behavour
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CMOS dynamic behavior
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CMOS inverter: transient response
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CMOS inverter: propagation delay
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CMOS dynamic behavior: capacitance
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CMOS inverter input & output capacitances
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Gate-drain and drain-bulk capacitance
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Wiring and load capacitance
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19
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Inverter capacitance calculations (ala backannotated Spice)
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Logic delay model
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20
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CMOS inverter dynamic characteristics: high-to-low
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CMOS inverter dynamic characteristics:low-to-high
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21
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Simplified delay model (RC)
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Impact of rise time to delay
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22
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Velocity saturation
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Delay vs. operating voltage Vdd
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Discharging via multiple NMOS transistors
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CMOS inverter delay summary
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Power dissipation
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Power dissipation
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CMOS power dissipation
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Power due to direct path currents
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Dynamic power consumption
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Static vs. dynamic current dissipation in CMOS inverter
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Power dissipation vs. capacitive load
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28
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The Inverter

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The Inverter

Hochgeladen von

Copyright:

Verfügbare Formate

KTH/ESDlab/HT

Noise margins in logic Delay definitions CMOS inverter characteristics

Noise sources in digital logic

DC characteristics: Voltage transfer curve

From analog signals to digital values

Regenerative property of digital logic

Simulated inverter chain response

CMOS Inverter Static Behavior

NMOS transistor characteristics

PMOS transistor characteristics

Basic CMOS inverter

CMOS inverter layout

Switch model of MOS transistor

Pull-up/pull-down via NMOS

CMOS inverter: steady state response

CMOS inverter: steady state responses

PMOS load lines

CMOS inverter load characteristics

CMOS inverter VTC

NMOS and PMOS transistor I-V curves in inverter

CMOS inverter VTC

CMOS static characteristics

CMOS inverter VTC vs. transistor sizing

Gate switching threshold

Example: VTC of CMOS inverter

Inverter Dynamic Behavour

CMOS dynamic behavior

CMOS inverter: transient response

CMOS inverter: propagation delay

CMOS dynamic behavior: capacitance

CMOS inverter input & output capacitances

Gate-drain and drain-bulk capacitance

Wiring and load capacitance

Inverter capacitance calculations (ala backannotated Spice)

Logic delay model

CMOS inverter dynamic characteristics: high-to-low

CMOS inverter dynamic characteristics:low-to-high

Simplified delay model (RC)

Impact of rise time to delay

Delay vs. operating voltage Vdd

Discharging via multiple NMOS transistors

CMOS inverter delay summary

CMOS power dissipation

Power due to direct path currents

Dynamic power consumption

Static vs. dynamic current dissipation in CMOS inverter

Power dissipation vs. capacitive load

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