C:\Users\Bernhard Boser\Documents \Files\Class\40\lecture\6 kTC

4/30/2009

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Reference:W:\Lib\MathCAD\Default\defaults.mcd

kT/C Noise
Objective: measure dR/R with high resolution (e.g. 1ppm) Output voltage Example: Vo := 1V r= R Ro Given v out Vs R o R Ro := 1k r := 1ppm + v out + Vs R o + R =0 Find( v out) Vs R Ro

Co := 1pF R := r Ro R = 1 m

v out := Vo r Q := Co v out

v out = 1 V Q = 1 10
18

coul

Q qe

= 6.242

electrons! 2 1 Co v out = k B Tr 2 2 1

Noise

Equipartition principle (thermodynamics) 2 rms noise voltage accross capacitor v out 2 k B Tr v out = Co k B Tr Co = 63.274 V k B = 13.805 rms 10
24

K v out = 1 V

Tr = 290 K no chance to detect!

Interpretation: variations of subsequent voltmeter readings (Gaussian) (rmds Vo)2 2 k B Tr v out = = 2 Co 2 k B Tr Co Vo

2

MDS

rmds :=

rmds = 89.483 ppm

improvements: - increase Vo (increased power dissipation) - increase Co (decreased bandwidth)

Power dissipation Po = Bandwidth

(2 Vo) 2
2 Ro 1 2 Ro 2

2 Vo Ro =

Po := 1 fb :=

2 Vo Ro 1

Po = 2 mW fb = 318.31 MHz

fb =

Co

Ro Co

Ro Co

higher capacitance is desirable in this case!

C:\Users\Bernhard Boser\Documents \Files\Class\40\lecture\6 kTC

4/30/2009

Page 2 of 2

Power / speed / accuracy tradeoff: rmds =

2

2 k B Tr Co Vo
2

Ro 2 Vo fb Po
2

1 Ro Co

4 k B Tr

rmds := Tradeoff ex:

4 k B Tr

rmds = 89.483 ppm

- double fb, double Po (rmds fixed) - cut power by 4x (keep fb), rmds / 2 2x change of rmds corresponds to 1 bit. Example: Ro = 1024 Ohm, dR = 1Ohm, 1024 levels --> 10 bits Ro = 1024 Ohm, dR = 2Ohm, 512 levels --> 9 bits

General: Conclusions:

fb Po MDS

= const

constant determined by circuit (designer skill)

Double resolution --> 4x power dissipation! (same bandwidth) Double bandwidth --> 2x power dissipation (same resolution) Fixed requirements and circuit topology (const) dictate power dissipation. Applies to RF (cell phones, wireless links), sensors (xcells, gyros), circuits (ADCs). Comparison with digital circuits: Supply voltage: Capacitance per gate (average): Complexity (number of gates): Activity factor: Clock rate: Power dissipation: Vdd := 1V C1 := 10fF N1 := 10
6

limited scaling opportunities scales

1 := 10% fs := 1GHz P1 := 1 2 N1 C1 Vdd 1 fs

2

P1 = 0.5 W

Accuracy: adding 1 bit results in a linear to quadratic increase of N1. E.g. 15Bit --> 16Bit Analog: Why digital: performance scales rubustness to noise "arbitrary" precision programmable relative ease of design N1

15

16

16 = 1.138 15

x power increase

4x power increase Why analog: inputs and outputs usually digital performs certain functions more efficient e.g. narrow band RF filter: many fewer degrees of freedom